Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises at least one semiconductor layer, a first scanning signal line and a second capacitor. The at least one semiconductor layer includes a first channel portion and a first conductive portion. The first scanning signal line and the first conductive part are overlapped to form a first capacitor, and the first scanning signal line and the first channel part are overlapped to form a first transistor; the second capacitor comprises a first conductive block and a second conductive block, the second conductive block is arranged between the first conductive block and the semiconductor layer comprising the first channel part, and the second conductive block is connected with the first conductive part; wherein in the orthographic projection on the reference surface, the first conductive block covers the part, arranged in the outer side boundary of the first conductive block, of the second conductive block; and / or the second capacitor further comprises a third conductive block, the third conductive block is arranged on the side, away from the second conductive block, of the first conductive block, and the third conductive block and the first conductive block are at least partially overlapped; and the third conductive block is connected with the first conductive part.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, display devices (such as mobile phones, notebook computers or tablet computers, etc.) are increasingly applied to people's lives. Among them, the organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display device has the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., and therefore receives widespread attention.

[0003] SUMMARY

[0004] In one aspect, a display panel is provided. The display panel includes at least one semiconductor layer, a first scan signal line and a second capacitor. The at least one semiconductor layer includes a first channel portion and a first conductive portion. The first scan signal line overlaps with the first conductive portion to form a first capacitor, and overlaps with the first channel portion to form a first transistor; the second capacitor includes a first conductive block and a second conductive block, the second conductive block is arranged between the first conductive block and the semiconductor layer including the first channel portion, and the second conductive block is connected with the first conductive portion; wherein, in the orthographic projection onto a reference plane, the first conductive block covers, and the second conductive block covers a part arranged within the outer side boundary of the first conductive block; and / or, the second capacitor further includes a third conductive block, the third conductive block is arranged on a side of the first conductive block away from the second conductive block, and the third conductive block at least partially overlaps with the first conductive portion; the third conductive block is connected with the first conductive portion.

[0005] In some embodiments, the second conductive block includes a first main portion and a first connecting portion. The orthographic projection of the first main portion onto the reference plane is arranged within the outer side boundary of the orthographic projection of the second conductive block onto the reference plane; the first connecting portion is connected with the first main portion; at least part of the orthographic projection of the first connecting portion onto the reference plane is arranged outside the outer side boundary of the orthographic projection of the second conductive block onto the reference plane, and is connected with the first conductive portion.

[0006] In some embodiments, the orthographic projection of the third conductive block onto the reference plane is arranged within the range of the orthographic projection of the first conductive block onto the reference plane; the display panel further includes a first connecting line, one end of the first connecting line is connected with the first conductive portion, and the other end is connected with the third conductive block.

[0007] In some embodiments, the third conductive block includes a second main body portion and a second connecting portion. A projection of the second main body portion on the reference plane is disposed within the outer boundary of the projection of the second conductive block on the reference plane. The second connecting portion is connected with the second main body portion. The second connecting portion is disposed on the periphery of the second main body portion. The display panel further includes a first connecting line, one end of the first connecting line being connected with the first conductive portion, and the other end of the first connecting line being connected with the second connecting portion.

[0008] In some embodiments, at least part of the projection of the second connecting portion on the reference plane is disposed outside the outer boundary of the projection of the first conductive block on the reference plane. The part of the second connecting portion disposed outside the outer boundary of the first conductive block is connected with the first conductive portion.

[0009] In some embodiments, the projection of the first connecting portion on the reference plane is staggered with the projection of the second connecting portion on the reference plane. The first connecting line is disposed on the side of the third conductive block away from the second conductive block. The first connecting line is further connected with the first connecting portion.

[0010] In some embodiments, the first conductive block is provided with a first through hole penetrating the first conductive block. The third conductive block extends into the first through hole and is connected with the second conductive block.

[0011] In some embodiments, the third conductive block includes a second main body portion and a second connecting portion. A projection of the second main body portion on the reference plane is disposed within the outer boundary of the projection of the second conductive block on the reference plane. The second connecting portion is connected with the second main body portion. The second connecting portion is disposed on the periphery of the second main body portion. The display panel further includes a first connecting line, one end of the first connecting line being connected with the first conductive portion, and the other end of the first connecting line being connected with the second connecting portion.

[0012] In some embodiments, the at least one semiconductor layer further comprises a second channel portion; the display panel further comprises a second scan signal line; the second scan signal line and the second channel portion overlap to form a second transistor; the second scan signal line comprises a first straight segment and a first bending segment. The first straight segment extends along a first direction; in the orthogonal projection onto the reference plane, along the first direction, the first straight segment is disposed on one side of the connecting portion; along a second direction, the first straight segment is disposed between the main body portion and the first scan signal line; the first direction intersects the second direction; in the orthogonal projection onto the reference plane, the first bending segment bends away from the side of the main body portion towards the first straight segment.

[0013] In some embodiments, the first scan signal line comprises a first wire segment. The orthogonal projection of the first wire segment onto the reference plane coincides with the orthogonal projection of the first conductive portion onto the reference plane, and the line width of the first wire segment is less than or equal to 2.5 μm.

[0014] In some embodiments, the display panel comprises a pixel circuit. The pixel circuit comprises a drive transistor, and the drive transistor comprises a fourth channel portion; the orthogonal projection of the fourth channel portion onto the reference plane partially coincides with the orthogonal projection of the second conductive block onto the reference plane, and the portion of the second conductive block that coincides with the fourth channel portion forms a gate electrode of the drive transistor.

[0015] In some embodiments, the pixel circuit further comprises a compensation transistor; a first electrode of the compensation transistor is connected to a second electrode of the drive transistor, and a second electrode of the compensation transistor is connected to the gate electrode of the drive transistor; wherein the first conductive portion forms the second electrode of the compensation transistor.

[0016] In some embodiments, the display panel further comprises a pixel circuit, and the pixel circuit comprises a data write transistor; the data write transistor is connected to a data signal terminal; wherein the first transistor is the data write transistor, and the portion of the first scan signal line that overlaps with the first channel portion forms a gate electrode of the data write transistor.

[0017] In some embodiments, the display panel further comprises a pixel circuit, and the pixel circuit further comprises a first reset transistor; a first electrode of the first reset transistor is connected to a first initialization signal terminal; the first reset transistor comprises a third channel portion; the orthogonal projection of the third channel portion onto the reference plane partially coincides with the orthogonal projection of the first scan signal line onto the reference plane, and the portion of the first scan signal line that coincides with the third channel portion forms a gate electrode of the first reset transistor.

[0018] In another aspect, a display device is provided. The display device includes the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0020] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0021] FIG. 2 is another structural diagram of a display device according to some embodiments;

[0022] FIG. 3 is a structural diagram of a display device including a display panel and a driving circuit board according to some embodiments;

[0023] FIG. 4 is a structural diagram of a display panel according to some embodiments;

[0024] FIG. 5 is a sectional view of FIG. 4 along the cutting line A-A;

[0025] FIG. 6 is another structural diagram of a display panel according to some embodiments;

[0026] FIG. 7 is yet another structural diagram of a display panel according to some embodiments;

[0027] FIG. 8 is a structural diagram of a second conductive block including a first main body portion and a first connecting portion according to some embodiments;

[0028] FIG. 9 is yet another structural diagram of a display panel according to some embodiments;

[0029] FIG. 10 is a structural diagram of a first conductive block provided with a first through hole according to some embodiments;

[0030] FIG. 11 is yet another structural diagram of a display panel according to some embodiments;

[0031] FIG. 12 is yet another structural diagram of a display panel according to some embodiments;

[0032] FIG. 13 is yet another structural diagram of a display panel according to some embodiments;

[0033] FIG. 14 is yet another structural diagram of a display panel according to some embodiments;

[0034] FIG. 15 is a structural diagram of a pixel circuit according to some embodiments;

[0035] FIG. 16 is yet another structural diagram of a display panel according to some embodiments;

[0036] FIG. 17 is another sectional view along the cutting line A-A in FIG. 4. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0038] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, and other forms of the term “comprise”, are used throughout the specification and claims in an open, inclusive sense, that is, as “including, but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0039] Hereinafter, the terms “first” and “second” are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of “a plurality of” is two or more.

[0040] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a remote location from each other. The term "coupled" as used herein encompasses the case where one or more intervening elements can exist. The embodiments disclosed herein are not necessarily limited to the details of the embodiments described.

[0041] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C," and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0042] "A and / or B" includes the following combinations: A alone, B alone, and a combination of A and B.

[0043] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to a determination" or "in response to a detection of," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" is, optionally, interpreted as meaning "upon a determination of" or "in response to a determination of" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0044] Use of "adapted to" or "configured to," as used herein, means open and inclusive language that does not exclude additional devices or steps that are adapted to or configured to perform the recited tasks or steps.

[0045] Additionally, use of "based on" means open and inclusive, as the process, step, calculation, or other action that is based on one or more stated conditions or values can in fact be based on additional conditions or values beyond those stated.

[0046] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, “parallel,” “perpendicular,” “equal” include the recited condition and conditions that are approximately the recited condition, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “parallel” includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel can be, for example, within 5°; “perpendicular” includes absolute perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular can also be, for example, within 5°. “Equal” includes absolute equality and approximate equality, where the acceptable deviation range for approximately equal can be, for example, a difference between the two that is less than or equal to 5% of either.

[0048] It will be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layer's and regions' characteristics are shown on the drawings, for example, the thickness of layers, regions, and / or areas can be exaggerated. It will also be appreciated that some variations can occur when depositing or patterning the layers and regions. Thus, members, regions, and / or areas can be shown with exaggerated dimensions in order to illustrate the example embodiments more clearly. Therefore, the exemplary embodiments should not be considered limited to the shapes shown in the drawings, but include any shapes that can be formed in the course of fabricating the example embodiments. For example, etched regions shown as rectangular will typically have curved features. Thus, the regions illustrated in the drawings are schematic and not intended to be limiting of the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0050] As shown in FIGS. 1 and 2, some embodiments of the disclosure provide a display device 1000, which can be any device that displays whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0051] Exemplarily, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation device, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, a flight display, etc.

[0052] In some examples, as shown in FIG. 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in FIG. 1.

[0053] In yet other examples, as shown in FIG. 2, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in FIG. 2.

[0054] In some embodiments, as shown in FIG. 3, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0055] The display panel 100 has opposite light-emitting and non-light-emitting sides 100A and 100B. The light-emitting side 100A is the side from which the display panel 100 can emit light (the upper side of the display panel 100 in FIG. 3), and the non-light-emitting side 100B is the other side opposite the light-emitting side 100A (the lower side of the display panel 100 in FIG. 3).

[0056] The driving circuit board 200 is disposed on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide a light-emitting signal to the display panel 100.

[0057] The housing 300 can be a box-shaped structure having an opening. The display panel 100 and the driving circuit board 200 can be disposed in the housing 300, and the cover plate 400 is disposed on the light-emitting side of the display panel 100 and at the opening of the housing 300.

[0058] As shown in FIG. 3, the longitudinal cross-section of the housing 300 can be U-shaped, for example. The display panel 100 and the driving circuit board 200 are disposed in the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0059] The type of the display panel 100 described above can include various types, which can be selected and disposed according to actual needs.

[0060] Exemplarily, the display panel 100 can be an organic light-emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, a mini / micro light emitting display (MLED) display panel, or the like, which are not specifically limited in the embodiments of the present disclosure.

[0061] In the following, some embodiments of the present disclosure are schematically described with the display panel 100 being an OLED display panel as an example.

[0062] In some embodiments, as shown in FIGS. 4 and 5, the display panel 100 includes a reference surface and a plurality of sub-pixels 20.

[0063] The material of the reference surface can include a polymer resin or glass. Exemplarily, the reference surface can be flexible, and the material of the reference surface includes one of a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formic acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Exemplarily, the reference surface can be rigid, and the material of the reference surface includes a glass material including SiO2 as a main component.

[0064] As shown in FIG. 4, a plurality of sub-pixels 20 are arranged on the reference surface. The plurality of sub-pixels 20 can be arranged in multiple rows and multiple columns, for example. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0065] The plurality of sub-pixels 20 can include first sub-pixels with a first color, second sub-pixels with a second color, and third sub-pixels with a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which are not limited in the embodiments of the present disclosure.

[0066] In some embodiments, as shown in FIGS. 4 and 5, each sub-pixel 20 includes a pixel circuit 21 and a light emitting device 22 arranged on the reference surface.

[0067] In some embodiments, the pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (Capacitor, abbreviated as C).

[0068] The transistors used in the circuit provided by some embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics. In some embodiments of the present disclosure, thin film transistors are taken as examples for illustration.

[0069] For example, the transistor 211 is an oxide thin film transistor. The oxide thin film transistor has a high carrier mobility, which can improve the response speed of the transistor 211.

[0070] In some embodiments, as shown in FIG. 5, the transistor 211 includes an active part 2111, a source 2112, a drain 2113, and a gate 2114. The source 2112 and the drain 2113 are in contact with the active part 2111, respectively. The storage capacitor 212 includes two oppositely arranged plates.

[0071] It should be noted that the source 2112 and the drain 2113 can be interchangeable, i.e., 2112 in FIG. 5 represents the drain, and 2113 represents the source.

[0072] In some examples, the active part 2111 includes a source part, a drain part, and a channel part. The channel part is arranged between the source part and the drain part. The source part is in contact with the source, and the drain part is connected to the drain.

[0073] In some embodiments, as shown in FIG. 5, the light emitting device 22 includes a first electrode 221, a light emitting functional layer 222, and a second electrode 223. The first electrode 221 can be electrically connected to the source 2112 or the drain 2113 of the transistor 211 as the driving transistor, for example. In FIG. 5, the first electrode 221 is electrically connected to the drain 2113 of the transistor 211. The material of the first electrode 221 includes indium tin oxide (ITO) or silver (Ag). The material of the second electrode includes aluminum (Al), Ag, or magnesium (Mg).

[0074] It should be noted that the first electrode 221 is the anode of the light emitting device 22, and the second electrode 223 is the cathode of the light emitting device 22. Alternatively, the first electrode 221 is the cathode of the light emitting device 22, and the second electrode 223 is the anode of the light emitting device 22. Hereinafter, the first electrode 221 is taken as the anode of the light emitting device 22, and the second electrode 223 is taken as the cathode of the light emitting device 22 as an example to illustrate the embodiments of the present disclosure.

[0075] As an example, as shown in FIG. 5, the second electrode 223 (cathode) is a whole layer structure.

[0076] The light emitting functional layer 222 can include only a light emitting layer, or can further include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) in addition to the light emitting layer.

[0077] In some embodiments, as shown in FIG. 5, the display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is arranged on the side of the plurality of sub-pixels 20 away from the reference surface, and is used to encapsulate the light emitting device 22 to improve the service life of the light emitting device 22. The encapsulation layer 30 can be an encapsulation film or an encapsulation substrate, which is not limited in the embodiments of the present disclosure.

[0078] Exemplarily, the encapsulation layer 30 can include one encapsulation film, or two or more encapsulation films arranged in a stack. For example, as shown in FIG. 5, the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 arranged in a stack in a direction perpendicular to and away from the reference surface. The materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

[0079] In some embodiments, as shown in FIG. 6, the display panel 100 further includes at least one semiconductor layer 40 including a first channel portion 41 and a first conductive portion 42.

[0080] In some examples, the display panel 100 includes only one semiconductor layer 40, i.e., the display panel 100 includes a first semiconductor layer including the first channel portion 41 and the first conductive portion 42.

[0081] In other examples, as shown in FIG. 6, the display panel includes two semiconductor layers 40, i.e., the display panel 100 includes a first semiconductor layer and a second semiconductor layer. The first channel portion 41 is arranged in the first semiconductor layer, and the first conductive portion 42 is arranged in the second semiconductor layer; or the first channel portion 41 is arranged in the second semiconductor layer, and the first conductive portion 42 is arranged in the first semiconductor layer.

[0082] Exemplarily, the first semiconductor layer is a low-temperature polysilicon semiconductor layer, and the second semiconductor layer is an oxide semiconductor layer. In this way, low-temperature polysilicon transistors and oxide transistors can be integrated on one display panel 100, and the advantages of both can be utilized (low-temperature polysilicon thin film transistors have high mobility and fast charging, and oxide thin film transistors have low leakage current), which can reduce the power consumption of the display panel 100 and improve the display quality of the display panel 100.

[0083] As shown in FIG. 6, the display panel 100 further includes a first scan signal line 60. The first scan signal line 60 is connected to the pixel circuit 21. The first scan signal line 60 overlaps with the first conductive portion 42 to form a first capacitor 1, and overlaps with the first channel portion 41 to form a first transistor 2, and the first scan signal line 60 is used to control the conduction and cutoff of the first transistor 2.

[0084] As shown in FIG. 6, the display panel 100 further includes a second capacitor 50 (for example, a storage capacitor 212 in the pixel circuit 21). The second capacitor 50 includes a first conductive block 51 and a second conductive block 52, the second conductive block 52 is disposed between the first conductive block 51 and the semiconductor layer 40 including the first channel portion 41, and the second conductive block 52 is connected with the first conductive portion 42. That is, the first capacitor 1 and the second capacitor 50 are connected in parallel.

[0085] In the related art, the lateral crosstalk of the display panel is more serious and the brightness uniformity is poor, which leads to poor display effect of the display panel. After research, the inventors found that the first conductive block is provided with a through hole, and the display panel further includes a connecting line, one end of the connecting line is connected with the first channel portion, and the other end of the connecting line passes through the through hole and is connected with the second conductive block. The first conductive block is provided with a through hole, which leads to a small overlapping area of the first conductive block and the second conductive block, which leads to a small capacitance of the second capacitor. In the case that the total capacitance of the first capacitor and the second capacitor is unchanged, the small capacitance of the second capacitor leads to a large capacitance of the first capacitor, which leads to a large voltage drop on the first scanning signal, which leads to more serious lateral crosstalk of the display panel and poor brightness uniformity.

[0086] In order to solve the above technical problems, as shown in FIG. 6, some embodiments of the present disclosure provide a display panel 100, in the orthographic projection to the reference plane, the first conductive block 51 covers, and the second conductive block 52 is provided with a part in the outer side boundary of the first conductive block 51.

[0087] That is, compared with the first conductive block in the related art, the part of the first conductive block 51 forming the second capacitor 50 in some embodiments of the present disclosure is not provided with a through hole. In this way, the relative area of the two plates of the second capacitor 50 can be increased, and the capacitance of the second capacitor 50 can be increased. At this time, in the case that the total capacitance of the first capacitor 1 and the second capacitor 50 is unchanged, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scanning signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improve the display effect of the display panel 100.

[0088] It can be understood that it needs to be explained that the reference plane is the plane where the display surface of the display panel 100 is located.

[0089] In some other embodiments, as shown in FIG. 7, the second capacitor 50 further includes a third conductive block 53. The third conductive block 53 is disposed on the side of the first conductive block 51 away from the second conductive block 52; the third conductive block 53 at least partially overlaps with the first conductive block 51, and the third conductive block 53 is connected with the first conductive portion 42.

[0090] In this way, the third conductive block 53 and the second conductive block 52 are connected, and the third conductive block 53 and the second conductive block 52 together form one plate of the second capacitor 50, so that the relative area of the two plates of the second capacitor 50 can be increased. At this time, in the case that the total capacitance of the first capacitor 1 and the second capacitor 50 does not change, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is conducive to improving the display effect of the display panel 100.

[0091] In some embodiments, as shown in FIG. 8, the second conductive block 52 includes a first body part 521 and a first connecting part 522. The orthographic projection of the first body part 521 on the reference surface is arranged within the outer side boundary of the orthographic projection of the second conductive block 52 on the reference surface. The first connecting part 522 is connected with the first body part 521, and at least part of the orthographic projection of the first connecting part 522 on the reference surface is arranged outside the outer side boundary of the orthographic projection of the second conductive block 52 on the reference surface and is connected with the first conductive part 42.

[0092] In some embodiments, as shown in FIG. 7, the orthographic projection of the third conductive block 53 on the reference surface is arranged within the range of the orthographic projection of the first conductive block 51 on the reference surface.

[0093] On this basis, the display panel 100 further includes a first connecting line 70, one end of the first connecting line 70 is connected with the first conductive part 42, and the other end is connected with the third conductive block 53. In this way, the third conductive block 53 and the first conductive part 42 are connected.

[0094] In some embodiments, as shown in FIG. 9, the third conductive block 53 includes a second body part 531 and a second connecting part 532. The orthographic projection of the second body part 531 on the reference surface is arranged within the outer side boundary of the orthographic projection of the second conductive block 52 on the reference surface. The second connecting part 532 is connected with the second body part 531, and the second connecting part 532 is arranged on the circumferential side of the second body part 531.

[0095] On this basis, the display panel 100 further includes a first connecting line 70, one end of the first connecting line 70 is connected with the first conductive part 42, and the other end is connected with the second connecting part 532. In this way, the third conductive block 53 and the first conductive part 42 are connected.

[0096] In some embodiments, as shown in FIG. 9, at least part of the orthographic projection of the second connecting part 532 on the reference surface is arranged outside the outer side boundary of the orthographic projection of the first conductive block 51 on the reference surface, and the part of the second connecting part 532 arranged outside the outer side boundary of the first conductive block 51 is connected with the first conductive part 42.

[0097] In this way, the relative area of the third conductive block 53 and the second conductive block 52 can be increased, the relative area of the two plates of the second capacitor 50 is further increased, and the capacitance of the second capacitor 50 is increased. At this time, the total capacitance of the first capacitor 1 and the second capacitor 50 is unchanged, the capacitance of the first capacitor 1 can be reduced, and the voltage drop of the first scan signal line 60 is further reduced, the lateral crosstalk of the display panel 100 is reduced, and the brightness uniformity of the display panel 100 is improved, which is beneficial to improve the display effect of the display panel 100.

[0098] In some embodiments, as shown in FIG. 9, the orthographic projection of the first connecting part 522 on the reference surface is staggered with the orthographic projection of the second connecting part 532 on the reference surface. The first connecting line 70 is also connected with the first connecting part 522.

[0099] In this way, the film layer between the second conductive block 52 and / or the third conductive block 53 and the first conductive block 51 is less, the distance between the second conductive block 52 and / or the third conductive block 53 and the first conductive block 51 can be reduced, the distance between the two plates of the second capacitor 50 is reduced, and the capacitance of the second capacitor 50 is further increased. At this time, the total capacitance of the first capacitor 1 and the second capacitor 50 is unchanged, the capacitance of the first capacitor 1 can be reduced, and the voltage drop of the first scan signal line 60 is further reduced, the lateral crosstalk of the display panel 100 is reduced, and the brightness uniformity of the display panel 100 is improved, which is beneficial to improve the display effect of the display panel 100.

[0100] In some embodiments, as shown in FIG. 10, the first conductive block 51 is provided with a first through hole 511 penetrating the first conductive block 51, and as shown in FIG. 11, the third conductive block 53 extends into the first through hole 511 and is connected with the second conductive block 52. In this way, the second conductive block 52 and the third conductive block 53 can be connected.

[0101] In some embodiments, as shown in FIG. 11, the third conductive block 53 includes a second main part 531 and a second connecting part 532. The orthographic projection of the second main part 531 on the reference surface is arranged within the outer side boundary of the orthographic projection of the second conductive block 52 on the reference surface. The second main part 531 extends into the first through hole 511 and is connected with the second conductive block 52. The second connecting part 532 is connected with the second main part 531, and at least part of the orthographic projection of the second connecting part 532 on the reference surface is arranged outside the outer side boundary of the orthographic projection of the second conductive block 52 on the reference surface.

[0102] On this basis, the display panel 100 further includes a first connecting line 70, one end of the first connecting line 70 is connected with the first conductive part 42, and the other end is connected with the second connecting part 532. In this way, the first conductive part 42 and the second conductive block 52 and the third conductive block 53 can be connected.

[0103] In some embodiments, as shown in FIG. 12, the second conductive block 52 includes a first body portion 521 and a first connecting portion 522. The orthographic projection of the first body portion 521 on the reference plane is disposed within the outer side boundary of the orthographic projection of the second conductive block 52 on the reference plane. At least part of the orthographic projection of the first connecting portion 522 on the reference plane is disposed outside the outer side boundary of the orthographic projection of the second conductive block 52 on the reference plane. The third conductive block 53 extends into the first through hole 511 and is connected with the first body portion 521.

[0104] On this basis, the display panel 100 further includes a first connecting line 70, one end of the first connecting line 70 being connected with the first conductive portion 42, and the other end being connected with the first connecting portion 522. In this way, the first conductive portion 42 can be connected with the second conductive block 52 and the third conductive block 53.

[0105] In some embodiments, as shown in FIG. 6, the at least one semiconductor layer 40 further includes a second channel portion 43. The display panel further includes a second scan signal line 80, the second scan signal line 80 being connected with the pixel circuit 21, and the second scan signal line 80 and the second channel portion 43 overlapping to form a second transistor 3. The second scan signal line 80 is used to control the conduction or cutoff of the second transistor 3.

[0106] For example, as shown in FIG. 6, the second channel portion 43 is disposed in the same layer as the first conductive portion 42.

[0107] As shown in FIGS. 13 and 14, the second scan signal line 80 includes a first straight segment 81 and a first bending segment 82. The first straight segment 81 extends along the first direction X. In the orthographic projection on the reference plane, along the first direction X, the first straight segment 81 is disposed on one side of the connecting portion (the first connecting portion 522 or the second connecting portion 532), and along the second direction Y, the first straight segment 81 is disposed between the body portion (the first body portion 521 or the second body portion 531) and the first scan signal line 60, and the first bending segment 82 bends away from the side of the body portion toward the first straight segment 81 to avoid the connecting portion. In this way, the size of the pixel circuit 21 along the second direction Y can be reduced, thereby increasing the number of pixel circuits 21 and being conducive to improving the resolution of the display panel 100.

[0108] In some embodiments, as shown in FIGS. 13 and 14, the first scan signal line 60 includes a first wire segment 61, the orthographic projection of the first wire segment 61 on the reference plane coincides with the orthographic projection of the first conductive portion 42 on the reference plane, and the line width of the first wire segment 61 is less than or equal to 2.5 μm.

[0109] In this way, the relative area of the first scan signal line 60 and the first conductive portion 42 can be reduced, the capacitance of the first capacitor 1 can be reduced, the voltage drop of the first scan signal line 60 can be reduced, the lateral crosstalk of the display panel 100 can be reduced, and the brightness uniformity of the display panel 100 can be improved, thereby improving the display effect of the display panel 100.

[0110] For example, the line width of the third wire segment is 2.5 μm, 2 μm, 1.4 μm, or 0.9 μm.

[0111] In some embodiments, some embodiments of the present disclosure are exemplarily described taking the pixel circuit 21 in a 7T1C structure as an example. As shown in FIG. 15, the pixel circuit 21 includes a driving transistor T1, a compensation transistor T2, a data writing transistor T3, a first reset transistor T4, a second reset transistor T5, a first light emitting transistor T6, a second light emitting transistor T7, and a first storage capacitor C1.

[0112] The control electrode (gate) of the driving transistor T1 is connected with the first node N1, the first electrode is connected with the second node N2, and the second electrode is connected with the third node N3. The first electrode of the compensation transistor T2 is connected with the third node N3, the second electrode is connected with the first node N1, and the control electrode is connected with the first scan signal end GATE1. The first electrode of the data writing transistor T3 is connected with the data signal end DATA, the second electrode is connected with the second node N2, and the control electrode is connected with the second scan signal end GATE2. The first electrode of the first reset transistor T4 is connected with the first initialization signal end VINIT1, the second electrode is connected with the anode of the light emitting device 22, and the control electrode is connected with the first reset signal end RESET1. The first electrode of the second reset transistor T5 is connected with the second initialization signal end VINIT2, the second electrode is connected with the first node N1, and the control electrode is connected with the second reset signal end RESET2. The first electrode of the first light emitting transistor T6 is connected with the first voltage signal end VDD, the second electrode is connected with the second node N2, and the control electrode is connected with the light emitting signal end EM. The first electrode of the second light emitting transistor T7 is connected with the third node N3, the second electrode is connected with the anode of the light emitting device 22, and the control electrode is connected with the light emitting signal end EM.

[0113] In addition, as shown in FIG. 15, the cathode of the light emitting device 22 is connected with the second voltage signal end VSS. The level output by the second voltage signal end VSS is lower than the level output by the first voltage signal end VDD.

[0114] In some embodiments, as shown in FIG. 16, the driving transistor T1 includes a fourth channel portion T13, a projection of the fourth channel portion T13 on the reference surface partially overlaps with a projection of the second conductive block 52 on the reference surface, and a portion of the second conductive block 52 that overlaps with the fourth channel portion T13 forms a gate of the driving transistor T1. In some embodiments, the fourth channel portion T13 is disposed in the first semiconductor layer 101.

[0115] On this basis, as shown in FIG. 16, the first conductive portion 42 forms a second electrode of the compensation transistor T2.

[0116] In some embodiments, the first transistor 2 is a data writing transistor T3, and a portion of the first scan signal line 60 that overlaps with the first channel portion 41 forms a gate of the data writing transistor T3.

[0117] In this way, in the case where all the sub-pixel gray scales are the same, the difference between the data signals written by the driving transistors T1 of the plurality of pixel circuits 21 can be reduced, and the brightness uniformity of the display panel 100 can be improved.

[0118] In some embodiments, as shown in FIG. 16, the first reset transistor T4 includes a third channel portion T43, a projection of the third channel portion T43 on the reference surface partially overlaps with a projection of the first scan signal line 60 on the reference surface, and a portion of the first scan signal line 60 that overlaps with the third channel portion T43 forms a gate of the first reset transistor T4.

[0119] In this way, the difference between the potentials of the anodes of the light emitting devices 22 of the plurality of sub-pixels 20 can be reduced, and the brightness uniformity of the display panel 100 can be improved.

[0120] In some examples, the first reset signal end RESET1 and the first scan signal end GATE1 in one pixel circuit 21 are connected to the same first scan signal line 60. In other examples, as shown in FIG. 16, the sub-pixels 20 are arranged in an array in multiple rows and multiple columns, the first scan signal end GATE1 in one pixel circuit 21 and the first reset signal end RESET1 in one pixel circuit 21 in the previous row of pixel circuits 21 are connected to the same first scan signal line 60.

[0121] The following describes the first conductive layer 103, the second conductive layer 104, the third conductive layer 105, the fourth conductive layer 106, and the fifth conductive layer 107 in combination with the film layers included in the display panel 100.

[0122] In some embodiments, as shown in FIG. 5, the pixel circuit 21 includes low-temperature polysilicon thin film transistors and oxide thin film transistors. At this time, in the direction perpendicular to the reference surface and away from the reference surface, the display panel 100 further includes a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, an oxide semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a second interlayer insulating layer ILD2, a first source-drain conductive layer SD1, a first planar layer PLN1, a second source-drain conductive layer SD2, and a second planar layer PLN2, which are sequentially arranged.

[0123] In this case, the first channel portion 41 is provided in the low-temperature polysilicon semiconductor layer ACT1, the second conductive block 52 and the first scan signal line 60 are provided in the first gate conductive layer GT1, the first conductive block 51 is provided in the second gate conductive layer GT2, the first conductive portion 42 and the second channel portion 43 are provided in the oxide semiconductor layer ACT2, the third conductive block 53 and the second scan signal line 80 are provided in the third gate conductive layer GT3, and the first connection line 70 is provided in the first source-drain conductive layer SD1.

[0124] In some other embodiments, as shown in FIG. 17, the pixel circuit 21 includes only low-temperature polysilicon thin film transistors. At this time, in the direction perpendicular to the reference surface and away from the reference surface, the display panel 100 further includes a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a first interlayer insulating layer ILD1, a first source-drain conductive layer SD1, a first planar layer PLN1, a second source-drain conductive layer SD2, and a second planar layer PLN2, which are sequentially arranged.

[0125] In this case, the first channel portion 41, the second channel portion 43, and the first conductive portion 42 are provided in the low-temperature polysilicon semiconductor layer ACT1, the second conductive block 52 and the first scan signal line 60 are provided in the first gate conductive layer GT1, the first conductive block 51 is provided in the second gate conductive layer GT2, the third conductive block 53 and the second scan signal line 80 are provided in the third gate conductive layer GT3, and the first connection line 70 is provided in the first source-drain conductive layer SD1.

[0126] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0127] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: at least one semiconductor layer comprising a first channel portion and a first conductive portion; a first scan signal line overlapping with the first conductive portion to form a first capacitor and overlapping with the first channel portion to form a first transistor; a second capacitor comprising a first conductive block and a second conductive block, the second conductive block being disposed between the first conductive block and the semiconductor layer comprising the first channel portion, and the second conductive block being connected with the first conductive portion; wherein, in a front projection onto a reference plane, the first conductive block covers a part of the second conductive block disposed within an outer boundary of the first conductive block; and / or, the second capacitor further comprises a third conductive block disposed on a side of the first conductive block away from the second conductive block, and the third conductive block at least partially overlaps with the first conductive portion; and the third conductive block is connected with the first conductive portion.

2. The display panel of claim 1, wherein, The second conductive block comprises: a first main body portion, a front projection onto the reference plane of which is disposed within an outer boundary of a front projection onto the reference plane of the second conductive block; a first connecting portion connected with the first main body portion; at least a part of the first connecting portion, a front projection onto the reference plane of which is disposed outside the outer boundary of the front projection onto the reference plane of the second conductive block, is connected with the first conductive portion.

3. The display panel of claim 2, wherein, A front projection onto the reference plane of the third conductive block is disposed within a range of a front projection onto the reference plane of the first conductive block. The display panel further comprises: a first connecting line; one end of the first connecting line is connected with the first conductive portion, and the other end is connected with the third conductive block.

4. The display panel of claim 2, wherein, The third conductive block comprises: a second main body portion, a front projection onto the reference plane of which is disposed within an outer boundary of a front projection onto the reference plane of the second conductive block; a second connecting portion connected with the second main body portion; the second connecting portion is disposed on a circumferential side of the second main body portion. The display panel further comprises: a first connecting line; one end of the first connecting line is connected with the first conductive portion, and the other end is connected with the second connecting portion.

5. The display panel of claim 4, wherein, At least a part of a front projection onto the reference plane of the second connecting portion is disposed outside an outer boundary of a front projection onto the reference plane of the first conductive block, and a part of the second connecting portion disposed outside the outer boundary of the first conductive block is connected with the first conductive portion.

6. The display panel of claim 5, wherein, A front projection onto the reference plane of the first connecting portion is disposed staggered with a front projection onto the reference plane of the second connecting portion. The first connecting line is disposed on a side of the third conductive block away from the second conductive block, and the first connecting line is further connected with the first connecting portion.

7. The display panel of claim 1, wherein, The first conductive block is provided with a first through hole penetrating through the first conductive block, and the third conductive block extends into the first through hole to be connected with the second conductive block.

8. The display panel of claim 7, wherein, The third conductive block comprises: a second main body portion, a front projection onto the reference plane of which is disposed within an outer boundary of a front projection onto the reference plane of the second conductive block; and the second main body portion extends into the first through hole to be connected with the second conductive block. The second connecting portion is connected with the second main body portion, and a projection of at least part of the second connecting portion on the reference surface is arranged outside a boundary of a projection of the second conductive block on the reference surface. The display panel further comprises: The first connecting line has one end connected with the first conductive portion and the other end connected with the second connecting portion.

9. The display panel according to any one of claims 2 to 8, wherein, The at least one semiconductor layer further comprises a second channel portion; The display panel further comprises: The second scanning signal line forms a second transistor with the second channel portion; the second scanning signal line comprises: The first straight line segment extends in a first direction; in a projection on the reference surface, the first straight line segment is arranged on one side of the connecting portion in the first direction; in the projection on the reference surface, the first straight line segment is arranged between the main body portion and the first scanning signal line in a second direction; the first direction intersects the second direction; The first bending segment bends away from the one side of the main body portion toward the first straight line segment in the projection on the reference surface.

10. The display panel according to any one of claims 1 to 9, wherein, The first scanning signal line comprises: The first wire segment has a line width less than or equal to 2.5 μm.

11. The display panel according to any one of claims 1-10, comprising: The pixel circuit comprises a driving transistor; the driving transistor comprises a fourth channel portion; The projection of the fourth channel portion on the reference surface partially overlaps with the projection of the second conductive block on the reference surface; a portion of the second conductive block that overlaps with the fourth channel portion forms a gate electrode of the driving transistor.

12. The display panel of claim 11, wherein, The pixel circuit further comprises: The compensation transistor has a first electrode connected with a second electrode of the driving transistor and a second electrode connected with the gate electrode of the driving transistor; the first conductive portion forms the second electrode of the compensation transistor.

13. The display panel according to any one of claims 1-12, further comprising: The pixel circuit comprises a data writing transistor; the data writing transistor is connected with a data signal terminal; the first transistor is the data writing transistor; a portion of the first scanning signal line that overlaps with the first channel portion forms a gate electrode of the data writing transistor.

14. The display panel according to any one of claims 1-13, further comprising: The pixel circuit further comprises a first reset transistor; the first reset transistor has a first electrode connected with a first initialization signal terminal; the first reset transistor comprises a third channel portion; a projection of the third channel portion on the reference surface partially overlaps with a projection of the first scanning signal line on the reference surface; a portion of the first scanning signal line that overlaps with the third channel portion forms a gate electrode of the first reset transistor.

15. A display device comprising the display panel according to any one of claims 1-14. ​

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