Display device and manufacturing method thereof

Abstract

The invention provides a display device and a method of manufacturing the same. The display device includes a first electrode disposed in a first conductive layer on a substrate; a first insulating layer covering the first conductive layer; a second electrode disposed in the second conductive layer on the first insulating layer; a second insulating layer covering the second conductive layer; an active layer of the transistor disposed in the semiconductor layer on the second insulating layer; a gate insulating layer disposed on a portion of the active layer; a third electrode disposed in the third conductive layer on the gate insulating layer; a third insulating layer covering the semiconductor layer, the gate insulating layer, and the third conductive layer; and a fourth electrode disposed in the fourth conductive layer on the third insulating layer. The fourth electrode overlaps the first electrode and is directly connected to the first electrode through a first contact hole passing through the first insulating layer, the second insulating layer, and the third insulating layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and a method of manufacturing a display device. Background Technology

[0002] With the development of multimedia technology, the importance of display devices has been continuously increasing. In response, various display devices, including light-emitting display devices, are being developed. Summary of the Invention

[0003] Technical issues

[0004] The problem to be solved by this disclosure is to provide a display device that can improve manufacturing efficiency and a method for manufacturing the display device.

[0005] The objectives of this invention are not limited to those described above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Technical solution

[0007] A display device according to an embodiment includes: a first electrode disposed in a first conductive layer on a substrate; a first insulating layer disposed on the substrate and covering the first conductive layer; a second electrode disposed in a second conductive layer on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering the second conductive layer; an active layer of a transistor disposed in a semiconductor layer on the second insulating layer; a gate insulating layer disposed on the second insulating layer and disposed on a portion of the active layer; a third electrode disposed in a third conductive layer on the gate insulating layer; a third insulating layer disposed on the second insulating layer and covering the semiconductor layer, the gate insulating layer, and the third conductive layer; and a fourth electrode disposed in a fourth conductive layer on the third insulating layer. The fourth electrode overlaps with the first electrode and is directly connected to the first electrode through a first contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

[0008] In one embodiment, the fourth electrode can be directly connected to the third electrode through a second contact hole that penetrates the third insulating layer, and the first electrode, the third electrode, and the fourth electrode can constitute the first capacitor electrode of the capacitor.

[0009] In an embodiment, the second electrode may overlap with at least one of the first, third, and fourth electrodes, and may constitute the second capacitor electrode of a capacitor.

[0010] In one embodiment, the display device may further include a fifth electrode disposed in a fourth conductive layer, spaced apart from the fourth electrode, and overlapping the second electrode. The fifth electrode can be directly connected to the second electrode through a third contact hole penetrating the second and third insulating layers, and can constitute a second capacitor electrode.

[0011] In one embodiment, the display device may further include: a fourth insulating layer disposed on the third insulating layer and covering the fourth conductive layer; and a sixth electrode disposed in the fifth conductive layer on the fourth insulating layer and overlapping the fifth electrode. The sixth electrode can be connected to the fifth electrode through a fourth contact hole penetrating the fourth insulating layer and can constitute a second capacitor electrode.

[0012] In an embodiment, the transistor may further include a gate electrode disposed in a third conductive layer and disposed overlapping a portion of the active layer.

[0013] In an embodiment, the transistor may further include at least one of a source electrode and a drain electrode, wherein the source electrode is disposed in the fourth conductive layer and connected to the source region of the active layer through a fifth contact hole penetrating the third insulating layer, and the drain electrode is disposed in the fourth conductive layer and connected to the drain region of the active layer through a sixth contact hole penetrating the third insulating layer.

[0014] In an embodiment, the transistor may further include a bottom electrode disposed in the second conductive layer and overlapping the active layer and the gate electrode.

[0015] In one implementation, the bottom electrode can be connected to the source electrode through a seventh contact hole that penetrates the second and third insulating layers.

[0016] In an embodiment, the display device may further include: a fourth insulating layer disposed on the third insulating layer and covering the fourth conductive layer; a bridging electrode disposed in the fifth conductive layer on the fourth insulating layer and connected to one of the source electrode and the drain electrode through an eighth contact hole penetrating the fourth insulating layer; and a fifth insulating layer disposed on the fourth insulating layer and covering the fifth conductive layer.

[0017] In an embodiment, the display device may further include: a light-emitting element layer disposed on a fifth insulating layer and including a light-emitting element connected to a bridging electrode through a ninth contact hole penetrating the fifth insulating layer; and an encapsulation layer covering the light-emitting element layer.

[0018] The display device according to an embodiment includes: a capacitor including a first electrode disposed in a first conductive layer on a substrate, a second electrode disposed in a second conductive layer on the first conductive layer, a third electrode disposed in a third conductive layer on the second conductive layer, and a fourth electrode disposed in a fourth conductive layer on the third conductive layer; a first insulating layer disposed between the first and second conductive layers; a second insulating layer disposed between the second and third conductive layers; and a third insulating layer disposed between the third and fourth conductive layers. The fourth electrode is directly connected to the first electrode through a first contact hole penetrating the first, second, and third insulating layers, and is directly connected to the third electrode through a second contact hole penetrating the third insulating layer.

[0019] In an embodiment, the capacitor may further include a fifth electrode, which is spaced apart from the fourth electrode, disposed in the fourth conductive layer, and overlaps with the second electrode. The fifth electrode can be directly connected to the second electrode through a third contact hole that penetrates the second and third insulating layers.

[0020] In one embodiment, the display device may further include: a fourth insulating layer disposed on the third insulating layer and covering the fourth conductive layer; and a fifth conductive layer disposed on the fourth insulating layer. The capacitor may further include a sixth electrode disposed in the fifth conductive layer and connected to the fifth electrode through a fourth contact hole penetrating the fourth insulating layer.

[0021] In an embodiment, the display device may further include: a semiconductor layer disposed between a second insulating layer and a third conductive layer; a gate insulating layer disposed between the semiconductor layer and the third conductive layer; and a transistor including an active layer disposed in the semiconductor layer and a gate electrode disposed in the third conductive layer and overlapping a portion of the active layer.

[0022] In one embodiment, a gate insulating layer may be disposed between the portion of the active layer and the gate electrode, and another portion of the active layer may be exposed.

[0023] A method for manufacturing a display device according to an embodiment includes: forming a first conductive layer including a first electrode and a first insulating layer covering the first conductive layer on a substrate; forming a second conductive layer including a second electrode and a second insulating layer covering the second conductive layer on the first insulating layer; forming a semiconductor layer including an active layer of a transistor and a gate insulating layer covering the semiconductor layer on the second insulating layer; forming a conductive film on the gate insulating layer; etching the conductive film and the gate insulating layer to form a first gate insulating layer and a gate electrode on a portion of the active layer, and a second gate insulating layer and a third electrode on a portion of the second insulating layer; forming a third insulating layer covering the active layer, the gate electrode, and the third electrode on the second insulating layer; forming a first contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer to expose a portion of the first electrode; and forming a fourth conductive layer on the third insulating layer, the fourth conductive layer including a fourth electrode directly connected to the first electrode through the first contact hole.

[0024] In an embodiment, the method may further include: during the formation of the first contact hole, further forming a second contact hole that penetrates the third insulating layer to expose a portion of the third electrode, and forming the fourth conductive layer may include directly connecting the fourth electrode to the third electrode through the second contact hole.

[0025] In an embodiment, the method may further include: during the formation of the first contact hole, further forming a third contact hole that penetrates the second and third insulating layers to expose a portion of the second electrode, and forming the fourth conductive layer may include further forming a fifth electrode that is spaced apart from the fourth electrode and directly connected to the second electrode through the third contact hole.

[0026] In an embodiment, the method may further include: during the formation of the first contact hole, further forming a plurality of contact holes that penetrate the third insulating layer to expose different portions of the active layer, and forming the fourth conductive layer may include further forming source electrodes and drain electrodes that are connected to the different portions of the active layer through the plurality of contact holes.

[0027] Further details of the implementation are included in the detailed description and accompanying drawings.

[0028] Beneficial effects

[0029] The display device according to the embodiments may include patterns disposed in a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate. The display device may also include an active layer disposed in a semiconductor layer between the second and third conductive layers. In the embodiments, patterns disposed in the conductive layers and / or semiconductor layers below the fourth conductive layer may be individually and / or in parallel connected to patterns disposed in the fourth conductive layer via individual contact holes. In the embodiments, the contact holes may be formed simultaneously using a single mask process.

[0030] According to the display device and the method for manufacturing the display device according to the embodiment, the pixel area of ​​the display panel can be utilized effectively, and the design space for forming pixels and wiring can be appropriately ensured. Furthermore, the number of mask processes used to manufacture the display panel can be reduced and / or minimized, and the manufacturing process of the display panel can be simplified. Therefore, the manufacturing cost of the display device can be reduced, and manufacturing efficiency can be improved.

[0031] The effects of the embodiments are not limited to those illustrated above, and many more different effects are included in this disclosure. Attached Figure Description

[0032] Figure 1 This is a plan view showing a display device according to one embodiment.

[0033] Figure 2 It is shown Figure 1 A floor plan of the display panel.

[0034] Figure 3 This is an equivalent circuit diagram of a pixel according to one embodiment.

[0035] Figure 4 This is a cross-sectional view showing a display panel according to one embodiment.

[0036] Figures 5 to 15 This is a cross-sectional view showing a method of manufacturing a display device according to one embodiment. Detailed Implementation

[0037] The advantages and features of this disclosure, as well as methods of implementing it, can be more readily understood from the following description with reference to the embodiments and accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of this disclosure to those skilled in the art, and this disclosure will be defined solely by the appended claims.

[0038] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or there may be intervening elements or layers. Throughout the specification, the same reference numerals denote the same elements. The shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings for the purpose of describing embodiments are merely examples, and this disclosure is not limited to the details shown.

[0039] Features of the various embodiments of this disclosure can be partially or entirely linked or combined with each other, and can technically operate and drive each other in various ways. Embodiments can be implemented independently of each other, or they can be implemented together in a coexisting relationship.

[0040] In the following description, specific embodiments will be described with reference to the accompanying drawings.

[0041] Figure 1 This is a plan view showing a display device 100 according to one embodiment. Figure 2 It is shown Figure 1 A floor plan of the display panel 110.

[0042] refer to Figure 1 and Figure 2 The display device 100 is a device for displaying moving or still images. The display device 100 can be used as a display screen for various devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). These are merely examples, and the display device 100 can be applied to a wide variety of other types of electronic devices.

[0043] In one embodiment, the display device 100 may be a light-emitting display device, such as an organic light-emitting display including organic light-emitting diodes, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, or an ultra-miniature light-emitting display including ultra-miniature light-emitting diodes such as micro-light-emitting diodes or nano-light-emitting diodes (micro-LEDs or nano-LEDs), but is not limited thereto. For example, the display device 100 may be another type of display device besides a light-emitting display device. In the following, an embodiment of the display device 100 as a light-emitting display device (e.g., an organic light-emitting display device) will be disclosed.

[0044] The display device 100 may include a display panel 110 comprising pixels PX and a first driver 120 and a second driver 130 configured to supply drive signals to the pixels PX. The display device 100 may also include additional components. For example, the display device 100 may further include a power supply unit for supplying electrical voltage to the pixels PX, the first driver 120, and the second driver 130, and a timing controller for controlling the operation of the first driver 120 and the second driver 130.

[0045] Display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be an area including pixels PX for displaying an image. For example, the display area DA may include a pixel area with pixels PX arranged therein. The non-display area NDA is an area other than the display area DA, and no image may be displayed in the non-display area NDA. In one embodiment, the non-display area NDA may be located around the display area DA and may surround the display area DA.

[0046] exist Figure 1 and Figure 2 The diagram defines a first direction D1, a second direction D2, and a third direction D3. In one embodiment, the first direction D1 may be the horizontal direction of the display panel 110, and the second direction D2 may be the vertical direction of the display panel 110. The third direction D3 may be the thickness direction of the display panel 110.

[0047] In one embodiment, the display panel 110 may have a rectangular shape in a plan view. Although Figure 1 and Figure 2 A display panel 110 is shown having a horizontal length longer than its vertical length, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the vertical length is longer than the horizontal length, or it may have a square shape or something similar. The display panel 110 may include angled corners or rounded corners.

[0048] The planar shape of the display panel 110 is not limited to the quadrilateral shape shown, and it can be applied in other shapes. For example, the display panel 110 can have a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or another shape in the planar view.

[0049] In one embodiment, the display panel 110 may be substantially flat on a plane defined by a first direction D1 and a second direction D2, and may have a uniform thickness in a third direction D3. Alternatively, the display panel 110 may be provided in a three-dimensional shape having a curved surface or such.

[0050] The display panel 110 can be provided as a rigid panel so as to be substantially non-deformable, or as a flexible panel that can be deformed to at least partially fold, bend, or roll. The display panel 110 can be provided to the display device 100 without bending, or can be provided to the display device 100 while being partially bent.

[0051] The display panel 110 may include a substrate SUB and pixels PX disposed on the substrate SUB. The pixels PX may be disposed on the substrate SUB in the display area DA.

[0052] The substrate SUB, which serves as a base component for manufacturing or providing the display panel 110, can form the base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA.

[0053] The display area DA can have various shapes depending on the implementation method. For example, the display area DA can have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes. In one implementation, the display area DA can have a shape that conforms to the shape of the display panel 110.

[0054] Pixels PX can be set and / or arranged in the display area DA. For example, the display area DA may include multiple pixel areas where pixels PX are arranged.

[0055] In one embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element located in each emission region and a pixel circuit connected to the light-emitting element. In the described embodiments, the term "connection" may include electrical connection and / or physical connection. Furthermore, unless otherwise specified as "direct connection" or "indirect connection," the term "connection" may include both direct and indirect connections. Each pixel circuit may include a transistor (e.g., a transistor including a drive transistor that generates a drive current corresponding to a data signal and at least one switching transistor) and at least one capacitor (e.g., a capacitor including a storage capacitor).

[0056] The non-display area NDA may include a pad area PA with pads PD. In one embodiment, the non-display area NDA may also include a drive circuit area located on at least one side of the display area DA. At least one driver, pad PD, and / or wiring may be provided in the non-display area NDA.

[0057] At least one driver, or a portion thereof, for driving pixel PX may be disposed in the driving circuit region. For example, circuit elements constituting the first driver 120 (e.g., driving transistors and driving capacitors constituting the stage circuitry of the first driver 120) may be disposed on the substrate SUB in the driving circuit region. In one embodiment, the circuit elements of the first driver 120 may be formed together with the pixel PX in the display panel 110. In one embodiment, the driving transistor disposed in the first driver 120 may be a transistor having a type and / or structure substantially the same as or similar to that of the transistor disposed in the pixel PX, and may be formed simultaneously with the transistor of the pixel PX.

[0058] Pads (PDs) can be disposed within pad areas (PAs). At least one circuit board (PCB) 140 can be disposed and / or integrated within the pad area (PA). In one embodiment, multiple PCBs 140 connected to different pads (PDs) can be disposed within the pad area (PA). Pads (PDs) can include signal pads and power pads for transmitting drive signals and power voltages required by the driving pixels (PX) and / or the first driver (120) to the display panel (110).

[0059] The first driver 120 and the second driver 130 can generate drive signals for controlling the operating timing, brightness, etc., of the pixel PX, and can supply the generated drive signals to the pixel PX. For example, the first driver 120 can be a gate driver including a scan driver, and can be connected to the pixel PX via a corresponding gate line. The first driver 120 can supply gate signals (e.g., control signals for controlling the driving timing of the pixel PX, including scan signals and / or transmit control signals) to the pixel PX. The second driver 130 can be a data driver including a source drive circuit, and can be connected to the pixel PX via a corresponding data line. The second driver 130 can supply corresponding data signals to the pixel PX.

[0060] In one embodiment, at least one of the first drivers 120 and the second driver 130, or a portion thereof, may be embedded in the display panel 110. For example, the first driver 120 or a portion thereof may be disposed and / or formed in the non-display area NDA and disposed on the substrate SUB of the display panel 110.

[0061] although Figure 1 The illustration shows a first driver 120 formed on one side of the display area DA (e.g., on the right side of the display area DA in the non-display area NDA), but the implementation is not limited to this. For example, the first driver 120 may be located only on the other side of the display area DA (e.g., on the left side of the display area DA in the non-display area NDA), or it may be located on both sides of the display area DA (e.g., on the left and right sides of the display area DA in the non-display area NDA). Optionally, a portion of the first driver 120 may be located in the non-display area NDA, and another portion of the first driver 120 may be located in a non-emitting area of ​​the display area DA (e.g., the area between the emitting areas of pixels PX).

[0062] In one embodiment, another driver, or a portion of the other driver, of the first driver 120 and the second driver 130 may be disposed or formed outside the display panel 110 for electrical connection to the display panel 110. For example, the second driver 130 may be implemented as multiple integrated circuit chips and may be disposed on a circuit board 140 electrically connected to the pixels PX of the display panel 110. The second driver 130 may be implemented as at least one integrated circuit chip and mounted on the display panel 110 in the non-display area NDA.

[0063] Circuit board 140 can be connected to display panel 110 via pad PD. In one embodiment, circuit board 140 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but is not limited thereto. In one embodiment, circuit board 140 may be connected to a timing controller and / or power supply unit via another circuit board, connector, or the like.

[0064] Figure 3 This is an equivalent circuit diagram illustrating a pixel PX according to one embodiment. For example, Figure 3 The image shows a pixel PX of a light-emitting display device including a light-emitting element (ED). Besides... Figure 3 In addition to the implementation method, the type and / or structure of the pixels PX that may be included in the display device 100 may be changed based on the implementation method.

[0065] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 A pixel PX may include a light-emitting element (ED) and pixel circuitry PC connected to (e.g., electrically connected to) the ED. The ED is the light source of the pixel PX, and it may be, for example, an organic light-emitting diode (OLED), but is not limited thereto. The pixel circuitry PC can control the emission timing and brightness of the ED.

[0066] The pixel circuit PC may include a transistor T and at least one capacitor C. For example, the pixel circuit PC may include first transistors T1 to fifth transistors T5 and a first capacitor C1 and a second capacitor C2. Although Figure 3 The embodiments shown all involve N-type transistors T, but the type of transistor T is not limited to this. For example, at least one transistor T can be formed from a P-type transistor.

[0067] The pixel circuit PC can supply a drive current Id to the light-emitting element ED in response to a drive signal supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC can supply a drive current Id to the light-emitting element ED in response to a corresponding gate signal GS supplied from the first driver 120 via a corresponding gate line GL and a data signal DATA supplied from the second driver 130 via a data line DL.

[0068] The first transistor T1 can be a driving transistor for the pixel PX, and the magnitude of its drain-source current (e.g., driving current Id) is determined based on the gate-source voltage. The second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5 can be switching transistors that are turned on or off based on their respective gate-source voltages. Based on the type (e.g., P-type or N-type) and / or operating conditions of each of the first to fifth transistors T5, the first electrode of each of the first to fifth transistors T1 can be a drain electrode (or drain region) or a source electrode (or source region), and their second electrodes can be electrodes different from the first electrodes. For example, when the first electrode is a drain electrode, the second electrode can be a source electrode.

[0069] Pixel PX can be connected to a first gate line GWL for transmitting a first gate signal GW (e.g., a scan signal), a second gate line GIL for transmitting a second gate signal GIN, a third gate line GRL for transmitting a third gate signal GR, an transmit control line ECL for transmitting a transmit control signal EM, and a data line DL for transmitting a data signal DATA. Furthermore, pixel PX can be connected to a first power line VDL for transmitting a first pixel voltage ELVDD (also referred to as the "first pixel power voltage") and a second power line VSL for transmitting a second pixel voltage ELVSS (also referred to as the "second pixel power voltage"). In one embodiment, pixel PX can also be connected to an initialization power line VIL for transmitting an initialization voltage VINT (also referred to as the "third pixel power voltage") and a reference power line VRL for transmitting a reference voltage VREF (also referred to as the "fourth pixel power voltage").

[0070] In one implementation, first transistors T1 through fifth transistors T5 may be located in each pixel region and may be oxide transistors (also referred to as "oxide semiconductor transistors") comprising oxide semiconductors (e.g., oxide semiconductor materials). For example, the active layer of each of the first transistors T1 through fifth transistors T5 may include oxide semiconductors. However, the implementation is not limited to this. For example, at least one transistor T may be formed of a semiconductor material other than oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0071] Oxide semiconductors can exhibit high carrier mobility and low leakage current, resulting in minimal voltage drop even with increased driving time of oxide transistors. For example, a pixel PX incorporating oxide transistors can be driven at low frequencies because changes in image brightness and / or color due to voltage drop are insignificant even when driving the image at low frequencies. When the first transistor T1 through the fifth transistor T5 are formed from oxide transistors, leakage current in the pixel PX can be reduced or prevented, thus reducing power consumption.

[0072] Oxide semiconductors are photosensitive, causing the current or similar parameters to change due to external light. In one embodiment, a light-blocking pattern or light-blocking electrode (e.g., a bottom electrode or a back gate electrode) can be disposed beneath the active layer included in at least one transistor T to block external light. This allows for the stabilization of the operating characteristics of the transistor T.

[0073] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode (e.g., a drain electrode) connected to a second node N2, and a second electrode (e.g., a source electrode) connected to a third node N3. The first electrode of the first transistor T1 may be connected to a first power line VDL via a fifth transistor T5, and its second electrode may be connected to a light-emitting element ED. The first transistor T1 may control the magnitude (e.g., current quantity) of the drive current Id flowing to the light-emitting element ED in response to a data signal DATA transmitted to the first node N1.

[0074] In one embodiment, the first transistor T1 may further include a bottom electrode BE (e.g., the bottom gate electrode or back gate electrode of the first transistor T1) connected to the third node N3. When the first transistor T1 is formed by connecting the bottom electrode BE of the first transistor T1 to the third node N3, such that the first transistor T1 is formed by a transistor with a dual-gate structure (e.g., a dual-gate transistor with a source synchronization structure), the operating characteristics of the first transistor T1 can be improved.

[0075] The second transistor T2 may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The second transistor T2 may be turned on by a first gate signal GW (e.g., a first gate signal GW representing a gate on-state voltage) transmitted to the first gate line GWL to connect the data line DL and the first node N1. Therefore, the data signal DATA transmitted via the data line DL can be sent to the first node N1.

[0076] The third transistor T3 may include a gate electrode connected to a third gate line GRL, a first electrode connected to a reference power line VRL, and a second electrode connected to a first node N1. The third transistor T3 may be turned on by a third gate signal GR transmitted through the third gate line GRL, and transmit a reference voltage VREF transmitted to the reference power line VRL to the first node N1.

[0077] The fourth transistor T4 may include a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3, and a second electrode connected to the initialization power line VIL. The fourth transistor T4 may be turned on by a second gate signal GIN transmitted through the second gate line GIL, and transmit the initialization voltage VINT transmitted to the initialization power line VIL to the third node N3.

[0078] The fifth transistor T5 may include a gate electrode connected to the emitt control line ECL, a first electrode connected to the first power line VDL, and a second electrode connected to the second node N2 (or the first electrode of the first transistor T1). The fifth transistor T5 may be turned on by an emitt control signal EM (e.g., an emitt control signal EM of the gate on-state voltage) transmitted to the emitt control line ECL to control the emitt timing of the pixel PX.

[0079] Each of the second transistor T2 through the fifth transistor T5 may or may not include a bottom electrode. In one embodiment, at least one of the second transistors T2 through the fifth transistor T5 may include a bottom electrode, and the bottom electrode of at least one switching transistor may be connected to the gate electrode of the respective switching transistor. When the bottom electrode of the switching transistor is connected to the gate electrode, the turn-off characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be ensured, leakage current can be reduced, and voltage stability can be improved. For example, since the switching transistor formed of an oxide transistor with a short channel length is formed in a dual-gate structure such as a gate synchronization structure or such a structure, the operating characteristics of the switching transistor can be improved.

[0080] The first capacitor C1 can be connected between the first node N1 and the third node N3. The first capacitor C1 is the storage capacitor of the pixel PX, and can store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal DATA (e.g., data voltage) therein.

[0081] The second capacitor C2 can be connected between the first power line VDL and the third node N3. In one embodiment, the capacitance of the second capacitor C2 can be smaller than the capacitance of the first capacitor C1.

[0082] The light-emitting element (ED) can be connected between the third node N3 and the second electric field line VSL. For example, the ED may include a first electrode (e.g., a positive electrode) connected to the third node N3, a second electrode (e.g., a negative electrode) facing away from the first electrode and connected to the second electric field line VSL, and a light-emitting layer disposed between the first and second electrodes. In one embodiment, the first electrode of the ED may be a separate electrode individually disposed in each pixel PX, and the second electrode of the ED may be a common electrode shared by multiple pixels PX. During the period when a drive current Id is supplied from the pixel circuit PC, the ED can emit light with a brightness corresponding to the drive current Id.

[0083] Figure 4 This is a cross-sectional view showing a display panel 110 according to one embodiment. For example, Figure 4 A portion of the display area DA of the display panel 110 is shown. Figure 4 An example of a display panel 110, which includes a light-emitting element ED (e.g., an organic light-emitting diode), is shown as an example of a display panel 110 to which embodiments can be applied.

[0084] Apart from Figures 1 to 3 In addition, refer to Figure 4 The display panel 110 may include a substrate SUB (also referred to as a "base layer"), a panel circuit layer PCL, a light-emitting element layer LEL, and a packaging layer ENL. The panel circuit layer PCL, the light-emitting element layer LEL, and the packaging layer ENL may be arranged to overlap each other on the substrate SUB. For example, relative to the display area DA, the panel circuit layer PCL, the light-emitting element layer LEL, and the packaging layer ENL may be sequentially disposed on the substrate SUB along a third direction D3. However, the implementation is not limited to this, and the positions of the panel circuit layer PCL, the light-emitting element layer LEL, and / or the packaging layer ENL may be changed.

[0085] In one embodiment, the display panel 110 may further include additional elements disposed above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, optical layer, and passivation layer may be disposed above the encapsulation layer ENL, or may be disposed between the light-emitting element layer LEL and the encapsulation layer ENL.

[0086] The substrate SUB, serving as the base component for forming the display panel 110, can be a rigid or flexible substrate (or film). In one embodiment, the substrate SUB can be a rigid substrate comprising an insulating material such as glass or the like, and can be non-bent. Alternatively, the substrate SUB can be a flexible substrate comprising polyimide or another insulating material and can be deformed to bend, fold, or roll, and can be bent or not bent. The type and / or material of the substrate SUB can be varied based on the implementation.

[0087] In one embodiment, the display panel 110 may also optionally include a barrier layer (e.g., an inorganic insulating layer capable of blocking moisture penetration) disposed between the substrate SUB and the panel circuit layer PCL. For example, the barrier layer may be disposed on the substrate SUB and the panel circuit layer PCL may be disposed on the barrier layer, or the panel circuit layer PCL may be disposed directly on the substrate SUB without a barrier layer.

[0088] The panel circuit layer PCL may include circuit elements and wiring (e.g., signal lines and power lines) that include transistors T and capacitors C containing pixels PX. In one embodiment, the panel circuit layer PCL may also include circuit elements of the first driver 120 (e.g., driving transistors and / or driving capacitors included in the first driver 120) and / or additional conductive patterns (e.g., bridging patterns).

[0089] Figure 4 An example is shown of a transistor T and a capacitor C disposed in any pixel region PXA as circuit elements that can be disposed in the panel circuit layer PCL (e.g., circuit elements that can be included in the panel circuit layer PCL). Figure 4 The transistor T can be a driving transistor or a switching transistor disposed in the pixel circuit PC of the corresponding pixel PX (e.g., included in the pixel circuit PC of the corresponding pixel PX). For example, Figure 4 The transistor T can be Figure 3 The first transistor T1. Figure 4 The capacitor C can be any capacitor C disposed in the pixel circuit PC of the corresponding pixel PX (e.g., included in the pixel circuit PC of the corresponding pixel PX). For example, Figure 4 The capacitor C can be Figure 3 The first capacitor C1. In the described embodiment, when an element is referred to as being "set in" another element, this can mean that the element is included in or set inside the other element.

[0090] The panel circuit layer (PCL) may include a conductive layer containing circuit elements, wiring, etc., and a semiconductor layer (SCL). Electrodes of the circuit elements (e.g., transistor T and capacitor C) constituting the PCL and conductive patterns (e.g., bridging electrodes BRE and / or wiring) connected to these electrodes and / or wiring may be disposed in the conductive layer. The active layer (ACT) of the transistor T disposed in the PCL may be disposed in the semiconductor layer (SCL).

[0091] In one embodiment, the panel circuit layer PCL may include a first conductive layer CDL1 (also referred to as a "first lower conductive layer" or "first bottom conductive layer"), a second conductive layer CDL2 (also referred to as a "second lower conductive layer" or "second bottom conductive layer"), a semiconductor layer SCL, a third conductive layer CDL3 (also referred to as a "gate conductive layer"), and a fourth conductive layer CDL4 (also referred to as a "first source / drain conductive layer" or "first data conductive layer") disposed sequentially on the substrate SUB along the third direction D3. In one embodiment, the panel circuit layer PCL may further include a fifth conductive layer CDL5 (also referred to as a "second source / drain conductive layer" or "second data conductive layer") disposed on the fourth conductive layer CDL4.

[0092] The electrodes, conductive patterns, and / or wiring disposed in the conductive layer of the panel circuit layer PCL (e.g., included in the conductive layer) may include at least one conductive material. For example, the electrodes, conductive patterns, and / or wiring disposed in each of the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, their alloys, or other conductive materials. In one embodiment, the electrodes, conductive patterns, and / or wiring disposed on the same conductive layer may be formed simultaneously using the same conductive material.

[0093] In one embodiment, the electrodes, conductive patterns, and / or wiring disposed in the conductive layers of the panel circuit layer PCL can have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns, and / or wiring disposed in the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 can have a single-layer or multi-layer structure.

[0094] The panel circuit layer PCL may also include multiple insulating layers and / or insulating patterns disposed on the substrate SUB. For example, the panel circuit layer PCL may include a first insulating layer INS1, a second insulating layer INS2, a gate insulating layer GI, a third insulating layer INS3, a fourth insulating layer INS4, and a fifth insulating layer INS5 disposed sequentially on the substrate SUB along the third direction D3.

[0095] The first insulating layer INS1 may be disposed between the first conductive layer CDL1 and the second conductive layer CDL2, and may cover the first conductive layer CDL1. For example, the first insulating layer INS1 may be disposed on the substrate SUB, and may cover the pattern of the first conductive layer CDL1, such as electrodes, wiring and / or conductive patterns disposed in the first conductive layer CDL1.

[0096] The second insulating layer INS2 can be disposed between the second conductive layer CDL2 and the semiconductor layer SCL, and can cover the second conductive layer CDL2. For example, the second insulating layer INS2 can be disposed on the first insulating layer INS1, and can cover the pattern of the second conductive layer CDL2, such as electrodes, wiring and / or conductive patterns disposed in the second conductive layer CDL2.

[0097] The gate insulating layer GI can be disposed on the second insulating layer INS2 and the semiconductor layer SCL. For example, the gate insulating layer GI can be disposed between the second insulating layer INS2, the semiconductor layer SCL and the third conductive layer CDL3. The gate insulating layer GI can cover at least a portion of the second insulating layer INS2 and at least a portion of the semiconductor layer SCL.

[0098] The third insulating layer INS3 may be disposed on the second insulating layer INS2. For example, the third insulating layer INS3 may be disposed between the third conductive layer CDL3 and the fourth conductive layer CDL4. The third insulating layer INS3 may cover the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3. For example, the third insulating layer INS3 may cover the patterns of the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3, such as the active layer ACT disposed in the semiconductor layer SCL, the insulating patterns disposed in the gate insulating layer GI (e.g., the first gate insulating layer GI1 and the second gate insulating layer GI2 that are integral or separate from each other), and the electrodes, wiring, and / or conductive patterns disposed in the third conductive layer CDL3.

[0099] The fourth insulating layer INS4 can be disposed between the fourth conductive layer CDL4 and the fifth conductive layer CDL5, and can cover the fourth conductive layer CDL4. For example, the fourth insulating layer INS4 can be disposed on the third insulating layer INS3, and can cover the pattern of the fourth conductive layer CDL4, such as electrodes, wiring and / or conductive patterns disposed in the fourth conductive layer CDL4.

[0100] In one embodiment, the fourth insulating layer INS4 may have a multilayer structure including an inorganic insulating layer and an organic insulating layer. For example, the fourth insulating layer INS4 may include a first inorganic layer IOL1 and a first organic layer ORL1 sequentially disposed on the third insulating layer INS3.

[0101] The fifth insulating layer INS5 can be disposed between the fifth conductive layer CDL5 and the light-emitting element layer LEL, and can cover the fifth conductive layer CDL5. For example, the fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4, and can cover the pattern of the fifth conductive layer CDL5, such as electrodes, wiring and / or conductive patterns disposed in the fifth conductive layer CDL5.

[0102] In one embodiment, the fifth insulating layer INS5 may have a multilayer structure including an inorganic insulating layer and an organic insulating layer. For example, the fifth insulating layer INS5 may include a second inorganic layer IOL2 and a second organic layer ORL2 sequentially disposed on the fourth insulating layer INS4.

[0103] In one embodiment, each of the first insulating layer INS1, the second insulating layer INS2, the gate insulating layer GI, the third insulating layer INS3, the first inorganic layer IOL1, and the second inorganic layer IOL2 may include at least one inorganic insulating layer comprising an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). For example, each of the first insulating layer INS1, the second insulating layer INS2, the gate insulating layer GI, the third insulating layer INS3, the first inorganic layer IOL1, and the second inorganic layer IOL2 may be a single layer or multiple layers of inorganic insulating layers.

[0104] In one embodiment, each of the first organic layer ORL1 and the second organic layer ORL2 may include at least one organic insulating layer comprising an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or another organic insulating material). The surfaces (e.g., top surfaces) of the first organic layer ORL1 and the second organic layer ORL2 may be substantially flat.

[0105] In one embodiment, at least one insulating layer included in the panel circuit layer PCL can be integrally disposed in the display area DA. For example, the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, the fourth insulating layer INS4, and the fifth insulating layer INS5 can be integrally disposed in the display area DA.

[0106] In one embodiment, the gate insulating layer GI may be partially disposed in the portion of each pixel region PXA and the display region DA that includes the pixel region PXA. In one embodiment, the gate insulating layer GI may include a first gate insulating layer GI1 (also referred to as a "first gate insulating pattern") disposed on a portion of each active layer ACT disposed in the semiconductor layer SCL and a second gate insulating layer GI2 (also referred to as a "second gate insulating pattern") disposed on a second insulating layer INS2 without overlapping with the active layer ACT. For example, the first gate insulating layer GI1 may be disposed between the portion of the active layer ACT that includes the channel region CH and the gate electrode GE, and the second gate insulating layer GI2 may be disposed between the second insulating layer INS2 and the third electrode E3 of the capacitor C disposed in the third conductive layer CDL3. The first gate insulating layer GI1 and the second gate insulating layer GI2 may be connected to each other to form an integrated insulating pattern, or they may be separate insulating patterns that are separated from each other in a planar view. However, the embodiments are not limited to this. For example, the gate insulating layer GI may be disposed integrally in the display region DA to integrally cover the second insulating layer INS2 and the semiconductor layer SCL.

[0107] Transistor T may include an active layer ACT (also referred to as an "active pattern" or "semiconductor pattern") and a gate electrode GE (e.g., a top gate electrode) disposed on a portion of the active layer ACT. In one embodiment, transistor T may also include at least one of a source electrode SE and a drain electrode DE. For example, transistor T may also include a source electrode SE connected to a source region SR of the active layer ACT and a drain electrode DE connected to a drain region DR of the active layer ACT. Optionally, transistor T may not include separate source electrodes and / or separate drain electrodes, and the source region SR and / or drain region DR of the active layer ACT may be connected to another circuit element, wiring, and / or conductive pattern to serve as the source electrode and / or drain electrode of transistor T.

[0108] In one embodiment, the transistor T may further include a bottom electrode BE (e.g., a bottom gate electrode) disposed beneath the active layer ACT. In one embodiment, the bottom electrode BE may be connected to an electrode of the transistor T and may be used as a back gate electrode for adjusting the characteristics of the transistor T. Since the bottom electrode BE is disposed beneath the active layer ACT, it can block external light from incident on the channel region CH of the active layer ACT and stabilize the operating characteristics of the transistor T.

[0109] In one implementation, transistor T can be an N-type transistor. For example, transistor T can be an N-type oxide transistor.

[0110] The bottom electrode BE can be disposed within the second conductive layer CDL2. For example, the second conductive layer CDL2 includes the bottom electrode BE and may optionally include additional conductive patterns. The second conductive layer CDL2 can be disposed between the first insulating layer INS1 and the second insulating layer INS2. The bottom electrode BE can overlap with the active layer ACT and the gate electrode GE. For example, the bottom electrode BE can be disposed below the active layer ACT to overlap at least a portion of the active layer ACT including the channel region CH, and can face the gate electrode GE with the active layer ACT interposed therebetween.

[0111] In one embodiment, the bottom electrode BE can be connected to the source electrode SE or the gate electrode GE of the transistor T. For example, the transistor T can be a driving transistor of the pixel PX, and the bottom electrode BE of the transistor T can be connected to the source electrode SE of the transistor T through a seventh contact hole CNT7 that penetrates the second insulating layer INS2 and the third insulating layer INS3. Alternatively, the transistor T can be a switching transistor of the pixel PX, and the bottom electrode BE of the transistor T can be connected to the gate electrode GE of the transistor T.

[0112] An active layer ACT can be disposed within a semiconductor layer SCL. For example, the semiconductor layer SCL includes the active layer ACT and may optionally include additional semiconductor patterns. The semiconductor layer SCL can be disposed on a second insulating layer INS2 that covers the second conductive layer CDL2, and can be covered by a gate insulating layer GI and a third insulating layer INS3.

[0113] The active layer ACT may include a channel region CH, with source regions SR and drain regions DR spaced apart from each other and the channel region CH interposed therebetween. For example, the source region SR and drain region DR may be located on opposite sides of the channel region CH. The channel region CH may be a region that retains semiconductor properties and does not become conductive. The source region SR and drain region DR, which are already conductive regions, may have a higher carrier concentration (e.g., electron concentration) than the channel region CH.

[0114] The active layer ACT can overlap with the bottom electrode BE and the gate electrode GE. For example, the portion of the active layer ACT that includes the channel region CH can overlap with the bottom electrode BE and the gate electrode GE.

[0115] In one embodiment, the active layer ACT may include an oxide semiconductor. For example, the active layer ACT may include an oxide semiconductor or other oxide semiconductor comprising at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf). In one embodiment, the active layer ACT may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO) or other oxide semiconductors.

[0116] In one implementation, the active layer ACT can be made of a high-mobility oxide semiconductor (e.g., having a 20cm² radius). 2 / Vs or 30cm 2 The active layer ACT can be formed from an oxide semiconductor material with a mobility of / Vs or higher. For example, the active layer ACT can be formed from indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO), and can have a 20cm² thickness. 2 / Vs or higher mobility. When the active layer ACT is formed of a high-mobility oxide semiconductor, the conductivity of the source region SR and drain region DR can be properly and / or easily ensured without performing additional doping processes. Furthermore, when the active layer ACT is formed of a high-mobility oxide semiconductor, it is possible to form transistors T with fine dimensions (e.g., including dimensions of the active layer ACT with width and / or length in the range of several micrometers to tens of micrometers), and to properly ensure the mobility of the transistor T.

[0117] A first gate insulating layer GI1 may be disposed on the active layer ACT. In one embodiment, the first gate insulating layer GI1 may be disposed only on a portion of the active layer ACT, and may not be disposed on another portion of the active layer ACT. For example, the first gate insulating layer GI1 may be disposed on the portion of the active layer ACT that includes the channel region CH, and may expose the source region SR and drain region DR of the active layer ACT.

[0118] Since the first gate insulating layer GI1 exposes the source region SR and the drain region DR, the source region SR and the drain region DR can become suitably and / or readily conductive during the manufacturing process of the display panel 110. For example, in the step of etching the gate insulating layer GI to expose at least a portion of the source region SR and at least a portion of the drain region DR, oxygen vacancies can appear in the source region SR and the drain region DR by means of an etching gas or the like. Therefore, without performing a separate doping process, the source region SR and the drain region DR can become suitably conductive in a subsequent process (e.g., the process of forming the third insulating layer INS3).

[0119] In one embodiment, to limit the carrier concentration of the source region SR and drain region DR and / or the mobility of the active layer ACT to an appropriate range, an oxygen-supplying layer may be formed between the first gate insulating layer GI1 and the gate electrode GE. For example, the transistor T may also include an oxygen-supplying layer disposed between the first gate insulating layer GI1 and the gate electrode GE and comprising an oxide semiconductor. The active layer ACT and the oxygen-supplying layer of the transistor T may comprise the same oxide semiconductor or different oxide semiconductors.

[0120] The gate electrode GE can be disposed on the first gate insulating layer GI1. The gate electrode GE can also be disposed in the third conductive layer CDL3. For example, the third conductive layer CDL3 includes the gate electrode GE and may optionally include additional conductive patterns. The third conductive layer CDL3 can be disposed on the second insulating layer INS2 and the gate insulating layer GI, and can be covered by the third insulating layer INS3.

[0121] The gate electrode GE can be disposed on the active layer ACT to overlap with the channel region CH. The gate electrode GE and the active layer ACT can be separated from each other and / or spaced apart, with the first gate insulating layer GI1 interposed therebetween.

[0122] The third insulating layer INS3 can be disposed on the gate electrode GE. The third insulating layer INS3 can cover the active layer ACT, the gate insulating layer GI, and the gate electrode GE.

[0123] The source electrode SE and drain electrode DE can be disposed on the third insulating layer INS3. The source electrode SE and drain electrode DE can also be disposed in the fourth conductive layer CDL4. For example, the fourth conductive layer CDL4 includes the source electrode SE and drain electrode DE, and may optionally include additional conductive patterns. The fourth conductive layer CDL4 can be disposed between the third insulating layer INS3 and the fourth insulating layer INS4.

[0124] The source electrode SE can be connected to a portion of the active layer ACT. For example, the source electrode SE can be connected to the source region SR of the active layer ACT through a fifth contact hole CNT5 penetrating the third insulating layer INS3. In one embodiment, the source electrode SE can also be connected to the bottom electrode BE through a seventh contact hole CNT7 penetrating the second insulating layer INS2 and the third insulating layer INS3.

[0125] The drain electrode DE can be connected to another part of the active layer ACT. For example, the drain electrode DE can be connected to the drain region DR of the active layer ACT through the sixth contact hole CNT6 that penetrates the third insulating layer INS3.

[0126] In one embodiment, at least one transistor T disposed in each pixel region PXA can be connected to a bridging electrode BRE disposed on a fourth insulating layer INS4 covering the fourth conductive layer CDL4, and can be connected to the light-emitting element ED of the corresponding pixel PX through the bridging electrode BRE. For example, the source electrode SE (or drain electrode DE) of the first transistor T1 disposed in each pixel region PXA can be connected to the bridging electrode BRE on the fourth insulating layer INS4 through an eighth contact hole CNT8 penetrating the fourth insulating layer INS4.

[0127] The bridging electrode BRE can be disposed in the fifth conductive layer CDL5. For example, the fifth conductive layer CDL5 includes the bridging electrode BRE and may optionally include additional conductive patterns. The fifth conductive layer CDL5 can be disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5. For example, the fifth conductive layer CDL5 can be disposed on the fourth insulating layer INS4 and covered by the fifth insulating layer INS5. The bridging electrode BRE can be connected to the first electrode ET1 of the light-emitting element ED disposed in the light-emitting element layer LEL through the ninth contact hole CNT9 penetrating the fifth insulating layer INS5.

[0128] The capacitor C may include a first capacitor electrode CE1 and a second capacitor electrode CE2 forming the capacitance. In one embodiment, the capacitor C may have a multilayer structure including multiple electrodes (or sub-electrodes). Therefore, the capacitance of the capacitor C can be ensured by effectively utilizing the area of ​​the pixel region PXA. For example, in a high-resolution display panel 110 with a relatively small pixel region PXA, at least one of the first capacitor electrode CE1 and the second capacitor electrode CE2 is formed by multiple electrodes, thereby appropriately ensuring the capacitance of the capacitor C while reducing the area occupied by the capacitor C.

[0129] In one embodiment, capacitor C may include a first electrode E1 disposed in a first conductive layer CDL1, a second electrode E2 disposed in a second conductive layer CDL2, a third electrode E3 disposed in a third conductive layer CDL3, and a fourth electrode E4 disposed in a fourth conductive layer CDL4. For example, the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, and the fourth conductive layer CDL4 may each include a first electrode E1, a second electrode E2, a third electrode E3, and a fourth electrode E4, respectively. In one embodiment, capacitor C may further include at least one of a fifth electrode E5 disposed in the fourth conductive layer CDL4 and a sixth electrode E6 disposed in the fifth conductive layer CDL5, spaced apart from the fourth electrode E4. For example, the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may each include a fifth electrode E5 and a sixth electrode E6, respectively.

[0130] In one embodiment, the fourth electrode E4 may overlap with the first electrode E1 and can be directly connected to the first electrode E1 through a first contact hole CNT1 that penetrates the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. In another embodiment, the fourth electrode E4 may overlap with the third electrode E3 and can be directly connected to the third electrode E3 through a second contact hole CNT2 that penetrates the third insulating layer INS3. For example, the fourth electrode E4 may be connected to the first electrode E1 and the third electrode E3 individually and / or in parallel through the first contact hole CNT1 and the second contact hole CNT2, respectively. In one embodiment, the first electrode E1 and the third electrode E3 may be connected to each other through the fourth electrode E4, but may not be directly connected to each other. The first electrode E1, the third electrode E3, and the fourth electrode E4 may form the first capacitor electrode CE1 of the capacitor C.

[0131] In one implementation, a portion E1' of the first electrode E1 may overlap with the transistor T. For example, in Figure 4 In this embodiment, the first electrode E1 below the fourth electrode E4 and the first electrode E1' below the active layer ACT (which are connected to form an integrated electrode in the plan view) can be different parts of the integrated electrode. However, the implementation is not limited to this. For example, the first electrode E1 located in the capacitor region and constituting the first capacitor electrode CE1 and another electrode, wiring and / or conductive pattern located in the transistor region and separated from the first electrode E1 can be provided in the first conductive layer CDL1.

[0132] In one embodiment, the third electrode E3 may be connected to the gate electrode GE of the first transistor T1 located in each pixel region PXA. For example, the third electrode E3 may be integrally disposed in the third conductive layer CDL3 with the gate electrode GE of the first transistor T1. For example, the third electrode E3 and the gate electrode GE of the first transistor T1 may be connected to each other in a planar view to form an integrated electrode. In this case, the first gate insulating layer GI1 located under the gate electrode GE of the first transistor T1 and the second gate insulating layer GI2 located under the third electrode E3 may be connected to each other to form an integrated insulating pattern.

[0133] The second electrode E2 may overlap with at least one of the first electrode E1, the third electrode E3, and the fourth electrode E4, and may form a capacitance between itself and the at least one electrode. The second electrode E2 may constitute a second capacitor electrode CE2.

[0134] In one embodiment, the second electrode E2 can be connected to the source electrode SE of the first transistor T1 located in each pixel region PXA. For example, the second electrode E2 can be integrally disposed in the second conductive layer CDL2 with the bottom electrode BE of the first transistor T1, and can be connected to the source electrode SE of the first transistor T1 through the seventh contact hole CNT7.

[0135] The fifth electrode E5 can overlap with the second electrode E2 and can be directly connected to the second electrode E2 through the third contact hole CNT3 that penetrates the second insulating layer INS2 and the third insulating layer INS3. The fifth electrode E5 can form the second capacitor electrode CE2 together with the second electrode E2. The fifth electrode E5 can be integrally formed with the source electrode SE of the first transistor T1 located in each pixel region PXA, or it can be formed separately from the source electrode SE.

[0136] The sixth electrode E6 may overlap with the fifth electrode E5 and may be connected to the fifth electrode E5 via the fourth contact hole CNT4 penetrating the fourth insulating layer INS4 (e.g., directly connected). The sixth electrode E6 may form the second capacitor electrode CE2 together with the second electrode E2 and the fifth electrode E5. The sixth electrode E6 may be integrally formed with the bridging electrode BRE located in each pixel region PXA, or it may be formed separately from the bridging electrode BRE.

[0137] In one embodiment, similar to the first capacitor electrode CE1 and / or the second capacitor electrode CE2, the display panel 110 may include multilayer wiring, which includes sub-wires disposed in at least two conductive layers disposed in the panel circuit layer PCL. For example, at least one wiring disposed in the display panel 110 (e.g., wiring formed in the display panel 110) may have a multilayer structure including at least two sub-wires among a first sub-wire disposed in a first conductive layer CDL1, a second sub-wire disposed in a second conductive layer CDL2, a third sub-wire disposed in a third conductive layer CDL3, a fourth sub-wire disposed in a fourth conductive layer CDL4, and a fifth sub-wire disposed in a fifth conductive layer CDL5. In one embodiment, the multilayer wiring may include at least one of the first, second, third, and fifth sub-wires and a fourth sub-wire. In one embodiment, the fourth sub-wire may be directly connected to the first, second, and / or third sub-wires through at least one contact hole penetrating the third insulating layer INS3, or may be connected to the fifth sub-wire through a contact hole penetrating the fourth insulating layer INS4. In one implementation, the first sub-wire, the second sub-wire, and / or the third sub-wire may not be directly connected to each other.

[0138] The light-emitting element layer (LEL) can be disposed on the panel circuit layer (PCL). For example, the LEL can be disposed on the fifth insulating layer (INS5) and can be located at least in the display area (DA).

[0139] The light-emitting element layer (LEL) may include light-emitting elements (EDs) for each of the pixels (PX). For example, the LEL may include a pixel-defining layer (PDL) (also referred to as a "dam") that separates the emission regions of the pixels (PX) and light-emitting elements (EDs) located in each emission region. In one embodiment, the LEL may also include spacers (SPCs) disposed on a portion of the pixel-defining layer (PDL).

[0140] Each light-emitting element ED may include a first electrode ET1 located in each emission region, a light-emitting layer EML and a second electrode ET2 disposed sequentially on the first electrode ET1. The first electrode ET1 of the light-emitting element ED may be connected to at least one transistor (e.g., a first transistor T1) included in the corresponding pixel PX.

[0141] The first electrode ET1 of the light-emitting element ED can be a single-layer or multi-layer electrode containing at least one conductive material. In one embodiment, the display panel 110 can be a front-emitting display panel, and the first electrode ET1 can include a reflective electrode layer with high reflectivity.

[0142] The emissive layer (EML) of a light-emitting element (ED) can comprise either a polymeric or a low-molecular-weight material. Light emitted from the EML can contribute to image display.

[0143] The second electrode ET2 of the light-emitting element ED may include a conductive material. In one embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA, covering the light-emitting layer EML and the pixel defining layer PDL. In one embodiment, the display panel 110 may be a front-emitting display panel, and the second electrode ET2 may include a transparent or translucent electrode layer.

[0144] The pixel defining layer (PDL) may have an opening corresponding to each emitting region and may surround the emitting region. For example, the pixel defining layer (PDL) may be formed to cover the edge of the first electrode ET1 of the light-emitting element ED and may include an opening exposing the remaining portion of the first electrode ET1. The area where the exposed first electrode ET1 and the light-emitting layer (EML) overlap may be the emitting region of each pixel PX. In one embodiment, the pixel defining layer (PDL) may include at least one organic insulating layer comprising an organic insulating material.

[0145] Spacer SPCs may be disposed on a portion of the pixel defining layer (PDL). The spacer SPC may include at least one organic insulating layer comprising an organic insulating material. The spacer SPC may include the same material as the pixel defining layer (PDL) or may include a different material. The pixel defining layer (PDL) and the spacer SPC may be formed sequentially using appropriate masking processes, or may be formed simultaneously and / or integrally using a halftone mask.

[0146] An encapsulation layer (ENL) can be disposed on the light-emitting element layer (LEL). The encapsulation layer (ENL) can cover the light-emitting element layer (LEL) in the display area (DA) and can extend to the non-display area (NDA) to contact the panel circuit layer (PCL). The encapsulation layer (ENL) can prevent oxygen or moisture from penetrating into the light-emitting element layer (LEL) and can reduce electrical and / or physical impacts on the panel circuit layer (PCL) and the light-emitting element layer (LEL).

[0147] In one embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially disposed on the light-emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer containing inorganic materials. The second encapsulation layer ENL2 may be an organic encapsulation layer containing organic materials.

[0148] Figures 5 to 15 This is a cross-sectional view illustrating a method of manufacturing a display device 100 according to one embodiment. For example, Figures 5 to 15 The manufacturing process is shown in sequence. Figure 4 The process of forming the display panel 110 includes the process of forming a panel circuit layer PCL, which consists of transistors T and capacitors C.

[0149] Apart from Figures 1 to 4 In addition, refer to Figure 5 A substrate SUB can be prepared that includes at least the display area DA. The display area DA may include the pixel area PXA.

[0150] Then, a first conductive layer CDL1 including the first electrode E1 can be formed on the substrate SUB. The pattern of the first conductive layer CDL1 including the first electrode E1 (e.g., an electrode, conductive pattern and / or at least one wiring disposed in the first conductive layer CDL1) can be formed by a film formation process (e.g., a deposition process) using at least one conductive material illustrated above and a patterning process of the conductive film (e.g., an etching process using a mask).

[0151] Subsequently, a first insulating layer INS1 covering the first conductive layer CDL1 can be formed on the substrate SUB. The first insulating layer INS1 can be formed by a film forming process using at least one insulating material (e.g., an inorganic insulating material) illustrated above.

[0152] Apart from Figures 1 to 5 In addition, refer to Figure 6 A second conductive layer CDL2, including a bottom electrode BE and a second electrode E2, can be formed on the first insulating layer INS1. The pattern of the second conductive layer CDL2, including the bottom electrode BE and the second electrode E2 (e.g., electrodes, conductive patterns, and / or at least one wiring disposed in the second conductive layer CDL2), can be formed by a film formation process (e.g., deposition process) using at least one conductive material exemplified above and a patterning process of the conductive film (e.g., etching process using a mask).

[0153] Then, a second insulating layer INS2 covering the second conductive layer CDL2 can be formed on the first insulating layer INS1. The second insulating layer INS2 can be formed by a film forming process using at least one insulating material (e.g., an inorganic insulating material) illustrated above.

[0154] Apart from Figures 1 to 6 In addition, refer to Figure 7 A semiconductor layer SCL, including an active layer ACT, can be formed on the second insulating layer INS2. For example, an active layer ACT can be formed in each transistor region on the second insulating layer INS2.

[0155] The active layer ACT of the transistor T, including the bottom electrode BE, can be formed to overlap with the bottom electrode BE. In one embodiment, the active layer ACT can be formed of an oxide semiconductor. For example, the active layer ACT can be formed by a film formation process and a patterning process (e.g., an etching process using a mask) using at least one of the oxide semiconductors illustrated above.

[0156] Then, a gate insulating layer GI covering the semiconductor layer SCL can be formed on the second insulating layer INS2. The gate insulating layer GI can first be integrally formed on the substrate SUB, including the display area DA, etc. The gate insulating layer GI can be formed by a film formation process using an insulating layer of at least one insulating material (e.g., an inorganic insulating material such as silicon oxide) illustrated above.

[0157] Apart from Figures 1 to 7 In addition, refer to Figure 8 A conductive film GCDL can be formed on the gate insulating layer GI. This is used to form... Figure 4 The conductive film GCDL of the third conductive layer CDL3 can be integrally formed in the display area DA. For example, the conductive film GCDL can be integrally formed on the gate insulating layer GI. The conductive film GCDL can be formed by a film formation process using at least one of the conductive materials illustrated above.

[0158] Apart from Figures 1 to 8 In addition, refer to Figure 9 The third conductive layer CDL3, including the gate electrode GE and the third electrode E3, can be formed by a patterning process of the conductive film GCDL. For example, the pattern of the third conductive layer CDL3, including the gate electrode GE and the third electrode E3, can be formed by an etching process using a mask (e.g., an electrode, conductive pattern, and / or at least one wiring disposed in the third conductive layer CDL3).

[0159] In one embodiment, a patterning process for the gate insulating layer GI can also be performed to form a pattern for the gate insulating layer GI (e.g., an insulating pattern including a first gate insulating layer GI1 and a second gate insulating layer GI2). In one embodiment, the gate insulating layer GI can be etched using a mask used in the etching process of the third conductive layer CDL3, or by using the third conductive layer CDL3 as a mask. For example, a mask having a shape corresponding to the shape of the third conductive layer CDL3 can be provided on the conductive film GCDL, and the conductive film GCDL and the gate insulating layer GI can be etched sequentially and / or continuously using the mask. Therefore, the gate insulating layer GI can be patterned in a shape corresponding to the shape of the third conductive layer CDL3. For example, the first gate insulating layer GI1 and the gate electrode GE can be formed on a portion of the active layer ACT, and the second gate insulating layer GI2 and the third electrode E3 can be formed on the portion of the second insulating layer INS2 where the active layer ACT is not provided.

[0160] In the process of etching the gate insulating layer GI, the properties of the active layer ACT can be altered, resulting in different characteristics in different parts of the active layer ACT. Therefore, the active layer ACT can be divided into multiple regions with different characteristics.

[0161] For example, oxygen vacancies can appear in the oxide semiconductor forming the active layer ACT primarily in the portions that do not overlap with the gate electrode GE and the first gate insulating layer GI1, due to etching gases or the like. Therefore, the active layer ACT can be divided into multiple regions with different characteristics (e.g., channel region CH, source region SR, and drain region DR). In one embodiment, oxygen vacancies may primarily occur in the portions of the active layer ACT that do not overlap with the gate electrode GE and the first gate insulating layer GI1 (e.g., source region SR and drain region DR), and may extend to portions that overlap with the gate electrode GE and / or the first gate insulating layer GI1.

[0162] Apart from Figures 1 to 9 In addition, refer to Figure 10 A third insulating layer INS3, covering the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3, can be formed on the second insulating layer INS2. For example, the third insulating layer INS3 can be formed on the third conductive layer CDL3 to cover the active layer ACT, the first gate insulating layer GI1, the second gate insulating layer GI2, the gate electrode GE, and the third electrode E3. The third insulating layer INS3 can be formed by a film formation process using at least one insulating material (e.g., an inorganic insulating material) exemplified above.

[0163] Hydrogen gas can flow into the active layer ACT during the process of forming the third insulating layer INS3 and / or the heat treatment processes before and after this process. Because of the hydrogen flow into the active layer ACT, a portion of the active layer ACT can become conductive primarily in areas containing a large number of oxygen vacancies (e.g., N-type conductivity). For example, the source region SR and the drain region DR can become conductive.

[0164] Apart from Figures 1 to 10 In addition to referencing Figure 11 Multiple contact holes, including the first contact hole CNT1, can be formed in at least the third insulating layer INS3. For example, the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fifth contact hole CNT5, the sixth contact hole CNT6, and the seventh contact hole CNT7 can be formed using an etching process with a mask. The first contact hole CNT1 can be formed to penetrate the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3, and can expose a portion of the first electrode E1. The second contact hole CNT2 can be formed to penetrate the third insulating layer INS3, and can expose a portion of the third electrode E3. The third contact hole CNT3 can be formed to penetrate the second insulating layer INS2 and the third insulating layer INS3, and can expose a portion of the second electrode E2. The fifth contact hole CNT5 can be formed to penetrate the third insulating layer INS3, and can expose a portion of the active layer ACT, such as a portion of the source region SR. The sixth contact hole CNT6 can be formed to penetrate the third insulating layer INS3, and can expose another portion of the active layer ACT, such as a portion of the drain region DR. The seventh contact hole CNT7 can be formed to penetrate the second insulating layer INS2 and the third insulating layer INS3, and can expose a portion of the bottom electrode BE. In one embodiment, the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fifth contact hole CNT5, the sixth contact hole CNT6, and the seventh contact hole CNT7 can be formed substantially simultaneously by a single mask process.

[0165] Apart from Figures 1 to 11 In addition to referencing Figure 12 A fourth conductive layer CDL4, comprising a source electrode SE, a drain electrode DE, a fourth electrode E4, and a fifth electrode E5, can be formed on the third insulating layer INS3. In one embodiment, when at least one of the source region SR and the drain region DR replaces at least one of the source electrode SE and the drain electrode DE, at least one of the source electrode SE and the drain electrode DE may not be formed.

[0166] A pattern of a fourth conductive layer CDL4, including a source electrode SE, a drain electrode DE, a fourth electrode E4, and / or a fifth electrode E5, can be formed by a film formation process (e.g., a deposition process) using at least one conductive material exemplified above and a patterning process of the conductive film (e.g., an etching process using a mask).

[0167] The source electrode SE can be formed to be connected to the source region SR through the fifth contact hole CNT5. In one embodiment, the source electrode SE of the first transistor T1 can be formed to be connected to the bottom electrode BE through the seventh contact hole CNT7. The drain electrode DE can be formed to be connected to the drain region DR through the sixth contact hole CNT6. The fourth electrode E4 can be formed to be connected to the first electrode E1 through the first contact hole CNT1, and can be formed to be connected to the third electrode E3 through the second contact hole CNT2. For example, the fourth electrode E4 can be formed to be directly connected to the first electrode E1 through the first contact hole CNT1 that penetrates the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 at once, and can be formed to be directly connected to the third electrode E3 through the second contact hole CNT2 that penetrates the third insulating layer INS3. The fifth electrode E5 can be formed to be spaced apart from the fourth electrode E4, and can be formed to be connected to the second electrode E2 through the third contact hole CNT3. For example, the fifth electrode E5 can be formed to be directly connected to the second electrode E2 through the third contact hole CNT3 that penetrates the second insulating layer INS2 and the third insulating layer INS3 at once.

[0168] Apart from Figures 1 to 12 In addition, refer to Figure 13 A fourth insulating layer INS4, covering a fourth conductive layer CDL4, can be formed on the third insulating layer INS3. For example, a first inorganic layer IOL1 covering the fourth conductive layer CDL4 and a first organic layer ORL1 covering the first inorganic layer IOL1 can be sequentially formed on the third insulating layer INS3. The first inorganic layer IOL1 can be formed using a film forming process employing at least one of the inorganic insulating materials illustrated above. The first organic layer ORL1 can be formed using a film forming process employing at least one of the organic insulating materials illustrated above.

[0169] Then, multiple contact holes can be formed in the fourth insulating layer INS4. For example, the fourth contact hole CNT4 and the eighth contact hole CNT8 can be formed by an etching process using a mask. The fourth contact hole CNT4 can be formed to penetrate the first inorganic layer IOL1 and the first organic layer ORL1, and can expose a portion of the fifth electrode E5. The eighth contact hole CNT8 can be formed to penetrate the first inorganic layer IOL1 and the first organic layer ORL1, and can expose a portion of the source electrode SE of at least one transistor T (e.g., the first transistor T1) formed in each pixel region PXA. In one embodiment, the fourth contact hole CNT4 and the eighth contact hole CNT8 can be formed substantially simultaneously by a single mask process.

[0170] Apart from Figures 1 to 13 In addition, refer to Figure 14 A fifth conductive layer CDL5, including a bridging electrode BRE and a sixth electrode E6, can be formed on the fourth insulating layer INS4. In one embodiment, when the second capacitor electrode CE2 does not include the sixth electrode E6, the sixth electrode E6 may not be formed.

[0171] The pattern of the fifth conductive layer CDL5, including the bridging electrode BRE and / or the sixth electrode E6 (e.g., the electrode, conductive pattern and / or at least one wiring disposed in the fifth conductive layer CDL5), can be formed by a film forming process (e.g., deposition process) using at least one conductive material exemplified above and a patterning process of the conductive film (e.g., etching process using a mask).

[0172] The bridging electrode BRE can be configured to be connected to the source electrode SE of the first transistor T1 via the eighth contact hole CNT8. The sixth electrode E6 can be configured to be connected to the fifth electrode E5 via the fourth contact hole CNT4.

[0173] Apart from Figures 1 to 14 In addition, refer to Figure 15 A fifth insulating layer INS5, covering a fifth conductive layer CDL5, can be formed on the fourth insulating layer INS4. For example, a second inorganic layer IOL2 covering the fifth conductive layer CDL5 and a second organic layer ORL2 covering the second inorganic layer IOL2 can be sequentially formed on the fourth insulating layer INS4. The second inorganic layer IOL2 can be formed using a film forming process employing at least one of the inorganic insulating materials illustrated above. The second organic layer ORL2 can be formed using a film forming process employing at least one of the organic insulating materials illustrated above.

[0174] Then, multiple contact holes can be formed in the fifth insulating layer INS5. For example, a ninth contact hole CNT9 can be formed in each pixel region PXA by an etching process using a mask. The ninth contact hole CNT9 can be formed to penetrate the second inorganic layer IOL2 and the second organic layer ORL2, and can expose a portion of the bridging electrode BRE.

[0175] Through the above process, the panel circuit layer PCL of the display panel 110 can be formed. In one embodiment, when the panel circuit layer PCL does not include the fifth conductive layer CDL5 and the fifth insulating layer INS5, the steps of forming the fifth conductive layer CDL5 and the fifth insulating layer INS5 can be omitted.

[0176] In one implementation, when as Figure 4 In the embodiment described above, when the display panel 110 includes a light-emitting element layer LEL and an encapsulation layer ENL disposed on the panel circuit layer PCL, the light-emitting element layer LEL and the encapsulation layer ENL can be sequentially formed on the panel circuit layer PCL. Through the above process, the display panel 110 according to the embodiment and the display device 100 including the display panel 110 can be manufactured.

[0177] As described above, according to the display device 100 and the method of manufacturing the display device 100 according to the embodiment, the display panel 110 may include a capacitor C having a multilayer structure, the multilayer structure including a first electrode E1, a second electrode E2, a third electrode E3, and a fourth electrode E4 respectively disposed in a first conductive layer CDL1, a second conductive layer CDL2, a third conductive layer CDL3, and a fourth conductive layer CDL4. Therefore, the capacitance of the capacitor C can be sufficiently and / or appropriately ensured while reducing the area of ​​the capacitor C. Furthermore, by effectively utilizing the limited pixel area PXA, appropriate design space for forming pixels PX and wiring can be ensured.

[0178] In one embodiment, the first conductive layer CDL1 and the second conductive layer CDL2 may be lower conductive layers (e.g., the lower conductive layer of the panel circuit layer PCL) located below the semiconductor layer SCL of the active layer ACT where the transistor T is disposed, and the third conductive layer CDL3 and the fourth conductive layer CDL4 may be upper conductive layers located above the semiconductor layer SCL. In another embodiment, the first electrode E1, the third electrode E3, and the fourth electrode E4 may constitute a multilayer first capacitor electrode CE1, and the first electrode E1 and the third electrode E3 may be individually and / or connected in parallel to the fourth electrode E4 through the first contact hole CNT1 and the second contact hole CNT2, respectively. In one embodiment, the capacitor C may further include a fifth electrode E5 disposed in the fourth conductive layer CDL4, and the fifth electrode E5 may be directly connected to the second electrode E2 and together with the second electrode E2 constitute the second capacitor electrode CE2. In one embodiment, the display panel 110 may further include a fifth conductive layer CDL5 on the fourth conductive layer CDL4, and the second capacitor electrode CE2 may further include a sixth electrode E6 disposed in the fifth conductive layer CDL5 and connected to the fifth electrode E5. In one embodiment, the resistance of the wiring can be reduced by designing multilayer wiring on the panel circuit layer PCL with a structure and / or connection method substantially the same as or similar to that of the first capacitor electrode CE1 and / or the second capacitor electrode CE2. In one embodiment, the active layer ACT of the transistor T disposed in the semiconductor layer SCL can be directly connected to the source electrode SE and / or drain electrode DE disposed in the fourth conductive layer CDL4 through the respective contact holes penetrating the third insulating layer INS3.

[0179] According to the embodiment, the patterns in the conductive layer and semiconductor layer SCL disposed below the fourth conductive layer CDL4 can be individually and / or in parallel connected to the patterns disposed in the fourth conductive layer CDL4. For example, electrodes, conductive patterns, and / or wiring disposed in the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3, and / or the active layer ACT disposed in the semiconductor layer SCL can be individually and / or in parallel connected to the electrodes, conductive patterns, and / or wiring disposed in the fourth conductive layer CDL4. Therefore, the number of mask processes used to manufacture the display panel 110 can be reduced and / or minimized, and the manufacturing process of the display panel 110 can be simplified. Therefore, the manufacturing cost of the display device 100 can be reduced, and the manufacturing efficiency of the display device 100 can be improved.

[0180] Furthermore, in this embodiment, bridging patterns may not be formed on the conductive layer below the fourth conductive layer CDL4 (e.g., the third conductive layer CDL3, etc.). For example, in order to utilize at least one pattern provided in the third conductive layer CDL3 as a bridging pattern, the area may be increased or a separate bridging pattern may not be formed on the third conductive layer CDL3. Therefore, sufficient design space can be ensured for electrodes, conductive patterns, and / or wiring provided on the third conductive layer CDL3.

[0181] Although embodiments of the invention have been described with reference to the accompanying drawings, those skilled in the art will understand that the invention can be implemented in other specific forms without altering the technical concept or essential features of the invention. Therefore, it should be understood that the above embodiments are exemplary in all respects and are not limiting.

Claims

1. A display device comprising: a first electrode provided in a first conductive layer over a substrate; a first insulating layer provided over the substrate and covering the first conductive layer; a second electrode provided in a second conductive layer over the first insulating layer; a second insulating layer provided over the first insulating layer and covering the second conductive layer; an active layer of a transistor provided in a semiconductor layer over the second insulating layer; a gate insulating layer provided over the second insulating layer and provided over a part of the active layer; a third electrode provided in a third conductive layer over the gate insulating layer; a third insulating layer provided over the second insulating layer and covering the semiconductor layer, the gate insulating layer, and the third conductive layer; and a fourth electrode provided in a fourth conductive layer over the third insulating layer, wherein the fourth electrode overlaps with the first electrode and is directly connected to the first electrode through a first contact hole that penetrates the first insulating layer, the second insulating layer, and the third insulating layer. the fourth electrode is directly connected to the third electrode through a second contact hole that penetrates the third insulating layer, and 2. The display device according to claim 1, wherein the first electrode, the third electrode, and the fourth electrode constitute a first capacitor electrode of a capacitor. the second electrode overlaps with at least one of the first electrode, the third electrode, and the fourth electrode and constitutes a second capacitor electrode of the capacitor.

3. The display device according to claim 2, wherein 4. The display device according to claim 3, further comprising a fifth electrode provided in the fourth conductive layer apart from the fourth electrode and overlapping with the second electrode, the fifth electrode is directly connected to the second electrode through a third contact hole that penetrates the second insulating layer and the third insulating layer and constitutes the second capacitor electrode. wherein 5. The display device according to claim 4, further comprising: a fourth insulating layer provided over the third insulating layer and covering the fourth conductive layer; and a sixth electrode provided in a fifth conductive layer over the fourth insulating layer and overlapping with the fifth electrode, wherein the sixth electrode is connected to the fifth electrode through a fourth contact hole that penetrates the fourth insulating layer and constitutes the second capacitor electrode. the transistor further comprises a gate electrode provided in the third conductive layer and overlapping with a part of the active layer. the transistor further comprises at least one of:

6. The display device according to claim 1, wherein a source electrode provided in the fourth conductive layer and connected to a source region of the active layer through a fifth contact hole that penetrates the third insulating layer; and 7. The display device of claim 6, wherein, a drain electrode provided in the fourth conductive layer and connected to a drain region of the active layer through a sixth contact hole that penetrates the third insulating layer. the transistor further comprises a bottom electrode provided in the second conductive layer and overlapping with the active layer and the gate electrode. the bottom electrode is connected to the source electrode through a seventh contact hole that penetrates the second insulating layer and the third insulating layer.

10. The display device according to claim 7, further comprising:

8. The display device of claim 7, wherein, ​ 9. The display device of claim 8, wherein, ​ ​ a fourth insulating layer provided over the third insulating layer and covering the fourth conductive layer; a bridge electrode provided in a fifth conductive layer over the fourth insulating layer and connected to one of the source electrode and the drain electrode through an eighth contact hole that penetrates the fourth insulating layer; and a fifth insulating layer provided over the fourth insulating layer and covering the fifth conductive layer.

11. The display device according to claim 10, further comprising: a light emitting element layer provided over the fifth insulating layer and including a light emitting element connected to the bridge electrode through a ninth contact hole that penetrates the fifth insulating layer; and a sealing layer covering the light emitting element layer.

12. A display device comprising: a capacitor including a first electrode provided in a first conductive layer over a substrate, a second electrode provided in a second conductive layer over the first conductive layer, a third electrode provided in a third conductive layer over the second conductive layer, and a fourth electrode provided in a fourth conductive layer over the third conductive layer; a first insulating layer provided between the first conductive layer and the second conductive layer; a second insulating layer provided between the second conductive layer and the third conductive layer; and a third insulating layer provided between the third conductive layer and the fourth conductive layer, wherein the fourth electrode is directly connected to the first electrode through a first contact hole that penetrates the first insulating layer, the second insulating layer, and the third insulating layer, and directly connected to the third electrode through a second contact hole that penetrates the third insulating layer. the capacitor further includes a fifth electrode which is spaced apart from the fourth electrode, provided in the fourth conductive layer, and overlaps with the second electrode, and 13. The display device of claim 12, wherein, the fifth electrode is directly connected to the second electrode through a third contact hole that penetrates the second insulating layer and the third insulating layer.

14. The display device according to claim 13, further comprising: a fourth insulating layer provided over the third insulating layer and covering the fourth conductive layer; and a fifth conductive layer provided over the fourth insulating layer, wherein the capacitor further includes a sixth electrode provided in the fifth conductive layer and connected to the fifth electrode through a fourth contact hole that penetrates the fourth insulating layer.

15. The display device according to claim 12, further comprising: a semiconductor layer provided between the second insulating layer and the third conductive layer; a gate insulating layer provided between the semiconductor layer and the third conductive layer; and a transistor including an active layer provided in the semiconductor layer and a gate electrode provided in the third conductive layer and overlapping with a part of the active layer. the gate insulating layer is provided between the part of the active layer and the gate electrode, and exposes another part of the active layer.

17. A method for manufacturing a display device, comprising:

16. The display device of claim 15, wherein, forming a first conductive layer including a first electrode and a first insulating layer covering the first conductive layer over a substrate; forming a second conductive layer including a second electrode and a second insulating layer covering the second conductive layer over the first insulating layer; ​ ​ forming a semiconductor layer including an active layer of a transistor over the second insulating layer and a gate insulating layer covering the semiconductor layer; forming a conductive film over the gate insulating layer; etching the conductive film and the gate insulating layer to form a first gate insulating layer and a gate electrode over a part of the active layer, and to form a second gate insulating layer and a third electrode over a part of the second insulating layer; forming a third insulating layer covering the active layer, the gate electrode, and the third electrode over the second insulating layer; forming a first contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer to expose a part of the first electrode; and forming a fourth conductive layer over the third insulating layer, the fourth conductive layer including a fourth electrode directly connected to the first electrode through the first contact hole.

18. The method of claim 17, further comprising: In forming the first contact hole, a second contact hole penetrating the third insulating layer to expose a part of the third electrode is further formed, wherein forming the fourth conductive layer includes directly connecting the fourth electrode to the third electrode through the second contact hole.

19. The method of claim 17, further comprising: In forming the first contact hole, a third contact hole penetrating the second insulating layer and the third insulating layer to expose a part of the second electrode is further formed, wherein forming the fourth conductive layer includes further forming a fifth electrode spaced apart from the fourth electrode and directly connected to the second electrode through the third contact hole.

20. The method of claim 17, further comprising: In forming the first contact hole, a plurality of contact holes penetrating the third insulating layer to expose different parts of the active layer are further formed, wherein forming the fourth conductive layer includes further forming a source electrode and a drain electrode connected to the different parts of the active layer through the plurality of contact holes.

Images