Process scheduling method and device, chip, electronic equipment and storage medium

Abstract

The application provides a process scheduling method and device, a chip, electronic equipment and a storage medium, relates to the chip design and manufacturing technical field, and comprises the following steps: acquiring a process identifier of a to-be-accelerated process dynamically in the process of executing a process of a chip; comparing the process identifier of the to-be-accelerated process with process identifiers corresponding to each hardware command queue of the chip, determining a target hardware command queue belonging to the to-be-accelerated process and containing a to-be-executed command package; and controlling a command processing engine of the chip to preferentially execute the to-be-executed command package in the target hardware command queue. The method and device provided by the application dynamically assign a specific process, so that the specific process can be preferentially processed and executed, the flexibility of process scheduling is improved, the flexible control demand for the execution order and timeliness of the process in a complex application scenario can be met, and the response speed and processing efficiency of the chip such as a graphics processing unit in executing a key process are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design and manufacturing, and particularly relates to a process scheduling method and device, a chip, an electronic device and a storage medium. BACKGROUND

[0002] With the wide application of a graphics processing unit (GPU) in the field of general-purpose computing, the GPU has become a core computing unit in scenarios such as data centers, artificial intelligence, scientific computing and high-performance computing. In a typical multi-user and multi-task environment, the GPU needs to process multiple processes from different application programs at the same time.

[0003] In the related art, the GPU usually allocates one or more hardware command queue devices (HCQD) to each process. A command processing engine (CPE) inside the GPU cyclically acquires and distributes command packets (Packet) from each active hardware component queue device through a specific arbitration or polling mechanism. This design ensures that each process can fairly share the hardware resources of the GPU and avoids a single task from monopolizing for a long time, which prevents other tasks from being executed. The process scheduling method in the related art cannot distinguish the urgency of the processes, and a high-priority process cannot be preferentially processed and executed, which cannot meet the flexible control requirements of the execution order and timeliness of the processes in complex application scenarios, and causes the GPU to respond slowly to critical processes and the system scheduling to be inflexible.

[0004] Therefore, how to improve the flexibility of process scheduling and improve the response speed of the GPU and other chips in executing critical processes has become a technical problem to be solved in the industry. SUMMARY

[0005] The present application provides a process scheduling method and device, a chip, an electronic device and a storage medium, which are used to solve the technical problem of how to improve the flexibility of process scheduling and improve the response speed of the GPU and other chips in executing critical processes.

[0006] The present application provides a process scheduling method, which comprises the following steps:

[0007] In the process of executing the process by the chip, the process identifier of a to-be-accelerated process is dynamically acquired;

[0008] The process identifier of the to-be-accelerated process is compared with the process identifiers corresponding to each hardware command queue of the chip, to determine a target hardware command queue belonging to the to-be-accelerated process and containing a to-be-executed command packet;

[0009] The command processing engine of the chip is controlled to execute the pending command package in the target hardware command queue preferentially.

[0010] In some embodiments, the process of dynamically obtaining the process identifier of the process to be accelerated during the execution of the chip execution process comprises:

[0011] dynamically obtaining a current value of a target register; the target register is used to write the process identifier of the process to be accelerated;

[0012] In the case where the current value is a preset invalid value, it is determined that there is no process to be accelerated;

[0013] In the case where the current value is not a preset invalid value, it is determined that there is a process to be accelerated and the process identifier of the process to be accelerated is determined based on the current value.

[0014] In some embodiments, after the determination that there is no process to be accelerated, the method further comprises:

[0015] The command processing engine is controlled to execute the command packages in each hardware command queue in turn.

[0016] In some embodiments, the comparison of the process identifier of the process to be accelerated with the process identifiers corresponding to each hardware command queue of the chip to determine the target hardware command queue belonging to the process to be accelerated and containing the pending command package comprises:

[0017] Based on the process identifier of the process to be accelerated and the process identifiers corresponding to each hardware command queue of the chip, a first mask is generated; the first mask is used to indicate the hardware command queue belonging to the process to be accelerated;

[0018] Based on the state of the command package in each hardware command queue, a second mask is generated; the second mask is used to indicate that each hardware command queue contains a pending command package;

[0019] Based on the first mask and the second mask, a third mask is generated; the third mask is used to indicate the target hardware command queue belonging to the process to be accelerated and containing the pending command package.

[0020] In some embodiments, the method further comprises:

[0021] In the case where the pending command package in the target hardware command queue is executed completely, a memory barrier instruction is written into the memory of the chip; the memory barrier instruction is used to indicate that the process to be accelerated has been processed.

[0022] In some embodiments, the method further comprises:

[0023] acquiring a command package state of each hardware command queue of the chip when all the to-be-executed command packages in the target hardware command queue are executed;

[0024] controlling the command processing engine to execute the to-be-executed command package in the at least one hardware command queue based on the command package state of each hardware command queue.

[0025] The application provides a process scheduling device, comprising:

[0026] The acquiring module is configured to dynamically acquire a process identifier of a to-be-accelerated process during execution of a process of the chip.

[0027] The comparing module is configured to compare the process identifier of the to-be-accelerated process with process identifiers corresponding to each hardware command queue of the chip, and determine a target hardware command queue belonging to the to-be-accelerated process and containing a to-be-executed command package.

[0028] The scheduling module is configured to control a command processing engine of the chip to preferentially execute the to-be-executed command package in the target hardware command queue.

[0029] The application provides a chip comprising the process scheduling device.

[0030] The application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the process scheduling method when executing the computer program.

[0031] The application provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program is executable by a processor to implement the process scheduling method.

[0032] The process scheduling method, device, chip, electronic device, and storage medium provided by the application can dynamically acquire a process identifier of a to-be-accelerated process, compare the process identifier of the to-be-accelerated process with process identifiers corresponding to each hardware command queue of the chip, determine a target hardware command queue belonging to the to-be-accelerated process and containing a to-be-executed command package, and control a command processing engine of the chip to preferentially execute the to-be-executed command package in the target hardware command queue, thereby achieving dynamic designation of a specific process without changing a basic architecture of the chip, allowing the specific process to be preferentially processed and executed, improving flexibility of process scheduling, meeting flexible control requirements for process execution order and timeliness in a complex application scenario, and improving response speed and processing efficiency of the chip such as a graphics processing unit in executing a key process. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0034] In order to more clearly illustrate the technical solutions in the application or the prior art, the accompanying drawings required by the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0035] Figure 1 is a schematic diagram of the hardware command queue provided by the application.

[0036] Figure 2 is one of the flow schematic diagrams of the process scheduling method provided by the application.

[0037] Figure 3 is the architectural schematic diagram of the process scheduling provided by the application.

[0038] Figure 4 is the second flow schematic diagram of the process scheduling method provided by the application.

[0039] Figure 5 is the structural schematic diagram of the process scheduling device provided by the application.

[0040] Figure 6 is the structural schematic diagram of the chip provided by the application.

[0041] Figure 7 is the structural schematic diagram of the electronic device provided by the application.

[0042] Reference signs:

[0043] 110: hardware command queue; 120: command processing engine; 310: target register;

[0044] 500: process scheduling device; 510: acquisition module; 520: comparison module; 530: scheduling module; 600: chip;

[0045] 710: processor; 720: communication interface; 730: memory; 740: communication bus. DETAILED DESCRIPTION

[0046] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort should belong to the scope of protection of the present application.

[0047] It should be noted that the terms "first", "second" and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units or modules does not necessarily have to include those steps or units or modules clearly listed, but can include other steps or units or modules not clearly listed or inherent to the process, method, product or device.

[0048] ‌ Figure 1 is a schematic diagram of the hardware command queue provided by the present application, as Figure 1 shown, in the chip design scheme of the related art, such as a graphics processor, each process can be assigned to a plurality of hardware devices for execution. The hardware command queue 110 is a buffer inside the hardware device for storing the to-be-executed commands in sequence, which is usually a First In First Out Queue (FIFO). After obtaining the command package, each hardware device will be stored in the hardware command queue. Different processes are executed in parallel on different hardware devices. The command processing engine 120 in the chip arbitrates to read the command package in each hardware command queue according to the state of the hardware command queue of the hardware device to which the current pipe belongs, and then distributes it to each execution unit for execution. The execution among multiple processes is essentially alternate serial execution.

[0049] If a process is to be given super-process authority to preferentially use the hardware device for acceleration execution, it is obviously impossible to achieve by the process scheduling method in the related art.

[0050] In order to solve the problems in the related art, Figure 2 is one of the flowcharts of the process scheduling method provided by the present application, as Figure 2 shown, the method comprises steps 210, 220 and 230.

[0051] Step 210, dynamically obtaining the process identifier of the process to be accelerated during the execution of the process on the chip.

[0052] Specifically, the execution subject of the process scheduling method provided by the embodiments of the present application is a process scheduling device or system. The device can be implemented by software, such as a process scheduling program running in a chip, or by hardware, such as a chip, a computer, a server, or the like, which executes the process scheduling method.

[0053] The chip in the embodiments of the present application can refer to a processor internally provided with a plurality of hardware command queues for multi-process processing. For example, it can be a graphics processing unit (GPU), a general-purpose computing on graphics processing units (GPGPU), a tensor processing unit (TPU), or other types of application-specific integrated circuits (ASICs) specially designed for artificial intelligence computing tasks.

[0054] The process to be accelerated refers to a specific process selected by the upper-layer software and expected to be executed at the highest priority and the fastest speed.

[0055] The process identifier is an identifier used to uniquely distinguish different processes at the hardware level of the chip. In a specific hardware implementation, the identifier can be an application space identifier (ASID) managed by a driver. When each process submits a task, the hardware will mark the task stream with the corresponding process identifier, so as to facilitate the hardware to distinguish the resource ownership.

[0056] Dynamically obtaining refers to the action of obtaining the process identifier of the process to be accelerated occurring during the normal operation of the chip. The upper-layer software (such as an operating system kernel, a device driver, or a specific application program) can decide which process needs to be accelerated at any time according to real-time business requirements. In a specific embodiment, the process identifier of the process to be accelerated can also be pre-set during system initialization or compilation.

[0057] There are various ways to obtain the process identifier. For example, the upper layer software can send a specific command to the chip through a predefined interface (e.g. a write operation of a specific register), which carries the process identifier of the process to be accelerated. After receiving the command, the chip can parse the process identifier. For another example, a shared memory region can be agreed between the chip and the host processor (e.g. the central processing unit). The upper layer software writes the process identifier of the process to be accelerated to a specific address of the memory region, and the chip periodically polls or reads the address after receiving a notification to obtain the process identifier. For another example, the host processor can directly deliver the process identifier to the chip through a specific hardware pin or on-chip bus signal.

[0058] Step 220: Compare the process identifier of the process to be accelerated with the process identifiers corresponding to the hardware command queues of the chip to determine the target hardware command queue belonging to the process to be accelerated and containing the to-be-executed command package.

[0059] Specifically, the hardware command queue is a hardware entity inside the chip for buffering to-be-executed instructions, usually a first-in-first-out queue. In a multi-tasking environment, the system allocates one or more hardware command queues for each or each group of processes, and each hardware command queue is explicitly associated with a process identifier, indicating its ownership.

[0060] The to-be-executed command package is the basic work unit submitted by the upper layer software to the hardware for execution, which contains specific computing instructions. Whether a hardware command queue contains a to-be-executed command package is the basis for judging whether it is in an active state.

[0061] Compare the process identifier of the process to be accelerated with the process identifiers corresponding to the hardware command queues of the chip. If the process identifier of the process to be accelerated is consistent with the process identifier corresponding to any hardware command queue and the hardware command queue contains a to-be-executed command package, then the hardware command queue is the target hardware command queue.

[0062] That is, the target hardware command queue is the queue that belongs to the process to be accelerated and indeed has a to-be-executed command package to be processed. There can be one or more such target hardware command queues.

[0063] Step 230: Control the command processing engine of the chip to preferentially execute the to-be-executed command package in the target hardware command queue.

[0064] Specifically, the command processing engine is a central dispatch unit inside the chip responsible for grabbing command packages from various hardware command queues and performing parsing and distribution. In the conventional mode, the command processing engine will use a polling or other fair algorithm to process all active hardware command queues in turn.

[0065] In the embodiments of the present application, the priority execution refers to an exclusive, non-preemptive highest priority execution mode. When it is determined that there is one or more target hardware command queues, the scheduling strategy of the command processing engine will change: it will suspend the processing of all non-target hardware command queues, and will focus on processing these target hardware command queues. The command processing engine will continuously and uninterruptedly acquire and execute the to-be-executed command package from these target queues until all target hardware command queues become empty. During this period, the tasks of all other ordinary processes (non-to-be-accelerated processes) will be suspended and waited, so as to realize the acceleration processing for the to-be-accelerated processes.

[0066] The process scheduling method provided by the embodiments of the present application dynamically acquires the process identifier of the to-be-accelerated process, compares the process identifier of the to-be-accelerated process with the process identifiers corresponding to the hardware command queues of the chip, determines the target hardware command queue belonging to the to-be-accelerated process and containing the to-be-executed command package, and controls the command processing engine of the chip to preferentially execute the to-be-executed command package in the target hardware command queue. The embodiments of the present application realize the dynamic designation of a specific process without changing the basic architecture of the chip, so that the specific process can be preferentially processed and executed, improve the flexibility of process scheduling, can meet the flexible control requirements of process execution order and timeliness in complex application scenarios, and improve the response speed and processing efficiency of the chip such as a graphics processing unit in executing a key process.

[0067] It should be noted that each embodiment of the present application can be freely combined, the order can be changed or the embodiments can be executed independently, and does not need to rely on or depend on a fixed execution order.

[0068] In some embodiments, the process identifier of the to-be-accelerated process is dynamically acquired during the execution of the process of the chip, and the method comprises the following steps.

[0069] The current value of the target register is dynamically acquired; the target register is used to write the process identifier of the to-be-accelerated process;

[0070] In the case that the current value is a preset invalid value, it is determined that there is no to-be-accelerated process;

[0071] In the case that the current value is not the preset invalid value, it is determined that there is a to-be-accelerated process and the process identifier of the to-be-accelerated process is determined based on the current value.

[0072] Specifically, a dedicated target register can be designed inside the chip. The register is a storage unit that can be read and written by software at the hardware level, and its core use is to provide the process identifier of the to-be-accelerated process to the hardware level.

[0073] The target register can be mapped to the chip's configuration space or input / output (I / O) space, allowing high-level software with sufficient privileges (such as device drivers) to set its value through a simple register write operation. The content written into this register is the process identifier of the process to be accelerated. For example, in a system that uses Address Space Identifiers (ASIDs) as process identifiers, when a driver decides to accelerate a process, it writes the ASID value of that process into this target register.

[0074] To enable and disable the acceleration function dynamically, this application embodiment sets a preset invalid value. This is a specially agreed-upon value outside the normal process identifier range. For example, if the valid process identifier range in the system is 0 to 65535, then a 32-bit register can select a specific value much greater than 65535, such as 0xdeadbeef, as the preset invalid value. This value itself does not represent any valid process; its sole purpose is to serve as a signal to notify the hardware that there is currently no process to be accelerated.

[0075] The chip reads the current value of the target register in real time or periodically.

[0076] If the current value read is a preset invalid value, the hardware determines that there is no acceleration request from the software. At this time, the entire priority scheduling mechanism is turned off, and the chip will execute its normal scheduling strategy, such as serving all processes in turn.

[0077] If the current value read is not a preset invalid value, the hardware determines that the priority scheduling function has been activated. At this time, the current value itself is identified by the hardware as the process identifier of the process to be accelerated. For example, if the register value is 100, the hardware locks the process with process identifier 100 as the process to be accelerated this time.

[0078] The process scheduling method provided in this application, by setting a target register and a preset invalid value, enables the upper-layer software to enable, switch, and disable the complex scheduling behavior of the underlying hardware with only one register write operation. This greatly simplifies the programming model and control logic at the software level. Moreover, the register-based communication method is fast for the hardware, ensuring the real-time and deterministic nature of process scheduling and providing a solid foundation for achieving high-performance dynamic process scheduling.

[0079] In some embodiments, after determining that there is no process to be accelerated, the method further includes:

[0080] The control command processing engine executes command packets from each hardware command queue in turn.

[0081] Specifically, determining that there is no process to be accelerated can include two cases: the first case refers to that after the system is started, no process is designated as a process to be accelerated, and the target register keeps its default invalid value; the second case refers to that a task of a previously designated process to be accelerated has been executed, or the upper-layer software actively cancels the acceleration state thereof based on business logic, and closes the priority scheduling function by writing a preset invalid value to the target register.

[0082] In the above two cases, the command processing engine will no longer only focus on the specific target hardware command queue, but instead, will execute the command packets in each hardware command queue in turn.

[0083] The process scheduling method provided in the embodiments of the present application executes the command packets in each hardware command queue in turn in the case where there is no process to be accelerated, thereby ensuring that all ordinary processes will not be delayed in processing due to the existence of the priority scheduling mechanism, maintaining the resource utilization and throughput of the entire chip, and enabling seamless switching between the two modes of priority acceleration and fair scheduling.

[0084] In some embodiments, the determining of the target hardware command queue that belongs to the process to be accelerated and contains the command packet to be executed comprises:

[0085] generating a first mask based on the process identifier of the process to be accelerated and the process identifiers corresponding to each hardware command queue of the chip; the first mask is used to indicate the hardware command queue that belongs to the process to be accelerated;

[0086] generating a second mask based on the state of the command packet in each hardware command queue; the second mask is used to indicate that each hardware command queue contains the command packet to be executed;

[0087] generating a third mask based on the first mask and the second mask; the third mask is used to indicate the target hardware command queue that belongs to the process to be accelerated and contains the command packet to be executed.

[0088] Specifically, in the embodiments of the present application, the mask is essentially a bit vector, each bit corresponds to each hardware command queue in the chip, and the corresponding value can represent the state of the corresponding hardware command queue.

[0089] There can be hardware command queues in the chip, wherein the hardware command queue can be marked as hcqdi, and the corresponding process identifier can be represented as hcqdi_asic. The process identifier of the process to be accelerated can be represented as reg_pro_asid.

[0090] The process identification of the process to be accelerated is compared with the process identification corresponding to each hardware command queue, to generate a first mask hcqd_pro_mask[n:1]. The first mask has n bits, and the i-th bit corresponds to the i-th hardware command queue.

[0091] If the comparison result is true (hcqdi_asic==reg_pro_asid), it indicates that the i-th hardware command queue belongs to the process to be accelerated, and the value of the i-th bit in the first mask is 1. If the comparison result is false (hcqdi_asic!=reg_pro_asid), it indicates that the i-th hardware command queue does not belong to the process to be accelerated, and the value of the i-th bit in the first mask is 0. The comparison process can be represented by code as follows: hcqdi_asic==reg_pro_asid?1:0.

[0092] Correspondingly, the generation process of the first mask can be represented by code as follows:

[0093] hcqd_pro_mask[n:1]={hcqdn_asid==reg_pro_asid?1:0,…,hcqd1_asid==reg_pro_asid?1:0}.

[0094] It can be understood that, through the value of each bit in the first mask, the hardware command queue belonging to the process to be accelerated can be determined.

[0095] According to the state of the command packet in each hardware command queue (whether it contains a to-be-executed command packet), a second mask hcqd_fifo_empty[n:1] can be generated. The second mask has n bits, and the i-th bit corresponds to the i-th hardware command queue.

[0096] If the i-th hardware command queue does not contain a to-be-executed command packet, the value of the i-th bit in hcqd_fifo_empty[n:1] is 1, indicating that the i-th hardware command queue is empty. If the i-th hardware command queue contains a to-be-executed command packet, the value of the i-th bit in hcqd_fifo_empty[n:1] is 0, indicating that the i-th hardware command queue is not empty. ​​​​​​​​​​​​​​​The hardware command queue is not empty.

[0097] Understandably, the value of each bit in the second mask can be used to determine whether each hardware command queue contains a command packet to be executed.

[0098] By performing calculations based on the first and second masks, a third mask, fw_use_hcqd_mask[n:1], can be generated. The third mask has... The bit, the th bit The bit corresponds to the th bit A hardware command queue.

[0099] We can first invert the second mask bitwise to determine the non-empty hardware command queue (containing the command packets to be executed). Then, we can perform a bitwise AND operation between the bit-inverted second mask and the first mask to obtain the third mask, which can be represented in code as follows:

[0100] fw_use_hcqd_mask[n:1]=hcqd_pro_mask[n:1]&!hcqd_fifo_empty[n:1].

[0101] If the third mask contains the first If the nth bit is 1, it means that the nth bit is 1. A hardware command queue that belongs to the process to be accelerated and contains command packages to be executed is the target hardware command queue.

[0102] It is understandable that the target hardware command queue is determined by the values ​​of each bit in the third mask.

[0103] The process scheduling method provided in this application transforms complex logical judgments into simple mask operations that can be completed within a single clock cycle. This avoids complex serial queries and judgments by software or firmware, greatly reduces decision latency, ensures the real-time performance and accuracy of identifying and locking the target hardware command queue, and improves the response speed of process scheduling.

[0104] In some embodiments, the method further includes:

[0105] Once all the command packets to be executed in the target hardware command queue have been completed, a memory barrier instruction is written into the chip's memory; the memory barrier instruction is used to indicate that the process to be accelerated has been processed.

[0106] Specifically, at least one bit in the third mask is 1 when there is a pending process to be accelerated and the pending process is scheduled preferentially. The command processing engine executes the command packets in the corresponding queue according to the mask. When a command packet is executed, the number of pending command packets in the hardware command queue where the command packet is located is reduced. When a hardware command queue is completely emptied, the non-empty state bit of the hardware command queue is invalidated. This change is reflected in the second mask in real time, and thus the corresponding bit in the third mask is also changed to 0. When all the target hardware command queues belonging to the pending process and initially non-empty are emptied, all the bits in the third mask are changed to 0.

[0107] The chip continuously monitors the state of the third mask. When it is detected that the value of the mask changes from a non-zero value to a full zero value, it is determined that the condition that all the pending command packets are executed is met.

[0108] The memory barrier instruction (fence) is a memory write operation for marking a completed event, which is automatically initiated by the hardware. It functions as a barrier, that is, it ensures that all the memory operations of the pending process occur before the barrier.

[0109] In the case that all the pending command packets in the target hardware command queue are executed, the memory barrier instruction is written into the memory of the chip.

[0110] After the upper-layer software initiates the acceleration request, it does not need to frequently query the state of each hardware queue, but can periodically monitor whether the memory barrier instruction is written into the memory. If the memory barrier instruction is detected, it can be considered that the pending process is processed.

[0111] In this case, the upper-layer software can determine whether the preferential scheduling needs to be closed according to the actual situation. If the upper-layer software needs to close the preferential scheduling, it only needs to write a preset invalid value into the target register.

[0112] The process scheduling method provided by the embodiment of the application establishes an efficient and low-overhead completion notification channel from hardware to software by automatically writing the memory barrier instruction into the memory, avoids the performance overhead and bus bandwidth occupation caused by a large number of invalid read operations of the upper-layer software for querying the state, and enables the system to respond to the task completion event with lower delay, thereby improving the cooperative processing efficiency and response capability of the entire system.

[0113] In some embodiments, the method further includes:

[0114] In the case that all the pending command packets in the target hardware command queue are executed, the state of the command packet of each hardware command queue of the chip is acquired;

[0115] If it is determined that there is at least one hardware command queue containing a command package to be executed, the control command processing engine is controlled to execute the command package to be executed in the at least one hardware command queue.

[0116] Specifically, when the task of the process to be accelerated is executed, the hardware notifies the upper-layer software. However, there is a certain delay from the time when the upper-layer software receives the notification to the time when it makes a decision and finally writes the preset invalid value into the target register to close the priority scheduling mode. The delay may include multiple links such as operating system scheduling and driver execution. During this period, if the command processing engine of the chip only stops working and waits for the software instruction, valuable hardware computing resources will be idle and wasted, especially when there are tasks of other normal processes to be executed in the system.

[0117] In the method provided in the embodiments of the present application, when the command packages to be executed in the target hardware command queue are all executed, the chip will not immediately enter the idle state, but will immediately reevaluate the load condition of the whole chip, that is, obtain the command package state of each hardware command queue of the chip, and re-generate the second mask. The hardware command queues here are no longer limited to the target hardware command queue, but all hardware command queues in the chip.

[0118] If it is determined that there is at least one hardware command queue (corresponding to a normal process) containing a command package to be executed (the re-generated second mask is not all 1), the control command processing engine is controlled to execute the command package to be executed in the hardware command queue, instead of idling and waiting.

[0119] After a round of command packages to be executed is executed, it is detected again whether the target register is written with the preset invalid value or a process identifier of a new process to be added.

[0120] The process scheduling method provided in the embodiments of the present application allows the chip to immediately process tasks of other normal processes after the task of the process to be accelerated is executed, without waiting for the slow response of the upper-layer software, greatly reduces the idle time of the hardware caused by waiting for the response of the software, and thus effectively improves the overall throughput and resource utilization of the chip in a multitasking environment.

[0121] Figure 3 is an architecture diagram of the process scheduling provided in the present application, as Figure 3As shown, the upper software writes the process identifier of the process to be accelerated in the target register 310. The process scheduling device in the chip compares the process identifier of the process to be accelerated with the process identifiers of each hardware command queue 110, generates a first mask; generates a second mask according to whether each hardware command queue contains a command package to be executed; calculates the first mask and the second mask to generate a third mask; determines the target hardware command queue according to the third mask, and controls the command processing engine 120 to preferentially execute the command package to be executed in the target hardware command queue.

[0122] Figure 4 is a second flowchart of the process scheduling method provided in the present application, as shown in the figure, the method is executed by a process scheduling device, and includes: Figure 4

[0123] Step 410, obtaining the current value of the target register.

[0124] Step 420, judging whether there is a process to be accelerated according to the current value of the target register.

[0125] Step 430, if there is no process to be accelerated, controlling the command processing engine to round-robin execute the command packages in each hardware command queue.

[0126] Step 440, if there is a process to be accelerated, comparing the process identifier of the process to be accelerated with the process identifiers of each hardware command queue to generate a first mask.

[0127] Step 450, generating a second mask according to whether each hardware command queue contains a command package to be executed.

[0128] Step 460, calculating the first mask and the second mask to generate a third mask.

[0129] Step 470, determining the target hardware command queue according to the third mask, and controlling the command processing engine to preferentially execute the command package to be executed in the target hardware command queue.

[0130] Step 480, in the case where the command packages to be executed in the target hardware command queue are all executed, writing a memory barrier instruction into the memory of the chip to indicate that the process to be accelerated has been processed.

[0131] Step 490, in the case where the command packages to be executed in the target hardware command queue are all executed, detecting the state of the command packages of each hardware command queue; in the case where it is determined that at least one hardware command queue contains a command package to be executed, controlling the command processing engine to execute the command package to be executed in the at least one hardware command queue.

[0132] ​For the command processing engine, there are n pipes, each pipe has m hardware command queues, each process only uses one hardware command queue, and each process has x command packets (pkts). Assuming that all command packets have the same execution time and take turns to participate in arbitration, to execute a certain process, according to the related art scheme, it needs to wait for x n m command packets to be executed before it can be determined that the process has been executed, and it is also impossible to implement priority scheduling for the process.

[0133] After adopting the process scheduling method provided in the embodiments of the present application, a certain process can be scheduled preferentially, and x command packets can be directly executed, thereby improving the flexibility of process scheduling and meeting the flexible control requirements of process execution order and timeliness in complex application scenarios.

[0134] The device provided in the embodiments of the present application is described below, and the device described below can be correspondingly referred to the method described above.

[0135] Figure 5 is a structural schematic diagram of the process scheduling device provided in the present application, as Figure 5 indicated, the process scheduling device 500 includes:

[0136] The acquisition module 510 is configured to dynamically acquire the process identifier of the to-be-accelerated process in the process of executing the process by the chip.

[0137] The comparison module 520 is configured to compare the process identifier of the to-be-accelerated process with the process identifiers corresponding to the hardware command queues of the chip, to determine a target hardware command queue belonging to the to-be-accelerated process and containing to-be-executed command packets.

[0138] The scheduling module 530 is configured to control the command processing engine of the chip to preferentially execute the to-be-executed command packets in the target hardware command queue.

[0139] The process scheduling device provided in the embodiments of the present application dynamically acquires the process identifier of the to-be-accelerated process, compares the process identifier of the to-be-accelerated process with the process identifiers corresponding to the hardware command queues of the chip, to determine a target hardware command queue belonging to the to-be-accelerated process and containing to-be-executed command packets, and controls the command processing engine of the chip to preferentially execute the to-be-executed command packets in the target hardware command queue. In this way, without changing the basic architecture of the chip, a specific process can be dynamically specified, so that the specific process can be preferentially processed and executed, the flexibility of process scheduling is improved, the flexible control requirements of process execution order and timeliness in complex application scenarios can be met, and the response speed and processing efficiency of the chip such as a graphics processor in executing a key process are improved.

[0140] Figure 6 is a structural schematic diagram of the chip provided in the present application, asFigure 6 As shown in the figure, the chip 600 comprises the process scheduling apparatus 500.

[0141] The chip provided by the embodiments of the present application, because of comprising the process scheduling apparatus in the above embodiments, realizes dynamically designating a specific process without changing the basic architecture of the chip, so that the specific process can be preferentially processed and executed, improves the flexibility of process scheduling, can meet the flexible control requirements of process execution order and timeliness in complex application scenarios, and improves the response speed and processing efficiency of the chip such as a graphics processor in executing a key process.

[0142] Figure 7 is a structural schematic diagram of an electronic device provided by the present application, as Figure 7 shown, the electronic device can comprise a processor (Processor) 710, a communications interface (Communications Interface) 720, a memory (Memory) 730 and a communications bus (Communications Bus) 740, wherein the processor 710, the communications interface 720, the memory 730 complete mutual communication through the communications bus 740. The processor 710 can invoke the logic command in the memory 730 to execute the method described in the above embodiments, for example:

[0143] In the process of executing the process by the chip, the process identifier of the process to be accelerated is dynamically acquired; the process identifier of the process to be accelerated is compared with the process identifiers corresponding to each hardware command queue of the chip to determine the target hardware command queue belonging to the process to be accelerated and containing the to-be-executed command package; and the command processing engine of the chip is controlled to preferentially execute the to-be-executed command package in the target hardware command queue.

[0144] In addition, the logic command in the above memory can be realized in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, includes a plurality of commands to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. And the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0145] The processor in the electronic device provided by the embodiments of the present application can call the logical instructions in the memory to implement the above method, the specific implementation manners of which are consistent with the foregoing method implementation manners, and the same beneficial effects can be achieved, which will not be described here again.

[0146] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method provided by the foregoing embodiments.

[0147] The specific implementation manners of which are consistent with the foregoing method implementation manners, and the same beneficial effects can be achieved, which will not be described here again.

[0148] The embodiments of the present application provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the method.

[0149] The device embodiments described above are only schematic, wherein the units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments. Those skilled in the art can understand and implement without creative labor.

[0150] Through the description of the foregoing embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary universal hardware platforms, and of course, can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software products, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and include a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0151] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A process scheduling method, characterized by, The method comprises the steps of: dynamically obtaining a process identifier of a process to be accelerated during execution of a process by a chip; comparing the process identifier of the process to be accelerated with process identifiers corresponding to each hardware command queue of the chip to determine a target hardware command queue belonging to the process to be accelerated and containing a command package to be executed; controlling a command processing engine of the chip to preferentially execute the command package to be executed in the target hardware command queue; the comparison of the process identifier of the process to be accelerated with the process identifiers corresponding to each hardware command queue of the chip to determine the target hardware command queue belonging to the process to be accelerated and containing the command package to be executed comprises: generating a first mask based on the process identifier of the process to be accelerated and the process identifiers corresponding to each hardware command queue of the chip; the first mask is used to indicate the hardware command queues belonging to the process to be accelerated; generating a second mask based on the state of the command package in each hardware command queue; the second mask is used to indicate that each hardware command queue contains the command package to be executed; generating a third mask based on the first mask and the second mask; the third mask is used to indicate the target hardware command queue belonging to the process to be accelerated and containing the command package to be executed.

2. The process scheduling method of claim 1, wherein, The dynamic obtaining of the process identifier of the process to be accelerated during the execution of the process by the chip comprises: dynamically obtaining a current value of a target register; the target register is used to write the process identifier of the process to be accelerated; in the case that the current value is a preset invalid value, it is determined that there is no process to be accelerated; in the case that the current value is not the preset invalid value, it is determined that there is a process to be accelerated and the process identifier of the process to be accelerated is determined based on the current value.

3. The process scheduling method of claim 2, wherein, After the determination that there is no process to be accelerated, the method further comprises: controlling the command processing engine to execute the command packages in each hardware command queue in turn.

4. The process scheduling method according to any one of claims 1 to 3, characterized in that, The method further comprises: in the case that all the command packages to be executed in the target hardware command queue are executed, writing a memory barrier instruction into a memory of the chip; the memory barrier instruction is used to indicate that the process to be accelerated has been processed.

5. The process scheduling method according to any one of claims 1 to 3, characterized in that, The method further comprises: in the case that all the command packages to be executed in the target hardware command queue are executed, obtaining the state of the command package of each hardware command queue of the chip; in the case that it is determined based on the state of the command package of each hardware command queue that at least one hardware command queue contains the command package to be executed, controlling the command processing engine to execute the command package to be executed in the at least one hardware command queue.

6. A process scheduling apparatus characterized by comprising: The method comprises: an obtaining module, configured to dynamically obtain a process identifier of a process to be accelerated during execution of a process by a chip; a comparison module, configured to compare the process identifier of the process to be accelerated with process identifiers corresponding to each hardware command queue of the chip to determine a target hardware command queue belonging to the process to be accelerated and containing a command package to be executed; a scheduling module, configured to control a command processing engine of the chip to preferentially execute the command package to be executed in the target hardware command queue. The process identifier of the process to be accelerated is compared with the process identifiers corresponding to each hardware command queue of the chip, and a target hardware command queue belonging to the process to be accelerated and containing a command package to be executed is determined, comprising: generating a first mask based on the process identifier of the process to be accelerated and the process identifiers corresponding to each hardware command queue of the chip; the first mask is used to indicate the hardware command queues belonging to the process to be accelerated; generating a second mask based on the state of the command package in each hardware command queue; the second mask is used to indicate that each hardware command queue contains a command package to be executed; generating a third mask based on the first mask and the second mask; the third mask is used to indicate the target hardware command queue belonging to the process to be accelerated and containing a command package to be executed.

7. A chip, characterized by The process scheduling device of claim 6 is included.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the process scheduling method of any one of claims 1 to 5. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the process scheduling method of any one of claims 1 to 5.

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