Multi-chip cooperative control method and device based on SPI (Serial Peripheral Interface)

Abstract

The invention relates to the field of chip control, and discloses a multi-chip cooperative control method and device based on SP I. The method comprises the steps that the task type of a to-be-processed task is determined, and the task type of the to-be-processed task is used for reflecting the calculation requirement and the power consumption requirement of the to-be-processed task; m chips are determined from N chips according to the task type of the to-be-processed task and the computing power and the load state of each chip in the N chips of the multi-chip system, and the N chips communicate with one another through a serial peripheral interface (SPI); and determining a target chip from the M chips according to the task type of the to-be-processed task, and allocating the to-be-processed task to the target chip. By adopting the technical scheme, the problem that the tasks cannot be reasonably scheduled is solved. According to the method, the reasonability of task scheduling is improved, the task execution delay is reduced, the waste and overload risk of chip resources are effectively avoided, and the utilization rate of chips and the overall stability of the system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip control, and in particular to a multi-chip cooperative control method and device based on SPI. BACKGROUND

[0002] With the rapid development of high-performance computing, artificial intelligence and edge computing technologies, multi-chip systems are widely used in various intelligent devices due to their higher computing power and flexibility. A multi-chip system is usually composed of multiple chips with different computing capabilities, and these chips exchange data and synchronize states through high-speed communication interfaces to achieve parallel processing of tasks.

[0003] In a multi-chip system, the task scheduling strategy directly affects the overall performance, energy efficiency and response speed of the system. However, most current task scheduling methods still rely on static allocation mechanisms, i.e., tasks are allocated to specific chips according to pre-set rules before system operation. Such methods are difficult to achieve optimal utilization of resources when facing scenarios where task characteristics frequently change.

[0004] In addition, different chips have significant differences in computing power, power consumption characteristics, etc. Existing scheduling strategies often fail to fully consider the matching relationship between task individual needs and chip characteristics, resulting in some chips being in an overload state while others are in an idle or low-load state, affecting the overall efficiency and stability of the system. Therefore, how to achieve more intelligent and efficient task allocation and cooperative control in a multi-chip system has become a problem that needs to be solved in current technology development.

[0005] The prior art has the problem of being unable to reasonably schedule tasks. SUMMARY

[0006] The present application provides a multi-chip cooperative control method and device based on SPI to solve the problem of being unable to reasonably schedule tasks.

[0007] In a first aspect, to solve the above technical problems, the present application provides a multi-chip cooperative control method based on SPI, comprising: determining the task type of a to-be-processed task, wherein the task type of the to-be-processed task is used to reflect the computing demand and power consumption demand of the to-be-processed task; determining M chips from N chips of a multi-chip system according to the task type of the to-be-processed task, the computing power and load state of each chip of the N chips, wherein N is an integer greater than or equal to 2, M is a positive integer not greater than N, and the N chips communicate with each other using a serial peripheral interface (SPI); determining a target chip from the M chips according to the task type of the to-be-processed task, and allocating the to-be-processed task to the target chip.

[0008] Preferably, the determining the task type of the to-be-processed task comprises: determining task data of the to-be-processed task according to the computing request; determining a computing intensity and a power consumption requirement of the to-be-processed task according to the task data; and determining the task type of the to-be-processed task based on a preset classification rule according to the computing intensity and the power consumption requirement of the to-be-processed task.

[0009] Preferably, the determining the M chips from the N chips according to the task type of the to-be-processed task, the computing capability and the load state of each chip of the N chips in the multi-chip system comprises: determining a task feature weight of the to-be-processed task according to the task type of the to-be-processed task; respectively calculating a load distribution coefficient of each chip of the N chips according to the task feature weight, the computing capability and the load state of each chip of the N chips in the multi-chip system; respectively calculating a task distribution evaluation value of each chip according to the load distribution coefficient of each chip and a priority weight of the to-be-processed task, to obtain N task distribution evaluation values corresponding to the N chips; and determining the M chips from the N chips according to the N task distribution evaluation values and a preset evaluation threshold, wherein a task distribution evaluation value of each chip of the M chips is greater than the preset evaluation threshold.

[0010] Preferably, the determining the target chip from the M chips according to the task type of the to-be-processed task and distributing the to-be-processed task to the target chip comprises: determining a comprehensive score of each chip of the M chips in the computing capability and the load state; determining a reference comprehensive score corresponding to a required chip according to the task type of the to-be-processed task; and determining the target chip from the M chips according to the reference comprehensive score and the comprehensive score of each chip of the M chips.

[0011] Preferably, after the to-be-processed task is distributed to the target chip, the method further comprises: determining a dynamic load distribution curve of an i-th chip of the N chips by: continuously acquiring load data of the i-th chip according to a preset acquisition frequency; calculating a load fluctuation amplitude corresponding to the i-th chip according to the load data of the i-th chip and the acquisition frequency, to obtain a load fluctuation data set corresponding to the i-th chip; in a case where there is a load fluctuation amplitude with an amplitude exceeding a preset threshold in the load fluctuation data set, extracting a load change trend of the load data of the i-th chip by using a sliding window method, to obtain a change trend feature set; analyzing the change trend feature set by using a linear regression method, to determine a future load prediction value; and generating the dynamic load distribution curve of the i-th chip according to the future load prediction value and the load data of the i-th chip monitored in real time.

[0012] Preferably, the method further comprises: in a case where it is determined according to the dynamic load distribution curve of the target chip that the load of the target chip after a preset time is greater than a load balancing threshold, determining Q chips from N-1 chips in the multi-chip system according to the task type of the to-be-processed task and the computing capability and load state of each of the N-1 chips, wherein Q is a positive integer not greater than N-1, and the N-1 chips are chips other than the target chip in the N chips; determining a switching chip from the Q chips according to the task type of the to-be-processed task; determining resource overhead of switching the to-be-processed task from the target chip to the switching chip; and in a case where the resource overhead meets a preset condition, switching the to-be-processed task from the target chip to the switching chip.

[0013] Preferably, after the to-be-processed task is allocated to the target chip, the method further comprises: determining a distribution delay of a target instruction and a response speed of the target chip in response to the target instruction, wherein the target instruction is used to instruct to allocate the to-be-processed task to the target chip; and optimizing a sending priority of an instruction sent to the target chip according to the distribution delay and the response speed.

[0014] In a second aspect, the present application provides a multi-chip cooperative control device based on SPI, comprising: a first determining module configured to determine a task type of a to-be-processed task, wherein the task type of the to-be-processed task is used to reflect computing demand and power consumption demand of the to-be-processed task; a second determining module configured to determine M chips from N chips in a multi-chip system according to the task type of the to-be-processed task and the computing capability and load state of each of the N chips, wherein N is an integer greater than or equal to 2, M is a positive integer not greater than N, and the N chips communicate with each other through a serial peripheral interface (SPI); and a third determining module configured to determine a target chip from the M chips according to the task type of the to-be-processed task and allocate the to-be-processed task to the target chip.

[0015] In a third aspect, the present application further provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the multi-chip cooperative control method based on SPI according to any one of the above-mentioned aspects when executing the computer program.

[0016] In a fourth aspect, the present application further provides a computer readable storage medium, comprising a stored computer program, wherein the computer readable storage medium controls a device where the computer readable storage medium is located to execute the multi-chip cooperative control method based on SPI according to any one of the above-mentioned aspects when the computer program runs.

[0017] The application first determines the task type according to the computing requirement and power consumption requirement of the task to be processed, realizes the identification of the task characteristics, then selects M currently available chips from N chips according to the task type of the task to be processed and the real-time load state of each chip in the multi-chip system, and finally selects the most suitable target chip from the M chips according to different task types (such as high computing requirement type or low power consumption requirement type) to perform task allocation. The method avoids the limitations of the traditional static scheduling strategy, improves the accuracy and adaptability of task scheduling by dynamically matching the task type and the chip running state. From the technical effect, the scheme not only improves the rationality of task scheduling, reduces the task execution delay, but also effectively avoids the waste and overload risk of chip resources, improves the utilization rate of chips and the overall stability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a flowchart of a multi-chip cooperative control method based on SPI provided by the first embodiment of the application;

[0019] Figure 2 is a structural schematic diagram of a multi-chip cooperative control device based on SPI provided by the second embodiment of the application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0021] Referring to Figure 1 The first embodiment of the application provides a multi-chip cooperative control method based on SPI, which includes the following steps S11-S13:

[0022] S11, determining the task type of the task to be processed, wherein the task type of the task to be processed is used to reflect the computing requirement and power consumption requirement of the task to be processed;

[0023] In an exemplary embodiment, the above step S11 can be realized by the following steps S21-S23:

[0024] Step S21: determining the task data of the task to be processed according to the computing request;

[0025] It should be noted that the computing request is a computing request submitted by a user. The task data includes but is not limited to: the computing amount (such as the number of operations, the number of floating point operations) of the task, the expected execution time (the expected completion time of the task) and the power consumption requirement (the energy consumption index per unit time during the execution of the task).

[0026] Further, the obtained task data is standardized. Specifically, the original numerical values in the task data are uniformly processed and normalized by a pre-established data analysis tool to ensure the effective execution of subsequent classification rules. For example, the power consumption requirement is normalized to the interval [0, 1] to form a standardized task feature set. This standardization process helps to eliminate data differences between different tasks and improve the accuracy of task classification.

[0027] Step S22: determining the computing intensity and power consumption requirement of the to-be-processed task according to the task data;

[0028] It should be noted that the computing intensity (operations / second) of the to-be-processed task is equal to the computing amount of the task divided by the expected execution time.

[0029] Step S23: determining the task type of the to-be-processed task based on a preset classification rule according to the computing intensity and power consumption requirement of the to-be-processed task.

[0030] Optionally, first, it is judged whether the computing intensity of the task is higher than a first preset threshold value. If it is higher than the threshold value, it is initially classified as a high computing requirement class task, and an initial task type identifier is generated. Then, it is further judged whether the power consumption requirement of the task is lower than a second preset threshold value. If the condition is met, it is reclassified as a low power consumption requirement class task, and the final task classification information is formed.

[0031] Through the above two judgment mechanisms, fine division of the task type is realized, which not only considers the computing requirement of the task, but also takes into account its energy consumption characteristics, thereby avoiding the problem of uneven resource allocation that may be caused by single-dimensional classification. For example, if a task is classified as "high computing low power consumption", the system can preferentially allocate it to a high-performance low-power chip to meet the computing requirement while reducing the overall energy consumption.

[0032] Finally, according to the task classification information, a corresponding characteristic classification label is generated for the task by a label division tool in combination with the characteristic classification requirement. The label can be used for subsequent quick identification and matching of the task scheduling system, such as being marked as "high computing requirement class" or "low power consumption requirement class", thereby providing clear guidance for task scheduling.

[0033] By the technical scheme, automatic identification and classification of the task type are realized, the accuracy and adaptability of task scheduling are significantly improved, the system can maintain efficient operation in a complex and changeable task environment, unnecessary energy waste is reduced, and obvious economic and technical benefits are brought.

[0034] S12, determining M chips from the N chips according to the task type of the to-be-processed task, the computing capability and the load state of each chip in the N chips of the multi-chip system, wherein N is an integer greater than or equal to 2, M is a positive integer not greater than N, and the N chips communicate with each other by using a serial peripheral interface (SPI);

[0035] In an exemplary embodiment, the step S12 can be implemented by the following steps S31-S34:

[0036] Step S31: determining a task feature weight of the to-be-processed task according to the task type of the to-be-processed task;

[0037] It should be noted that in the multi-chip system, different tasks have significant differences in requirements for computing capability and energy consumption. In order to realize efficient matching between tasks and chips, it is necessary to first assign a corresponding task feature weight to the task according to the task type.

[0038] The task type usually includes a high-computing-demand class and a low-power-consumption-demand class.

[0039] Each type corresponds to a different task feature weight, which is used to highlight the core requirements of the task in subsequent calculations. For example: a high-computing-demand class task: task feature weight T = 1.5 (emphasizing computing capability); a low-power-consumption-demand class task: task feature weight T = 0.8 (emphasizing energy consumption control); the weight value can be pre-set in the system configuration or dynamically adjusted according to the task execution history data.

[0040] For example, assuming that a task is classified as a high-computing-demand class, the system reads the classification label of the task from the task scheduling database and assigns a task feature weight T = 1.5 to the task according to a preset rule, which is used for subsequent calculation of the load distribution coefficient.

[0041] Step S32: calculating a load distribution coefficient of each chip in the N chips of the multi-chip system according to the task feature weight, the computing capability and the load state of each chip;

[0042] It should be noted that after obtaining the task feature weight, the system will combine the computing capability (C) and the current load state (L) of each chip to calculate the load distribution coefficient (P) of each chip, which is used to evaluate the adaptation degree of the chip under the current task.

[0043] The formula for calculating the load distribution coefficient is: P = C / (L+T);

[0044] C is the computing power of the chip (such as the number of floating point operations per second), L is the current load of the chip (such as the current task processing amount), and T is the task characteristic weight (such as 1.5 or 0.8).

[0045] It should be noted that the higher the coefficient, the more suitable the chip is for processing the current task.

[0046] For example, assuming that the computing power of chip X1 is 100 billion floating point operations per second (C = 1000), the current load is 50 billion (L = 500), and the task characteristic weight T = 1.5, then: P = 1000 / (500+1.5)≈1.997;

[0047] And the computing power of chip Y1 is 200 billion per second, the current load is 40 billion, and the task characteristic weight is still 1.5, then: P = 200 / (40+1.5)≈4.86;

[0048] Although the overall performance of chip Y1 is lower, its load is lighter, so the distribution coefficient is higher, and it may be more advantageous in some low-power tasks.

[0049] Step S33: calculating the task distribution evaluation value of each chip according to the load distribution coefficient of each chip and the priority weight of the task to be processed, respectively, to obtain N task distribution evaluation values corresponding to N chips;

[0050] It should be noted that after obtaining the load distribution coefficient of each chip, the priority weight W of the task itself is combined to further calculate the task distribution evaluation value Q of each chip, which is used for finally screening M target chips.

[0051] The formula for calculating the task distribution evaluation value is: Q = P x W; wherein P is the load distribution coefficient, and W is the task priority weight (such as between 0.6 and 1.0).

[0052] It should be noted that the evaluation value reflects the comprehensive adaptation ability of the chip under the current task, and the higher the value, the more suitable the chip is as a candidate target.

[0053] For example, assuming that the priority weight W of task A is 0.9, and the load distribution coefficient P of chip X1 is 1.997, then: Q = 1.997 x 0.9≈1.797; P of chip Y1 is 4.86, and W is 0.6, then: Q = 4.86 x 0.6≈2.916.

[0054] Although the computing capability of chip X1 is stronger, the task allocation evaluation value of chip X1 is lower than that of chip Y1 due to the high load, and therefore chip Y1 can be preferentially selected in some low-power-consumption tasks.

[0055] Step S34: determining M chips from the N chips according to the N task allocation evaluation values and a preset evaluation threshold, wherein the task allocation evaluation value of each chip in the M chips is greater than the preset evaluation threshold.

[0056] After obtaining the task allocation evaluation values of all the chips, the system sets a preset evaluation threshold for screening the chips meeting the task requirements.

[0057] For example, the preset threshold is set to 1.5, and all the chips with Q≥1.5 are selected as candidate chips to form the set of M chips.

[0058] For example, it is assumed that there are totally 10 chips in the system, and the task allocation evaluation values of the chips are calculated as shown in Table 1:

[0059] Table 1

[0060]

[0061]

[0062] If the preset evaluation threshold is 1.5, the chips meeting the condition are shown in Table 2:

[0063] Table 2

[0064] Chip number Q value X1 1.797 X2 1.650 X4 2.100 X6 2.916 X8 1.600 X10 1.800

[0065] That is, M=6, and the system selects the most suitable task execution chip from the 6 chips to complete the preliminary task allocation.

[0066] It should be noted that by the above steps S31 to S34, the present application realizes dynamic screening of M chips suitable for executing the current task from the task type, in combination with the computing capability and load state of the chips. The method fully considers multiple dimensions such as task demand, chip performance, load state and task priority, improves the intelligent level of task scheduling, ensures that the task meets the performance demand, avoids chip overload, and improves the overall stability and resource utilization of the system.

[0067] S13, determining a target chip from the M chips according to the task type of the to-be-processed task, and allocating the to-be-processed task to the target chip.

[0068] In an exemplary embodiment, the above step S13 can be implemented by the following steps S41-S43:

[0069] Step S41: Determine the comprehensive score of each chip in the M chips in terms of computing capability and load status;

[0070] It should be noted that in a multi-chip system, the computing capability and current load status of each chip are different. In order to more accurately match the task requirements, the system will first evaluate each chip, taking into account its computing capability and current load status, and give a comprehensive score.

[0071] This score is not simply a performance ranking, but a combination of the computing capability of the chip and the current load status. For example, a chip may have strong performance, but if it is currently carrying a large number of tasks and has a high load, its comprehensive score will not be high. Conversely, a chip with moderate performance but low load may be more suitable for the current task.

[0072] The system will calculate a comprehensive score value for each chip, which will be used for subsequent task matching judgment.

[0073] For example, suppose there are 6 chips available in the system. One of them has very strong performance, but is currently running close to full load; another has slightly lower performance but is currently lightly loaded. The system will take into account both factors and give the chip with strong performance but high load a moderate score and the chip with moderate performance but low load a higher score. This way, it can more reasonably reflect whether the chip is currently suitable for executing a new task.

[0074] Step S42: Determine the reference comprehensive score corresponding to the required chip according to the task type of the task to be processed;

[0075] Different task types have different requirements for chips. For example, some tasks require high-performance chips to complete quickly, while some tasks focus more on low-power operation. Therefore, before determining the target chip, the system will set a "reference comprehensive score" according to the type of the current task.

[0076] This reference score can be understood as a minimum requirement for the chip's ability. Only chips with a comprehensive score that meets or exceeds this reference value are considered suitable for executing the task.

[0077] For example, suppose the current task is an image recognition task that requires high computing power, and the system classifies it as a high-computing-demand task. According to the preset rules, the system will set a relatively high reference comprehensive score, such as 0.75. All chips with a comprehensive score below 0.75 will be excluded, and only chips with a score of 0.75 or above will be retained as candidates.

[0078] If the current task is a low-power data collection task, the system sets a lower reference comprehensive score, such as 0.65, so that more chips can participate in task allocation, especially those with lighter loads and lower energy consumption.

[0079] Step S43: Determine a target chip from the M chips according to the reference comprehensive score and the comprehensive score of each chip in the M chips.

[0080] It should be noted that after obtaining the comprehensive score of each chip and the reference score required by the task, the system will screen all chips whose comprehensive scores meet or exceed the reference score as candidate chips.

[0081] If only one chip meets the condition, it is directly selected as the target chip; if multiple chips meet the condition, the most suitable one is selected to execute the task according to the task priority, load balancing requirement or historical matching situation.

[0082] For example, if there are 6 chips in the system, and the comprehensive scores of 4 of them meet the reference score of the current task. The system will further screen among these 4 chips, such as preferentially selecting the chip with the lowest load and the fastest response, or selecting the chip that has performed the best in the past for similar tasks. Finally, a chip most suitable for the current task is determined to execute the task.

[0083] It should be noted that this selection method ensures the flexibility and efficiency of task allocation, meets the task requirements, avoids overloading some chips, and improves the stability and resource utilization of the entire system.

[0084] Through the above steps S41-S43, the target chip most suitable for executing the current task is dynamically selected from multiple candidate chips according to the task type and chip state. This method not only considers the performance and load state of the chip, but also sets a reasonable screening standard in combination with the task type, improving the intelligent level of task scheduling and helping to realize efficient cooperative control of the multi-chip system.

[0085] The steps S11-S13 are as follows: first, the task type is determined according to the calculation requirement and the power consumption requirement of the to-be-processed task, so as to realize the identification of the task characteristics; then, M currently available chips are selected from N chips according to the task type of the to-be-processed task and the real-time load state of each chip in the multi-chip system; and finally, the most suitable target chip is selected from the M chips according to different task types (such as high calculation requirement type or low power consumption requirement type) to perform task allocation. The method avoids the limitations of the traditional static scheduling strategy, improves the accuracy and adaptability of task scheduling by dynamically matching the task type and the chip running state. From the technical effect, the scheme not only improves the rationality of task scheduling and reduces the task execution delay, but also effectively avoids the waste of chip resources and the risk of overload, improves the utilization rate of the chip and the overall stability of the system.

[0086] In an exemplary embodiment, after the to-be-processed task is allocated to the target chip, the method further comprises: determining a dynamic load distribution curve of an i-th chip in the N chips by the following steps S51-S55:

[0087] Step S51: continuously acquiring the load data of the i-th chip according to a preset acquisition frequency;

[0088] It should be noted that during the task execution process, the system will periodically collect the load data of each chip to master the change of its running state. The acquisition frequency can be set according to the system requirement, for example, collecting once every 5 seconds. This periodic data acquisition method can help the system to master the dynamic performance of the chip during the task execution process and provide basic data for subsequent analysis.

[0089] For example, it is assumed that the system includes two chips Z1 and Z2. The calculation capability of Z1 is stronger, and Z2 is more suitable for low-power tasks. The system sets to collect the load data once every 5 seconds. At a certain time point, the load of Z1 is 60%, and the load of Z2 is 25%. Then, the load is recorded once every 5 seconds, and the collection is continued for 10 times to form a data set including time information and load value.

[0090] Step S52: calculating the load fluctuation amplitude corresponding to the i-th chip according to the load data of the i-th chip and the acquisition frequency, to obtain a load fluctuation data set corresponding to the i-th chip;

[0091] It should be noted that after obtaining the load data at multiple time points, the system calculates the load change amplitude between adjacent time points to obtain the load fluctuation of the chip. The size of the fluctuation amplitude reflects the stability of the chip load. If the fluctuation amplitude is large, it means that the load of the chip changes dramatically, which may face the risk of overload or resource waste.

[0092] For example, continuing with the Z1 chip as an example, the system collects load values in the order of: 60%, 62%, 65%, 58%, 60%. By comparing the values at adjacent time points, the system can calculate the fluctuation amplitude each time: +2%, +3%, -7%, -2%. These values constitute the load fluctuation dataset of the Z1 chip, which is used for subsequent analysis.

[0093] Step S53: In the case where there is a load fluctuation amplitude in the load fluctuation dataset that exceeds a preset threshold, a sliding window method is used to extract the load change trend of the load data of the i-th chip, obtaining a change trend feature set;

[0094] It should be noted that the system will judge the load fluctuation dataset. If it finds that some fluctuation amplitudes exceed the preset threshold (for example, 5%), it means that the load of the chip has changed abnormally and needs to be further analyzed. At this time, the system will use the sliding window method to analyze the data. The sliding window can be set to a fixed length, for example, the last 5 collected data are analyzed each time, and the window content is updated continuously as new data is added.

[0095] In this way, the system can extract the short-term change trend of the chip load, such as whether the load is rising or falling, the change rate, etc., forming a change trend feature set.

[0096] For example, still taking the Z1 chip as an example, there is a -7% fluctuation in its load fluctuation, which exceeds the preset threshold of 5%. The system starts sliding window analysis, setting the window size to 5 collected data. The data in the first window is 60%, 62%, 65%, 58%, 60%, and the system analyzes and finds that the load first rises and then falls, with a slight downward trend as a whole. Subsequently, the window slides and new data is added, and the trend is analyzed again. This trend feature set provides a basis for subsequent prediction.

[0097] Step S54: Using a linear regression method to analyze the change trend feature set to determine the future load prediction value;

[0098] It should be noted that after obtaining the load change trend, the system will use prediction methods such as linear regression to predict the future load of the chip. This prediction can help the system to discover potential overload or resource idle risks in advance, thereby optimizing the task scheduling strategy.

[0099] For example, the system fits a load change curve based on the past 10 load data of Z1 chip combined with the change trend feature set, and predicts that the load of Z1 may drop to 59% in the next 5 seconds. Then the system compares the predicted value with the actual monitored load value (such as 58.5%) to verify the accuracy of the prediction. Through this prediction mechanism, the system can adjust the task allocation in advance to avoid chip overload or resource waste.

[0100] Step S55: generating a dynamic load distribution curve of the i-th chip according to the future load prediction value and the real-time monitored load data of the i-th chip.

[0101] It should be noted that after obtaining the prediction value and real-time data, the system combines the two to generate a visual dynamic load distribution curve. This curve can intuitively show the historical changes and future trends of the chip load. Through the visualization tool, the system can more intuitively grasp the running state of the chip and provide a graphical reference for subsequent task scheduling.

[0102] For example, the system combines the real-time load data of Z1 chip with the prediction value to draw a dynamic load distribution curve. The curve shows that the load of Z1 fluctuates around 60% and has a slight downward trend. While the load curve of Z2 shows that its load is stable at about 25%. Through these curves, the system can determine that Z1 is more suitable for continuing to perform high-computing-demand tasks, while Z2 is more suitable for low-power tasks, thereby optimizing the overall task allocation strategy.

[0103] It should be noted that through the above S51 to S55, the application realizes dynamic monitoring of the running state of the chip and prediction of the load trend. This method not only can grasp the load change of the chip in real time, but also can provide forward-looking decision basis for task scheduling through trend analysis and prediction. At the same time, through the visual display of the dynamic load distribution curve, the observability and controllability of the system are enhanced.

[0104] In one exemplary embodiment, the method further comprises the following steps S61-S64:

[0105] Step S61: in the case where it is determined according to the dynamic load distribution curve of the target chip that the load of the target chip after a preset time is greater than a load balancing threshold, determining Q chips from N-1 chips in the multi-chip system according to the task type of the to-be-processed task and the computing ability and load state of each chip in the N-1 chips, wherein Q is a positive integer not greater than N-1, and the N-1 chips are chips other than the target chip in the N chips;

[0106] Step S62: determining a switching chip from the Q chips according to the task type of the to-be-processed task.

[0107] Step S63: determining resource overhead of switching the to-be-processed task from the target chip to the switching chip;

[0108] Step S64: switching the to-be-processed task from the target chip to the switching chip when the resource overhead meets preset conditions.

[0109] It should be noted that the system continuously collects and analyzes real-time load data of each chip, and generates a dynamic load distribution curve of the chip through time series analysis. Through the curve, the system can predict the load change trend of the chip in the future. If the prediction result shows that the load of the target chip at a certain time point in the future (for example, 10 seconds later) will exceed the preset load balancing threshold, it means that the chip will face an overload risk. At this time, the system will select Q chips as candidate switching chips from the remaining N-1 chips according to the task type of the current task, the computing power and load state of each chip.

[0110] For example, assuming that there are 3 chips in the system: Z1 (high performance), Z2 (medium performance), and Z3 (low power consumption). The current task is assigned to Z1 for execution. Through dynamic load distribution curve analysis, the system predicts that Z1 will have a load exceeding 85% (the set load balancing threshold) in 5 seconds, which is an overload risk.

[0111] At this time, the system selects chips suitable for the current task from Z2 and Z3. If the current task is a high-computing-demand task, Z2 may become a candidate; if it is a low-power-consumption task, Z3 may also be selected. Finally, the system may select Z2 as the candidate switching chip.

[0112] After determining the switching chip, the system evaluates the resource overhead required for migrating the task from the current target chip to the switching chip. This includes: data transmission delay; task state synchronization overhead; communication cost between chips; and task interruption time caused by the switching process. These overheads are comprehensively evaluated to determine whether the task migration is "worth performing".

[0113] For example, assuming that the task is migrated from Z1 to Z2, data transmission through an intermediate buffer area is required, with an expected delay of 2 seconds and a task interruption time of 0.5 seconds. The system considers that the overhead is within an acceptable range, so it determines that the migration is feasible. During the task switching process, the system synchronizes the task state through the SPI interface to ensure that the task can continue to execute seamlessly on the new chip. After the switching is completed, the system updates the task allocation state and continues to monitor the load change of the new target chip.

[0114] Through S61 to S64, the dynamic identification of the chip overload risk in the task execution process and the task switching mechanism are realized. The mechanism can not only predict the load change trend in advance, but also intelligently evaluate the migration overhead, ensure that the task is dynamically migrated without excessively affecting the system performance, and thus improve the stability, resource utilization and task response efficiency of the system.

[0115] In an exemplary embodiment, after the to-be-processed task is allocated to the target chip, the method further comprises: determining a distribution delay of a target instruction and a response speed of the target chip in response to the target instruction, wherein the target instruction is used to indicate that the to-be-processed task is allocated to the target chip; and optimizing a sending priority of the instruction sent to the target chip according to the distribution delay and the response speed.

[0116] It should be noted that in the task scheduling process, the system generates cooperative control instructions for controlling task allocation, and sends these instructions to the target chip. Due to the communication delay between chips, different load states and processing capacity differences, there will be a certain distribution delay between the generation of the instruction and the actual execution of the instruction. At the same time, after the target chip receives the instruction, it will respond and execute the instruction according to its current load state and performance, and the speed of this process is the response speed of the chip.

[0117] The system collects and records the instruction receiving time, execution time and response state of each chip through a communication mechanism such as SPI interface, so as to calculate the distribution delay of each instruction and the response speed of the corresponding chip.

[0118] For example, assume that there are three chips X, Y and Z in the system: chip X has the strongest performance and the fastest response speed, with an average response time of 1 second; chip Y has medium performance, with a response time of 2 seconds; and chip Z has lower performance, with a response time of 3 seconds.

[0119] The system sends a task allocation instruction to chip X, and the total time from instruction generation to execution completion is 1.5 seconds, of which 0.5 seconds is the instruction distribution delay and 1 second is the chip response time.

[0120] By continuously collecting these data, the system can establish an instruction distribution delay data set and a chip response speed data set to provide a basis for subsequent optimization.

[0121] After obtaining the instruction distribution delay and the chip response speed, the system will comprehensively consider these two factors to dynamically adjust the sending priority of the instruction. The core goal is to ensure that chips with fast response and low delay are scheduled in time to avoid task accumulation or system instability caused by high delay or low response speed.

[0122] Specifically: for chips with fast response speed and low load, the system will raise the priority of their scheduling instructions, so that they can receive new tasks earlier; for chips with slow response speed and high load, the system will appropriately lower the priority of their scheduling instructions to avoid further burden; if the system detects that a chip frequently has instruction conflicts or response delays within a certain period of time, it will also actively adjust the instruction scheduling frequency and priority of the chip.

[0123] For example, at a certain moment, chip X and chip Y both receive multiple task scheduling instructions. Through conflict detection tools, the system analyzes and finds that under the current load, the instruction conflict probability of chip X is 30%, which exceeds the preset threshold of 20%, indicating that it may face scheduling pressure. At this time, the system will dynamically adjust the instruction priority, for example: preferentially send new task instructions to chip Y because its current load is low and its response is stable; temporarily suspend some instructions sent to chip X or lower its priority and wait for its load to decrease before scheduling. Through this dynamic adjustment mechanism, the system can effectively avoid instruction conflicts and improve overall scheduling efficiency and system stability.

[0124] In an exemplary embodiment, the method further comprises the steps of:

[0125] S71: Extract the task execution time and execution interruption frequency data of each chip from the task allocation execution state to generate a task execution time data set and an execution interruption frequency data set as the basis data for evaluating the chip cooperation state;

[0126] It should be noted that during task execution, the system will continuously collect the task execution state of each chip through communication mechanisms such as SPI interface. These states mainly include: task execution time: the time taken by a chip to complete a task; execution interruption frequency: the number of times a task is interrupted during execution.

[0127] The system organizes these data in chronological order to generate two data sets: a task execution time data set that records the execution time of each chip in different tasks; and an execution interruption frequency data set that records the frequency of interruptions that occur during task execution for each chip.

[0128] These data constitute the basic information for evaluating the chip cooperation state and provide support for subsequent analysis.

[0129] For example, assume that there are three chips A, B, and C in the system, and during a task execution: chip A takes 10 seconds and is interrupted 2 times; chip B takes 15 seconds and is interrupted 3 times; and chip C takes 8 seconds and is interrupted 1 time.

[0130] S72: Based on the task execution duration dataset and the execution interruption frequency dataset, use a statistical analysis tool to calculate the collaboration efficiency between chips, and compare it with the preset collaboration efficiency threshold to determine whether the chip collaboration efficiency meets the standard; if not, generate a chip collaboration efficiency dataset for subsequent task scheduling optimization;

[0131] It should be noted that after obtaining the basic data, the system will use statistical analysis tools to process these data, focusing on analyzing the collaboration efficiency between chips. Collaboration efficiency refers to the coordination of task completion time, interruption frequency, and task switching during the process of multiple chips working together to complete a task.

[0132] The system will set a collaboration efficiency threshold (e.g. 80%) and compare it with the actual calculated collaboration efficiency to determine whether the current system collaboration state meets the requirements. If the collaboration efficiency is lower than the threshold, it means that there are problems in the coordination of task collaboration between chips, such as: a certain chip has a long task execution time; a certain chip frequently interrupts, affecting the overall progress; task switching between chips is not timely, etc.

[0133] At this time, the system will generate a chip collaboration efficiency dataset to record which chips perform poorly in which tasks, providing optimization basis for subsequent task scheduling.

[0134] For example, the collaboration efficiency of chips A, B, and C is 75%, which is lower than the set threshold of 80%. Further analysis shows that chip B has a high interruption frequency and long task execution time, which slows down the overall task progress. The system generates a chip collaboration efficiency dataset accordingly, recording that chip B has performance bottlenecks in this task.

[0135] S73: According to the chip collaboration efficiency dataset, use a data comparison tool to analyze the resource allocation accuracy, if the resource allocation accuracy is lower than the preset accuracy threshold, adjust the task allocation balance, generate a resource allocation accuracy dataset, and generate a task execution completion report combining the task allocation execution state, and feedback to the task scheduling module to optimize the subsequent task allocation strategy.

[0136] It should be noted that after obtaining the chip collaboration efficiency data, the system will further analyze the resource allocation accuracy of the current task allocation. Resource allocation accuracy refers to whether the task is reasonably allocated to the most suitable chip for execution.

[0137] The system will set a resource allocation accuracy threshold (e.g. 85%) and compare it with the actual analysis result. If the accuracy is lower than the threshold, it means that there are unreasonable phenomena in the current task allocation, such as: a high-performance chip is allocated a low-load task; a low-performance chip is allocated a high-load task; a chip has a high load, and other chips have a low load.

[0138] At this point, the system will adjust its task allocation strategy, such as shifting some tasks from high-load chips to low-load chips, to improve the overall system's task execution efficiency. The system will generate a resource allocation precision dataset and, combined with status information during task execution (such as execution time and number of interrupts), generate a task completion report. This report will be fed back to the task scheduling module to optimize the next round of task allocation strategy.

[0139] For example, system analysis revealed that the resource allocation accuracy was only 78%, lower than the standard of 85%. Further comparison showed that chip C had a low load, while chip B had an excessively high load. Therefore, the system transferred some tasks from chip B to chip C and generated a resource allocation accuracy dataset and a task completion report. The report detailed the task execution status, collaboration efficiency, and resource allocation status of each chip and fed back to the scheduling module, providing optimization suggestions for the next round of task allocation.

[0140] Reference Figure 2 The second embodiment of the present invention provides a multi-chip collaborative control device based on SPI, comprising:

[0141] The first determining module 202 is used to determine the task type of the task to be processed, wherein the task type of the task to be processed is used to reflect the computing requirements and power consumption requirements of the task to be processed.

[0142] The second determining module 204 is used to determine M chips from the N chips according to the task type of the task to be processed, the computing power and load status of each chip in the N chips of the multi-chip system, where N is an integer greater than or equal to 2, M is a positive integer not greater than N, and the N chips communicate with each other using a serial peripheral interface SPI.

[0143] The third determining module 206 is used to determine the target chip from the M chips according to the task type of the task to be processed, and to assign the task to be processed to the target chip.

[0144] The aforementioned device first determines the task type based on the computational and power consumption requirements of the task to be processed, thus identifying the task characteristics. Then, based on the task type and the real-time load status of each chip in the multi-chip system, it selects M currently available chips from N chips. Finally, based on different task types (such as high computational demand or low power consumption demand), it selects the most suitable target chip from the M chips for task allocation. This method avoids the limitations of traditional static scheduling strategies, improving the accuracy and adaptability of task scheduling by dynamically matching task type with chip operating status. From a technical perspective, this scheme not only improves the rationality of task scheduling and reduces task execution latency, but also effectively avoids the waste of chip resources and the risk of overload, improving chip utilization and the overall stability of the system.

[0145] It should be noted that the SPI-based multi-chip collaborative control device provided in this embodiment of the invention is used to execute all the process steps of the SPI-based multi-chip collaborative control method in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0146] This invention also provides an electronic device. The electronic device includes a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps described in the embodiments of the above-described SPI-based multi-chip cooperative control method, for example... Figure 1 The step S11 shown. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the above-described device embodiments, such as the first determining module.

[0147] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0148] The electronic device may be a desktop computer, laptop, handheld computer, or smart tablet, etc. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the above components are merely examples of electronic devices and do not constitute a limitation on the electronic device. It may include more or fewer components than described above, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0149] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the electronic device, connecting all parts of the electronic device via various interfaces and lines.

[0150] The memory can be used to store the computer programs and / or modules. The processor implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory and by calling data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, RAM, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0151] Wherein, if the modules / units integrated in the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0152] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0153] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A multi-chip cooperative control method based on SPI, characterized in that, include: Determine the task type of the task to be processed, wherein the task type of the task to be processed is used to reflect the computing and power consumption requirements of the task to be processed; Based on the task type of the task to be processed, the computing power and load status of each of the N chips in the multi-chip system, M chips are determined from the N chips, where N is an integer greater than or equal to 2, and M is a positive integer not greater than N. The N chips communicate with each other using a serial peripheral interface (SPI). The target chip is determined from the M chips according to the task type of the task to be processed, and the task to be processed is assigned to the target chip.

2. The method according to claim 1, characterized in that, The process of determining the task type to be processed includes: Determine the task data of the task to be processed based on the calculation request; The computational intensity and power consumption requirements of the task to be processed are determined based on the task data. Based on preset classification rules, the task type of the task to be processed is determined according to the computational intensity and power consumption requirements of the task to be processed.

3. The method according to claim 1, characterized in that, The step of determining M chips from the N chips based on the task type of the task to be processed, the computing power and load status of each chip in the multi-chip system, includes: The task feature weights of the task to be processed are determined based on the task type of the task to be processed. The load allocation coefficient of each chip is calculated based on the task feature weight, the computing power of each chip in the N chips of the multi-chip system, and the load status. The task allocation evaluation value of each chip is calculated based on the load allocation coefficient of each chip and the priority weight of the task to be processed, so as to obtain N task allocation evaluation values ​​corresponding to N chips. Based on the N task allocation evaluation values ​​and a preset evaluation threshold, M chips are determined from the N chips, wherein the task allocation evaluation value of each of the M chips is greater than the preset evaluation threshold.

4. The method according to claim 1, characterized in that, The step of determining the target chip from the M chips according to the task type of the task to be processed, and assigning the task to the target chip, includes: Determine the comprehensive score of each of the M chips in terms of computing power and load status; Determine the reference comprehensive score corresponding to the required chip based on the task type of the task to be processed; The target chip is determined from the M chips based on the reference comprehensive score and the comprehensive score of each of the M chips.

5. The method according to claim 1, characterized in that, After assigning the task to be processed to the target chip, the method further includes: The dynamic load distribution curve of the i-th chip among the N chips is determined by the following method: The load data of the i-th chip is continuously acquired according to a preset acquisition frequency; The load fluctuation amplitude corresponding to the i-th chip is calculated based on the load data of the i-th chip and the acquisition frequency to obtain the load fluctuation dataset corresponding to the i-th chip; If there is a load fluctuation amplitude in the load fluctuation dataset that exceeds a preset threshold, the load change trend of the load data of the i-th chip is extracted using the sliding window method to obtain the change trend feature set. The trend feature set is analyzed using linear regression to determine the future load forecast. The dynamic load distribution curve of the i-th chip is generated based on the predicted future load value and the real-time monitored load data of the i-th chip.

6. The method according to claim 5, characterized in that, The method further includes: If, based on the dynamic load distribution curve of the target chip, it is determined that the load of the target chip is greater than the load balancing threshold after a preset time, Q chips are determined from the N-1 chips according to the task type of the task to be processed, the computing power and load status of each chip in the N-1 chips of the multi-chip system, where Q is a positive integer not greater than N-1, and the N-1 chips are the chips other than the target chip among the N chips; The switching chip is determined from the Q chips based on the task type of the task to be processed; Determine the resource overhead of switching the task to be processed from the target chip to the switching chip; When the resource overhead meets the preset conditions, the task to be processed is switched from the target chip to the switching chip.

7. The method according to claim 1, characterized in that, After assigning the task to be processed to the target chip, the method further includes: Determine the distribution delay of the target instruction and the response speed of the target chip in response to the target instruction, wherein the target instruction is used to instruct the task to be processed to be assigned to the target chip; The sending priority of instructions sent to the target chip is optimized based on the distribution delay and the response speed.

8. A multi-chip collaborative control device based on SPI, characterized in that, include: The first determining module is used to determine the task type of the task to be processed, wherein the task type of the task to be processed is used to reflect the computing requirements and power consumption requirements of the task to be processed. The second determining module is used to determine M chips from the N chips based on the task type of the task to be processed, the computing power and load status of each chip in the N chips of the multi-chip system, where N is an integer greater than or equal to 2, and M is a positive integer not greater than N. The N chips communicate with each other using a serial peripheral interface SPI. The third determining module is used to determine the target chip from the M chips according to the task type of the task to be processed, and to assign the task to be processed to the target chip.

9. An electronic device, characterized in that, The system includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements a multi-chip cooperative control method based on SPI as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform a multi-chip cooperative control method based on SPI as described in any one of claims 1 to 7.

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