A performance analysis method, device, equipment, storage medium and program product

Abstract

The application relates to the computer technical field, and in particular to a performance analysis method and device, equipment, a storage medium and a program product. The method comprises the following steps: receiving an instruction to be executed; acquiring access data of the instruction at a memory bank level. The access data represents relevant information of a memory bank in which the instruction is mapped into a primary instruction cache when a general-purpose computing graphics processor initiates access to the primary instruction cache. The processing capacity of the primary instruction cache is determined according to the access data. The processing capacity of the primary instruction cache represents the comprehensive efficiency in a data processing process when the primary instruction cache responds to instruction access of the general-purpose computing graphics processor. The performance of the primary instruction cache is analyzed according to the processing capacity of the primary instruction cache, and the abnormal reason of the primary instruction cache is determined. The method can accurately determine the abnormal reason of the primary instruction cache.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a performance analysis method, apparatus, device, storage medium, and program product. Background Technology

[0002] With the widespread application of general-purpose computing on graphics processing units (GPGPUs), existing performance analysis methods for GPGPUs, such as the NVIDIA Compute Utility (NCU) and traditional cache performance analysis methods, mostly focus on macro-level metrics. When a GPGPU experiences a performance bottleneck, it cannot accurately determine the cause of the anomaly. Summary of the Invention

[0003] This application provides a performance analysis method, apparatus, device, storage medium, and program product for accurately determining the causes of anomalies in the Level 1 instruction cache.

[0004] In a first aspect, embodiments of this application provide a performance analysis method, the method comprising:

[0005] Receive instructions to be executed;

[0006] Retrieve access data at the memory level for instructions. The access data represents the relevant information of the instructions being mapped to the memory in the Level 1 instruction cache when the general-purpose computing graphics processor initiates an access to the Level 1 instruction cache.

[0007] The processing capacity of the Level 1 instruction cache is determined based on the access data. The processing capacity of the Level 1 instruction cache represents the overall efficiency of the Level 1 instruction cache in the data processing process when it is handling instruction access from a general-purpose computing graphics processor.

[0008] Based on the processing capacity of the L1 instruction cache, a performance analysis of the L1 instruction cache is conducted to determine the cause of L1 instruction cache anomalies.

[0009] Compared to existing instruction cache metric systems, this application uses storage-level access data to determine different metrics, enabling finer-grained micro-performance analysis. This allows for precise identification of the causes of anomalies in the first-level instruction cache, facilitating more accurate optimization based on these causes. Furthermore, by performing performance analysis during the instruction data processing phase, this application can adapt to the performance analysis needs of different architectures and application scenarios.

[0010] Optionally, the access data includes first information, second information, and third information, wherein the first information is used to quantify the cumulative number of behaviors of the L1 instruction cache at each stage of data processing, the second information is used to represent the state and load of the storage, and the third information is used to represent the performance output of the L1 instruction cache.

[0011] The above method obtains access data at different levels, which facilitates more accurate and detailed performance analysis based on the access data.

[0012] Optionally, the metrics used to represent processing capabilities include any one of the first metric, the second metric, and the third metric, wherein the first metric represents the ability of the Level 1 instruction cache to receive and carry instruction requests from the general-purpose computing graphics processor, the second metric represents the request hit and data retrieval efficiency of the Level 1 instruction cache, and the third metric represents the data output and link transmission performance of the Level 1 instruction cache.

[0013] In the above method, the processing capacity of the first-level instruction cache is represented by indicators of different dimensions during the data processing process, which makes it easier to determine the cause of the anomaly in a more refined way in the subsequent implementation.

[0014] Optionally, the above determination of the processing capacity of the first-level instruction cache based on access data specifically includes:

[0015] The first indicator is determined based on the cumulative data from the data reception phase in the first information.

[0016] Alternatively, the second indicator can be determined based on the cumulative data from the data retrieval phase in the first information.

[0017] Alternatively, the second indicator can be determined based on the data in the storage unit related to data retrieval in the second information;

[0018] Alternatively, the third indicator can be determined based on the performance output data related to the data return in the third information.

[0019] In the above method, performance indicators are determined based on the data received during the data reception stage, the data retrieved during the data retrieval stage, and the data returned during the data return stage. This facilitates the subsequent accurate quantitative evaluation of the operational status of each stage of data transmission and micro-level performance analysis.

[0020] Optionally, performance analysis of the Level 1 instruction cache can be performed based on its processing capacity to determine the causes of any anomalies. This includes:

[0021] If the first indicator meets the preset rules, it is determined that the first-level instruction cache data reception link is abnormal.

[0022] If the second indicator meets the preset rules, it is determined that the first-level instruction cache data retrieval link is abnormal.

[0023] If the third indicator meets the preset rules, it is determined that the first-level instruction cache data return link is abnormal.

[0024] In the above method, the link where the anomaly is located can be determined based on preset rules and indicators, which facilitates accurate identification of the anomaly. At the same time, determining whether an anomaly exists based on preset rules and indicators can simplify the anomaly identification process, quickly locate whether the current state is abnormal, and improve the efficiency of anomaly detection.

[0025] Optionally, the above methods also include:

[0026] If it is determined that the data receiving link of the first-level instruction cache is abnormal, the cause of the abnormality is determined to be frequent thread beam switching or data path blockage in the storage controller to transmit instructions to the first-level instruction cache based on the cumulative data of the data receiving stage in the first information.

[0027] If it is determined that the L1 instruction cache data retrieval link is abnormal, based on the cumulative data of the data retrieval stage in the first information, or the data of the storage bank related to data retrieval in the second information, determine the cause of the abnormality as instruction jitter, or poor instruction layout, or unbalanced load of multiple storage banks, or insufficient prefetch capability, or low bandwidth utilization efficiency of the storage controller.

[0028] If it is determined that the data return link of the first-level instruction cache is abnormal, based on the performance output data related to data return in the third information, the cause of the abnormality is determined to be unbalanced load of multiple instruction schedulers or low bandwidth utilization of the first-level instruction cache.

[0029] In the above method, the cause of the anomaly is determined by the access data obtained at different stages of the data processing. This allows for a more refined determination of the cause of the anomaly from multiple dimensions, which facilitates subsequent precise optimization based on the determined cause of the anomaly.

[0030] Optionally, the first metric mentioned above includes at least one or more of the following: the efficiency of merging instruction requests, the proportion of transmission downtime caused by the queue reaching its capacity limit to the number of active cycles; the second metric includes at least one or more of the following: the miss rate, the average read latency, the utilization rate of each memory bank, the prefetch rate, and the instruction success rate; the second metric includes at least one or more of the following: the average bandwidth and the proportion of the data stream returned by each instruction scheduler to the global data stream.

[0031] The above method, through the multi-dimensional parameters of each indicator, facilitates the subsequent determination of the cause of the anomaly in a more refined manner.

[0032] Secondly, embodiments of this application provide a performance analysis apparatus, the apparatus comprising:

[0033] The transceiver module is used to receive instructions to be executed.

[0034] The transceiver module is also used to obtain access data of instructions at the memory level. The access data represents the relevant information of the instructions being mapped to the memory in the first-level instruction cache when the general-purpose computing graphics processor initiates an access to the first-level instruction cache.

[0035] The processing module is used to determine the processing capacity of the first-level instruction cache based on the access data. The processing capacity of the first-level instruction cache represents the overall efficiency of the first-level instruction cache in the data processing process when it is accessed by the general-purpose computing graphics processor.

[0036] The processing module is also used to perform performance analysis on the level 1 instruction cache based on its processing capacity, and to determine the cause of any abnormalities in the level 1 instruction cache.

[0037] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the processor implements any of the methods described in the first aspect above.

[0038] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the methods in the first aspect.

[0039] Fifthly, embodiments of this application also provide a computer program product, including a computer program that is executed by a processor to implement any of the methods described in the first aspect above.

[0040] The technical effects of any of the implementation methods in aspects two through five can be found in the technical effects of the corresponding implementation methods in aspect one, and will not be repeated here. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating a performance analysis method provided in this application embodiment;

[0043] Figure 2 A schematic diagram illustrating a distribution instruction request provided in an embodiment of this application;

[0044] Figure 3A schematic diagram illustrating another distribution instruction request provided in an embodiment of this application;

[0045] Figure 4 A schematic diagram illustrating another distribution instruction request provided in an embodiment of this application;

[0046] Figure 5 A schematic diagram illustrating another distribution instruction request provided in an embodiment of this application;

[0047] Figure 6 This is a schematic diagram of data retrieval provided in an embodiment of this application;

[0048] Figure 7 A schematic diagram illustrating a data return method provided in an embodiment of this application;

[0049] Figure 8 This is a schematic diagram of a performance analysis structure provided in an embodiment of this application;

[0050] Figure 9 This is a schematic diagram of the structure of a performance analysis device provided in an embodiment of this application. Detailed Implementation

[0051] The following explanations of some terms used in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0052] 1. A general-purpose computing on graphics processing unit (GPGPU) is a computer chip that uses a graphics processing unit to perform general-purpose computing tasks.

[0053] 2. Static Random-Access Memory (SRAM) is a type of random access memory. "Static" means that as long as this type of memory is powered on, the data stored within it will remain constant.

[0054] 3. Instruction cache: The instruction cache is an important component of the CPU cache, belonging to the L1 cache. Together with the data cache, it forms the processor's storage subsystem, used to temporarily store instruction data read from main memory. A hierarchical mechanism prioritizes access to instructions in the cache, reducing the number of accesses to main memory.

[0055] 4. "Multiple" refers to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C. Similarly, the understanding of descriptions such as "at least one" is similar. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0056] 5. In the embodiments of this application, the ordinal numbers such as "first" and "second" are used to distinguish multiple objects, and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the priority or importance of these two thresholds.

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] The application scenarios described in this application are for the purpose of more clearly illustrating the technical solutions of this application, and do not constitute a limitation on the technical solutions provided in this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided in this application are also applicable to similar technical problems. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0059] Driven by the digital wave, general-purpose graphics processing units (GPUs) widely support high-performance computing scenarios such as deep learning, scientific computing, and big data processing. While existing performance analysis techniques for GPUs, such as instruction cache metrics and traditional cache performance analysis methods, provide a foundation for performance analysis, they still have significant limitations. The macroscopic metrics of current technologies struggle to capture the fine-grained behavior within the instruction cache, making it difficult to accurately pinpoint the cause of performance bottlenecks in GPUs.

[0060] To address the aforementioned problems, this application provides a performance analysis method, which includes: receiving an instruction to be executed; obtaining access data of the instruction at the memory level. The access data represents information about how the instruction is mapped to a bank in the Level 1 instruction cache when the general-purpose graphics processor (GPU) initiates an access to the Level 1 instruction cache; determining the processing capability of the Level 1 instruction cache based on the access data, whereby the processing capability of the Level 1 instruction cache represents its overall performance in data processing when handling instruction access from the GPU; and performing performance analysis on the Level 1 instruction cache based on its processing capability to determine the causes of any anomalies in the Level 1 instruction cache.

[0061] Compared to existing instruction cache metric systems, this application uses storage-level access data to determine different metrics, enabling finer-grained micro-performance analysis. This allows for precise identification of the causes of anomalies in the first-level instruction cache, facilitating more accurate optimization based on these causes. Furthermore, by performing performance analysis during the instruction data processing phase, this application can adapt to the performance analysis needs of different architectures and application scenarios.

[0062] It is understood that either a terminal or a server can be used to implement the performance analysis determination method provided in this application embodiment. In this application embodiment, the server can be a standalone server or a server cluster consisting of multiple servers. The terminal can be various electronic devices with a display screen and support web browsing, including but not limited to smartphones, tablets, desktop computers, etc.

[0063] The following explanation uses the performance analysis method provided in this application as an example, implemented by a terminal. Figure 1 As shown, this application provides a flowchart of a performance analysis method.

[0064] Step S101: Receive the instruction to be executed.

[0065] Step S102: Obtain the access data of the instruction at the memory level.

[0066] The access data represents information about how instructions are mapped to storage in the Level 1 instruction cache when a general-purpose computing graphics processor initiates an access to the Level 1 instruction cache.

[0067] The access data may include first information, second information, and third information. The first information quantifies the cumulative behavior of the Level 1 instruction cache at each stage of data processing. The first information includes one or more of the following: number of active cycles, number of first cycles, number of second cycles, number of third cycles, number of misses, total number of accesses, first duration, number of valid read requests, and number of bytes returned by the storage controller to the Level 1 instruction cache. The second information indicates the status and load of the storage units. The second information includes at least the number of instruction requests sent by the general-purpose graphics processor to each storage unit in the Level 1 instruction cache. The third information indicates the performance output of the Level 1 instruction cache. The third information includes one or more of the following: the traffic returned by the Level 1 instruction cache to the instruction scheduler via the return interface (Ret) and the number of bytes returned by the Level 1 instruction cache to the instruction scheduler.

[0068] Step S103: Determine the processing capacity of the first-level instruction cache based on the access data.

[0069] The processing capacity of the Level 1 instruction cache represents the overall performance of the Level 1 instruction cache in the data processing process when it is accessed by instructions from a general-purpose computing graphics processor.

[0070] Step S104: Perform performance analysis on the L1 instruction cache based on its processing capacity to determine the cause of any L1 instruction cache anomalies.

[0071] The metrics used to represent the processing capability of the Level 1 instruction cache include any one of the first, second, and third metrics. Specifically, the first metric represents the Level 1 instruction cache's ability to receive and process instruction requests from the general-purpose graphics processing unit (GPU); the second metric represents the Level 1 instruction cache's request hit and data retrieval efficiency; and the third metric represents the Level 1 instruction cache's data output and link transmission performance.

[0072] The following section explains the parameters included in accessing data, the parameters included in the first, second, and third indicators, and the reasons for anomalies in the first-level instruction cache, based on different stages of the data processing process:

[0073] I. Data Reception Stage

[0074] The terminal can determine the first indicator based on the cumulative data from the data reception phase in the first information. The first indicator includes at least one or more of the following: the efficiency of merging instruction requests, and the proportion of transmission downtime caused by the queue reaching its capacity limit to the number of active cycles.

[0075] In some embodiments, after the terminal receives the instruction to be executed through an external interface, the Central Processing Unit (CPU) parses and schedules the instruction. The CPU transmits the instruction to the General Purpose Graphics Processing Unit (GPGPU). The GPGPU generates an instruction request corresponding to the instruction. The instruction request may include parameters such as instruction access type (read / write), instruction priority identifier, and data length. The GPGPU determines the address mapping relationship between the Level 1 instruction cache and memory, and sends this mapping relationship to the instruction scheduler (Sequence, SQ). The instruction scheduler distributes the instruction request to the corresponding memory interface based on the address mapping relationship. For example, such as... Figure 2 As shown in the figure, this application embodiment provides a schematic diagram of a distribution instruction request. Figure 2 The first-level instruction cache includes memory bank 0, memory bank 1, memory bank 2, and memory bank 3. The instruction dispatcher can distribute instruction requests to each memory bank, such as memory bank 0.

[0076] When the instruction dispatcher distributes instruction requests to the tag buffer, it can first determine which instruction requests can be merged. For example, if multiple instruction requests access contiguous memory addresses or belong to the same computation task, the instruction dispatcher can package these multiple instruction requests into a single merge request before distributing them together. In this way, the tag buffer only needs to process one request to complete the operation of multiple instructions, avoiding individual responses, thus reducing processing times and data transfer overhead. For instruction requests with non-contiguous addresses and unrelated tasks, the instruction dispatcher can process them as non-mergeable requests and distribute them individually. Mergeable requests are subsets of instruction requests. Non-mergeable requests are subsets of instruction requests.

[0077] To evaluate the scheduling efficiency of a warp, the terminal can obtain the number of merge cycles and the number of active cycles. The number of merge cycles represents the number of cycles required to merge merge requests from at least two threads into a single transaction. The number of active cycles represents the number of cycles in which the L1 instruction cache is active. The terminal can determine the merge efficiency based on the number of merge cycles and the number of active cycles. The merge efficiency is the ratio of the number of merge cycles to the number of active cycles. The merge efficiency satisfies the following formula:

[0078]

[0079] in, To improve merging efficiency. This represents the number of merged cycles. This represents the number of active cycles.

[0080] The preset rule for the aforementioned merging efficiency can be to compare the merging efficiency with a first threshold. If the merging efficiency is less than the first threshold, it is determined that the data receiving link of the first-level instruction cache is abnormal, and the reason for the abnormality is frequent thread switching and low instruction hotspot density. For example, assuming the merging efficiency is 4% and the first threshold is 5%. If the merging efficiency is 4%, which is less than the first threshold of 5%, the terminal can determine that the data receiving link of the first-level instruction cache is abnormal, and the reason for the abnormality is frequent thread switching and low instruction hotspot density. It is understood that the aforementioned first threshold is preset by those skilled in the art. The first threshold can be changed according to different application scenarios. For example, the first threshold can be 5%. Or, for example, the first threshold can be 4%. The preset rule in the embodiments of this application is preset by those skilled in the art. The preset rule can be changed according to different application scenarios. For example, the preset rule can be to set different preset rules for different parameters, such as comparing parameter values ​​with thresholds.

[0081] In the above method, frequent thread switching and low instruction hotspot density are determined by merging efficiency, which can accurately identify the root cause of the performance problem and facilitate subsequent optimization based on the performance problem.

[0082] In other embodiments, the instruction dispatcher can distribute multiple instruction requests to a tag buffer. The tag buffer determines whether an instruction request has been matched. For example, such as... Figure 3 As shown, Figure 3 This is a schematic diagram illustrating another distribution instruction request provided in an embodiment of this application. Figure 3 If an instruction request hits, it can retrieve data from Static Random Access Memory (SRAM). In other embodiments, if an instruction request misses, it first enters a miss queue (Miss Fifo). This miss queue stores missed instruction requests. After waiting for a period of time, instruction requests in the miss queue are transferred to a pending buffer queue for further processing. The miss queue typically has a certain number of empty slots to temporarily store missed instruction requests. For example, Figure 3 The missed instruction queue has 15 empty slots. The pending buffer queue also has 15 empty slots. When a missed instruction request needs to be temporarily stored in the missed instruction queue, the general-purpose computing graphics processor (GPU) first checks if there are any empty slots in the missed instruction queue. If there are empty slots, the missed instruction request can enter the missed instruction queue to wait for processing. If the 15 empty slots are full, subsequent missed requests cannot enter the missed instruction queue, causing instruction stalling and affecting the processing efficiency of the GPU. In some embodiments, instruction requests can be directly temporarily stored in the pending buffer queue.

[0083] To promptly determine the congestion status of the aforementioned queues, the terminal can also obtain the first cycle count. The first cycle count represents the number of stalled cycles caused when an instruction request misses an instruction in the Level 1 instruction cache, preventing entry into the miss queue due to it reaching its capacity limit. The terminal determines a first percentage based on the first cycle count and the number of active cycles. The first percentage is the proportion of the first cycle count to the number of active cycles. The first percentage satisfies the following formula:

[0084]

[0085] in, It accounts for the largest proportion. This is the number of the first cycle. This represents the number of active cycles.

[0086] The preset rule for the aforementioned first percentage can be to compare the first percentage with a second threshold. If the first percentage is greater than the second threshold, it is determined that the data reception link of the first-level instruction cache is abnormal, and the reason for the abnormality is frequent thread switching of the code corresponding to the instruction. For example, suppose the first percentage is 8%. The second threshold can be 5%. If the first percentage of 8% is greater than the second threshold of 5%, the terminal can determine that the data reception link of the first-level instruction cache is abnormal, and the reason for the abnormality is frequent thread switching of the code corresponding to the instruction. It is understood that the aforementioned second threshold is preset by those skilled in the art. The second threshold can be changed according to different application scenarios. For example, the second threshold can be 5%. Or, for example, the second threshold can be 4%.

[0087] Optionally, the terminal can also obtain a second cycle count. The second cycle count represents the number of pause cycles caused by the suspended buffer queue reaching its capacity limit. The terminal determines a second percentage based on the active cycle count and the second cycle count. The second percentage represents the proportion of the second cycle count to the total active cycle count. The second percentage satisfies the following formula:

[0088]

[0089] in, It is the second largest proportion. This is the number of the second cycle. This represents the number of active cycles.

[0090] The preset rules for the aforementioned first and second percentages can be to compare them with a third threshold. If the first percentage is greater than the third threshold, and the second percentage is also greater than the third threshold, then the data reception link of the first-level instruction cache is determined to be abnormal. The cause of the abnormality is frequent thread switching and a lack of concentration of hot instructions. For example, suppose the third threshold is 5%, the first percentage is 6%, and the second percentage is 7%. If both the first percentage (6%) and the second percentage (%) are greater than the third threshold (5%), then the terminal can determine that the data reception link of the first-level instruction cache is abnormal, and the cause of the abnormality is frequent thread switching and a lack of concentration of hot instructions. It is understood that the aforementioned third threshold is preset by those skilled in the art. The third threshold can be changed according to different application scenarios. For example, the third threshold can be 5%. Or, for example, the third threshold can be 4%.

[0091] The preset rules for the aforementioned first and second percentages can also be to compare the first percentage with a fourth threshold and the second percentage with a fifth threshold. If the first percentage is less than the fourth threshold and the second percentage is greater than the fifth threshold, then it is determined that the data reception link of the Level 1 instruction cache is abnormal. The cause of the abnormality is that the data path from the Large-scale Storage Controller (LSC) to the Level 1 instruction cache is blocked. For example, suppose the fourth threshold is 2%, the fifth threshold is 7%, the first percentage is 1%, and the second percentage is 8%. If the first percentage of 1% is less than the fourth threshold of 2% and the second percentage of 8% is greater than the fifth threshold of 7%, then the terminal can determine that the data reception link of the Level 1 instruction cache is abnormal, and the cause of the abnormality is that the data path from the storage controller to the Level 1 instruction cache is blocked. It is understood that the aforementioned fourth and fifth thresholds are preset by those skilled in the art. The fourth and fifth thresholds can be changed according to different application scenarios. For example, the fourth threshold can be 5% and the fifth threshold can be 8%. Or, for another example, the fourth threshold can be 2% and the fifth threshold can be 9%.

[0092] Optionally, the terminal can also obtain a third cycle count. The third cycle count represents the number of stalled cycles caused by the pending buffer queue reaching its capacity limit, preventing the processing of newly added instructions output in the waiting queue from being processed. The terminal determines a third percentage based on the active cycle count and the third cycle count. The third percentage represents the proportion of the third cycle count to the active cycle count. The third percentage satisfies the following formula:

[0093]

[0094] in, It accounts for the third largest share. This is the number of the third cycle. This represents the number of active cycles.

[0095] The preset rule for the aforementioned third percentage can be to compare the third percentage with a sixth threshold. If the third percentage is greater than the sixth threshold, it is determined that the data reception link of the Level 1 instruction cache is abnormal, and the reason for the abnormality is that there is a blockage in the data path from the storage controller to the Level 1 instruction cache. For example, suppose the sixth threshold is 5%, and the third percentage is 8%. The third percentage of 8% is greater than the sixth threshold of 5%, then the terminal can determine that the data reception link of the Level 1 instruction cache is abnormal, and the reason for the abnormality is that there is a blockage in the data path from the storage controller to the Level 1 instruction cache. It is understood that the aforementioned sixth threshold is preset by those skilled in the art. The sixth threshold can be changed according to different application scenarios. For example, the sixth threshold can be 5%. Or, for example, the sixth threshold can be 4%.

[0096] It is understandable that the proportion of transmission downtime caused by queues reaching their capacity limits relative to the number of active cycles includes one or more of the first, second, and third proportions mentioned above. Queues include suspended buffer queues and miss waiting queues.

[0097] In the above method, by analyzing queue blocking in a hierarchical manner, the root cause of the abnormal problem can be accurately determined, which facilitates subsequent optimization based on the cause of the abnormality.

[0098] II. Data Retrieval Stage

[0099] The terminal can determine the second indicator based on the cumulative data from the data retrieval phase in the first information. Alternatively, it can determine the second indicator based on the data from the storage units related to data retrieval in the second information. The second indicator includes at least one or more of the following: miss rate, average read latency, utilization rate per storage unit, prefetch rate, and instruction success rate.

[0100] In some embodiments, after the instruction dispatcher distributes an instruction request to the corresponding memory bank, if the memory bank does not find valid data in its own memory unit (i.e., a data miss), the memory bank can report a miss status to the instruction dispatcher. To determine the cache status of instruction requests, the terminal can obtain the number of misses and the total number of accesses. The number of misses represents the number of instruction requests that the general-purpose graphics processor (GPGPU) initiated to the Level 1 instruction cache but missed, and the total number of accesses represents the number of instruction requests sent by the GPGPU to the Level 1 instruction cache. The terminal can determine the miss rate based on the number of misses and the total number of accesses. The miss rate is the percentage of misses to the total number of accesses. Since the Level 1 instruction cache uses a multi-memory parallel storage architecture, each memory bank independently counts the received instruction requests and misses. Therefore, the number of misses is the sum of the number of instruction requests that the GPGPU initiated to the memory bank but missed, and the total number of accesses is the sum of the number of instruction requests sent by the GPGPU to the memory bank. The miss rate satisfies the following formula:

[0101]

[0102] in, This represents the number of instruction requests that the GPGPU sent to memory bank n but were not successfully requested. n is the memory bank number, and n is an integer. Miss rate This represents the number of misses. This represents the total number of visits. This represents the number of instruction requests that the GPGPU sends to memory bank n.

[0103] The preset rule for the aforementioned miss rate can be to compare the miss rate with a seventh threshold. If the miss rate is greater than the seventh threshold, it is determined that the Level 1 instruction cache data retrieval link is abnormal, and the cause of the abnormality is instruction jitter. For example, suppose the miss rate is 11% and the seventh threshold is 10%. The miss rate of 11% is greater than the seventh threshold of 10%, so the terminal can determine that the Level 1 instruction cache data retrieval link is abnormal, and the cause of the abnormality is instruction jitter. It is understood that the aforementioned seventh threshold is preset by those skilled in the art. The seventh threshold can be changed according to different application scenarios. For example, the seventh threshold can be 10%. Or, for example, the seventh threshold can be 13%.

[0104] In the above method, the efficiency of the instruction cache is quantified by the miss rate, which can accurately evaluate the working efficiency of the cache, determine the cause of the first-level instruction cache anomaly, and provide detailed data support for subsequent instruction layout optimization.

[0105] In other embodiments, during the process of the instruction dispatcher distributing instruction requests to the memory, the tag buffer can determine the instruction address of the instruction request to decide whether to retrieve data directly from the memory or read data from the memory controller. For example, as... Figure 4 As shown in the figure, this application embodiment provides another schematic diagram of a distribution instruction request. Figure 4 In this process, when the instruction dispatcher sends an instruction request to the tag buffer, the tag buffer first determines whether the requested instruction can be directly retrieved from the currently associated storage. If the data corresponding to the instruction exists in the storage, the tag buffer will directly route the request to the corresponding storage, completing a fast response. If the instruction is not found in the storage, the tag buffer needs to initiate an instruction read request to the storage controller. At this time, the instruction request is temporarily stored in a queue that can temporarily store instruction requests, waiting for the storage controller to return the instruction data. Since the storage controller's read process is relatively long, the waiting process from the issuance of the request to the return of data will increase the processing delay of the instruction request, thus affecting the overall instruction read efficiency.

[0106] To determine the time efficiency of instruction fetching, the terminal can obtain the first duration and the number of valid fetch requests. The first duration represents the total waiting period caused by non-missing requests among the instruction requests initiated by the general-purpose graphics processor (GPGPU). The number of valid fetch requests is the number of instruction requests issued by the GPGPU that successfully initiated and completed the data fetch operation. The number of valid fetch requests is a subset of all instruction requests issued by the GPGPU. The terminal can determine the average fetch latency based on the first duration and the number of valid fetch requests. The average fetch latency represents the average time consumed by the GPGPU from initiating an instruction request to successfully acquiring data. For example, the terminal can divide the first duration by the number of valid fetch requests to obtain the average fetch latency. The average fetch latency satisfies the following formula:

[0107]

[0108] in, This represents the average read latency. This is the first duration. The number of valid read requests.

[0109] The preset rule for the aforementioned average read latency time can be to compare the average read latency time with an eighth threshold. If the average read latency time is greater than the eighth threshold, then the L1 instruction cache data retrieval link is determined to be abnormal, and the cause of the abnormality is poor instruction layout. For example, suppose the average read latency time is 8%, and the eighth threshold is 5%. The average read latency time of 8% is greater than the eighth threshold of 5%. Then the terminal can determine that the L1 instruction cache data retrieval link is abnormal, and the cause of the abnormality is poor instruction layout. It is understood that the aforementioned eighth threshold is preset by those skilled in the art. The eighth threshold can be changed according to different application scenarios. For example, the eighth threshold can be 5%. Or, for example, the eighth threshold can be 4%.

[0110] In the above method, the efficiency of the instruction cache is quantified by the average read latency, which can accurately evaluate the working efficiency of the cache, determine the cause of anomalies in the first-level instruction cache, and provide detailed data support for subsequent instruction layout optimization.

[0111] In other embodiments, to further determine the balance of memory accesses to the L1 instruction cache, the terminal can obtain the number of instruction requests sent by the general-purpose graphics processor (GPGPU) to each memory bank in the L1 instruction cache. The terminal can determine the utilization rate of each memory bank based on the number of instruction requests sent by the GPGPU to each memory bank in the L1 instruction cache. Here, the memory bank utilization rate represents the load level of the memory bank. Specifically, for any memory bank, the terminal divides the number of instruction requests sent by the GPGPU to that memory bank in the L1 instruction cache by a first data point to obtain the utilization rate of that memory bank. Here, the first data point is the sum of the number of instruction requests sent by the GPGPU to each memory bank in the L1 instruction cache. For example, as... Figure 5 As shown, Figure 5 This is a schematic diagram illustrating another distribution instruction request provided in an embodiment of this application. Figure 5 The Level 1 instruction cache includes memory bank 0, memory bank 1, memory bank 2, and memory bank 3. The instruction dispatcher can distribute instruction requests to each memory bank. The first quantity is the number of instruction requests sent by the general-purpose graphics processor (GPGPU) to memory bank 0. The second quantity is the number of instruction requests sent by the GPGPU to memory bank 1. The third quantity is the number of instruction requests sent by the GPGPU to memory bank 2. The fourth quantity is the number of instruction requests sent by the GPGPU to memory bank 3. For memory bank 2, the terminal can divide the number of instruction requests sent by the GPGPU to memory bank 2 in the Level 1 instruction cache by the first quantity to obtain the utilization rate of memory bank 2. The utilization rate of memory bank 2 satisfies the following formula:

[0112]

[0113] in, The utilization rate of storage unit 2. The number of instruction requests sent by a general-purpose computing graphics processor to all memory locations in the Level 1 instruction cache. The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 0 (first number). The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 1 (second number). The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 2 (third number). The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 3 (fourth quantity).

[0114] The preset rule for the utilization rate of the aforementioned storage units can be to determine the minimum and maximum utilization rates of each storage unit. If the difference between the minimum and maximum utilization rates of each storage unit is greater than a ninth threshold, an anomaly is determined in the L1 instruction cache data retrieval link, the cause of which is an uneven load across multiple storage units. For example, suppose the utilization rate of storage unit 0 is 85%, storage unit 1 is 40%, storage unit 2 is 90%, and storage unit 3 is 35%. The ninth threshold is 10%. Among the utilization rates of each storage unit, the minimum is 35% (storage unit 3) and the maximum is 90% (storage unit 2). The difference between the maximum and minimum is 90% - 35% = 55%. Since the difference between the maximum and minimum is 55%, which is greater than the ninth threshold of 10%, the terminal can determine that the L1 instruction cache data retrieval link is abnormal, the cause of which is an uneven load across multiple storage units. It is understood that the aforementioned ninth threshold is preset by those skilled in the art. The ninth threshold can be changed according to different application scenarios. For example, the ninth threshold can be 5%. Or, for example, the ninth threshold can be 10%.

[0115] The above method analyzes the state and load of memory banks in the L1 instruction cache to achieve memory bank-level usage distribution analysis, which can accurately determine the cause of L1 instruction cache anomalies and provide detailed data support for subsequent instruction layout optimization.

[0116] In other embodiments, to determine whether an anomaly occurred during data retrieval, the terminal can also obtain the number of prefetch requests sent to each memory bank by the Level 1 instruction cache. The terminal can determine the prefetch rate based on the number of instruction requests sent by the general-purpose computing graphics processor to each memory bank in the Level 1 instruction cache and a first set of data. The prefetch rate represents the proportion of prefetched instructions that successfully hit the actual accessed data. Specifically, the terminal can divide the second set of data by the first set of data to determine the prefetch rate. The second set of data is the sum of the number of prefetch requests sent to all memory banks by the Level 1 instruction cache. For example, assuming the Level 1 instruction cache includes memory bank 0, memory bank 1, memory bank 2, and memory bank 3, the prefetch rate satisfies the following formula:

[0117]

[0118] in, This represents the prefetch rate. The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 0. The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 1. The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 2. The number of instruction requests sent by the general-purpose computing graphics processor to memory bank 3. The number of prefetch requests sent to memory bank 0 received by the Level 1 instruction cache. The number of prefetch requests sent to memory bank 1 received by the level 1 instruction cache. The number of prefetch requests sent to memory bank 2 received by the level 1 instruction cache. The number of prefetch requests sent to memory bank 3 received by the Level 1 instruction cache.

[0119] The preset rule for the aforementioned prefetch rate can be to compare the prefetch rate with a tenth threshold. If the prefetch rate is less than the tenth threshold, it is determined that the Level 1 instruction cache data retrieval link is abnormal, and the reason for the abnormality is insufficient utilization of prefetch capacity. For example, assuming the tenth threshold is 5% and the prefetch rate is 3%, then the prefetch rate of 3% is less than the tenth threshold of 5%, and it is determined that the Level 1 instruction cache data retrieval link is abnormal, and the reason for the abnormality is insufficient utilization of prefetch capacity. It is understood that the aforementioned tenth threshold is preset by those skilled in the art. The tenth threshold can be changed according to different application scenarios. For example, the tenth threshold can be 5%. Or, for example, the tenth threshold can be 3%.

[0120] The above method can evaluate the effectiveness of the prefetch strategy by quantifying the proportion and effect of prefetch requests, determine whether the abnormality of the first-level instruction cache is due to insufficient utilization of prefetch capability, and provide detailed data support for subsequent instruction layout optimization.

[0121] In other embodiments, to determine whether an anomaly occurred during data retrieval, the terminal can also obtain the number of bytes returned by the Level 1 instruction cache to the instruction scheduler and the number of bytes returned by the storage controller to the Level 1 instruction cache. The terminal determines the instruction effectiveness rate based on the number of bytes returned by the Level 1 instruction cache to the instruction scheduler and the number of bytes returned by the storage controller to the Level 1 instruction cache. Here, the instruction effectiveness rate represents the utilization rate of the prefetched data. For example, such as... Figure 6 As shown, this application provides a data retrieval diagram. Figure 6 The first byte represents the number of bytes returned by the storage controller to the Level 1 instruction cache. The second byte represents the number of bytes returned by the Level 1 instruction cache to the instruction dispatcher. The terminal can divide the number of bytes returned by the Level 1 instruction cache to the instruction dispatcher by the number of bytes returned by the storage controller to the Level 1 instruction cache to obtain the instruction efficiency. The instruction efficiency satisfies the following formula:

[0122]

[0123] in, This ensures the efficiency of the instruction. This represents the number of bytes returned by the storage controller to the Level 1 instruction cache. The number of bytes returned to the instruction dispatcher from the level 1 instruction cache.

[0124] The preset rule for the above-mentioned instruction effectiveness can be to compare the instruction effectiveness with an eleventh threshold. If the instruction effectiveness is less than the eleventh threshold, it is determined that the Level 1 instruction cache data retrieval link is abnormal, and the cause of the abnormality is low storage controller bandwidth utilization. For example, assuming the eleventh threshold is 80% and the instruction effectiveness is 75%, then the instruction effectiveness of 75% is less than the threshold of 80%, and the terminal can determine that the Level 1 instruction cache data retrieval link is abnormal, and the cause of the abnormality is low storage controller bandwidth utilization. It is understood that the above-mentioned eleventh threshold is preset by those skilled in the art. The eleventh threshold can be changed according to different application scenarios. For example, the eleventh threshold can be 90%. Or, for example, the eleventh threshold can be 85%.

[0125] In the above method, by determining the efficiency of instructions, the frequency of bandwidth usage can be accurately assessed, and whether there is bandwidth waste can be identified.

[0126] III. Data Return Phase

[0127] The terminal can determine the third metric based on the performance output data related to data return in the third information. The third metric includes at least one or more of the following: average bandwidth and the proportion of the data stream returned by each instruction scheduling transmitter to the total global data stream.

[0128] In other embodiments, when returning data traffic, the primary instruction buffer can send the returned data stream to the arbiter. The arbiter transmits the data stream to the instruction scheduling transmitter through the return operation (Ret) channel, completing the data return operation. To determine if there are any anomalies in the data return, the terminal can obtain the traffic (in 32-bit units) returned by the primary instruction buffer to the instruction scheduling transmitter through the return interface. The terminal can determine the traffic share of each instruction scheduling transmitter based on the traffic of each return operation in the instruction scheduling transmitter. Here, the traffic share represents the proportion of the data stream returned by a single instruction scheduling transmitter to the global data stream. Specifically, for any instruction scheduling transmitter, the terminal can divide the first traffic by the second traffic to obtain the traffic share of that instruction scheduling transmitter. Here, the first traffic is the sum of the traffic of return operations in a single instruction scheduling transmitter. The second traffic is the sum of the traffic of return operations in all instruction scheduling transmitters.

[0129] The following example illustrates the traffic percentage mentioned above: For example, ... Figure 7 The diagram shown is a schematic representation of a data return method provided in this application embodiment. Figure 7 In this architecture, the Level 1 instruction cache includes memory bank 0, memory bank 1, memory bank 2, and memory bank 3. The Level 1 instruction cache can send the returned data stream to the arbitrator. The arbitrator transmits the data stream to instruction scheduling transmitters SQ0, SQ1, SQ2, and SQ3 through the return operation channel. The return traffic received by instruction scheduling transmitter SQ0 includes the traffic from the first return operation (Ret0) and the traffic from the second return operation (Ret1) in instruction scheduling transmitter SQ0. The return traffic received by instruction scheduling transmitter SQ1 includes the traffic from the third and fourth return operations in instruction scheduling transmitter SQ1. The return traffic received by instruction scheduling transmitter SQ2 includes the traffic from the fifth and sixth return operations in instruction scheduling transmitter SQ2. The return traffic received by command scheduling transmitter SQ3 includes the traffic from the seventh return operation and the traffic from the eighth return operation in command scheduling transmitter SQ3. The second traffic then satisfies the following formula:

[0130]

[0131] in, This is the second flow rate. The traffic for the first return operation in the instruction scheduling transmitter SQ0. The traffic for the second return operation in the instruction scheduling transmitter SQ0. The traffic for the third return operation in the instruction scheduling transmitter SQ1. The traffic for the fourth return operation in the instruction scheduling transmitter SQ1. The flow of the fifth return operation in the instruction scheduling transmitter SQ2. The traffic for the sixth return operation in the instruction scheduling transmitter SQ2. For the flow of the seventh return operation in the instruction scheduling transmitter SQ3. For the flow of the eighth return operation in the instruction scheduling transmitter SQ3.

[0132] The traffic share of the instruction scheduling transmitter SQ0 satisfies the following formula:

[0133]

[0134] in, This represents the traffic percentage of the instruction scheduling transmitter SQ0. This represents the first flow of the return operation in the instruction scheduling transmitter SQ0. This is the second flow rate.

[0135] The traffic share of the instruction scheduling transmitter SQ1 satisfies the following formula:

[0136]

[0137] in, The traffic percentage for the instruction scheduling transmitter SQ1. This represents the first flow of the return operation in the instruction scheduling transmitter SQ1. This is the second flow rate.

[0138] The traffic share of the command scheduling transmitter SQ2 satisfies the following formula:

[0139]

[0140] in, This represents the traffic percentage of the instruction scheduling transmitter SQ2. This represents the first flow of the return operation in the instruction scheduling transmitter SQ2. This is the second flow rate.

[0141] The traffic share of the command scheduling transmitter SQ3 satisfies the following formula:

[0142]

[0143] in, This represents the traffic percentage of the instruction scheduling transmitter SQ3. This represents the first flow of the return operation in the instruction scheduling transmitter SQ3. This is the second flow rate.

[0144] The preset rule for the traffic share of the aforementioned command scheduling transmitters can be that if the difference between the maximum and minimum traffic share of each command scheduling transmitter is greater than the twelfth threshold, it is determined that the first-level command cache data return link is abnormal, and the cause of the abnormality is an unbalanced load among multiple command scheduling transmitters. For example, suppose the traffic share of command scheduling transmitter SQ0 is 85%, the traffic share of command scheduling transmitter SQ1 is 83%, the traffic share of command scheduling transmitter SQ2 is 90%, and the traffic share of command scheduling transmitter SQ3 is 65%. The twelfth threshold is 20%. Among the traffic shares of each command scheduling transmitter, the minimum is 65% (command scheduling transmitter SQ3), and the maximum is 90% (command scheduling transmitter SQ2). Then the difference between the maximum and minimum is 90% - 65% = 25%. Since the difference between the maximum and minimum is 25%, which is greater than the twelfth threshold of 20%, the terminal can determine that the first-level command cache data return link is abnormal, and the cause of the abnormality is an unbalanced load among multiple command scheduling transmitters. It is understood that the aforementioned twelfth threshold is preset by those skilled in the art. The twelfth threshold can be changed according to different application scenarios. For example, the twelfth threshold could be 20%. Or, for another example, the twelfth threshold could be 10%.

[0145] In the above method, by determining the traffic share of the instruction scheduling transmitter, the load balancing of the instruction scheduling transmitter can be accurately assessed, which can provide guidance for subsequent thread optimization.

[0146] In other embodiments, to determine whether there are any anomalies in the data return, the terminal can also determine the average bandwidth based on the number of active cycles and the number of bytes returned to the instruction scheduler from the Level 1 instruction cache. The average bandwidth represents the number of data bytes actually transmitted per unit clock cycle. A higher average bandwidth indicates more efficient bandwidth utilization. For example, the terminal can divide the number of active cycles by the number of bytes actually returned by the storage controller to obtain the average bandwidth. The average bandwidth satisfies the following formula:

[0147]

[0148] in, This represents the average bandwidth. This represents the number of active cycles. The number of bytes returned to the instruction dispatcher from the level 1 instruction cache.

[0149] The preset rule for the aforementioned average bandwidth can be to compare the average bandwidth with a thirteenth threshold. If the average bandwidth is less than or equal to the thirteenth threshold, it is determined that the L1 instruction cache data return link is abnormal, and the reason for the abnormality is low bandwidth utilization of the L1 instruction cache. For example, suppose the average bandwidth is 800B / cycle (meaning 800 bytes of data can be transmitted per clock cycle). The thirteenth threshold is 1024B / cycle (meaning 1024 bytes of data can be transmitted per clock cycle). The average bandwidth of 800B / cycle is less than the thirteenth threshold of 1024B / cycle, so it is determined that the L1 instruction cache data return link is abnormal, and the reason for the abnormality is low bandwidth utilization of the L1 instruction cache. It is understood that the aforementioned thirteenth threshold is preset by those skilled in the art. The thirteenth threshold can be changed according to different application scenarios. For example, the twelfth threshold can be 1000B / cycle. Another example is that the thirteenth threshold is 1024B / cycle.

[0150] In the above method, by determining the average bandwidth, the frequency of bandwidth usage can be accurately assessed, and whether there is bandwidth waste can be identified.

[0151] Based on the same technical concept, Figure 8 An exemplary schematic diagram of a performance analysis structure provided in an embodiment of this application is shown, illustrating the process that the device can execute.

[0152] like Figure 8 As shown, the device specifically includes:

[0153] The transceiver module 801 is used to receive instructions to be executed;

[0154] The transceiver module 801 is also used to obtain access data of instructions at the memory level. The access data represents the relevant information of the instructions being mapped to the memory in the first-level instruction cache when the general-purpose computing graphics processor initiates access to the first-level instruction cache.

[0155] The processing module 802 is used to determine the processing capacity of the first-level instruction cache based on the access data. The processing capacity of the first-level instruction cache represents the overall performance of the first-level instruction cache in the data processing process when it is accessed by the general-purpose computing graphics processor.

[0156] The processing module is also used to perform performance analysis on the level 1 instruction cache based on its processing capacity, and to determine the cause of any abnormalities in the level 1 instruction cache.

[0157] Optionally, the access data includes first information, second information, and third information, wherein the first information is used to quantify the cumulative number of behaviors of the L1 instruction cache at each stage of data processing, the second information is used to represent the state and load of the storage, and the third information is used to represent the performance output of the L1 instruction cache.

[0158] Optionally, the metrics used to represent the processing capability of the Level 1 instruction cache include any one of the first metric, the second metric, and the third metric. The first metric represents the ability of the Level 1 instruction cache to receive and carry instruction requests from the general-purpose computing graphics processor. The second metric represents the request hit and data retrieval efficiency of the Level 1 instruction cache. The third metric represents the data output and link transmission performance of the Level 1 instruction cache.

[0159] Optionally, the processing module 802, which determines the processing capacity of the first-level instruction cache based on the access data, is specifically used for:

[0160] The first indicator is determined based on the cumulative data from the data reception phase in the first information.

[0161] Alternatively, the second indicator can be determined based on the cumulative data from the data retrieval phase in the first information.

[0162] Alternatively, the second indicator can be determined based on the data in the storage unit related to data retrieval in the second information;

[0163] Alternatively, the third indicator can be determined based on the performance output data related to the data return in the third information.

[0164] Optionally, the above-mentioned performance analysis of the L1 instruction cache based on its processing capacity to determine the cause of L1 instruction cache anomalies is specifically performed by processing module 802 as follows:

[0165] If the first indicator meets the preset rules, it is determined that the first-level instruction cache data reception link is abnormal.

[0166] If the second indicator meets the preset rules, it is determined that the first-level instruction cache data retrieval link is abnormal.

[0167] If the third indicator meets the preset rules, it is determined that the first-level instruction cache data return link is abnormal.

[0168] Optionally, the processing module 802 is also used for:

[0169] If it is determined that the data receiving link of the first-level instruction cache is abnormal, the cause of the abnormality is determined to be frequent thread beam switching or data path blockage in the storage controller to transmit instructions to the first-level instruction cache based on the cumulative data of the data receiving stage in the first information.

[0170] If it is determined that the L1 instruction cache data retrieval link is abnormal, based on the cumulative data of the data retrieval stage in the first information, or the data of the storage bank related to data retrieval in the second information, determine the cause of the abnormality as instruction jitter, or poor instruction layout, or unbalanced load of multiple storage banks, or insufficient prefetch capability, or low bandwidth utilization efficiency of the storage controller.

[0171] If it is determined that the data return link of the first-level instruction cache is abnormal, based on the performance output data related to data return in the third information, the cause of the abnormality is determined to be unbalanced load of multiple instruction schedulers or low bandwidth utilization of the first-level instruction cache.

[0172] Optionally, the first metric includes at least one or more of the following: the efficiency of instruction request merging, the proportion of transmission downtime caused by the queue reaching its capacity limit to the number of active cycles; the second metric includes at least one or more of the following: the miss rate, the average read latency, the utilization rate of each memory bank, the prefetch rate, and the instruction success rate; the third metric includes at least one or more of the following: the average bandwidth and the proportion of the data stream returned by each instruction scheduler to the global data stream.

[0173] Based on the same technical concept, this application also provides an electronic device that can realize the functions of the aforementioned performance analysis device.

[0174] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0175] At least one processor 901 and a memory 902 connected to at least one processor 901. In this embodiment, the specific connection medium between the processor 901 and the memory 902 is not limited. Figure 9 The example shown is the connection between processor 901 and memory 902 via bus 900. Bus 900 is... Figure 9 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. The Bus 900 can be divided into address bus, data bus, control bus, etc., for ease of representation. Figure 9 The term is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Alternatively, the processor 901 can also be called a controller; there is no restriction on the name.

[0176] In this embodiment, memory 902 stores instructions executable by at least one processor 901. By executing the instructions stored in memory 902, at least one processor 901 can perform a performance analysis method as described above. Processor 901 can implement... Figure 9 The functions of each module in the device shown.

[0177] The processor 901 is the control center of the device. It can connect to various parts of the control device through various interfaces and lines. By running or executing instructions stored in memory 902 and calling data stored in memory 902, the processor can perform various functions and process data, thereby monitoring the device as a whole.

[0178] In one possible design, processor 901 may include one or more processing units. Processor 901 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, driver interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into processor 901. In some embodiments, processor 901 and memory 902 may be implemented on the same chip; in some embodiments, they may also be implemented on separate chips.

[0179] The processor 901 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of a performance analysis method disclosed in the embodiments of this application can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0180] Memory 902, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 902 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 902 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 902 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0181] By designing and programming the processor 901, the code corresponding to one of the performance analysis methods described in the foregoing embodiments can be embedded into the chip, enabling the chip to execute it during operation. Figure 1The illustrated embodiment presents a performance analysis method. How to design and program the processor 901 is a technique well-known to those skilled in the art and will not be described further here.

[0182] It should be noted that the electronic device provided in this application embodiment can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Here, the parts that are the same as those in the method embodiment and the beneficial effects will not be described in detail.

[0183] This application also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to execute a performance analysis method described in the above embodiments.

[0184] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0185] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the function specified in one or more boxes.

[0186] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0187] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0188] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A performance analysis method, characterized in that, The method includes: Receive instructions to be executed; Obtain the access data of the instruction at the memory level, where the access data represents the relevant information of the instruction being mapped to the memory in the first-level instruction cache when the general-purpose computing graphics processor initiates an access to the first-level instruction cache; The processing capacity of the first-level instruction cache is determined based on the access data. The processing capacity of the first-level instruction cache represents the overall efficiency of the first-level instruction cache in the data processing process when it responds to instruction access from the general-purpose computing graphics processor. Based on the processing capacity of the level 1 instruction cache, a performance analysis is performed on the level 1 instruction cache to determine the cause of any anomalies.

2. The method according to claim 1, characterized in that, The access data includes first information, second information, and third information. The first information is used to quantify the cumulative number of behaviors of the Level 1 instruction cache at each stage of the data processing process. The second information is used to represent the state and load of the storage. The third information is used to represent the performance output of the Level 1 instruction cache.

3. The method according to claim 2, characterized in that, The metrics used to represent the processing capability of the Level 1 instruction cache include any one of the first metric, the second metric, and the third metric. The first metric represents the ability of the Level 1 instruction cache to receive and carry instruction requests from the general-purpose computing graphics processor. The second metric represents the request hit and data retrieval efficiency of the Level 1 instruction cache. The third metric represents the data output and link transmission performance of the Level 1 instruction cache.

4. The method according to claim 3, characterized in that, Determining the processing capacity of the first-level instruction cache based on the access data specifically includes: The first indicator is determined based on the cumulative data from the data reception phase in the first information; Alternatively, the second indicator can be determined based on the cumulative data from the data retrieval phase in the first information. Alternatively, the second indicator can be determined based on the data in the storage unit related to data retrieval in the second information; Alternatively, the third indicator can be determined based on the performance output data related to the data return in the third information.

5. The method according to claim 3 or 4, characterized in that, The step of performing performance analysis on the Level 1 instruction cache based on its processing capacity to determine the cause of any anomalies in the Level 1 instruction cache specifically includes: If the first indicator meets the preset rules, it is determined that the first-level instruction cache data reception link is abnormal; If the second indicator meets the preset rule, it is determined that the first-level instruction cache data retrieval link is abnormal; If the third indicator meets the preset rule, it is determined that the first-level instruction cache data return link is abnormal.

6. The method according to claim 5, characterized in that, The method further includes: If it is determined that the data receiving link of the first-level instruction cache is abnormal, the cause of the abnormality is determined to be frequent thread beam switching or data path blockage of the instruction transmitted from the storage controller to the first-level instruction cache based on the cumulative data of the data receiving stage in the first information. If it is determined that the data retrieval link of the first-level instruction cache is abnormal, the cause of the abnormality is determined to be instruction jitter, or poor instruction layout, or unbalanced load of multiple memory banks, or insufficient prefetch capability, or low bandwidth utilization efficiency of the storage controller, based on the cumulative data of the data retrieval stage in the first information or the data of the storage bank related to data retrieval in the second information. If it is determined that the data return link of the first-level instruction cache is abnormal, the cause of the abnormality is determined to be unbalanced load of multiple instruction schedulers or low bandwidth utilization of the first-level instruction cache based on the performance output data related to data return in the third information.

7. The method according to claim 3 or 4, characterized in that, The first metric includes at least one or more of the following: the efficiency of merging instruction requests, and the proportion of transmission downtime caused by the queue reaching its capacity limit to the number of active cycles; the second metric includes at least one or more of the following: the miss rate, the average read latency, the utilization rate of each memory bank, the prefetch rate, and the instruction success rate; the second metric includes at least one or more of the following: the average bandwidth and the proportion of the data stream returned by each instruction scheduler to the global data stream.

8. A performance analysis device, characterized in that, The device includes: The transceiver module is used to receive instructions to be executed. The transceiver module is also used to obtain access data of the instruction at the storage level. The access data represents the relevant information of the instruction being mapped to the storage in the first-level instruction cache when the general-purpose computing graphics processor initiates access to the first-level instruction cache. The processing module is used to determine the processing capability of the first-level instruction cache based on the access data. The processing capability of the first-level instruction cache represents the overall performance of the first-level instruction cache in the data processing process when it responds to instruction access from the general-purpose computing graphics processor. The processing module is further configured to perform performance analysis on the first-level instruction cache based on its processing capacity, and determine the cause of any anomalies in the first-level instruction cache.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for causing the computer to perform the method of any one of claims 1-7.

11. A computer program product, characterized in that, When the computer program product is invoked by a computer, it causes the computer to perform the method as described in any one of claims 1-7.

Images