An I2C interface and its working method

Abstract

This invention discloses an I2C interface and its operating method. The I2C interface is integrated into a chip and used to realize signal transmission with external interfaces. Specifically, the I2C interface includes a register module, a core processing module, and an open-drain output module. The operating method of the I2C interface includes: the open-drain output module acquiring an open-drain enable signal from the register module, receiving an output control signal output from the core processing module, performing operator operations on the open-drain enable signal and the output control signal to obtain an open-drain output control signal, and outputting the open-drain output control signal to a PAD in the chip, so that the PAD outputs an open-drain signal to the external interface. This solution enables the I2C interface to use push-pull output PADs, allowing it to output signals fully compliant with the I2C communication protocol even when the PAD does not have open-drain output functionality, thus achieving normal communication with other interfaces.

Description

Technical Field

[0001] This invention relates to an I2C interface and its working method, belonging to the field of computer technology. Background Technology

[0002] The I2C bus (Inter-Integrated Circuit) is a simple, bidirectional, two-wire synchronous serial bus developed by Philips. It connects different nodes to the same bus system via a clock line (SCL) and a data line (SDA), enabling effective communication with devices connected to the bus. The I2C bus requires both the clock line (SCL) and the data line (SDA) to adhere to open-drain output rules. This open-drain output rule ensures normal communication between nodes and is crucial for eliminating the risk of level conflicts between nodes, supporting multi-master arbitration, achieving voltage adaptation, and reducing communication power consumption. Therefore, the open-drain output function is of paramount importance in the implementation of the I2C interface.

[0003] In traditional I2C interface implementations, the I2C bus outputs push-pull control signals to the chip PAD (Peripheral Access Device). To comply with open-drain output rules, it is necessary to rely entirely on the open-drain output function of the PAD technology to convert the push-pull control signals into open-drain signals that conform to the I2C protocol specification, thereby enabling normal communication with other interfaces.

[0004] However, in this traditional implementation, if the target chip's PAD library does not provide such a dedicated open-drain PAD, or if the PAD's open-drain function is unavailable for other reasons, then the standard I2C communication function cannot be implemented. Secondly, when the chip needs to be migrated across different semiconductor process nodes or different foundries, the original open-drain PAD may not be directly compatible, requiring the design team to find, verify, or customize new PADs, thereby increasing the chip's design cycle and cost. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides an I2C interface and its operating method.

[0006] Therefore, according to a first aspect of the present invention, an I2C interface is provided, the I2C interface being integrated into a chip for signal transmission with an external interface of the chip, characterized in that the I2C interface specifically includes: a register module, a core processing module, and an open-drain output module;

[0007] The register module is connected to the open-drain output module and is used to output an open-drain enable signal to the open-drain output module.

[0008] The core processing module is connected to the open-drain output module and is used to output control signals to the open-drain output module.

[0009] The open-drain output module is connected to the register module and the core processing module, and is used to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module, and output the open-drain output control signal according to the open-drain enable signal and the output control signal. The open-drain output control signal is a signal that conforms to the I2C communication protocol rules.

[0010] The open-drain output module is also used to output the open-drain output control signal to the PAD in the chip, so that the PAD outputs the open-drain signal to the outside of the chip.

[0011] According to a second aspect of the present invention, a method for operating an I2C interface is provided, the method comprising:

[0012] Step S1: The open-drain output module obtains the open-drain enable signal from the register module and receives the output control signal output by the core processing module;

[0013] Step S2: The open-drain output module performs calculations on the open-drain enable signal and the output control signal to obtain an open-drain output control signal. The open-drain output control signal includes an open-drain output data signal and an open-drain output enable signal that conform to the I2C communication protocol.

[0014] Step S3: The open-drain output module outputs the open-drain output control signal to the PAD in the chip, so that the PAD outputs an open-drain signal conforming to the I2C communication protocol to the outside of the chip.

[0015] According to a third aspect of the present invention, a chip is provided, characterized in that the chip includes the I2C interface described above, and the chip communicates with an interface or device outside the chip through the I2C interface.

[0016] In the technical solution provided by this invention, the open-drain output function of the I2C interface is "moved forward" from the PAD to the open-drain output module inside the I2C interface. This allows the open-drain output control signal output by the open-drain output module to control the open-drain output outside the chip, thereby eliminating the dependence on the open-drain function of the PAD. This solution enables the I2C interface to use push-pull output PADs, meaning that even when the PAD does not have open-drain output functionality, the output signal can still fully comply with the I2C communication protocol, thus enabling normal communication between the I2C interface and other interfaces. Furthermore, the I2C interface provided by this invention is also compatible with PADs that have open-drain functionality, greatly improving the autonomy, flexibility, and portability of chip design. Attached Figure Description

[0017] To illustrate more clearly, the embodiments of the present invention or the prior art will be briefly described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the I2C working structure;

[0019] Figure 2 This is a schematic diagram of the working structure of the I2C interface in the traditional method;

[0020] Figure 3 This is a schematic diagram illustrating the changes in the I2C interface output signal in the traditional method;

[0021] Figure 4 This is a schematic diagram of an I2C interface structure provided in Embodiment 1 of the present invention;

[0022] Figure 5 This is a schematic diagram of the first open-drain output submodule structure in the I2C interface provided in Embodiment 1 of the present invention;

[0023] Figure 6 This is a schematic diagram of the second open-drain output submodule structure in the I2C interface provided in Embodiment 1 of the present invention;

[0024] Figure 7 This is a schematic diagram of the I2C interface output signal change in the solution provided in Embodiment 1 of this application;

[0025] Figure 8 This is a schematic diagram of an I2C interface workflow provided in Embodiment 2 of the present invention;

[0026] Figure 9 This is a truth table for I2C interface output provided in Embodiment 2 of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0028] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of devices and methods consistent with some aspects of the invention as detailed in the appended claims.

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Example 1

[0030] Before describing the I2C interface provided in this application, we will first explain the relevant background information of the embodiments of this application.

[0031] like Figure 1 As shown, the I2C bus connects different nodes to the same bus system via the clock line SCL and the data line SDA. It employs a unique timing control method, address addressing mechanism, and open-drain output rule to achieve effective communication between multiple master and slave nodes. Because the I2C bus requires both the clock line SCL and the data line SDA to adhere to the open-drain output rule, both lines need to be externally pulled up to ensure the stability of the high-level voltage on the lines.

[0032] Figure 2 This diagram illustrates the working structure of an I2C interface in a traditional design. The chip PAD, located on the silicon substrate inside the chip, is the physical interface connecting the chip to external devices and is not directly visible to the user. The PAD is connected to pins on the packaged chip via metal wires. These pins are divided into input and output pins, used for receiving external signals and outputting signals, respectively, thus serving as signal transmission pins. The I2C interface outputs push-pull control signals to the chip PAD via the clock line SCL and data line SDA. This typically relies on the open-drain output capability of the PAD technology to convert the push-pull control signals into open-drain signals, enabling normal communication with other interfaces.

[0033] Figure 3 This diagram illustrates the signal changes of an I2C interface in a traditional design. In traditional designs, the signals output by a chip using an I2C interface must conform to the I2C communication protocol when communicating with other interfaces. Specifically, they must comply with the open-drain output rules of the I2C bus. This typically requires a PAD (Packet Anchor) with open-drain functionality. This PAD processes the signal received from the I2C interface to obtain the open-drain signal output by the chip to other interfaces. This signal is high impedance when the I2C push-pull output is high and low impedance when the push-pull output is low. If the PAD itself does not have open-drain output functionality, the signal output by the PAD will not conform to the I2C communication protocol, thus preventing the I2C interface from communicating normally with other interfaces. Therefore, in traditional I2C interface chips, the use of the I2C interface within the chip depends entirely on the open-drain functionality of the PAD.

[0034] Based on this, the present application provides an I2C interface and its working method. The I2C interface provided by the present application can be independent of the open-drain function of the PAD, thereby reducing the cost of the chip and expanding the application scenarios of the I2C interface.

[0035] The I2C interface and its working method provided in this application will be described in detail below.

[0036] like Figure 4 As shown, this embodiment of the invention provides an I2C interface, which is integrated into a chip and used to realize signal transmission with an external interface of the chip. The I2C interface includes: a register module, a core processing module, and an open-drain output module.

[0037] The register module is connected to the open-drain output module and is used to output an open-drain enable signal to the open-drain output module.

[0038] The core processing module is connected to the open-drain output module and is used to output control signals to the open-drain output module.

[0039] The open-drain output module is connected to the register module and the core processing module. It is used to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module. Based on the open-drain enable signal and the output control signal, it outputs the open-drain output control signal. The open-drain output control signal is a signal that conforms to the I2C communication protocol rules.

[0040] The open-drain output module is also used to output the open-drain output control signal to the PAD in the chip, so that the PAD outputs the open-drain signal to the outside of the chip;

[0041] Specifically, the open-drain output module includes a first open-drain output submodule and a second open-drain output submodule. The first open-drain output submodule and the second open-drain output submodule are respectively connected to the register module and the core processing module. They are used to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module, and output the open-drain output control signal according to the open-drain enable signal and the output control signal, and output the open-drain output control signal to the PAD in the chip.

[0042] Furthermore, the first open-drain output submodule is connected to the clock line open-drain enable signal line in the register module, the clock line output enable signal line and the clock line output data signal line in the core processing module, and is used to receive the clock line open-drain enable signal output by the register module, the clock line output enable signal in the output control signal output by the core processing module, and the clock line output data signal in the output control signal output by the core processing module.

[0043] The second open-drain output submodule is connected to the open-drain enable signal line of the data line in the register module, the enable signal line of the data line output in the core processing module, and the output data signal line of the data line output. It is used to receive the open-drain enable signal of the data line output from the register module, the enable signal of the data line output in the output control signal of the core processing module, and the output data signal of the data line output in the output control signal of the core processing module.

[0044] In this embodiment, the chip further includes a first PAD and a second PAD. A first open-drain output submodule is connected to the first PAD of the chip and is used to output a clock line open-drain output enable signal and a clock line open-drain output data signal to the first PAD of the chip according to a clock line open-drain enable signal, a clock line output enable signal, and a clock line output data signal, so that the first PAD outputs a clock line open-drain signal conforming to the I2C communication protocol to the outside of the chip. A second open-drain output submodule is connected to the second PAD and is used to output a data line open-drain output enable signal and a data line open-drain output data signal to the second PAD of the chip according to a data line open-drain enable signal, a data line output enable signal, and a data line output data signal, so that the second PAD outputs a data line open-drain signal conforming to the I2C communication protocol to the outside of the chip.

[0045] Specifically, the first PAD and the second PAD output clock line open-drain signal and data line open-drain signal to the outside of the chip, respectively;

[0046] One feasible approach, such as Figure 5 As shown, the first open-drain output submodule specifically includes a first AND gate, a first NOT gate, a second AND gate, a second NOT gate, and a third AND gate;

[0047] The first AND gate is connected to the first NOT gate, the register module, and the core processing module. It is used to perform calculations on the clock line open-drain enable signal output by the register module, the clock line output enable signal and the clock line output data signal in the output control signal output by the core processing module, to obtain a first result, and output the first result to the first NOT gate.

[0048] The first NOT gate is connected to the first AND gate and the second AND gate to perform calculations on the first result output by the first AND gate to obtain the second result, and then output the second result to the second AND gate;

[0049] The second AND gate is connected to the first NOT gate and the core processing module. It is used to calculate the clock line open-drain output enable signal by performing calculations based on the clock line output enable signal in the output control signal output by the core processing module and the second result.

[0050] The second NOT gate is connected to the register module and the third AND gate. It is used to perform calculations on the open-drain clock line enable signal output by the register module to obtain the third result, and then output the third result to the third AND gate.

[0051] The third AND gate is connected to the core processing module and the second NOT gate, and is used to calculate the open-drain clock line output data signal based on the clock line output data signal in the output control signal output by the core processing module and the third result.

[0052] One feasible approach, such as Figure 6As shown, the second open-drain output submodule specifically includes a fourth AND gate, a third NOT gate, a fifth AND gate, a fourth NOT gate, and a sixth AND gate;

[0053] The fourth AND gate is connected to the third NOT gate, the register module, and the core processing module. It is used to perform calculations on the open-drain enable signal of the data line output from the register module, the data line output enable signal of the output control signal output from the core processing module, and the data line output data signal to obtain the fourth result. The fourth result is then output to the third NOT gate.

[0054] The third NOT gate is connected to the fourth AND gate and the fifth AND gate to perform operations on the fourth result output by the fourth AND gate to obtain the fifth result, and then output the fifth result to the fifth AND gate;

[0055] The fifth AND gate is connected to the third NOT gate and the core processing module. It is used to calculate the open-drain output enable signal of the data line based on the data line output enable signal in the output control signal output by the core processing module and the fifth result.

[0056] The fourth NOT gate is connected to the register module and the sixth AND gate. It is used to perform calculations on the open-drain enable signal of the data line output by the register module to obtain the sixth result, and then output the sixth result to the sixth AND gate.

[0057] The sixth AND gate is connected to the core processing module and the fourth NOT gate. It is used to calculate the open-drain output data signal of the data line based on the data line output data signal in the output control signal output by the core processing module and the result of the sixth AND gate.

[0058] Using the I2C interface provided by the above solution, even when using a push-pull output PAD (i.e., the PAD does not have open-drain output function), the output signal can still fully comply with the I2C communication protocol, thereby enabling normal communication with other interfaces.

[0059] like Figure 7The diagram illustrates the signal change from the I2C interface output signal to the chip PAD in this application. With the I2C open-drain enable enabled, the core processing module outputs data with high and low level changes, similar to existing technologies. The core processing module outputs a high level when enabled. The open-drain output module receives the output control signal from the core processing module. The output enable signal only becomes high when the output data signal of the output control signal is low; otherwise, it remains low. This is a typical open-drain output signal mode. Under the control of the open-drain output module, the signal reaching the PAD exhibits a high impedance state when the I2C interface open-drain output enable is low and a low impedance state when the output enable is high. The signal already conforms to the open-drain output rules of the I2C bus, so there are no further requirements for the PAD function. After the signal passes through the PAD, it becomes an open-drain signal output to the outside of the chip. At this time, the I2C interface does not depend on whether the PAD has open-drain function. Whether the PAD has open-drain function or not, it can output an open-drain signal that conforms to the I2C communication protocol. Compared with the traditional I2C interface, the I2C interface provided by this application has higher compatibility. Whether the PAD has open-drain output function or not, it can output a signal that fully conforms to the I2C communication protocol, thereby realizing normal communication between the I2C interface and other interfaces.

[0060] Furthermore, in the I2C interface provided in this embodiment, when the PAD has open-drain functionality, the I2C open-drain enable is turned off, and the output through the PAD is also an open-drain signal that conforms to the I2C communication protocol. Example 2

[0061] Embodiment 2 of the present invention provides an I2C interface working method, which can be executed by an electronic device or implemented by one or more chips in the electronic device.

[0062] like Figure 8 As shown, the I2C interface working methods include:

[0063] Step 101: The open-drain output module obtains the open-drain enable signal from the register module and receives the output control signal from the core processing module.

[0064] In this embodiment, the open-drain enable signal includes a clock line open-drain enable signal and a data line open-drain enable signal;

[0065] One feasible approach is that the open-drain enable signal in the register module is specifically configured as an open-drain enable connection line in the register module. A configuration of 1 indicates that the open-drain enable signal is 1, indicating that the open-drain function is enabled, while a configuration of 0 indicates that the open-drain enable signal is 0, indicating that the open-drain function is not enabled.

[0066] In this embodiment, the output control signal includes an output enable signal and an output data signal;

[0067] In this embodiment, the output control signals output by the core processing module include clock line output enable signal, clock line output data signal, data line output enable signal, and data line output data signal. The hardware gate circuit structure for the open-drain output module to process the received clock line output control signals (clock line output enable signal and clock line output data signal) and data line output control signals (data line output enable signal and data line output data signal) output by the core processing module is the same. Therefore, in this embodiment, the signals output by the core processing module are uniformly referred to as output control signals, and the signals output by the open-drain output module are uniformly referred to as open-drain output control signals.

[0068] In this embodiment, when the PAD in the chip has open-drain functionality, the open-drain enable signal in the register module can also be configured to 0, indicating that the open-drain function of the I2C interface is not enabled. At this time, the PAD is used to output the open-drain signal to the outside of the chip.

[0069] Step 102: The open-drain output module performs calculations on the open-drain enable signal and the output control signal to obtain the open-drain output control signal. The open-drain output control signal includes an open-drain output data signal and an open-drain output enable signal that conform to the I2C communication protocol.

[0070] In this embodiment, operator operations specifically include AND and NOT operations;

[0071] One implementable method, step 102 specifically includes: the open-drain output module performing an AND operation on the open-drain enable signal, the output enable signal in the output control signal, and the output data signal in the output control signal to obtain a first result; performing a NOT operation on the first result to obtain a second result; performing an AND operation on the second result and the output enable signal in the output control signal to obtain an open-drain output module output enable signal; performing a NOT operation on the open-drain enable signal to obtain a third result; and performing an AND operation on the third result and the output data signal in the output control signal to obtain an open-drain output module output data signal.

[0072] For example, if the open-drain enable signal is 1, the output data signal in the output control signal is 0, and the output enable signal in the output control signal is 1, the open-drain output module performs operator operations to obtain an open-drain output module output enable signal of 1 and an open-drain output module output data signal of 0.

[0073] Step 103: The open-drain output module outputs the open-drain output control signal to the PAD in the chip, so that the PAD outputs an open-drain signal conforming to the I2C communication protocol to the outside of the chip.

[0074] In this embodiment, as Figure 9The table below shows the truth table for the I2C interface output signals. When the open-drain function of the I2C interface is enabled, the open-drain enable is 1; when the open-drain function is disabled, the open-drain enable is 0. When the PAD has open-drain functionality, the PAD open-drain enable is 1; when the PAD does not have open-drain functionality, the PAD open-drain enable is 0. When the core processing module outputs data at a high level, the core processing module outputs data as 1; when the core processing module outputs data at a low level, the core processing module outputs data as 0. When the core processing module output enable is high, the core processing module output enable is 1; when the core processing module output enable is low, the core processing module output enable is 0. When the open-drain output module outputs data at a high level, the open-drain output module outputs data as 1; when the open-drain output module outputs data at a low level, the open-drain output module outputs data as 0. When the open-drain output module output enable is high, the drain output module output enable is 1; when the open-drain output module output enable is low, the drain output module output enable is 0.

[0075] In this embodiment, if the I2C open-drain function is enabled, the PAD can output an open-drain signal to the outside of the chip regardless of whether the PAD has an open-drain function. If the I2C open-drain function is not enabled and the PAD has an open-drain function, the PAD will output the open-drain signal to the outside of the chip.

[0076] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0077] This invention also provides a chip that includes the I2C interface described in Embodiment 1, and the chip communicates with external interfaces or devices through the I2C interface.

[0078] In this embodiment, the PAD connected to the I2C interface in the chip can be a PAD with open-drain function or a PAD without open-drain function.

[0079] In this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order; the term "multiple" refers to two or more unless otherwise explicitly defined. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. The terms "install," "connect," "link," "fix," etc., should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0080] In the description of this invention, it should be understood that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0081] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, equivalent variations made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. An I2C interface, said I2C interface being integrated into a chip for signal transmission with an external interface of the chip, characterized in that, The I2C interface includes: a register module, a core processing module, and an open-drain output module; The register module is connected to the open-drain output module and is used to output an open-drain enable signal to the open-drain output module. The core processing module is connected to the open-drain output module and is used to output control signals to the open-drain output module. The open-drain output module is connected to the register module and the core processing module, and is used to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module, and output the open-drain output control signal according to the open-drain enable signal and the output control signal. The open-drain output control signal is a signal that conforms to the I2C communication protocol rules. The open-drain output module is also used to output the open-drain output control signal to the PAD in the chip, so that the PAD outputs the open-drain signal to the outside of the chip. The open-drain output module includes a first open-drain output submodule and a second open-drain output submodule; The first open-drain output submodule and the second open-drain output submodule are respectively connected to the register module and the core processing module, and are used to receive the open-drain enable signal output by the register module and the output control signal output by the core processing module, and output the open-drain output control signal according to the open-drain enable signal and the output control signal, and output the open-drain output control signal to the PAD in the chip; The first open-drain output submodule is connected to the clock line open-drain enable signal line in the register module, and is used to read the clock line open-drain enable signal output by the register module; The first open-drain output submodule is connected to the clock line output enable signal line in the core processing module, and is used to receive the clock line output enable signal in the output control signal output by the core processing module. The first open-drain output submodule is also connected to the clock line output data signal line in the core processing module, and is used to receive the clock line output data signal in the output control signal output by the core processing module; The second open-drain output submodule is connected to the open-drain data line enable signal line in the register module and is used to receive the open-drain data line enable signal output by the register module. The second open-drain output submodule is connected to the data line output enable signal line in the core processing module, and is used to receive the data line output enable signal in the output control signal output by the core processing module. The second open-drain output submodule is also connected to the data line output data signal line in the core processing module, and is used to receive the data line output data signal in the output control signal output by the core processing module.

2. The I2C interface according to claim 1, characterized in that, The first open-drain output submodule is connected to the first PAD of the chip and is used to output a clock line open-drain output enable signal and a clock line open-drain output data signal to the first PAD of the chip according to the clock line open-drain enable signal, the clock line output enable signal and the clock line output data signal, so that the first PAD outputs a clock line open-drain signal conforming to the I2C communication protocol to the outside of the chip.

3. The I2C interface according to claim 1, characterized in that, The first open-drain output submodule specifically includes a first AND gate, a first NOT gate, a second AND gate, a second NOT gate, and a third AND gate; The first AND gate is connected to the first NOT gate, the register module, and the core processing module, and is used to perform calculations on the clock line open-drain enable signal output by the register module, the clock line output enable signal and the clock line output data signal in the output control signal output by the core processing module, to obtain a first result, and output the first result to the first NOT gate; The first NOT gate is connected to the first AND gate and the second AND gate, and is used to perform a calculation on the first result output by the first AND gate to obtain a second result, and output the second result to the second AND gate; The second AND gate is connected to the first NOT gate and the core processing module, and is used to calculate the clock line open-drain output enable signal based on the clock line output enable signal in the output control signal output by the core processing module and the second result. The second NOT gate is connected to the register module and the third AND gate, and is used to perform calculations on the clock line open-drain enable signal output by the register module to obtain a third result, and output the third result to the third AND gate; The third AND gate is connected to the core processing module and the second NOT gate, and is used to calculate the open-drain clock line output data signal based on the clock line output data signal in the output control signal output by the core processing module and the third result.

4. The I2C interface according to claim 1, characterized in that, The second open-drain output submodule is connected to the second PAD of the chip and is used to output a data line open-drain output enable signal and a data line open-drain output data signal to the second PAD of the chip according to the data line open-drain enable signal, the data line output enable signal and the data line output data signal, so that the second PAD outputs a data line open-drain signal conforming to the I2C communication protocol to the outside of the chip.

5. The I2C interface according to claim 1, characterized in that, The second open-drain output submodule specifically includes a fourth AND gate, a third NOT gate, a fifth AND gate, a fourth NOT gate, and a sixth AND gate; The fourth AND gate is connected to the third NOT gate, the register module, and the core processing module. It is used to perform an AND operation on the open-drain enable signal of the data line output from the register module, the data line output enable signal of the output control signal output from the core processing module, and the data line output data signal to obtain a fourth result. The fourth result is then output to the third NOT gate. The third NOT gate is connected to the fourth AND gate and the fifth AND gate, and is used to perform calculations on the fourth result output by the fourth AND gate to obtain the fifth result, and output the fifth result to the fifth AND gate; The fifth AND gate is connected to the third NOT gate and the core processing module, and is used to calculate the open-drain output enable signal of the data line based on the data line output enable signal in the output control signal output by the core processing module and the fifth result. The fourth NOT gate is connected to the register module and the sixth AND gate, and is used to perform calculations on the open-drain enable signal of the data line output by the register module to obtain the sixth result, and output the sixth result to the sixth AND gate; The sixth AND gate is connected to the core processing module and the fourth NOT gate, and is used to calculate the open-drain output data signal of the data line based on the data line output data signal in the output control signal output by the core processing module and the sixth result.

6. A method for operating an I2C interface according to any one of claims 1-5, characterized in that, The method includes: Step S1: The open-drain output module obtains the open-drain enable signal from the register module and receives the output control signal output by the core processing module; Step S2: The open-drain output module performs calculations on the open-drain enable signal and the output control signal to obtain an open-drain output control signal. The open-drain output control signal includes an open-drain output data signal and an open-drain output enable signal that conform to the I2C communication protocol. Step S3: The open-drain output module outputs the open-drain output control signal to the PAD in the chip, so that the PAD outputs an open-drain signal conforming to the I2C communication protocol to the outside of the chip.

7. A chip, characterized in that, The chip includes an I2C interface as described in any one of claims 1-5, and the chip communicates with an external interface or device through the I2C interface.

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