Multi-core processor chip, storage access method and device of multi-core processor chip

Abstract

The disclosure provides a multi-core processor chip, a memory access method and device of the multi-core processor chip, and relates to the technical field of computer processors. The multi-core processor chip comprises at least one processor core, a general processor core, a first address space mapping module and a first core interconnection interface, the general processor core supports cache coherence; at least one input / output core, an input / output core comprises a memory interface, a directory, a second address space mapping module and a second core interconnection interface; the first address space mapping module and the second address space mapping module both store an address space mapping table, the address space mapping table stores a mapping relationship between a memory address accessed by the processor core and a memory interface of the input / output core; the directory stores cache coherence information of cache blocks corresponding to memory interfaces of the corresponding input / output core and other input / output cores.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer processors, and in particular to a multi-die processor chip, a memory access method and device of the multi-die processor chip. BACKGROUND

[0002] Multi-Die integrated chips are a core technology path to meet the demand for computing power, energy efficiency and agile implementation of data center servers. Through heterogeneous integration, modular expansion and other characteristics, it provides cloud vendors with bottom hardware support that balances performance, cost and sustainability, and has become the preferred choice for large-scale data center server computing power infrastructure. The yield of large single-chip decreases sharply with the increase of area, and Multi-Die divides the system into multiple small dies, which significantly reduces the overall manufacturing cost and shortens the market cycle. Most of the current mainstream cloud server general-purpose processors (CPU) adopt Multi-Die architecture.

[0003] Multi-Die processors allow different functional dies to adopt their own optimal processes to form a chip together, such as a 7nm process CPU die and a 12nm process IO die packaged together to form a chip, which breaks through the limitations of single-chip process, optimizes energy efficiency ratio, and reduces manufacturing cost. Multi-Die can realize system iteration by replacing part of the die, such as upgrading the CPU die or upgrading the IO die alone, avoiding the redesign of the whole chip.

[0004] The traditional multi-die processor chip has a large overall area, and the dies are connected through a D2D (Die to Die) interface, which brings the problem that the access delay within the die is small, the access delay across the die is large, and the farther the distance, the larger the access delay. SUMMARY

[0005] The present application aims to at least solve one of the technical problems in the related art to some extent.

[0006] To achieve the above object, one object of the present application is to provide a multi-core processor chip, comprising: at least one processor core, the processor core comprising a general processor core, a first address space mapping module and a first core interconnection interface, the general processor core supporting cache coherency; at least one input / output core, the input / output core comprising a memory interface, a directory, a second address space mapping module and a second core interconnection interface; the first address space mapping module and the second address space mapping module each storing an address space mapping table, the address space mapping table storing a mapping relationship between a memory address accessed by the processor core and the memory interface of the input / output core; the directory storing cache coherency information of cache blocks corresponding to the memory interface of the corresponding input / output core and other input / output cores.

[0007] A second object of the present application is to provide a memory access method of a multi-core processor chip.

[0008] A third object of the present application is to provide a memory access device of a multi-core processor chip.

[0009] A fourth object of the present application is to provide an electronic device.

[0010] A fifth object of the present application is to provide a non-transitory computer readable storage medium.

[0011] A sixth object of the present application is to provide a computer program product.

[0012] To achieve the above object, one object of the present application is to provide a multi-core processor chip, comprising: at least one processor core, the processor core comprising a general processor core, a first address space mapping module and a first core interconnection interface, the general processor core supporting cache coherency; at least one input / output core, the input / output core comprising a memory interface, a directory, a second address space mapping module and a second core interconnection interface; the first address space mapping module and the second address space mapping module each storing an address space mapping table, the address space mapping table storing a mapping relationship between a memory address accessed by the processor core and the memory interface of the input / output core; the directory storing cache coherency information of cache blocks corresponding to the memory interface of the corresponding input / output core and other input / output cores.

[0013] The multi-core processor chip provided by the present application, each input / output core of the multi-core chip stores not only the directory corresponding to the input / output core itself but also the directories corresponding to other input / output cores, so that all directory information can be accessed on the local input / output core without accessing the directories on other input / output cores, thereby reducing long-delay access across cores and improving the performance of the multi-core processor chip.

[0014] According to one embodiment of the present application, the directory includes a plurality of sub-directories; each sub-directory corresponds to one or more memory interfaces; the sub-directory stores cache coherence information of a cache block corresponding to the memory interface corresponding to the sub-directory; the cache coherence information includes a presence position and a presence state of the cache block in each processor core.

[0015] According to one embodiment of the present application, the presence position of the cache block in each processor core is stored in the form of a bit vector.

[0016] According to one embodiment of the present application, the presence state includes an invalid state, a shared state, and an exclusive state.

[0017] According to one embodiment of the present application, the input / output core further includes a high-speed interface and / or a low-speed interface.

[0018] According to one embodiment of the present application, the address space mapping table supports dynamic configuration according to access requirements of a currently running program.

[0019] According to one embodiment of the present application, the first core interconnect and the second core interconnect of the processor core and the input / output core that have a connection relationship are arranged adjacently; and the second core interconnects of different input / output cores that have a connection relationship are arranged adjacently.

[0020] According to one embodiment of the present application, within the same input / output core, the sub-directories and the memory interfaces corresponding to the sub-directories are arranged adjacently; and the memory interfaces and the second core interconnect are arranged according to an access frequency of the processor core.

[0021] The memory interface supports dynamic grouping according to access requirements of a currently running program; when designing the multi-core processor chip, the access wire ports of the memory interfaces in the same initial grouping are designed based on a nearest placement principle according to an initial grouping scheme of the memory interfaces.

[0022] To achieve the above object, a second embodiment of the present application provides a storage access method of a multi-core processor chip, applied to the chip described above, including: when a processor core initiates memory access, querying an address space mapping table stored in a first address space mapping module in the processor core to obtain a target memory interface corresponding to a target memory address to be accessed; querying a directory in an input / output core having a connection relationship with the processor core to obtain target cache coherence information corresponding to the target memory interface; based on the target cache coherence information, determining a target processor core storing a target cache block corresponding to the target memory interface and closest to the processor core, and reading the target cache block in the target processor core.

[0023] According to one embodiment of the present application, the configuration process of the address space mapping table comprises: configuring the address space mapping table according to the access requirement of the currently running program.

[0024] According to one embodiment of the present application, the configuration of the address space mapping table according to the access requirement of the currently running program comprises: grouping the memory interfaces based on the access requirement to obtain at least one group; dividing the memory addresses corresponding to the chip into each group to obtain the group memory addresses corresponding to each group respectively; for any group, dividing the group memory addresses corresponding to the group into each memory interface contained in the group to obtain the memory blocks corresponding to each memory interface in the group respectively; and establishing the address space mapping table based on the correspondence between the memory interfaces and the memory blocks.

[0025] According to one embodiment of the present application, the division of the memory addresses corresponding to the chip into each group to obtain the group memory addresses corresponding to each group respectively comprises: if the group is one, taking the memory addresses of the chip as the group memory addresses of the group; and if the group is multiple, determining the group identification bits based on the number of groups and dividing the memory addresses corresponding to the chip into each group according to the group identification bits to obtain the group memory addresses corresponding to each group respectively.

[0026] According to one embodiment of the present application, the division of the group memory addresses corresponding to the group into each memory interface contained in the group to obtain the memory blocks corresponding to each memory interface in the group respectively comprises: if the group contains one memory interface, taking the group memory addresses corresponding to the group as the memory blocks corresponding to the memory interface contained in the group; and if the group contains multiple memory interfaces, determining the cross identification bits in combination with the number of memory interfaces in the group and the number of memory row bytes, and dividing the group memory addresses corresponding to the group into each memory interface contained in the group according to the cross identification bits to obtain the memory blocks corresponding to each memory interface in the group respectively.

[0027] According to one embodiment of the present application, when the access requirement of the currently running program changes, the address space mapping table is dynamically updated according to the changed access requirement.

[0028] According to one embodiment of the present application, after the address space mapping table is updated, the directory information corresponding to the memory interfaces where the address mapping changes is synchronously updated.

[0029] To achieve the above object, the third aspect of the present application provides a storage access device of a multi-core processor chip, comprising: a first query module, configured to query an address space mapping table stored in a first address space mapping module in a processor core when a memory access is initiated by the processor core, to obtain a target memory interface corresponding to a target memory address to be accessed; a second query module, configured to query a directory in an input / output core connected to the processor core, to obtain target cache coherence information corresponding to the target memory interface; and a reading module, configured to determine a target processor core storing a target cache block corresponding to the target memory interface and closest to the processor core based on the target cache coherence information, and read the target cache block in the target processor core.

[0030] According to an embodiment of the present application, the storage access device of the multi-core processor chip further comprises a configuration module, configured to configure the address space mapping table according to an access requirement of a currently running program.

[0031] According to an embodiment of the present application, the configuration module is further configured to group the memory interfaces based on the access requirement to obtain at least one group, divide the memory addresses corresponding to the chip into each group to obtain group memory addresses corresponding to each group respectively, divide the group memory addresses corresponding to any group into each memory interface contained in the group to obtain memory blocks corresponding to each memory interface in the group respectively, and establish the address space mapping table based on the correspondence between the memory interfaces and the memory blocks.

[0032] According to an embodiment of the present application, the configuration module is further configured to, if the group is one, take the memory addresses of the chip as the group memory addresses of the group, and if the group is multiple, determine group identification bits based on the number of groups and divide the memory addresses corresponding to the chip into each group according to the group identification bits to obtain group memory addresses corresponding to each group respectively.

[0033] According to an embodiment of the present application, the configuration module is further configured to, if the group contains one memory interface, take the group memory addresses corresponding to the group as the memory blocks corresponding to the memory interface contained in the group, and if the group contains multiple memory interfaces, determine cross identification bits in combination with the number of memory interfaces in the group and the number of memory row bytes, and divide the group memory addresses corresponding to the group into each memory interface contained in the group according to the cross identification bits to obtain memory blocks corresponding to each memory interface in the group respectively.

[0034] According to an embodiment of the present application, the configuration module is further configured to, when the access requirement of the currently running program changes, dynamically update the address space mapping table according to the changed access requirement.

[0035] According to one embodiment of the present application, the configuration module is further configured to: after the address space mapping table is updated, synchronously update directory information corresponding to the memory interface where the address mapping change occurs.

[0036] To achieve the above object, the fourth aspect of the present application provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to implement the storage access method of the multi-corelet processor chip according to the second aspect of the present application.

[0037] To achieve the above object, the fifth aspect of the present application provides a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are used to implement the storage access method of the multi-corelet processor chip according to the second aspect of the present application.

[0038] To achieve the above object, the sixth aspect of the present application provides a computer program product comprising a computer program, which, when executed by a processor, implements the storage access method of the multi-corelet processor chip according to the second aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 is an exemplary architecture diagram of a multi-corelet processor chip shown in the present application.

[0041] Figure 2 is an architecture diagram of a processor corelet shown in the present application.

[0042] Figure 3 is an architecture diagram of an input / output corelet shown in the present application.

[0043] Figure 4 is an architecture diagram of an 8-processor corelet, 1-input / output corelet integrated multi-corelet processor chip embodiment shown in the present application.

[0044] Figure 5 is an architecture diagram of an 8-processor corelet, 4-input / output corelet integrated multi-corelet processor chip embodiment shown in the present application.

[0045] Figure 6 is a schematic diagram of an exemplary implementation of a storage access method of a multi-corelet processor chip shown in the present application.

[0046] Figure 7is an exemplary schematic diagram of a method of configuring an address space mapping table according to access requirements of a current running program shown in the present application.

[0047] Figure 8 is an exemplary schematic diagram of a memory access device of a multi-core processor chip shown in the present application.

[0048] Figure 9 is a schematic diagram of an electronic device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0049] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which the same or similar notations used throughout the drawings and the specification denote the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, and should not be understood as limiting the present application.

[0050] Figure 1 is an exemplary architecture schematic diagram of a multi-core processor chip shown in the present application, as shown in Figure 1 the multi-core processor chip comprises at least one processor core and at least one input / output core.

[0051] wherein, Figure 2 is an architecture schematic diagram of a processor core shown in the present application, as shown in Figure 2 the processor core comprises one or more general-purpose processor cores (CPU cores), a first address space mapping module, and a first core interconnection interface, and the general-purpose processor cores support cache coherence.

[0052] wherein, Figure 3 is an architecture schematic diagram of an input / output core shown in the present application, as shown in Figure 3 the input / output core comprises a memory interface, a directory, a second address space mapping module, and a second core interconnection interface.

[0053] wherein, Figure 3 For example, the number of memory interfaces is 8, and the number of memory interfaces can be set according to actual requirements.

[0054] wherein, Figure 3 For example, the number of second core interconnection interfaces is 8, and the number of second core interconnection interfaces can be set according to actual requirements.

[0055] wherein, the first address space mapping module and the second address space mapping module each store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by the processor core and the memory interface of the input / output core.

[0056] The address space mapping table can be dynamically configured according to the access requirements of the currently running program.

[0057] The second address space mapping table can be used to forward the request to other input / output granules by address matching when a memory access request has arrived at a certain input / output granule and the target address of the request does not belong to the local range of the current input / output granule.

[0058] Among them, refer to Figure 1 To understand this, the first interconnect interface of the processor chip and the second interconnect interface of the input / output chip can be connected to realize the connection between the processor chip and the input / output chip.

[0059] Among them, refer to Figure 1 It can be understood that different input / output chips can be connected through a second chip interconnect interface.

[0060] The memory interface can be various types of memory, such as DDR (Double Data Rate) memory and LPDDR (Low Power Double Data Rate) memory. The memory interface is responsible for accessing the memory space corresponding to a multi-chip processor; that is, the multi-chip processor accesses memory through the memory interface.

[0061] Among them, such as Figure 3 As shown, in some optional configurations, the input / output chips can also include high-speed interfaces and / or low-speed interfaces. The number of high-speed and / or low-speed interfaces can be set according to actual needs.

[0062] High-speed interfaces include PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) and ETH (Ethernet).

[0063] Low-speed interfaces include UART (Universal Asynchronous Receiver-Transmitter), I2C (Inter-Integrated Circuit), and SPI (Serial Peripheral Interface).

[0064] The directory is mainly used to maintain cache coherency of the multi-core processor chip. The directory stores cache coherency information of cache blocks corresponding to memory interfaces of the input / output core and other input / output cores in the multi-core processor chip.

[0065] In the present application, for any memory interface, all memory addresses corresponding to the memory interface are referred to as a memory block corresponding to the memory interface. The cache block corresponding to the memory block is stored in a general processor core of the processor core as needed.

[0066] For any input / output core, the directory contained therein includes a plurality of sub-directories. Figure 3 For example, the input / output core shown in FIG. 1 includes a plurality of sub-directories, which are the directory of the input / output core or the directory of other input / output cores.

[0067] Each sub-directory corresponds to one or more memory interfaces. The sub-directory is used to store cache coherency information of cache blocks corresponding to the memory interfaces.

[0068] The cache coherency information includes a presence position and a presence state of the cache block in each processor core.

[0069] The presence position of the cache block in each processor core is stored in the form of a bit vector. If the cache block corresponding to the memory address of the memory interface exists in the cache of which processor core, the position corresponding to the bit vector is set to 1, otherwise, the position corresponding to the bit vector is set to 0.

[0070] In some implementable manners, the presence position of the cache block in each processor core can also be stored in the form of a number table. Each processor core corresponds to a unique number. If the cache block corresponding to the memory address of the memory interface exists in the cache of which processor core, the number of the processor core is recorded in the directory.

[0071] The presence state includes an invalid state (Invalid), a shared state (Shared), and an exclusive state (Exclusive). In some protocols, the presence state can also include an owning state and a modified state.

[0072] In the physical layout, the first core interconnect and the second core interconnect that have a connection relationship between the processor core and the input / output core are arranged adjacently to make the access of the processor core as close as possible.

[0073] In different input / output cores, the second core interconnects that have a connection relationship are arranged adjacently.

[0074] The sub-directories are arranged adjacent to the memory interfaces corresponding thereto in the same input-output corelet.

[0075] The memory interfaces and the second corelet interface are connected to each other according to the access frequency of the processor corelet to optimize the layout of the wires.

[0076] The memory interfaces support dynamic grouping according to the access requirement of the currently running program. When designing the multi-core processor chip, the access wire ports of the memory interfaces in the same initial grouping are designed based on the principle of placing nearby according to the initial grouping scheme of the memory interfaces, so as to optimize the signal transmission efficiency.

[0077] Preferably, the initial grouping scheme can be set as 1 group for every 2 memory interfaces, and the access wire ports of the 2 memory interfaces in the same initial grouping are designed based on the principle of placing nearby. In this way, the subsequent dynamic grouping requirements can be compatible, that is, even in the process of dynamic grouping according to the access requirement of the currently running program, as long as the number of memory interfaces in each group is a multiple of 2, the signal transmission efficiency can be optimized to the greatest extent by means of the pre-designed wires.

[0078] The application can be understood in combination with Figure 4 Figure 4 is an embodiment architecture diagram of a multi-core processor chip integrated with 8 processor corelets and 1 input-output corelet shown in the application. As shown in Figure 4 Figure 4 The directory of the input-output corelet in Figure 4 includes 8 sub-directories, namely Figure 4 The input-output corelet in includes 8 memory interfaces, namely memory interface 0~memory interface 7, which can be set as 1 directory corresponding to 1 memory interface, that is, directory 0 corresponds to memory interface 0, which is used to save the existence position and existence state of the cache block corresponding to memory interface 0 in each processor corelet; directory 1 corresponds to memory interface 1, which is used to save the existence position and existence state of the cache block corresponding to memory interface 1 in each processor corelet; directory 2 corresponds to memory interface 2, which is used to save the existence position and existence state of the cache block corresponding to memory interface 2 in each processor corelet; and so on.

[0079] When the physical layout is performed, as shown in Figure 4 ​As shown, assuming that processor core 0 and processor core 1 frequently access the memory corresponding to memory interface 0 and memory interface 1, processor core 2 and processor core 3 frequently access the memory corresponding to memory interface 2 and memory interface 3, processor core 4 and processor core 5 frequently access the memory corresponding to memory interface 4 and memory interface 5, and processor core 6 and processor core 7 frequently access the memory corresponding to memory interface 6 and memory interface 7, then processor core 0 and processor core 1 are physically arranged close to the core interconnect interface of the input / output core, and the two processor cores most frequently access the continuously-addressed memory interface 0 and memory interface 1 and the corresponding directory 0 and directory 1; similarly, processor core 2 and processor core 3 are physically arranged close to the core interconnect interface of the input / output core, and the two processor cores most frequently access the continuously-addressed memory interface 2 and memory interface 3 and the corresponding directory 2 and directory 3; similarly, processor core 4 and processor core 5 are physically arranged close to the core interconnect interface of the input / output core, and the two processor cores most frequently access the continuously-addressed memory interface 4 and memory interface 5 and the corresponding directory 4 and directory 5; and similarly, processor core 6 and processor core 7 are physically arranged close to the core interconnect interface of the input / output core, and the two processor cores most frequently access the continuously-addressed memory interface 6 and memory interface 7 and the corresponding directory 6 and directory 7. Figure 4 The bold black line indicates the part of the memory interface access line, as shown in Figure 4 The two memory interface (such as DDR (Double Data Rate) memory) access line ports are placed as close as possible to achieve the goal of the shortest physical line to speed up access.

[0080] Among them, Figure 4 The 8 first address space mapping modules and 1 second address space mapping module in each of the address space mapping tables store the mapping relationship between the memory address accessed by the processor core and the memory interface of the input / output core.

[0081] It can be understood in combination with Figure 5 , Figure 5 is an embodiment of a multi-core processor chip with 8 processor cores and 4 input / output cores according to the present application, as shown in Figure 5As shown, the input-output kernel 0 includes the memory interface 0 and the memory interface 1, the input-output kernel 1 includes the memory interface 2 and the memory interface 3, the input-output kernel 2 includes the memory interface 4 and the memory interface 5, and the input-output kernel 3 includes the memory interface 6 and the memory interface 7. The input-output kernel 0 stores not only the directory of the memory addresses of the memory interface 0 and the memory interface 1 corresponding to the input-output kernel 0 itself, but also the directories of the memory addresses of the memory interface 2 and the memory interface 3 corresponding to the input-output kernel 1, and the directories of the memory addresses of the memory interface 4 and the memory interface 5 corresponding to the input-output kernel 2, and the directories of the memory addresses of the memory interface 6 and the memory interface 7 corresponding to the input-output kernel 3. Similarly, the input-output kernel 1 stores the directories of the memory addresses of the memory interface 0 and the memory interface 1 corresponding to the input-output kernel 0, the directories of the memory addresses of the memory interface 2 and the memory interface 3 corresponding to the input-output kernel 1 itself, and the directories of the memory addresses of the memory interface 4 and the memory interface 5 corresponding to the input-output kernel 2, and the directories of the memory addresses of the memory interface 6 and the memory interface 7 corresponding to the input-output kernel 3.

[0082] wherein, Figure 5 The eight first address space mapping modules and the four second address space mapping modules in the memory access method of the multi-kernel processor chip store address space mapping tables, which store the mapping relationship between the memory addresses accessed by the processor kernels and the memory interfaces of the input-output kernels.

[0083] The multi-kernel processor chip proposed in the present application stores not only the directory corresponding to each input-output kernel of the multi-kernel chip itself, but also the directories corresponding to other input-output kernels. Therefore, all the directory information can be accessed on the local input-output kernel, and there is no need to access the directories on other input-output kernels, thereby reducing the long delay access across the kernels and improving the performance of the multi-kernel processor chip.

[0084] Based on the multi-kernel processor chip proposed in the present application introduced above, the memory access method of the multi-kernel processor chip applied to the multi-kernel processor chip is introduced next.

[0085] Figure 6 is a schematic diagram of an exemplary embodiment of the memory access method of a multi-kernel processor chip proposed in the present application, as shown in Figure 6 The memory access method of the multi-kernel processor chip includes the following steps:

[0086] S601, when a processor kernel initiates a memory access, querying the address space mapping table stored in the first address space mapping module in the processor kernel to obtain the target memory interface corresponding to the target memory address to be accessed.

[0087] S602, querying the directory in the input-output kernel having a connection relationship with the processor kernel to obtain the target cache coherence information corresponding to the target memory interface.

[0088] S603, based on the target cache coherence information, determining the target processor kernel storing the target cache block corresponding to the target memory interface and being closest to the processor kernel, and reading the target cache block in the target processor kernel.

[0089] The following will be taken as an example to introduce the specific implementation of S601-S603. Figure 5

[0090] According to the above introduction, the input / output kernel 0 not only stores the directory of the memory addresses of the memory interface 0 and the memory interface 1 corresponding to the input / output kernel 0, but also stores the directory of the memory addresses of the memory interface 2 and the memory interface 3 corresponding to the input / output kernel 1, the directory of the memory addresses of the memory interface 4 and the memory interface 5 corresponding to the input / output kernel 2, and the directory of the memory addresses of the memory interface 6 and the memory interface 7 corresponding to the input / output kernel 3.

[0091] When the processor kernel 0 of the multi-kernel processor chip queries the address space mapping table stored in the first address space mapping module in the processor kernel 0, the memory address addr5 of the memory interface 5 to be accessed is obtained, and the access process is as follows: the processor kernel 0 accesses the nearest input / output kernel 0, and since the input / output kernel 0 contains the input / output kernel 2 directory which stores the directory corresponding to the memory of the memory interface 5, the processor kernel 0 obtains the state of the cache block corresponding to the memory address addr5 of the memory interface 5 from the input / output kernel 2 directory contained in the input / output kernel 0 and the cache block exists in which processor kernel. For example, the cache block of the memory address addr5 obtained by querying the input / output kernel 2 directory contained in the input / output kernel 0 is in a shared state (Shared), and the directory bit vector is {00000100}, which represents from left to right in the bit vector whether a backup exists in the 7th processor kernel to the 0th processor kernel. Since the value corresponding to the processor kernel 2 is 1, a backup also exists in the processor kernel 2. After querying the directory, the data of the cache block shared backup of the addr5 address can be directly obtained through the link of the input / output kernel 0→input / output kernel 1→processor kernel 2. The entire access path is processor kernel 0→input / output kernel 0 (accessing the directory)→input / output kernel 1→processor kernel 2 (obtaining data), which greatly reduces the storage access delay of the multi-kernel processor chip. The process of processor kernel 0→input / output kernel 0→input / output kernel 1→input / output kernel 2 (accessing the directory)→input / output kernel 1→processor kernel 2 (obtaining data) is avoided. The 6-hop long-delay cross-kernel access is shortened to 4-hop, saving 2-hop cross-kernel access, which greatly improves the performance of the multi-kernel processor chip.

[0092] The address space mapping table can be a fixed address space mapping table, or can be dynamically configured according to the access requirements of the currently running program.

[0093] Figure 7 ​is an exemplary schematic diagram of a method of configuring an address space mapping table according to access requirements of a currently running program, as shown in Figure 7 The method of configuring an address space mapping table according to access requirements of a currently running program comprises the following four steps:

[0094] S701, grouping the memory interfaces based on access requirements to obtain at least one group.

[0095] In some implementations, the memory interfaces can be divided into groups, where m is an integer greater than or equal to 0. For example, the memory interfaces can be divided into 1 group, 2 groups, 4 groups, 8 groups, etc.

[0096] Exemplarily, taking Figure 4 for example, if the address space used by each processor core of the multi-core processor chip covers the entire chip, then the 8 memory interfaces of the entire chip can be grouped together, i.e., memory interface 0, memory interface 1, memory interface 2, memory interface 3, memory interface 4, memory interface 5, memory interface 6, and memory interface 7 form a group.

[0097] Exemplarily, taking Figure 4 for example, if the address space used by each processor core of the multi-core processor chip is relatively small, and a block of memory can be covered by one memory interface, then each memory interface can be a separate group, i.e., memory interface 0 corresponds to group 0, memory interface 1 corresponds to group 1, and so on, and memory interface 7 corresponds to group 7.

[0098] Exemplarily, taking Figure 4 for example, if the address space used by each processor core is covered by the address space of 4 memory interfaces, then every 4 memory interfaces can form a group. That is, memory interface 0, memory interface 1, memory interface 2, and memory interface 3 correspond to group 0, and memory interface 4, memory interface 5, memory interface 6, and memory interface 7 correspond to memory group 1.

[0099] As mentioned above, the subdirectory corresponds to one or more memory interfaces, i.e., it can be understood that the subdirectory and the memory interface can be decombined and recombined according to the access requirements of the currently running program. The subdirectory and the memory interface required by the program running on the processor core can be combined together to achieve efficient access.

[0100] S702, dividing the memory addresses corresponding to the chip into groups to obtain the group memory addresses corresponding to each group.

[0101] The memory interfaces have been grouped as described above, and the following describes the grouping mapping of the complete memory addresses corresponding to the entire chip based on the grouping of the memory interfaces.

[0102] If the obtained group is one, the memory address of the whole chip is taken as the group memory address of the group.

[0103] If the obtained group is multiple, the group identification bit is determined based on the number of groups, and the memory address corresponding to the whole chip is divided into each group according to the group identification bit, to obtain the group memory address corresponding to each group respectively.

[0104] The group memory address refers to the memory address corresponding to the corresponding group.

[0105] In the present application, if the memory interface is divided into groups, the high m bits of the memory address are taken as the group identification bit, so as to ensure that the memory addresses in the continuous address space can be divided into the same group, and the nearby access of the processor core is ensured.

[0106] For example, if the physical address of the multi-core processor chip is 39 bits, that is, the physical address paddr[38:0]. It is assumed that the memory interface is divided into groups, which are group 0~group 3, that is, the value of m is 2. At this time, paddr[38:37] is taken as the group identification bit. If paddr[38:37] is 00, it corresponds to group 0; if paddr[38:37] is 01, it corresponds to group 1; if paddr[38:37] is 10, it corresponds to group 2; if paddr[38:37] is 11, it corresponds to group 3.

[0107] For example, if the physical address of the multi-core processor chip is 39 bits, that is, the physical address paddr[38:0]. It is assumed that the memory interface is divided into groups, which are group 0 and group 1, that is, the value of m is 1. At this time, paddr

[38] is taken as the group identification bit. If paddr

[38] is 0, it corresponds to group 0; if paddr

[38] is 1, it corresponds to group 1.

[0108] For example, if the physical address of the multi-core processor chip is 39 bits, that is, the physical address paddr[38:0]. It is assumed that the memory interface is divided into groups, which are group 0~group 7, that is, the value of m is 3. At this time, paddr[38:36] is taken as the group identification bit.

[0109] S703, for any group, the group memory address corresponding to the group is divided into each memory interface contained in the group, to obtain the memory block corresponding to each memory interface in the group respectively.

[0110] If the obtained group contains one memory interface, the group memory address corresponding to the group is taken as the memory block corresponding to the memory interface contained in the group.

[0111] If the obtained group contains multiple memory interfaces, the memory in the group uses cross-addressing mode, and the low address in the group determines which memory interface corresponding to the memory in the group, so as to fully exert the parallelism of memory access. And the cross-addressing takes the memory row size as the granularity of cross-addressing, guarantees the operation on the open page of the memory (Open Page), and reduces the precharge of the memory row. Specifically, the cross identification bit is determined in combination with the number of memory interfaces in the group and the number of memory row bytes, and the group memory address corresponding to the group is divided into each memory interface contained in the group according to the cross identification bit, to obtain the memory block corresponding to each memory interface in the group.

[0112] In the present application, if the number of memory interfaces in the group is p is a positive integer, the number of memory row bytes is q is a positive integer, paddr[q+p-1:q] is taken as the cross identification bit.

[0113] For example, assuming that each group contains 2 memory interfaces, that is, p=1, if the number of memory row bytes is that is, q=12, paddr

[12] is taken as the cross identification bit. Taking the group 0 containing the memory interface 0 and the memory interface 1 as an example, if the paddr

[12] bit of the group memory address corresponding to the group 0 is 0, the address is mapped to the memory corresponding to the memory interface 0; if the paddr

[12] bit of the group memory address corresponding to the group 0 is 1, the address is mapped to the memory corresponding to the memory interface 1. In this way, it is ensured that when writing into the grain, it is accessed according to a row, to guarantee more memory access on the open page of the memory (Open Page) and reduce the delay caused by the precharge of the memory row. The addresses corresponding to the memory interfaces in the group of other groups are also mapped in this way, which will not be described here.

[0114] For example, assuming that each group contains 4 memory interfaces, that is, p=2, if the number of memory row bytes is that is, q=12, paddr[13:12] is taken as the cross identification bit.

[0115] For example, assuming that each group contains 8 memory interfaces, that is, p=3, if the number of memory row bytes is that is, q=12, paddr[14:12] is taken as the cross identification bit.

[0116] For example, assuming that each group contains a memory interface if the number of memory row bytes is that is, q=12, paddr[12+p-1:12] is used as the cross identification bit.

[0117] S704, based on the correspondence between the memory interface and the memory block, an address space mapping table is established.

[0118] The correspondence between the memory interface and the memory block has been obtained, and the address space mapping table can be established based on the correspondence.

[0119] Further, the address space mapping table can be dynamically configured according to the access demand of the currently running program as introduced above. It is not difficult to understand that when the access demand of the currently running program changes, the address space mapping table is dynamically updated again according to the changed access demand.

[0120] Further, it is not difficult to understand that after the address space mapping table is updated, the memory interface whose address mapping changes and the corresponding cache block in each processor core and the state of the cache block also change, so the directory information corresponding to the memory interface whose address mapping changes also needs to be updated synchronously.

[0121] Figure 8 is an exemplary schematic diagram of a storage access device of a multi-core processor chip shown in the present application, as Figure 8 shown, the storage access device 800 of the multi-core processor chip includes a first query module 801, a second query module 802 and a reading module 803, wherein:

[0122] The first query module 801 is configured to, when the processor core initiates memory access, query the address space mapping table stored by the first address space mapping module in the processor core to obtain the target memory interface corresponding to the target memory address to be accessed.

[0123] The second query module 802 is configured to query the directory in the input / output core having a connection relationship with the processor core to obtain the target cache coherence information corresponding to the target memory interface.

[0124] The reading module 803 is configured to determine the target processor core having the target cache block corresponding to the target memory interface and being closest to the processor core based on the target cache coherence information, and read the target cache block in the target processor core.

[0125] Further, the storage access device 800 of the multi-core processor chip further includes a configuration module configured to configure the address space mapping table according to the access demand of the currently running program.

[0126] Further, the configuration module is further configured to: group the memory interfaces based on the access demand to obtain at least one group; divide the memory addresses corresponding to the chip into the groups to obtain group memory addresses corresponding to the groups respectively; for any group, divide the group memory addresses corresponding to the group into the memory interfaces included in the group to obtain memory blocks corresponding to the memory interfaces in the group respectively; and establish an address space mapping table based on the correspondence between the memory interfaces and the memory blocks.

[0127] Further, the configuration module is further configured to: if the number of groups is one, use the memory addresses of the chip as the group memory addresses of the groups; and if the number of groups is more than one, determine group identification bits based on the number of groups, and divide the memory addresses corresponding to the chip into the groups according to the group identification bits to obtain group memory addresses corresponding to the groups respectively.

[0128] Further, the configuration module is further configured to: if the group includes one memory interface, use the group memory addresses corresponding to the group as the memory blocks corresponding to the memory interface included in the group; and if the group includes a plurality of memory interfaces, determine cross identification bits based on the number of memory interfaces in the group and the number of memory row bytes, and divide the group memory addresses corresponding to the group into the memory interfaces included in the group according to the cross identification bits to obtain memory blocks corresponding to the memory interfaces in the group respectively.

[0129] Further, the configuration module is further configured to: when the access demand of the currently running program changes, dynamically update the address space mapping table according to the changed access demand.

[0130] Further, the configuration module is further configured to: after the address space mapping table is updated, synchronously update the directory information corresponding to the memory interfaces for which the address mapping changes.

[0131] To implement the above-mentioned embodiments, the embodiments of the present application further propose an electronic device 900, as shown in the figure, the electronic device 900 comprises a processor 901 and a memory 902 in communication connection with the processor 901, and the memory 902 stores instructions executable by at least one processor 901, and the instructions are executed by the at least one processor 901 to implement the memory access method of the multi-core processor chip as shown in the above-mentioned embodiments. Figure 9

[0132] To implement the above-mentioned embodiments, the embodiments of the present application further propose a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are used to make a computer implement the memory access method of the multi-core processor chip as shown in the above-mentioned embodiments.

[0133] To implement the above-mentioned embodiments, the embodiments of the present application further propose a computer program product comprising a computer program, and the computer program is executed by a processor to implement the memory access method of the multi-core processor chip as shown in the above-mentioned embodiments.​

[0134] In addition, the terms "first", "second", etc. are used only to describe various features and do not imply or imply relative importance or a number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0135] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, the person skilled in the art can combine and combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0136] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A multi-chip processor chip, characterized in that, include: At least one processor core, the processor core comprising a general-purpose processor core, a first address space mapping module and a first core interconnect interface, the general-purpose processor core supporting cache coherency; At least one input / output chip, the input / output chip including a memory interface, a directory, a second address space mapping module, and a second chip interconnection interface; Both the first address space mapping module and the second address space mapping module store an address space mapping table, which stores the mapping relationship between the memory addresses accessed by the processor chip and the memory interfaces of the input / output chip; The directory stores cache consistency information for cache blocks corresponding to the memory interfaces of its own input / output chip and other input / output chips.

2. The chip according to claim 1, characterized in that, in: The directory includes multiple subdirectories; Each of the subdirectories corresponds to one or more memory interfaces; The subdirectory stores cache consistency information of the cache blocks corresponding to its memory interface; The cache consistency information includes the location and state of the cache block in each of the processor chips.

3. The chip according to claim 2, characterized in that, The location of the cache block in each of the processor chips is stored in bit vector form.

4. The chip according to claim 2, characterized in that, The existence states include invalid state, shared state, and exclusive state.

5. The chip according to claim 1, characterized in that, The input / output chip also includes a high-speed interface and / or a low-speed interface.

6. The chip according to any one of claims 1-5, characterized in that, in: The address space mapping table can be dynamically configured according to the access requirements of the currently running program.

7. The chip according to claim 2, characterized in that, in: The first chip interconnect interface and the second chip interconnect interface, which are connected to the processor chip and the input / output chip, are arranged adjacent to each other. The second chip interconnect interfaces that are connected to different input / output chips are arranged adjacently.

8. The chip according to claim 7, characterized in that, in: Within the same input / output chip, the subdirectory is arranged adjacent to its corresponding memory interface; and, The interconnect interface between the memory interface and the second chip is optimized in terms of routing layout based on the access frequency of the processor chip.

9. The chip according to claim 2, 7, or 8, characterized in that, in: The memory interface supports dynamic grouping based on the access requirements of the currently running program. When designing the multi-chip processor chip, the access traces of each memory interface in the same initial group are designed based on the principle of proximity, according to the initial grouping scheme for the memory interface.

10. A memory access method for a multi-chip processor, applied to the chip according to any one of claims 1-9, characterized in that, include: When the processor chip initiates memory access, it queries the address space mapping table stored in the first address space mapping module within the processor chip to obtain the target memory interface corresponding to the target memory address to be accessed. Query the directory within the input / output core that has a connection relationship with the processor core to obtain the target cache consistency information corresponding to the target memory interface; Based on the target cache consistency information, a target processor chip that stores the target cache block corresponding to the target memory interface and is closest to the processor chip is determined, and the target cache block in the target processor chip is read.

11. The method according to claim 10, characterized in that, The configuration process of the address space mapping table includes: Configure the address space mapping table according to the access requirements of the currently running program.

12. The method according to claim 11, characterized in that, The step of configuring the address space mapping table according to the access requirements of the currently running program includes: Based on the access requirements, the memory interfaces are grouped to obtain at least one group; The memory address corresponding to the chip is divided into each of the groups to obtain the group memory address corresponding to each group. For any of the aforementioned groups, the corresponding group memory address is divided into each memory interface contained therein, resulting in memory blocks corresponding to each memory interface within the group. Based on the correspondence between the memory interface and the memory block, the address space mapping table is established.

13. The method according to claim 12, characterized in that, The step of dividing the memory address corresponding to the chip into each group to obtain the group memory address corresponding to each group includes: If there is only one group, the memory address of the chip is used as the group memory address of the group; If there are multiple groups, a group identifier bit is determined based on the number of groups, and the memory address corresponding to the chip is divided into each group according to the group identifier bit to obtain the group memory address corresponding to each group.

14. The method according to claim 13, characterized in that, The step of dividing the corresponding group memory address into its constituent memory interfaces to obtain the memory blocks corresponding to each memory interface within the group includes: If the group contains one memory interface, the group memory address corresponding to the group is taken as the memory block corresponding to the memory interface it contains; If the group contains multiple memory interfaces, the cross-identity bit is determined by combining the number of memory interfaces in the group with the number of bytes in the memory row, and the group memory address corresponding to the group is divided into each memory interface it contains according to the cross-identity bit, so as to obtain the memory block corresponding to each memory interface in the group.

15. The method according to any one of claims 11-14, characterized in that, The method further includes: When the access requirements of the currently running program change, the address space mapping table is dynamically updated according to the changed access requirements.

16. The method according to claim 15, characterized in that, The method further includes: After the address space mapping table is updated, the directory information corresponding to the memory interface whose address mapping has changed is updated synchronously.

17. A memory access device for a multi-chip processor, characterized in that, include: The first query module is used to query the address space mapping table stored in the first address space mapping module within the processor core when the processor core initiates memory access, so as to obtain the target memory interface corresponding to the target memory address to be accessed. The second query module is used to query the directories within the input / output cores that are connected to the processor core, and obtain the target cache consistency information corresponding to the target memory interface; The read module is used to determine, based on the target cache consistency information, the target processor chip that stores the target cache block corresponding to the target memory interface and is closest to the processor chip, and to read the target cache block in the target processor chip.

18. An electronic device comprising: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 10-16.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 10-16.

20. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 10-16.

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