Fpga hybrid routing architecture with spatially heterogeneous interconnect fabric and evaluation method

Abstract

The present disclosure provides an FPGA hybrid wiring architecture with a spatially heterogeneous interconnection structure and an evaluation method. The FPGA hybrid wiring architecture with a spatially heterogeneous interconnection structure comprises: an FPGA chip divided into a plurality of sub-areas, each of the plurality of sub-areas being provided with a plurality of types of interconnection chips; each of the plurality of types of interconnection chips being provided with a wiring block connected with a logic block; the wiring block being provided to consist of one or more grouped areas, each area consisting of a first-level multiplexer group and a second-level multiplexer group, and the internal structure of the wiring block being determined according to a method of setting the internal structure of the wiring block. In addition, the present disclosure proposes a corresponding evaluation method for the FPGA hybrid wiring architecture with a spatially heterogeneous interconnection structure. The present disclosure aims to solve the problems of uneven resource utilization, serious wiring detour, and large area and delay waste of the traditional FPGA wiring structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip design, in particular to an FPGA hybrid routing architecture with spatial heterogeneous interconnection structure and an evaluation method. BACKGROUND

[0002] Most existing FPGAs adopt a global uniform routing structure, that is, all regions adopt the same interconnection topology (for example, CB-SB structure connected by single-level MUX). However, such uniform structure cannot effectively adapt to the difference in routing demand of different regions in actual applications, resulting in waste of resources in some regions, while in some other regions, the routing is too congested and has to be detoured, increasing the routing area and critical path delay.

[0003] Some commercial FPGAs introduce multi-level MUX structure to improve interconnection flexibility, but still do not fully utilize the spatial non-uniformity. Most existing academic researches only optimize the structure itself, and lack of architecture optimization mechanism for changes in routing demand of different regions. Therefore, there is an urgent need for a hybrid routing architecture with different interconnection structures in different regions to improve overall performance.

[0004] Therefore, the prior art still needs to be improved and improved.

[0005] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In order to solve at least one of the above problems, and one or more of other potential problems, the present disclosure proposes an FPGA hybrid routing architecture with spatial heterogeneous interconnection structure, aiming to solve the problems of uneven resource utilization, serious routing detour, large area and delay waste of traditional FPGA routing structure.

[0007] In a first aspect of the present disclosure, a FPGA hybrid routing architecture with spatially heterogeneous interconnect structure is provided, which comprises: an FPGA chip divided into a plurality of sub-areas, each of the plurality of sub-areas is provided with a plurality of types of interconnect tiles; each of the plurality of types of interconnect tiles is provided with a routing block connected with a logic block; the routing block is provided to be composed of one or more group areas, each area is composed of a first level multiplexer group and a second level multiplexer group, and a method of setting the internal structure of the routing block comprises: determining the type to which the interconnect tile where the routing block is located belongs; determining the number of groups to which the second level multiplexer group output is connected with the logic block input; determining the number of groups to which the second level multiplexer group output is connected with the wire; determining the number of multiplexers in the first level multiplexer group in each group area within the routing block; determining the selectivity of the first level multiplexer group in each group area within the routing block with respect to the second level multiplexer group connected with the logic block input; determining the selectivity of the first level multiplexer group in each group area within the routing block with respect to the second level multiplexer group connected with the wire.

[0008] Further, in some embodiments, the method of setting the internal structure of the routing block further comprises: determining the selectivity of the direct wire in each group area within the routing block with respect to the second level multiplexer group connected with the logic block input; determining the selectivity of the direct wire in each group area within the routing block with respect to the second level multiplexer group connected with the wire.

[0009] Further, in some embodiments, the determining the number of groups to which the second level multiplexer group output is connected with the logic block input comprises: determining the number of groups to which the second level multiplexer group output is connected with the logic block input; storing the number of groups as a logic block input group number parameter .

[0010] Further, in some embodiments, the determining the number of groups to which the second level multiplexer group output is connected with the wire comprises: determining the number of groups to which the second level multiplexer group output is connected with the wire; storing the number of groups as a wire group number parameter .

[0011] Further, in some embodiments, determining the gating property of the first-level multiplexer group in each group region within the wiring block with respect to the second-level multiplexer group connected to the logic block input includes: determining the number M2pN of multiplexers M2pN connected to the first-level multiplexer group in each group region within the wiring block and connected to the logic block input; determining the total number M1N of multiplexers M1N in the first-level multiplexer group in each group region within the wiring block; and obtaining the gating property as a gating ratio parameter for the logic block input group of the two-level multiplexers. ,in .

[0012] Further, in some embodiments, determining the gating property of the first-level multiplexer group in each group region within the wiring block with respect to the second-level multiplexer group connected to the logic block input includes: determining the number M2wN of multiplexers M2wN connected to any multiplexer in the second-level multiplexer group connected to the connection in each group region within the wiring block and multiplexers M1N in the first-level multiplexer group within the same region; determining the total number M1N of multiplexers M1N in the first-level multiplexer group in each group region within the wiring block; and obtaining the gating property as a gating ratio parameter for the two-level multiplexer connection group. ,in .

[0013] Further, in some embodiments, determining the gating property of direct connections in each group of regions within the wiring block with respect to the second-level multiplexer group connected to the logic block input includes: determining the number D2pdN of multiplexers connected to any multiplexer in the second-level multiplexer group connected to the logic block input in each group of regions within the wiring block and the direct connections in that region; determining the total number D1dN of direct connections in each group of regions within the wiring block; and obtaining the gating property as a gating ratio parameter for the direct-connect multiplexer logic block input group. ,in .

[0014] Further, in some embodiments, determining the gating property of direct connections in each group of areas within the cabling block with respect to the second-level multiplexer group connected to the connection includes: determining the number D2wdN of multiplexers connected to any multiplexer in the second-level multiplexer group connected to the connection in each group of areas within the cabling block and the direct connections in that area; determining the total number D1dN of direct connections in each group of areas within the cabling block; and obtaining the gating property as a gating ratio parameter for direct-connect multiplexer connection groups. ,in .

[0015] Furthermore, in some embodiments, the method for partitioning the FPGA chip into multiple regions includes: dividing the FPGA chip into R regions by rows or columns; setting up to use a maximum of K different types of interconnect chips; and determining the type of interconnect chip used in each region through a mapping vector P.

[0016] In a second aspect of this disclosure, an evaluation method for the aforementioned FPGA hybrid routing architecture is proposed. The method includes: acquiring description information and corresponding timing report information of the FPGA hybrid routing architecture; converting the description information to acquire corresponding routing resource graphs and global features; statistically analyzing the frequency information of critical path nodes based on the timing report information; and acquiring the routing availability and area-delay product values ​​of the FPGA based on the acquired routing resource graphs, global features, and frequency information of critical path nodes.

[0017] This disclosure has the following advantages over the prior art:

[0018] In some embodiments of this disclosure, by dividing the FPGA chip into multiple sub-regions, and setting various types of interconnect chips in each sub-region, combined with the internal structure of the wiring block, the method of this disclosure allows for dynamic selection of an appropriate interconnect structure based on the wiring pressure of different regions, avoiding resource waste and excessive congestion. Furthermore, by reducing redundant MUX structures, a more compact interconnect layout is achieved, saving wiring area. Furthermore, by optimizing local interconnect structures, wiring path detours are reduced, improving timing performance. In addition, in some embodiments, wiring detour distances are reduced, significantly improving wiring compactness, thereby comprehensively improving performance and resource efficiency. Attached Figure Description

[0019] The above and other features, advantages and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description, wherein:

[0020] Figure 1 This diagram illustrates an interconnect chip array based on a typical single-topology wiring block.

[0021] Figure 2 A schematic diagram of an interconnect chip array using multiple types of wiring blocks according to an embodiment of the present disclosure is shown;

[0022] Figure 3 A schematic diagram of the internal structure of an interconnect chip according to an embodiment of the present disclosure is shown;

[0023] Figure 4 A schematic diagram of the internal structure of a wiring block of an interconnect chip according to an embodiment of the present disclosure is shown;

[0024] Figure 5 A schematic diagram of the internal structure of a wiring block of another interconnect chip according to an embodiment of the present disclosure is shown; and

[0025] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0026] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0027] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0028] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0029] It should be noted that the interconnect tile in this disclosure may be referred to as a "block" or "piece" in some embodiments; the routability in this disclosure may be referred to as wiring capability or routable capability in some embodiments; the wire in this disclosure may be referred to as a conductor in some embodiments; and the multiplexer (MUX) in this disclosure may be referred to as a multiplexer in some embodiments.

[0030] It should be understood that, due to the limitation to a single-topology cabling architecture, i.e., all cabling blocks use cabling blocks with a single topology, such as... Figure 1As shown, these methods ignore the uneven utilization of multiplexers (MUX) across different regions, which can lead to excessive routing and wasted area for connections targeting a fixed application. For example, if the central part requires high routing capability, areas at the edges, even if infrequently called, might also be arranged with high routing capability, resulting in wasted space at the edges. Furthermore, these methods typically require frequent calls to the VTR for FPGA architecture evaluation, leading to excessive runtime overhead. This, in turn, limits the number of iterations for exploration and may cause opportunities to miss better solutions.

[0031] To address at least one of the aforementioned problems, and one or more other potential problems, this disclosure proposes an FPGA hybrid routing architecture with a spatially heterogeneous interconnect structure. This FPGA hybrid routing architecture includes: an FPGA chip divided into multiple sub-regions, each sub-region being provided with multiple types of interconnect chips, such as... Figure 2 As shown, its comparison Figure 1 All interconnect chips of the same type Figure 2 At least one type of interconnect is shown for each line in this disclosure; however, it should be understood that the type of interconnect in this disclosure is not necessarily as described above. Figure 2 Arranged as shown, Figure 2 The interconnect pieces in this example are merely exemplary. Furthermore, in some embodiments, each of the various types of interconnect pieces is provided with wiring blocks connected to logic blocks, such as... Figure 3 As shown, in Figure 3 In the diagram, the logic block (LB) is schematically drawn in the lower left corner, primarily showing the routing block (RB) that demonstrates its routing functionality. Furthermore, in some embodiments, the routing block is configured to consist of one or more grouped regions, for example, in... Figure 4 The image is divided into upper and lower grouped regions, defined by dashed boxes. Further, in some embodiments, each grouped region consists of a first-level multiplexer group (L1-MUXes) and a second-level multiplexer group (L2-MUXes), for example, in... Figure 4 In the diagram, multiple connections (e.g., inputs from logic block outputs (LB outputs) or other wires, divided near the left end, serve as inputs to the first-level multiplexer group (L1-MUXes). It should also be noted that in the first grouping region (the upper dashed box), the first-level multiplexer group (L1-MUXes) is shown as three multiplexers. In the second grouping region (the lower dashed box), the first-level multiplexer group (L1-MUXes) is shown as another three multiplexers. It should also be understood that in some embodiments, the multiplexers can be multi-stage, and...Figure 4 The example only shows two levels. More levels can be achieved by adding one or more multiplexers with electrical connections between the first-level multiplexer group (L1-MUXes) and the second-level multiplexer group (L2-MUXes).

[0032] Furthermore, in some embodiments, a method 100 for configuring the internal structure of a wiring block is described in more detail. This method 100 includes: step 110, determining the type of the interconnect chip to which the wiring block belongs, for example, using... Figure 2 The method divides and implements various types of connection chip layout structures; step 120, determines the number of groups connected to the output of the second-stage multiplexer group and the input of the logic block, such as... Figure 4 As shown, on the L2-MUXes side, there are two multiplexers whose outputs are schematically connected to the LB input. Clearly, the number of groups shown in the diagram is denoted as one group, i.e., Gp=1. Gp will be further described in the following implementation. Step 130: Determine the number of groups connected to the outputs of the L2-MUXes, as shown... Figure 4 As shown, on one side of the second-level multiplexer group (L2-MUXes), there are two sets of multiplexers (each set has two multiplexers). Their outputs are schematically connected to wires. Clearly, the number of groups in the diagram is recorded as two, i.e., Gw=2. Gw will be further described in the following implementation. Step 140: Determine the number of multiplexers in the first-level multiplexer group within each area of ​​the wiring block, as follows... Figure 4 As shown, in the first grouping region (i.e., the upper dashed box in the figure), the number of multiplexers is obviously 3 in the figure, i.e., Nf=3, where Nf is further described in the following implementation; Step 150, determine the selectivity of the first-level multiplexer group in each grouping region within the wiring block with respect to the second-level multiplexer group connected to the logic block input, as follows. Figure 4 As shown in the diagram, it is denoted as The following implementation further describes Pp; Step 160, determine the gating property of the first-level multiplexer group in each area within the wiring block with respect to the second-level multiplexer group connected to the wiring, such as... Figure 4 As shown in the diagram, it is denoted as Among them, regarding Further details are provided in the following implementation section.

[0033] Furthermore, in some embodiments, a method 200 for configuring the internal structure of a wiring block is also proposed. This method 200, in addition to the steps in method 100, further includes: step 170, determining the gating of direct connections within each group of regions within the wiring block with respect to the second-level multiplexer group connected to the logic block input, such as...Figure 5 As shown; Step 180, determine the gating of direct connections within each group of areas in the wiring block with respect to the second-level multiplexer group to which the connections are connected, such as... Figure 5 As shown.

[0034] Furthermore, in some embodiments, regarding step 120, determining the number of groups connected to the output of the second-stage multiplexer group and the logic block input specifically includes: determining the number of groups (illustrated as LB input connected group 1) connected to the output of the second-stage multiplexer group and the logic block input (LB input) (such groups) Figure 4 (Only 1 in the group); store the number of the group as a logic block input group number parameter. ,and Figure 4 middle .

[0035] Furthermore, in some embodiments, regarding step 130, determining the number of groups connected to the output of the second-stage multiplexer group and the wire specifically includes: determining the number of groups (illustrated as wire connected group 1 and wire connected group 2) connected to the output of the second-stage multiplexer group and the wire (such groups). Figure 4 There are 2 in total); store the number of the groups as a parameter for the number of connection groups. ,and Figure 4 middle .

[0036] Further, in some embodiments, regarding step 150, determining the glossability of the first-level multiplexer group in each group region within the wiring block with respect to the second-level multiplexer group connected to the logic block input specifically includes: determining the number M2pN of multiplexers M2pN in each group region within the wiring block that are connected to the second-level multiplexer group connected to the logic block input and the first-level multiplexer group in the same region, for example, in the first group region ( Figure 4 In the second-level multiplexer group (within the upper dashed box and connected to the logic block input), any one of the two multiplexers is connected to any one of the multiplexers in the first-level multiplexer group in that group region, i.e., M2pN=3; further, determine the total number M1N of multiplexers in the first-level multiplexer group in the first group region within the wiring block, for example, in the first group region ( Figure 4 If the first-level multiplexer group (within the upper dashed box) contains three multiplexers, then the total number M1N = 3; further, the gating ratio parameter of the input group of the two-level multiplexer logic block is obtained. ,in , that is Figure 4As shown in Pp.

[0037] Further, in some embodiments, regarding step 160, determining the selectivity of the first-level multiplexer group in each group region within the wiring block with respect to the second-level multiplexer group connected to the logic block input specifically includes: determining the number M2wN of multiplexers M2wN in each group region within the wiring block that are connected to the second-level multiplexer group connected to the wiring and the first-level multiplexer group in the same region, for example, in the first group region ( Figure 4 Any one of the two multiplexers in the second-level multiplexer group (within the upper dashed box and connected by the connecting line) is connected to two multiplexers in the first-level multiplexer group in that group area, i.e., M2pN=2; further, determine the total number M1N of multiplexers in the first-level multiplexer group in each group area within the wiring block, for example, in the first group area ( Figure 4 If the first-level multiplexer group (within the upper dashed box) contains three multiplexers, then the total number M1N = 3; further, the selectivity is obtained as the selection ratio parameter of the two-level multiplexer connection group. ,in , that is Figure 4 As shown in Pw. Alternative sites can also be... Figure 5 Taking the lower dashed box as an example, within the second group area, the gating ratio parameter of the two-stage multiplexer connection group can also be obtained. ,in .

[0038] Further, in some embodiments, regarding step 170, determining the glossability of direct connections within each group of regions in the wiring block with respect to the second-level multiplexer group connected to the logic block input specifically includes: determining the number D2pdN of multiplexers D2pdN in each group of regions in the wiring block that are connected to the direct connections within the region by any multiplexer in the second-level multiplexer group connected to the logic block input, for example, in the first group of regions ( Figure 5 In the second-level multiplexer group (within the upper dashed box and connected to the logic block input), either of the two multiplexers is not connected to any direct connection in that group area, i.e., D2pdN=0; further, the total number of direct connections D1dN in each group area within the wiring block is determined, for example, Figure 5 In the first group of regions, there is a single connection (entering the wiring block without being connected to the MUX), i.e., D1dN=1; further, the gating property is obtained as the gating ratio parameter of the input group of the direct-connect multiplexer logic block. ,in =D2pdN / D1dN, such asFigure 5 The following is what is shown: .

[0039] Further, in some embodiments, regarding step 180, determining the glossability of direct connections within each group of regions in the cabling block with respect to the second-level multiplexer group connected to the connection specifically includes: determining the number D2wdN of multiplexers D2wdN in each group of regions in the cabling block that are connected to the direct connections of any multiplexer in the second-level multiplexer group connected to the connection within the region, for example, in the first group of regions ( Figure 5 In the second-level multiplexer group (within the upper dashed box and connected by the connecting line), either of the two multiplexers is connected to a direct connection in that group area, i.e., D2pdN=2; further, determine the total number of direct connections D1dN in each group area within the wiring block, for example, Figure 5 In the first group of regions, there is a single connection (entering the wiring block without being connected to the MUX), i.e., D1dN=1; further, the selectivity is obtained as the selection ratio parameter of the direct-connect multiplexer connection group. , among which Figure 5 As shown Alternative locations can also be... Figure 1 Taking the lower dashed box as an example, within the second group area, the gating ratio parameter of the two-stage multiplexer connection group can also be obtained. ,in .

[0040] Furthermore, in some embodiments, the method for dividing the FPGA chip into multiple regions includes: dividing the FPGA chip into R regions by rows or columns, where R is a set positive integer; setting a maximum of K different types of interconnect chips to be used, where K is a set positive integer; and determining the type of interconnect chip used in each region through a mapping vector P, where the mapping vector P is a vector parameter set based on R and K.

[0041] It should be understood that in some embodiments, wiring resource utilization can be improved: adaptive interconnect structures can be dynamically selected based on the wiring pressure in different areas, avoiding resource waste and excessive congestion. Furthermore, wiring area can be reduced: by reducing redundant MUX structures, a more compact interconnect layout can be achieved, saving wiring area. Further, critical path latency can be reduced: by optimizing local interconnect structures, wiring path detours can be reduced, improving timing performance. Further, wiring detour distances can be reduced: improving wiring compactness, thereby comprehensively improving performance and resource efficiency. It should also be understood that the so-called hybrid FPGA wiring structure can be an arrangement of interconnect chips (such as MUX topologies) with different parameter configurations in different areas, realizing a spatially heterogeneous wiring structure. Further, two-level MUX topology parameter modeling can define parameterized interconnect structures (such as the number of MUX groups, connection ratio, bypass ratio, etc.) to describe the internal structure of the wiring block. Even further, the region partitioning and mapping mechanism can divide the chip into several regions through row / column directions and map the corresponding wiring block types. Furthermore, for the routing block arrangement methods used in the various embodiments of this disclosure, the parallel Bayesian optimization design space exploration algorithm can be used to automatically search for the optimal routing structure configuration in a large-scale parameter space; and it can also support the extension of the EDA toolchain, that is, it can extend the VTR architecture description file and RRG generator to support hybrid structure modeling and simulation.

[0042] It should also be understood that Figure 2 and Figure 3 In comparison, two types of interconnect chip arrangements are shown, and further, through Figure 4 and even Figure 5 and Figure 4 The detailed internal structure of a routing block is shown step by step. Furthermore, the MUX topology of the routing block includes first-level MUXs (L1-MUXes), which connect to the LB output and input lines; and second-level MUXs (L2-MUXes), which connect to the LB input and the output lines on the right side, as shown... Figure 5 or Figure 4 As shown on the right. The connections between the lines and L1-MUXs follow a round-robin scheme to achieve a uniform distribution. The parameters used for accurate modeling and extensive exploration will be elaborated further. For example, the L2-MUXes driving the LB inputs and the L2-MUXes driving the connections are grouped and indexed separately. and These represent the number of groups in each group. Furthermore, every two group regions with the same index share the same input from L1-MUXes via a crossbar switch. The number of L1-MUXes for each group region is defined as... The total number of L1-MUXes in a wiring block. The total number of L2-MUXes It can be calculated using formulas (1) and (2) respectively, where Indicates the number of LB inputs. This indicates the number of connections in one of the four directions (North (N), East (E), West (W), and South (S)) of a wiring block.

[0043] (1),

[0044] (2),

[0045] and These represent the proportions of L1-MUXs connected to the LB input-driven MUX and the wire-driven MUX within the same grouping region. For example... Figure 5 or Figure 4 As shown on the right, the MUX within a dashed box belongs to the same grouping region. The value is 3. and The values ​​are 1 and 0.67 respectively, because, for example, ​ The LB input driver MUX in the first group area (the upper dashed box) can be connected to all L1-MUXs in the same group, while each connected driver MUX in the second group area (the lower dashed box) can only be connected to 2 out of 3 L1-MUXs.

[0046] Furthermore, this disclosure also proposes an evaluation method 500 for the aforementioned FPGA hybrid routing architecture. Method 500 includes: step 510, obtaining description information and corresponding timing report information of the FPGA hybrid routing architecture; step 530, obtaining the corresponding routing resource map and global features based on the description information; step 550, statistically analyzing the frequency information of critical path nodes based on the timing report information; and step 570, obtaining the FPGA's roamability and area-delay product values ​​based on the obtained routing resource map, global features, and the frequency information of critical path nodes. Additionally, this disclosure also proposes an evaluation apparatus for the aforementioned FPGA hybrid routing architecture. The above evaluation method or apparatus can predict the roamability and area-delay product of the interconnect architecture using a GEF model, significantly reducing the number of calls to traditional evaluation tools.

[0047] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0048] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An FPGA hybrid routing architecture with spatial heterogeneous interconnect structure, characterized in that, include: An FPGA chip is divided into multiple sub-regions, and each sub-region is provided with multiple types of interconnect chips; Each of the various types of interconnects is provided with a wiring block connected to a logic block; The wiring block is configured to consist of one or more grouped regions, each region consisting of a first-level multiplexer group and a second-level multiplexer group, and the method for configuring the internal structure of the wiring block includes: Determine the type of the interconnect chip to which the wiring block belongs; Determine the number of groups connected to the outputs of the second-stage multiplexer group and the inputs of the logic blocks; Determine the number of groups connected to the output of the second-stage multiplexer; Determine the number of multiplexers in the first-level multiplexer group within each group of areas in the cabling block; Determine the selectivity of the first-level multiplexer group in each region within the wiring block with respect to the second-level multiplexer group connected to the logic block input; Determine the selectivity of the first-level multiplexer group in each area within the cabling block with respect to the second-level multiplexer group connected to the wiring.

2. The FPGA hybrid routing architecture according to claim 1, characterized in that, The method for setting the internal structure of the wiring block further includes: Determine the gating of direct connections within each group of regions in the wiring block with respect to the second-stage multiplexer group connected to the logic block input; Determine the selectivity of direct connections within each group of areas in the wiring block with respect to the second-level multiplexer group to which the connections are connected.

3. The FPGA hybrid routing architecture according to claim 1, characterized in that, Determining the number of groups connected to the output of the second-stage multiplexer group and the input of the logic block includes: Determine the number of groups connected to the outputs of the second-stage multiplexer group and the inputs of the logic blocks; The number of the groups is stored as a logic block input group number parameter. .

4. The FPGA hybrid routing architecture according to claim 1, characterized in that, Determining the number of groups connected to the output of the second-stage multiplexer group includes: Determine the number of groups connected to the output of the second-stage multiplexer; The number of the groups is stored as a parameter for the number of connection groups. .

5. The FPGA hybrid routing architecture according to claim 1, characterized in that, The determination of the gating property of the first-level multiplexer group in each region within the wiring block with respect to the second-level multiplexer group connected to the logic block input includes: Determine the number M2pN of any multiplexer in the second-level multiplexer group connected to the logic block input and connected to the first-level multiplexer group in the same area within each group of regions of the wiring block. Determine the total number M1N of multiplexers in the first-level multiplexer group within each group of regions in the wiring block; The gating property is obtained as the gating ratio parameter of the input group of the two-stage multiplexer logic block. ,in .

6. The FPGA hybrid routing architecture according to claim 1, characterized in that, The determination of the gating property of the first-level multiplexer group in each region within the wiring block with respect to the second-level multiplexer group connected to the logic block input includes: Determine the number M2wN of any multiplexer in the second-level multiplexer group connected to the wiring in each group area within the wiring block and connected to the multiplexer in the first-level multiplexer group in the same area; Determine the total number M1N of multiplexers in the first-level multiplexer group within each group of regions in the wiring block; The gating property is obtained as the gating ratio parameter of the two-stage multiplexer connection group. ,in .

7. The FPGA hybrid routing architecture according to claim 2, characterized in that, The determination of the gating property of direct connections within each group of regions in the wiring block with respect to the second-level multiplexer group connected to the logic block input includes: Determine the number D2pdN of any multiplexer in the second-level multiplexer group connected to the logic block input and directly connected to the multiplexer in the same area within each group of regions in the wiring block. Determine the total number of direct connections D1dN within each group of areas in the wiring block; The gating property is obtained as the gating ratio parameter of the input group of the direct-connect multiplexer logic block. ,in .

8. The FPGA hybrid routing architecture according to claim 2, characterized in that, The determination of the gating property of direct connections within each group of regions in the wiring block with respect to the second-level multiplexer group to which the connection is connected includes: Determine the number of multiplexers D2wdN in each group of areas within the wiring block that are connected to the second-level multiplexer group by the connection and are directly connected to the multiplexers in the area. Determine the total number of direct connections D1dN within each group of areas in the wiring block; The selectivity is obtained as the selection ratio parameter of the direct-connect multiplexer connection group. ,in .

9. The FPGA hybrid routing architecture according to claim 1, characterized in that, Methods for partitioning FPGA chips into multiple regions include: Divide the FPGA chip into R regions by rows or columns; Configure a maximum of K different types of interconnect chips to be used; The type of interconnect chip used in each region is determined by mapping vector P.

10. An evaluation method for an FPGA hybrid routing architecture as described in any one of claims 1-9, characterized in that, The method includes: Obtain the description information and corresponding timing report information of the FPGA hybrid routing architecture; The corresponding cabling resource map and global features are obtained by converting the described information. The frequency of critical path nodes is statistically analyzed based on the time-series report information. The FPGA's routeability and area delay product values ​​are obtained based on the acquired routing resource map, global features, and frequency information of critical path nodes.

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