Display device

Abstract

The embodiment of the application provides a display device, a light-emitting driving circuit is arranged in a sub-pixel driving circuit, after a first voltage signal is obtained, the light-emitting driving circuit obtains first compensation data through sub-pixel discharge, threshold compensation is carried out on the light-emitting current data obtained, and the driving signal generated by the light-emitting driving circuit based on the compensated light-emitting current data can avoid the influence of threshold voltage drift on the accuracy of the driving signal, and the time length adjusting circuit in the sub-pixel driving circuit controls the driving time length of the driving signal output by the light-emitting driving circuit based on light-emitting time length data, so that the accuracy of light-emitting control of the sub-pixel is further improved, and the improvement of the display picture quality is helpful.

Description

Technical Field

[0001] Embodiments of this application relate to the field of display technology, and more particularly to a display device. Background Technology

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0003] The pixel driving circuit of a micro LED can drive the micro LED to emit light by combining a pulse width modulation (PWM) driving circuit and a pulse amplitude modulation (PAM) driving circuit. The PWM driving circuit controls the light emission duration of the micro LED, and the PAM driving circuit controls the light emission current of the micro LED. The brightness of the micro LED is determined by the light emission duration and the light emission current.

[0004] The PAM driving circuit includes transistors. PAM adjusts the current value of driving the micro LED based on the transistors and driving data. However, the threshold voltage drift of the transistors affects the accuracy of the driving current value generated by the PAM driving circuit. Therefore, how to improve the driving accuracy of the pixel driving circuit has become the focus of research. Summary of the Invention

[0005] This application provides a display device to solve the above-mentioned technical problems.

[0006] This application provides a display device, including:

[0007] Gate driving circuit, data driving circuit, power supply circuit, at least one sub-pixel and corresponding sub-pixel driving circuit;

[0008] The sub-pixel driving circuit includes:

[0009] The light-emitting driving circuit is electrically connected to the gate driving circuit, the data driving circuit, and the power supply circuit. The light-emitting driving circuit includes a first threshold compensation unit and a first storage unit, and is configured to obtain a first light-emitting control signal, a first scan signal, and light-emitting current data.

[0010] The first threshold compensation unit writes a first voltage signal to the first storage unit under the control of the first scan signal and the first light emission control signal in the first level state;

[0011] The first threshold compensation unit is controlled by the first scanning signal and the first light emission control signal in the second level state to discharge the first voltage signal to the power supply circuit through the sub-pixel to obtain the first compensation data;

[0012] The target current driving data is obtained by coupling the light-emitting current data and the first compensation data through the first storage unit;

[0013] The duration adjustment circuit is electrically connected to the gate driving circuit and the data driving circuit, and is configured to obtain light emission duration data and generate a control signal based on the light emission duration data.

[0014] The light emission driving data and the duration adjustment data are electrically connected and are also configured to generate a driving signal based on the target current driving data;

[0015] Based on the control signal, the driving duration of the driving signal is controlled.

[0016] The sub-pixel is electrically connected to the light-emitting driving circuit and is configured to emit light based on the driving signal.

[0017] In the display device provided in this application embodiment, the sub-pixel driving circuit includes a light-emitting driving circuit. After obtaining a first voltage signal, the light-emitting driving circuit obtains first compensation data through sub-pixel discharge and performs threshold compensation on the obtained light-emitting current data. The driving signal generated by the light-emitting driving circuit based on the compensated light-emitting current data can avoid the threshold voltage drift affecting the accuracy of the driving signal. During the process of obtaining the first compensation data, the light-emitting driving circuit adjusts the circuit to different operating conditions based on the first scanning signal and the first light-emitting control signal in multiple level states, which improves the utilization rate of the control signal and reduces control costs and equipment production costs. In addition, the duration adjustment circuit in the sub-pixel driving circuit adjusts the driving duration of the output driving signal of the light-emitting driving circuit based on the light-emitting duration data, which further improves the accuracy of sub-pixel light-emitting control and helps to improve the display quality. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram of the structure of a display provided according to an exemplary embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the structure of a display provided in this application according to another exemplary embodiment;

[0021] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in accordance with an exemplary embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a sub-pixel driving circuit provided in an exemplary embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the equivalent structure of a sub-pixel driving circuit provided in an exemplary embodiment of this application;

[0024] Figure 6 This is a timing diagram of the driving signals for a sub-pixel driving circuit provided in this application according to an exemplary embodiment;

[0025] Figure 7A This is an operational state diagram of a sub-pixel driving circuit provided in this application according to an exemplary embodiment;

[0026] Figure 7B This is an operational state diagram of a sub-pixel driving circuit provided in this application according to another exemplary embodiment;

[0027] Figure 7C This is an operational state diagram of a sub-pixel driving circuit provided in this application according to another exemplary embodiment;

[0028] Figure 7D This is an operational state diagram of a sub-pixel driving circuit provided in this application according to another exemplary embodiment;

[0029] Figure 7E This is an operational state diagram of a sub-pixel driving circuit provided in this application according to another exemplary embodiment;

[0030] Figure 7F This is an operational state diagram of a sub-pixel driving circuit provided in this application according to another exemplary embodiment.

[0031] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment. It should be further understood that the terms "comprising" or "including" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0034] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise expressly specified. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0035] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0036] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0037] A schematic diagram of the display device is shown below. Figure 1 and Figure 2As shown, the system includes a control circuit 250, a data drive circuit 20, a gate drive circuit 30, a display panel 40, and a power supply circuit 280. The control circuit 250 and the data drive circuit 20 are electrically connected, as are the gate drive circuit 30 and the display panel 40.

[0038] The display panel has a power line 90, multiple gate lines 60, multiple data lines 50 and multiple pixel units 80. The multiple pixel units 80 are arranged in an array, and each pixel unit 80 is located in the area where the gate line 60 and the data line 50 intersect.

[0039] The gate driving circuit 30 is electrically connected to the gate line 60. The gate driving circuit 30 is configured to obtain clock signals and trigger signals from the control circuit 250, generate gate driving signals according to the clock signals and trigger signals, and transmit the gate driving signals to the corresponding pixel unit 80 through the gate line 60 to control the transistors in the pixel unit 80 to be turned on or off.

[0040] More specifically, the gate driving circuit 30 can be fabricated as a separate gate driver integrated circuit (GDIC). Alternatively, the gate driving circuit 30 can be integrated into the display panel; this integration is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 via a COG (Chip on Glass) process, or via a COF (Chipon Film) process. In the COF process, the component is electrically connected to the display panel 40 via a flexible printed circuit (FPC).

[0041] The data driving circuit 20 is a circuit that drives the data line 50. It is configured to acquire display data from the control circuit 250, convert it into an analog data voltage (Vdata), and transmit the analog data voltage through the data line 50 to the corresponding pixel unit 80, so that the sub-pixel 802 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the brightness of the sub-pixel 802.

[0042] The data driver circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, and output buffer, etc.

[0043] The power supply circuit 280 is a circuit that provides stable electrical signals and is configured to provide the corresponding power signals to the display panel 40, control circuit 250, data drive circuit 20 and gate drive circuit 30.

[0044] In one configuration, each pixel unit 80 includes three sub-pixel circuits 810, used to display red light, blue light, and green light respectively. In another configuration, each pixel unit 80 includes four sub-pixel circuits 810, used to display red light, blue light, green light, and white light respectively. No specific limitation is made here.

[0045] The color of light emitted by each sub-pixel circuit 810 is determined by the properties of its sub-pixel 802. The sub-pixel 802 can be any light-emitting device, including but not limited to OLED and micro LED.

[0046] A micro LED is a miniature light-emitting device manufactured using inorganic semiconductor layers. A micro LED typically includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, including vertical, horizontal, and flip-chip types, and is not particularly limited to a specific structure.

[0047] More specifically, a sub-pixel circuit 810 includes a pixel driving circuit 801 and a light-emitting element 802 (i.e., a sub-pixel). The pixel driving circuit 801 is electrically connected to the sub-pixel 802 and is configured to drive the sub-pixel 802 to emit light. The signals required by the pixel driving circuit 801 include a driving signal, a scan signal, and an emission control signal (EM control signal).

[0048] The driving signal can be generated by the control circuit 250 or obtained from an external source. This includes, but is not limited to, a start pulse signal, a clock signal, and an enable signal. The light emission control signal can be a global signal provided by the control circuit 250 or a signal generated by the gate driving circuit 30; no specific limitation is made here. The scanning signal is a successive displacement signal generated by the gate driving circuit 30.

[0049] If the EM control signal is a global signal generated by the control circuit 250, the gate drive circuit 30 obtains the EM control signal from the control circuit 250 and transmits the EM control signal to the corresponding pixel drive circuit 801 through the gate line 60.

[0050] If both the EM control signal and the scan signal are generated by the gate drive circuit 30, the gate drive circuit 30 includes a scan signal generation circuit 301 and an EM generation circuit 302. The scan signal is output by the scan signal generation circuit 301, and the EM control signal is output by the EM generation circuit 302.

[0051] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in an exemplary embodiment of the present application, including a PWM driving circuit 803 and a PAM driving circuit 804.

[0052] The PWM drive circuit 803 is configured to acquire the light emission duration data PWMD and the adjustment signal SWEEP, and adjust the level of the first light emission control signal it generates according to the light emission duration data PWMD and the adjustment signal SWEEP. The level of the first light emission control signal is either a first level or a second level.

[0053] The PAM driver circuit 804 and the PWM driver circuit 803 are electrically connected to the light-emitting element LED and are configured to acquire a first light-emitting control signal and light-emitting current data PAMD, generate a driving signal based on the first light-emitting control signal and light-emitting current data PAMD, and drive the light-emitting element LED to emit light.

[0054] Among them, the first light emission control signal is an electrical signal that regulates the light emission duration of the light-emitting element LED, and the light emission current data PAMD is data that regulates the magnitude of the current passing through the light-emitting element LED.

[0055] The circuit structure and principle of the PWM drive circuit 803 and the PAM drive circuit 804 are explained below, assuming that the transistors in the traditional pixel drive circuit are all P-type transistors.

[0056] The PWM drive circuit 803 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a sixth transistor T6, and a second capacitor C2.

[0057] The first transistor T1 is electrically connected to power line 90 at its first terminal and to gate line 60 at its control terminal. It is configured to obtain an initialization signal RESET from its control terminal and a reference signal REF from its first terminal. When the initialization signal RESET is low, it is turned on and outputs the reference signal REF from its second terminal. The reference signal REF is a low-level signal.

[0058] The first terminal of the sixth transistor T6 is electrically connected to the data line 50, and the control terminal is electrically connected to the gate line 60. It is configured to obtain the scan signal SN from its control terminal and the light emission duration data PWMD from its first terminal. When the scan signal SN is low, it is turned on and the light emission duration data PWMD is output from its second terminal.

[0059] The control terminal of the fourth transistor T4 is electrically connected to the gate line 60, the first terminal is electrically connected to the control terminal of the third transistor T3, and the second terminal is electrically connected to the second terminal of the third transistor T3. It is configured to obtain the scan signal SN from its control terminal and turn on when the scan signal SN is low. It forms a threshold compensation structure with the third transistor T3.

[0060] The control terminal of the third transistor T3 is electrically connected to the second terminal of the first transistor T1, and the first terminal is electrically connected to the second terminal of the sixth transistor T6. It is configured to transmit an electrical signal to the control terminal when the fourth transistor T4 is turned on and its first terminal obtains the light emission duration data PWMD, until the third transistor T3 is turned off. When it is turned off, the potential at that point is determined from its control terminal to be the light emission duration data PWMD after threshold voltage compensation.

[0061] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the third transistor T3, and is configured to store the light emission duration data of threshold voltage compensation generated by the control terminal of the third transistor T3 at its first terminal.

[0062] The second terminal of the second capacitor C2 is electrically connected to the power line 90, and is also configured to obtain the power signal SWEEP from the power line 90 at its second terminal, and adjust the voltage value of its first terminal according to the voltage change at its second terminal.

[0063] The first terminal of the second transistor T2 is electrically connected to the power supply line 90, the second terminal is electrically connected to the first terminal of the third transistor T3, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a high-level fourth electrical signal VGH from its first terminal and a light emission control signal EM from its control terminal. When the light emission control signal EM is low, it is turned on and transmits the fourth electrical signal VGH obtained from its first terminal to the first terminal of the third transistor T3.

[0064] The third transistor T3 is also configured to receive an electrical signal generated at the first terminal of the second capacitor C2 from its control terminal when the fourth transistor T4 is turned off, and to receive a fourth electrical signal VGH from its first terminal. It is turned on when the difference between the potential values ​​at its control terminal and its first terminal is less than a preset threshold, and turned off when the difference between the potential values ​​at its control terminal and its first terminal is greater than or equal to the preset threshold.

[0065] When the third transistor T3 is turned on, the potential difference between its first and second terminals is negligible, which can be equivalent to a short circuit between the two terminals. At the same time, the fourth transistor T4 between the control terminal of the third transistor T3 and the first terminal is turned on, which can also be equivalent to a short circuit. This causes the third transistor T3 to be unable to achieve negative bias, thus making it impossible to compensate for the threshold voltage of the light emission duration data. As a result, the pixel driving circuit drives the light emission element to emit light for an inaccurate duration.

[0066] The PWM drive circuit 803 also includes a fifth transistor T5, the first terminal of the fifth transistor T5 and the second terminal of the third transistor T3 are electrically connected, the second terminal of the fifth transistor T5 is electrically connected to the power supply line 90, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a light emission control signal EM from its control terminal and a third electrical signal VGL from its second terminal. It is turned on when the light emission control signal EM is low and outputs the third electrical signal VGL from its first terminal.

[0067] Since the aspect ratio of the third transistor T3 is greater than that of the fifth transistor T5, when both the third transistor T3 and the fifth transistor T5 are turned on, the potential of the second terminal of the third transistor T3 is the same as the potential of the fourth electrical signal VGH; when the third transistor T3 is turned off and the fifth transistor T5 is turned on, the potential of the second terminal of the third transistor T3 is the same as the potential of the third electrical signal VGL.

[0068] The PAM driver circuit 804 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a third capacitor C3, and a driver transistor T10.

[0069] The first terminal of the ninth transistor T9 is electrically connected to the data line 50, the control terminal is electrically connected to the gate line 60, and the second terminal is electrically connected to the second terminal of the third capacitor C3 and the control terminal of the driving transistor T10. It is configured to obtain the light emission current data PAMD from its first terminal and the scan signal SN from its control terminal. When the scan signal SN is low, it is turned on and outputs the light emission current data PAMD, which is stored in the third capacitor C3.

[0070] The first end of the driving transistor T10 is coupled to the power line 90, and the second end is electrically connected to the sub-pixel LED. It is configured to obtain a first voltage signal VDD from its first end and generate a driving signal to drive the sub-pixel LED to emit light when it obtains the light emission current data PAMD from its first end.

[0071] The driving signal includes a driving current value, which is proportional to the luminous brightness of the sub-pixel LED. The larger the driving current value, the brighter the luminous brightness of the sub-pixel LED.

[0072] The first terminal of the eighth transistor T8 is electrically connected to the power supply line 90, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a first voltage signal VDD from its first terminal and a light emission control signal EM from its control terminal. It is turned on when the light emission control signal EM is low, and outputs the first voltage signal VDD from its second terminal.

[0073] The first terminal of the seventh transistor T7 is electrically connected to the second terminal of the eighth transistor T8, and its control terminal is electrically connected to the second terminal of the third transistor T3. It is configured to obtain a first voltage signal VDD from its first terminal and turn off when the potential of the second terminal of the third transistor T3 is the potential of the fourth electrical signal VGH, without affecting the data stored in the third capacitor C3, thus maintaining the light-emitting state of the sub-pixel LED.

[0074] The seventh transistor T7 is also configured to turn on when the potential at the second terminal of the third transistor T3 is the potential of the third electrical signal VGL, and output the first voltage signal VDD, so that the driving transistor T10 turns off based on the first voltage signal VDD, stops the generation of the driving signal, and causes the sub-pixel LED to stop emitting light.

[0075] During the process of generating the drive current value for the driving transistor T10, its transistor characteristics need to be considered. The current value is: ,

[0076] Where I represents the driving current value, μ represents the electron mobility in the driving transistor T10, Cox represents the capacitance of the gate oxide layer in the driving transistor, W represents the width of the driving transistor, L represents the length of the driving transistor, Vgs represents the voltage difference between the control terminal and the first terminal of the driving transistor, i.e., VDD-PAMD, and Vth represents the threshold voltage of the driving transistor.

[0077] Because the threshold voltage of the driving transistor T10 is not constant and can drift, the driving current value generated by PAMD based on the same luminous current data will deviate due to the influence of the threshold voltage, affecting the accuracy of the driving current value generated by the PAM driving circuit. Therefore, improving the driving accuracy of the pixel driving circuit has become a key research focus.

[0078] To address the aforementioned problems, this application provides a display device to resolve these technical issues. The technical concept of this application is as follows: a sub-pixel driving circuit is provided, which includes a light-emitting driving circuit. After obtaining a first voltage signal, the light-emitting driving circuit obtains first compensation data through sub-pixel discharge. Threshold compensation is then performed on the obtained light-emitting current data. The driving signal generated by the light-emitting driving circuit based on the compensated light-emitting current data avoids threshold voltage drift affecting the accuracy of the driving signal. Furthermore, the duration adjustment circuit in the sub-pixel driving circuit regulates the driving duration of the output driving signal based on light-emitting duration data, further improving the precision of sub-pixel light emission control and contributing to the improvement of display image quality.

[0079] The pixel driving circuit proposed in this application will be explained in detail below. Figure 4 This is a schematic diagram of the structure of a pixel driving circuit provided in an exemplary embodiment of this application.

[0080] like Figure 4 As shown, the sub-pixel LED driving circuit provided in this application includes a light-emitting driving circuit 805.

[0081] The light-emitting driving circuit 805 is electrically connected to the gate line 60, the data line 50, and the power line 90. The light-emitting driving circuit 805 includes a first threshold compensation unit 808 and a first storage unit 809. The light-emitting driving circuit 805 is configured to obtain a first light-emitting control signal EM1, a first scan signal S1, and light-emitting current data PAMD.

[0082] The first threshold compensation unit 808 writes the first voltage signal VDD to the first storage unit 809 under the control of the first scan signal S1 and the first light emission control signal EM1 which is in the first level state.

[0083] The first threshold compensation unit 808 is controlled by the first scanning signal S1 and the first light emission control signal EM1 in the second level state to discharge the first voltage signal VDD to the power line 90 through the sub-pixel LED to obtain the first compensation data.

[0084] The first compensation data is constructed based on the first threshold compensation unit 808.

[0085] In some embodiments, the light-emitting driving circuit 805 is configured to couple the light-emitting current data PAMD and the first compensation data through the first storage unit 809 to obtain target current driving data; the target current driving data is driving data that compensates the threshold voltage of the first threshold compensation unit 808 in the light-emitting current data PAMD.

[0086] In some embodiments, the light-emitting driving circuit 805 includes a control circuit 807;

[0087] The control circuit 807 is electrically connected to the power line 90 and the gate line 60, and is also electrically connected to the first threshold compensation unit 808 through point A. It is configured to obtain the first light emission control signal EM1. When the first light emission control signal EM1 is in the first level state, the first voltage signal VDD provided by the power line 90 is transmitted to the first threshold compensation unit 808.

[0088] The first threshold compensation unit 808 is electrically connected to the gate line 60 and is also electrically connected to the first memory unit 809 through point C. It is configured to obtain the first scan signal S1 and be controlled by the first scan signal S1 to write the first voltage signal VDD into the first memory unit 809.

[0089] The first threshold compensation unit 808 is configured to construct a threshold compensation structure based on the first scan signal S1 and the first voltage signal VDD.

[0090] The control circuit 807 is also electrically connected to the sub-pixel LED via point E and to the first threshold compensation unit 808 via point B. It is configured to construct a path between the first threshold compensation unit 808 and the sub-pixel LED when the first light emission control signal EM1 is in the second level state, controlled by the first scan signal S1.

[0091] The first storage unit 809 is configured to discharge its stored first voltage signal VDD to the power line 90 through the first threshold compensation unit 808, the path and the sub-pixel LED to obtain first compensation data.

[0092] Point C is set as the first end of the first threshold compensation unit 808, and point B is set as the second end of the first threshold compensation unit 808. The first threshold compensation unit 808 is configured to discharge the electrical signal stored in the first storage unit 809 based on the threshold compensation structure, the path constructed by the control circuit 807, and the sub-pixel LED, until the voltage difference between its first end and its second end is equal to the conduction voltage of the threshold compensation structure, and then stop discharging. The first compensation data after threshold voltage compensation of the first threshold compensation unit 808 and the threshold voltage compensation of the sub-pixel LED is determined at its first end, and the second compensation data after threshold voltage compensation of the sub-pixel LED is determined at its second end.

[0093] The driving end of the sub-pixel LED is electrically connected to the control circuit 807, and the non-driving end is electrically connected to the power line 90.

[0094] Without considering the voltage drop on the path constructed by the control circuit 807, the voltage values ​​at points B and E are determined to be the sum of the second voltage signal VSS provided by the power supply line 90 and the threshold voltage of the sub-pixel LED, as the second compensation data.

[0095] Taking into account the voltage drop on the path constructed by the control circuit 807, the voltage value at point B is determined to be the sum of the second voltage signal VSS provided by the power line 90, the threshold voltage of the sub-pixel LED, and the voltage drop on the path, as the second compensation data.

[0096] The sum of the second compensation data and the threshold voltage of the first threshold compensation unit 808 is used as the first compensation data.

[0097] In some embodiments, the first storage unit 809 is electrically connected to the gate line 60 and the power supply line 90, and is configured to obtain a reference electrical signal Vref during the process of the first threshold compensation unit 808 obtaining the first compensation data. In the process of determining the first compensation data, the reference electrical signal Vref is used as a reference to calculate the data related to the first compensation data, so as to ensure the accuracy of the data calculation.

[0098] The first storage unit 809 is also configured to obtain luminous current data PAMD after storing the first compensation data;

[0099] Based on the difference between the voltage value of the reference electrical signal Vref and the voltage value of the luminous current data PAMD, the first compensation data is coupled and adjusted to obtain the target current driving data.

[0100] The first threshold compensation unit 808 includes a driving transistor T5, which is configured to control the driving transistor T5 to generate a driving signal based on the target current driving data and the second compensation data.

[0101] In some embodiments, the sub-pixel LED driving circuit further includes a duration adjustment circuit 806.

[0102] The duration adjustment circuit 806 is electrically connected to the gate line 60 and the data line 50, and is configured to obtain the light emission duration data PWMD and generate a control signal based on the light emission duration data PWMD.

[0103] The light-emitting driving circuit 805 and the duration adjustment circuit 806 are electrically connected and are also configured to generate a driving signal based on the target current driving data;

[0104] Since the target current drive data includes the threshold voltage of the first threshold compensation unit 808, it cancels out the threshold voltage in the calculation formula when determining the drive current value of the drive signal, thereby avoiding the influence of the threshold voltage during the generation of the drive current value.

[0105] The light-emitting driving circuit 805 is also configured to adjust the driving duration of the driving signal based on the control signal;

[0106] The sub-pixel LED and the light-emitting driving circuit 805 are electrically connected and configured to emit light based on the driving signal.

[0107] In the above technical solution, the sub-pixel LED driving circuit includes a light-emitting driving circuit 805. After obtaining the first voltage signal VDD, the light-emitting driving circuit 805 obtains the first compensation data through the discharge of the sub-pixel LED, and performs threshold compensation on the obtained light-emitting current data PAMD. The driving signal generated by the light-emitting driving circuit 805 based on the compensated light-emitting current data PAMD can avoid the threshold voltage drift affecting the accuracy of the driving signal. During the process of obtaining the first compensation data, the light-emitting driving circuit 805 adjusts the circuit to different operating conditions based on the first scan signal S1 and the first light-emitting control signal EM1 which is in multiple level states, thereby improving the utilization rate of the control signal and reducing control costs and equipment production costs. In addition, the duration adjustment circuit 806 in the sub-pixel LED driving circuit adjusts the driving duration of the output driving signal of the light-emitting driving circuit 805 based on the light-emitting duration data PWMD, further improving the accuracy of the light-emitting control of the sub-pixel LED and contributing to the improvement of display quality.

[0108] In some embodiments, the duration adjustment circuit 806 includes a data processing unit.

[0109] The data processing unit includes a second threshold compensation unit 8062 and a second storage unit 8061, and is electrically connected to a data line 50 and a gate line 60. It is configured to obtain a first light emission control signal EM1 and a reference electrical signal Vref, and is controlled by the first light emission control signal EM1 to write the reference electrical signal Vref into the second storage unit 8061.

[0110] The data processing unit is also configured to obtain the second light emission control signal EM2 and the light emission duration data PWMD, and to write the threshold-compensated light emission duration data PWMD into the second storage unit 8061 under the control of the second light emission control signal EM2.

[0111] The adjustment signal SWEEP is obtained, and the emission duration data PWMD after threshold compensation is adjusted based on the change of the adjustment signal SWEEP to obtain the target duration adjustment data.

[0112] In some embodiments, the duration adjustment circuit 806 includes a reference potential input unit. Figure 4 In the circuit structure shown, the reference potential input unit includes a first voltage write transistor T11 and a second voltage write transistor T13.

[0113] The reference potential input unit is electrically connected to the power supply line 90 and the gate line 60, and is configured to obtain a first reference electrical signal VGH, a second reference electrical signal (e.g., a reference electrical signal Vref) and a third light emission control signal EM3, and is controlled by the third light emission control signal EM3 to output the first reference electrical signal VGH and the second reference electrical signal Vref to the data processing unit.

[0114] The second threshold compensation unit 8062 includes a second gating transistor T10, which is electrically connected to a reference potential input unit and a second storage unit 8061. The data processing unit is configured to control the conduction state of the second gating transistor T10 by target duration adjustment data.

[0115] When the second selection transistor T10 is turned on, a first control sub-signal is output based on the first reference electrical signal VGH. The first control sub-signal is the signal that controls the control circuit 807 to construct the path.

[0116] When the second selection transistor T10 is turned off, a second control sub-signal is output based on the second reference electrical signal Vref. The second control sub-signal is the signal that controls the control circuit 807 to turn off the path.

[0117] The control signal includes either the first control sub-signal or the second control sub-signal.

[0118] In the above technical solution, when the duration adjustment data generates the control signal, the obtained light emission duration data PWMD is also pre-compensated for threshold. When controlling the conduction state of the second selection transistor T10, it will cancel out the threshold voltage in its conduction condition, thus avoiding the influence of threshold voltage drift on the accuracy of determining the conduction state, thereby improving the accuracy of driving duration control of the driving signal.

[0119] The following is based on Figure 4 Using the schematic diagram of the sub-pixel LED driving circuit shown as an example, the pixel driving circuit proposed in this application will be explained in detail. Except for the first gating transistor T7 and the second gating transistor T10, which are both P-type transistors, all other transistors in this sub-pixel LED driving circuit are N-type transistors.

[0120] In some embodiments, the control circuit 807 includes a first light-emitting control transistor T1.

[0121] The first terminal of the first light-emitting control transistor T1 is electrically connected to the power supply line 90, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a first voltage signal VDD from its first terminal and a first light-emitting control signal EM1 from its control terminal, and its conduction state is controlled by the first light-emitting control signal EM1.

[0122] The first light-emitting control transistor T1 is turned on when the first light-emitting control signal EM1 is high, and outputs the first voltage signal VDD; it is turned off when the first light-emitting control signal EM1 is low, and stops outputting the first voltage signal VDD.

[0123] In some embodiments, the first threshold compensation unit 808 includes a first compensation transistor T4.

[0124] The first terminal of the first compensation transistor T4 is electrically connected to the second terminal of the first light-emitting control transistor T1, and its second terminal is electrically connected to the first terminal of the first memory cell 809. Its control terminal is electrically connected to the gate line 60. It is configured to obtain a first scan signal Gn-1 from its control terminal and a first voltage signal VDD from its first terminal, and its conduction state is controlled by the first scan signal Gn-1.

[0125] The first compensation transistor T4 is turned on when the first scan signal Gn-1 is high, and outputs the first voltage signal VDD to the first storage cell 809 to reset the first storage cell 809 in preparation for the discharge operation when the compensation electrical signal is determined later; the first compensation transistor T4 is turned on when the first scan signal Gn-1 is low, and stops outputting the first voltage signal VDD.

[0126] In some embodiments, the first storage unit 809 includes a first capacitor C1.

[0127] The first terminal of the first capacitor C1 is electrically connected to the second terminal of the first compensation transistor T4, and a first voltage signal VDD is obtained at the first terminal.

[0128] In some embodiments, the first memory cell 809 includes a third transistor T3.

[0129] The first terminal of the third transistor T3 is electrically connected to the power supply line 90, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a reference electrical signal Vref from its first terminal and a first scan signal Gn-1 from its control terminal, and its conduction state is controlled by the first scan signal Gn-1.

[0130] The third transistor T3 is turned on when the first scan signal Gn-1 is high, and outputs the reference electrical signal Vref from its second terminal; it is turned off when the first scan signal Gn-1 is low, and stops the output of the reference electrical signal Vref.

[0131] In some embodiments, the first memory cell 809 includes a second transistor T2.

[0132] The first terminal of the second transistor T2 is electrically connected to the data line 50, and its control terminal is electrically connected to the gate line 60. It is configured to obtain the light emission current data PAMD from its first terminal and the second scan signal Gn from its control terminal, and to control its conduction state by the second scan signal Gn.

[0133] The second transistor T2 is turned on when the second scan signal Gn is high, and outputs the light emission current data PAMD from its second terminal; it is turned off when the second scan signal Gn is low, and stops the output of the light emission current data PAMD.

[0134] In some embodiments, the second terminal of the first capacitor C1 is electrically connected to the second terminal of the third transistor T3 and the second terminal of the second transistor T2, and is configured to adjust the voltage value of its second terminal based on the electrical signal obtained from its second terminal.

[0135] In some embodiments, before the first capacitor C1 obtains the first compensation data at its first terminal, the electrical signal obtained at its second terminal is the reference electrical signal Vref provided by the third transistor T3. The acquisition process of the first compensation data is carried out based on the reference electrical signal Vref, which ensures the accuracy of the first compensation data.

[0136] In other embodiments, when the first capacitor C1 obtains the light-emitting current data PAMD at its second terminal, the voltage difference generated at its second terminal is the difference between the light-emitting current data PAMD and the voltage value corresponding to the reference electrical signal Vref. Based on its coupling effect, the voltage difference generated at its first terminal is the same as the voltage difference generated at its second terminal. Then, the voltage value at its second terminal is adjusted to the sum of the voltage value corresponding to the first compensation data and the voltage difference, and this voltage is determined as the target current driving data.

[0137] In some embodiments, the first threshold compensation unit 808 further includes a driving transistor T5.

[0138] The first terminal of the driving transistor T5 is electrically connected to the first terminal of the first compensation transistor T4, and its control terminal is electrically connected to the second terminal of the first compensation transistor T4 and the first terminal of the first capacitor C1. It is configured to conduct based on the first voltage signal VDD after the first voltage signal VDD is written into the first capacitor C1.

[0139] The driving transistor T5 is also configured to, when it is turned on and the first compensation transistor T4 is turned on, form a threshold compensation structure with the first compensation transistor T4; the threshold compensation structure is a diode structure, and a schematic diagram of the diode structure is shown below. Figure 5 The YLED shown has a control terminal voltage value that is higher than its second terminal voltage value. The difference in voltage is the turn-on voltage of the threshold compensation structure.

[0140] In some embodiments, the turn-on voltage of the first threshold compensation unit 808 is the turn-on voltage of the threshold compensation structure, and also the threshold voltage of the driving transistor T5.

[0141] The control terminal of the driving transistor T5 serves as the first terminal of the threshold compensation unit, and the second terminal of the driving transistor T5 serves as the second terminal of the threshold compensation unit.

[0142] After the control circuit 807 establishes the path, the diode YLED, the path, and the sub-pixel LED constitute the discharge path of the first capacitor C1 to the power line 90. The voltage value of the first terminal of the first capacitor C1 is the voltage value of the first voltage signal VDD, which is higher than the voltage value of the second voltage signal VSS provided by the power line 90 electrically connected to the discharge path. Then the first capacitor C1 discharges to the power line 90 through the discharge path until the discharge stops.

[0143] In some embodiments, the second end of the sub-pixel LED is electrically connected to the power line 90 and is configured to determine the voltage value of its first end as a second compensation voltage value based on the second voltage signal VSS obtained from its second end and its threshold voltage; the second compensation voltage value is the voltage value of the second voltage signal VSS compensated for the threshold voltage of the sub-pixel LED.

[0144] Without considering the voltage drop of the path constructed by the control circuit 807 between points B and E, when the voltage value at the first terminal of the first capacitor C1 drops to the sum of the threshold voltage of the sub-pixel LED, the threshold voltage of the diode YLED, and the voltage value of the second voltage signal VSS, the discharge stops, and the first capacitor C1 uses this sum as the first compensation voltage value.

[0145] Taking into account the voltage drop of the path constructed by the control circuit 807 between points B and E, when the voltage value at the first terminal of the first capacitor C1 drops to the sum of the threshold voltage of the sub-pixel LED, the threshold voltage of the diode YLED, the on-state voltage drop of the first circuit, and the voltage value of the second voltage signal VSS, the discharge stops, and the first capacitor C1 uses this sum as the first compensation voltage value.

[0146] In some embodiments, the control circuit 807 includes a first gating transistor T7.

[0147] The first terminal and the control terminal of the first selection transistor T7 are electrically connected to the gate line 60. It is configured to obtain a first scan signal Gn-1 from its first terminal and a first light emission control signal EM1 from its control terminal, and its conduction state is controlled by the first light emission control signal EM1.

[0148] The first selection transistor T7 is turned on when the first light-emitting control signal EM1 is low, and outputs the first scan signal Gn-1; it is turned off when the first light-emitting control signal EM1 is high, and stops outputting the first scan signal Gn-1.

[0149] In some embodiments, the control circuit 807 includes a second light-emitting control transistor T6.

[0150] The first terminal (point B) of the second light-emitting control transistor T6 is electrically connected to the first threshold compensation unit 808, its control terminal (point F) is electrically connected to the second terminal of the first gating transistor T7, and its second terminal (point E) is electrically connected to the sub-pixel LED. It is configured to obtain the first scan signal Gn-1 from its control terminal and control its conduction state by the first scan signal Gn-1.

[0151] The second light-emitting control transistor T6 is turned on when the first scan signal Gn-1 is high, and a discharge path is constructed during the threshold compensation process. Its on-state voltage drop is the voltage drop of the path constructed by the control circuit 807; it is turned off when the first scan signal Gn-1 is low.

[0152] In some embodiments, the driving transistor T5 is configured to obtain target current driving data from its control terminal and generate a driving signal based on the target current driving data and a second compensation voltage value.

[0153] The current value of the drive signal is: ,

[0154] ;

[0155] but ;

[0156] Where I represents the driving current value, μ represents the electron mobility in driving transistor T5, Cox represents the capacitance of the gate oxide layer in driving transistor T5, W represents the width of driving transistor T5, L represents the length of driving transistor T5, Vgs represents the voltage difference between the control terminal and the second terminal of driving transistor T5, and Vth5 represents the threshold voltage of driving transistor T5. VSS represents the voltage value of the second voltage signal, VLED represents the threshold voltage of the sub-pixel LED, and Vref represents the voltage value of the reference electrical signal Vref.

[0157] Based on the above driving current values, it can be seen that the threshold voltage has been canceled out, and its value is no longer affected by the threshold voltage.

[0158] In some embodiments, the reference potential input unit includes a first voltage write transistor T11.

[0159] The first voltage write transistor T11 is electrically connected to the first terminal of the power supply line 90 and the control terminal is electrically connected to the gate line 60. It is configured to obtain a first reference electrical signal VGH from its first terminal and a third light emission control signal EM3 from its control terminal, and its conduction state is controlled by the third light emission control signal EM3.

[0160] The first voltage writing transistor T11 is turned on when the third light-emitting control signal EM3 is high, and outputs the first reference electrical signal VGH; the first voltage writing transistor T11 is turned off when the third light-emitting control signal EM3 is low.

[0161] In some embodiments, the reference potential input unit includes a second voltage write transistor T13.

[0162] The second voltage write transistor T13 is electrically connected to the second terminal of the power supply line 90 and the control terminal is electrically connected to the gate line 60. It is configured to obtain a second reference electrical signal Vref from its second terminal and a third light emission control signal EM3 from its control terminal, and its conduction state is controlled by the third light emission control signal EM3.

[0163] The second voltage writing transistor T13 is turned on when the third light-emitting control signal EM3 is high, and outputs the first reference electrical signal VGH from its first terminal; the second voltage writing transistor T13 is turned off when the third light-emitting control signal EM3 is low.

[0164] In some embodiments, the reference potential input unit includes a write transistor T8.

[0165] The first terminal of the write transistor T8 is electrically connected to the data line 50, its control terminal is electrically connected to the gate line 60, and its second terminal is electrically connected to the first terminal of the second select transistor T10. It is configured to obtain the light emission duration data PWMD from its first terminal and the second light emission control signal EM2 from its control terminal, and its conduction state is controlled by the second light emission control signal EM2.

[0166] The write transistor T8 is turned on when the second light-emitting control signal EM2 is high, and writes the light-emitting duration data PWMD to the second light-emitting control signal EM2; it is turned off when the second light-emitting control signal EM2 is low.

[0167] In some embodiments, the duration adjustment circuit includes a twelfth transistor T12.

[0168] The first terminal of the twelfth transistor T12 is electrically connected to the power supply line 90, its control terminal is electrically connected to the gate line 60, and its second terminal is electrically connected to the first terminal of the third capacitor C3. It is configured to obtain a reference electrical signal Vref from its first terminal and a first scan signal Gn-1 from its control terminal, and its conduction state is controlled by the first scan signal Gn-1.

[0169] The twelfth transistor T12 is turned on when the first scan signal Gn-1 is high, and outputs a reference electrical signal Vref, which resets the first terminal of the third capacitor C3; it is turned off when the first scan signal Gn-1 is low.

[0170] In some embodiments, the second threshold compensation unit 8062 includes a second compensation transistor T9.

[0171] The first terminal of the second compensation transistor T9 is electrically connected to the control terminal of the second gating transistor T10, and its second terminal is electrically connected to the second terminal of the second gating transistor T10. Its control terminal is electrically connected to the gate line 60. It is configured to obtain a second light emission control signal EM2 from its control terminal and control its conduction state by the second light emission control signal EM2.

[0172] The second compensation transistor T9 is turned on when the second light emission control signal EM2 is high, shorting the control terminal and the second terminal of the second gating transistor T10. When the second gating transistor T10 is turned on, a threshold compensation structure is constructed. When the writing transistor T8 writes the light emission duration data PWMD, the threshold voltage compensation of the second gating transistor T10 is determined at the first terminal. It is turned off when the second light emission control signal EM2 is low.

[0173] In some embodiments, the second storage unit 8061 includes a third capacitor C3.

[0174] The second terminal of the third capacitor C3 is electrically connected to the power line 90 and is configured to obtain the adjustment signal SWEEP. When the adjustment signal SWEEP changes, the threshold-compensated light emission duration data PWMD stored at its first terminal is adjusted based on the amount of change as the target duration adjustment data.

[0175] The second gate transistor T10 is configured to have its conduction state controlled by target duration adjustment data when the second compensation transistor T9 is off.

[0176] The second selection transistor T10 is turned off when the target duration adjustment data is not within its conduction data range. The potential at point F is the potential of the second reference electrical signal Vref, which is also the potential of the second control sub-signal. The second control sub-signal is the signal that turns off the control circuit.

[0177] The second selection transistor T10 turns on when the target duration adjustment data is within its conduction data range. The potential at point F is the potential of the first reference electrical signal VGH, which is also the potential of the first control sub-signal. The first control sub-signal is the signal used by the control circuit to establish a path.

[0178] The following explanation uses an example where all transistors in the sub-pixel driving circuit are N-type transistors to illustrate its driving process. The circuit structure of the sub-pixel driving circuit is as follows: Figure 4 As shown, the corresponding driving signal timing diagram is as follows: Figure 6 As shown.

[0179] The following is combined with Figures 7A to 7F The process diagram shown is for Figure 4 The circuit structure shown is explained in terms of its operation within a display cycle. A display cycle T includes, in sequence, a charging phase t11, a compensation phase t12, a first data writing phase t13, a second data writing phase t14, and a display phase t15.

[0180] During the charging phase t11 in the driving signal timing diagram, the first scan signal Gn-1 and the first light emission control signal EM1 are at high level, the second scan signal Gn, the second light emission control signal EM2, and the third light emission control signal EM3 are at low level; the adjustment signal SWEEP is at the first preset level.

[0181] Since the first scan signal Gn-1 is at a high level, the third transistor T3 is turned on, and the reference electrical signal Vref obtained therefrom is written to the second terminal of the first capacitor C1; then the voltage value at the second terminal of the first capacitor C1 is Vref.

[0182] Since the first scan signal Gn-1 is high, the twelfth transistor T12 is turned on, and the reference electrical signal Vref obtained therefrom is written to the second terminal of the second capacitor C2 and the control terminal of the second gating transistor T10; then the voltage value at the second terminal of the second capacitor C2 and the control terminal of the second gating transistor T10 is Vref.

[0183] Since the reference electrical signal Vref is at a low level, the second gating transistor T10 is turned on.

[0184] Since the first light-emitting control signal EM1 is at a high level, the first light-emitting control transistor T1 is turned on, and the first voltage signal VDD obtained from its first terminal is transmitted to the first terminal of the first compensation transistor T4.

[0185] The first compensation transistor T4 is turned on based on the high-level first scan signal Gn-1, and the first voltage signal VDD obtained from its first terminal is written into the first terminal of the first capacitor C1.

[0186] Since the first light-emitting control signal EM1 is at a high level, the first gating transistor T7 is turned off, and the first scanning signal Gn-1 is not output to the second light-emitting control transistor T6.

[0187] Since the second light-emitting control signal EM2 and the third light-emitting control signal EM3 are both at low level, the first voltage writing transistor T11, the second voltage writing transistor T13, the writing transistor T8, and the second compensation transistor T9 are turned off.

[0188] The control terminal of the first selection transistor T7 does not receive an electrical signal, and its conduction state is the same as the last state of the previous cycle.

[0189] Sub-pixel LEDs do not emit light.

[0190] During the charging phase t11, the operating state of the sub-pixel driving circuit is as follows: Figure 7A As shown, the third transistor T3, the first light-emitting control transistor T1, the first compensation transistor T4, the second gating transistor T10, and the twelfth transistor T12, which are marked with arrows, are turned on, while the other transistors are turned off.

[0191] During the compensation phase t12 in the driving signal timing diagram, the first scan signal Gn-1 is at a high level, while the second scan signal Gn, the first light emission control signal EM1, the second light emission control signal EM2, and the third light emission control signal EM3 are at a low level; the adjustment signal SWEEP is at the first preset level.

[0192] Since the first scan signal Gn-1 is high, the third transistor T3 remains on and continues to write the reference signal Vref to the second terminal of the first capacitor C1.

[0193] Since the first light-emitting control signal EM1 is at a low level, the first light-emitting control transistor T1 is turned off, and the transmission of the first voltage signal VDD is stopped.

[0194] Since the first voltage signal VDD is at a high level, the driving transistor T5 is turned on;

[0195] Since the first scan signal Gn-1 is high, the first compensation transistor T4 is turned on, and together with the turned-on driving transistor T5, a threshold compensation structure is constructed to output the first voltage signal VDD.

[0196] Since the first light-emitting control signal EM1 is high, the first gating transistor T7 is turned on, and the first scan signal Gn-1 obtained from its first terminal is transmitted to the control terminal of the second light-emitting control transistor T6.

[0197] Since the first scanning signal Gn-1 is high, the second light-emitting control transistor T6 is turned on, and the first voltage signal VDD obtained from its first terminal is transmitted to the first terminal of the sub-pixel LED.

[0198] The sub-pixel LED is turned on based on the first voltage signal VDD, and together with the first threshold compensation unit 808 and the second light-emitting control transistor T6, it forms a discharge path between the first storage unit 809 and the power line 90.

[0199] The first storage cell 809 discharges through the discharge circuit, adjusting the voltage value of its first terminal until the discharge ends. The voltage value of the second terminal of the driving transistor T5 is determined to be the first compensation voltage value, and the voltage value of the first terminal of the first storage cell 809 is determined to be the second compensation voltage value.

[0200] Without considering the on-state voltage drop of the second light-emitting control transistor T6, the second compensation voltage value is the sum of the threshold voltage of the sub-pixel LED and the voltage value of the second voltage signal VSS, and the first compensation voltage value is the sum of the first compensation voltage value and the threshold voltage of the driving transistor T5.

[0201] Taking into account the on-state voltage drop of the second light-emitting control transistor T6, the second compensation voltage value is the sum of the threshold voltage of the sub-pixel LED, the voltage value of the second voltage signal VSS, and the on-state voltage drop of the second light-emitting control transistor T6, and the first compensation voltage value is the sum of the first compensation voltage value and the threshold voltage of the driving transistor T5.

[0202] The states of each component in the duration adjustment circuit 806 are the same as those in the previous stage, and will not be described again here.

[0203] Then, during the time period corresponding to compensation phase t12, the operating state of the sub-pixel driving circuit is as follows: Figure 7BAs shown, the third transistor T3, driving transistor T5, first compensation transistor T4, second light-emitting control transistor T6, first gating transistor T7, second gating transistor T10, and twelfth transistor T12, which are marked with arrows, are turned on, while the other transistors are turned off.

[0204] During the time period corresponding to the first data writing stage t13 in the driving signal timing diagram, the second scan signal Gn is at a high level, while the first scan signal Gn-1, the first light emission control signal EM1, the second light emission control signal EM2, and the third light emission control signal EM3 are at a low level; the adjustment electrical signal SWEEP is at the first preset level.

[0205] Since the first scan signal Gn-1 is at a low level, the third transistor T3 is turned off.

[0206] Since the first scan signal Gn-1 is at a low level, the first gating transistor T7 is turned off.

[0207] Since the second scan signal Gn is high, the second transistor T2 is turned on, and the luminous current data PAMD is written to the second terminal of the first capacitor C1.

[0208] The first capacitor C1 adjusts the first compensation voltage value stored at its first terminal based on the voltage change at its second terminal to determine the target current drive data.

[0209] The voltage change is PAMD-Vref. The target current drive data is the sum of the voltage change and the first compensation voltage value.

[0210] Without considering the on-state voltage drop of the second light-emitting control transistor T6, the voltage value of the target current drive data is: Where Vth5 represents the threshold voltage of the driving transistor T5. VLED represents the threshold voltage of the sub-pixel LED, and Vref represents the voltage value of the reference electrical signal REF.

[0211] Taking into account the on-state voltage drop of the second light-emitting control transistor T6, the voltage value of the target current drive data is: Where V1 represents the on-state voltage drop of the second light-emitting control transistor T6.

[0212] Since the first scan signal Gn-1 is at a low level, the first compensation transistor T4 is turned off and does not form a threshold compensation structure with the driving transistor T5.

[0213] Since the first scan signal Gn-1 is at a low level, the twelfth transistor T12 is turned off.

[0214] Then, during the time period corresponding to the first data writing stage t13, the operating state of the sub-pixel driving circuit is as follows: Figure 7C As shown, the second transistor T2, the first strobe transistor T7, and the second strobe transistor T10, which are marked with arrows, are turned on, while the other transistors are turned off.

[0215] During the time period corresponding to the second data writing stage t14 in the driving signal timing diagram, the first light emission control signal EM1, the second light emission control signal EM2, and the second scan signal Gn are at high level, the first scan signal Gn-1 and the third light emission control signal EM3 are at low level; the adjustment electrical signal SWEEP is at the first preset level.

[0216] Since the second light-emitting control signal EM2 is high, the writing transistor T8 is turned on, and the light-emitting duration data PWMD is written to the second selection transistor T10.

[0217] Since the second light-emitting control signal EM2 is at a high level, the second compensation transistor T9 is turned on, and together with the turned-on second gating transistor T10, a threshold compensation structure is constructed.

[0218] The threshold compensation structure writes the threshold voltage compensation light emission duration data PWMD of the second gating transistor T10 into the third capacitor C3 through discharge.

[0219] Since the first light-emitting control signal EM1 is at a high level, the first light-emitting control transistor T1 is turned on, and outputs the first voltage signal VDD to the driving transistor T5.

[0220] Based on the target current driving data obtained from its first terminal and the second compensation voltage value determined by its second terminal, the driving transistor T5 determines the current value of the driving signal and outputs the driving signal.

[0221] Without considering the on-state voltage drop of the second light-emitting control transistor T6, the current value of the driving signal is: ,

[0222] ;

[0223] but ;

[0224] Where I represents the driving current value, μ represents the electron mobility in driving transistor T5, Cox represents the capacitance of the gate oxide layer in driving transistor T5, W represents the width of driving transistor T5, L represents the length of driving transistor T5, Vgs represents the voltage difference between the control terminal and the second terminal of driving transistor T5, and Vth5 represents the threshold voltage of driving transistor T5. VLED represents the threshold voltage of the sub-pixel LED, and Vref represents the voltage value of the reference electrical signal REF.

[0225] Taking into account the on-state voltage drop of the second light-emitting control transistor T6, Where V1 represents the on-state voltage drop of the second light-emitting control transistor T6.

[0226] Since the control terminal of the second light-emitting control transistor T6 has not yet received a high-level signal, the second light-emitting control transistor T6 is turned off, and the sub-pixel LED does not emit light.

[0227] Then, during the time period corresponding to the second data writing stage t14, the operating state of the sub-pixel driving circuit is as follows: Figure 7D As shown, the second transistor T2, the first light-emitting control transistor T1, the driving transistor T5, the writing transistor T8, the second gating transistor T10, and the second compensation transistor T9, which are marked with arrows next to them, are turned on, while the other transistors are turned off.

[0228] During the time period corresponding to stage t15 shown in the driving signal timing diagram, the second scan signal Gn, the first light emission control signal EM1, and the third light emission control signal EM3 are at high levels, while the first scan signal Gn-1 and the second light emission control signal EM2 are at low levels; the adjustment signal SWEEP is a ramp signal that adjusts from the first preset level to the second preset level; Figure 6 In the waveform diagram shown, the voltage value of the regulating electrical signal SWEEP increases.

[0229] Since the third light-emitting control signal EM3 is at a high level, the first voltage writing transistor T11 is turned on, and the first reference electrical signal VGH obtained from its first terminal is written into the first terminal of the second gating transistor T10.

[0230] Since the third light-emitting control signal EM3 is high, the second voltage writing transistor T13 is turned on, and the second reference electrical signal Vref obtained from its second terminal is written into the second terminal of the second gating transistor T10.

[0231] Since the second light-emitting control signal EM2 is at a low level, the writing transistor T8 and the second compensation transistor T9 are turned off.

[0232] The third capacitor C3 adjusts the threshold compensation light emission duration data PWMD stored at its first terminal as the voltage value of the adjustment signal SWEEP increases, resulting in PWMD+Vth10+ΔSWEEP, which serves as the target duration adjustment data.

[0233] The second gating transistor T10 is turned off when the target duration adjustment data is not within its conduction data range;

[0234] The data processing unit outputs a second reference electrical signal Vref as a second control sub-signal; wherein the second reference electrical signal is at a low level.

[0235] Since the second reference electrical signal Vref is at a low level, the second light-emitting control transistor T6 is turned off and no driving signal is output, so the sub-pixel LED does not emit light.

[0236] During the non-light-emitting period corresponding to display phase t14, the operating state of the sub-pixel driving circuit is as follows: Figure 7E As shown, the second transistor T2, the first light-emitting control transistor T1, the driving transistor T5, the first voltage writing transistor T11, and the second voltage writing transistor T13, which are marked with arrows, are turned on, while the other transistors are turned off.

[0237] The second gating transistor T10 is turned on when the target duration adjustment data is within its turn-on data range;

[0238] Since the size of the second gating transistor T10 is larger than the size of the second voltage writing transistor T13, the voltage value at the second terminal of the second gating transistor T10 is the first reference electrical signal VGH.

[0239] The data processing unit outputs a first reference electrical signal VGH as a first control sub-signal; wherein the first reference electrical signal is at a high level;

[0240] The second light-emitting control transistor T6 is turned on based on the first reference electrical signal VGH, and transmits the driving signal to the sub-pixel LED to drive the sub-pixel LED to emit light.

[0241] During the light-emitting period corresponding to display phase t14, the operating state of the sub-pixel driving circuit is as follows: Figure 7F As shown, the second transistor T2, the first light-emitting control transistor T1, the driving transistor T5, the first voltage writing transistor T11, the second voltage writing transistor T13, the second gating transistor T10, and the second light-emitting control transistor T6, which are marked with arrows, are turned on, while the other transistors are turned off.

[0242] In other embodiments, the transistors in this application may be replaced with transistors of the opposite type, and their control logic is similar to that of the foregoing embodiments. They are only turned on when the transistor receives an inverted level electrical signal, and will not be described in detail here.

[0243] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0244] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display device, comprising: Gate driving circuit, data driving circuit, power supply circuit, at least one sub-pixel and corresponding sub-pixel driving circuit; The sub-pixel driving circuit is characterized by comprising: The light-emitting driving circuit is electrically connected to the gate driving circuit, the data driving circuit, and the power supply circuit. The light-emitting driving circuit includes a first threshold compensation unit and a first storage unit, and is configured to obtain a first light-emitting control signal, a first scan signal, and light-emitting current data. The first threshold compensation unit writes a first voltage signal to the first storage unit under the control of the first scan signal and the first light emission control signal in the first level state; The first threshold compensation unit is controlled by the first scanning signal and the first light emission control signal in the second level state to discharge the first voltage signal to the power supply circuit through the sub-pixel to obtain the first compensation data; The target current driving data is obtained by coupling the light-emitting current data and the first compensation data through the first storage unit; The duration adjustment circuit is electrically connected to the gate driving circuit and the data driving circuit, and is configured to obtain light emission duration data and generate a control signal based on the light emission duration data. The light-emitting driving circuit and the duration adjustment circuit are electrically connected and are also configured to generate a driving signal based on the target current driving data; Based on the control signal, the driving duration of the driving signal is controlled. The sub-pixel is electrically connected to the light-emitting driving circuit and is configured to emit light based on the driving signal.

2. The display device according to claim 1, characterized in that, The light-emitting driving circuit includes a control circuit; The control circuit is electrically connected to the power supply circuit, the first threshold compensation unit, and the gate drive circuit, and is configured to obtain the first light emission control signal. When the first light emission control signal is in a first level state, the first voltage signal provided by the power supply circuit is transmitted to the first threshold compensation unit. The first threshold compensation unit is electrically connected to the gate driving circuit and the first memory unit, and is configured to obtain the first scan signal, and be controlled by the first scan signal to write the first voltage signal into the first memory unit. The control circuit is also electrically connected to the sub-pixel and is configured to construct a path between the first threshold compensation unit and the sub-pixel when the first light emission control signal is in the second level state, controlled by the first scanning signal. The first storage unit is configured to discharge its stored first voltage signal to the power supply circuit through the first threshold compensation unit, the path, and the sub-pixel to obtain the first compensation data.

3. The display device according to claim 2, characterized in that, The control circuit includes a first light-emitting control transistor, a first terminal of the first light-emitting control transistor is electrically connected to the power supply circuit, and its control terminal is electrically connected to the gate driving circuit. It is configured to obtain the first voltage signal from its first terminal and obtain a first light-emitting control signal from its control terminal, and to output the first voltage signal by the first light-emitting control signal in a first level state. The first threshold compensation unit includes a first compensation transistor, a first terminal of the first compensation transistor is electrically connected to a second terminal of the first light-emitting control transistor, a second terminal of the first compensation transistor is electrically connected to a first terminal of the first memory cell, and a control terminal of the first compensation transistor is electrically connected to the gate driving circuit. The first compensation transistor is configured to obtain a first scan signal from its control terminal and a first voltage signal from its first terminal, and to write the first voltage signal into the first memory cell by the first scan signal.

4. The display device according to claim 3, characterized in that, The control circuit also includes: The first gating transistor has its first terminal and control terminal electrically connected to the gate driving circuit, and is configured to obtain the first scan signal from its first terminal and the first light emission control signal from its control terminal, and to output the first scan signal by the first light emission control signal which is in a second level state. The second light-emitting control transistor has its first terminal electrically connected to the first threshold compensation unit, its control terminal electrically connected to the second terminal of the first gating transistor, and its second terminal electrically connected to the sub-pixel. It is configured to obtain the first scan signal from its control terminal and control its conduction state by the first scan signal. The first threshold compensation unit further includes a driving transistor, the first end of which is electrically connected to the first end of the first compensation transistor, and its control end is electrically connected to the second end of the first compensation transistor and the first end of the first memory unit. It is configured to form a threshold compensation structure with the first compensation transistor when the first compensation transistor is turned on. The control terminal of the driving transistor serves as the first terminal of the first threshold compensation unit, and the second terminal of the driving transistor serves as the second terminal of the first threshold compensation unit. The on-state voltage of the threshold compensation structure is the threshold voltage of the driving transistor; The first threshold compensation unit is configured to discharge the electrical signal stored in the first storage unit based on the threshold compensation structure, the path constructed by the control circuit, and the sub-pixel, until the voltage difference between its first end and its second end is equal to the conduction voltage of the threshold compensation structure, and then stop discharging. The first end of the first unit determines the threshold voltage of the first threshold compensation unit and the first compensation data after threshold voltage compensation of the sub-pixel, and the second end of the second compensation data after threshold voltage compensation of the sub-pixel.

5. The display device according to any one of claims 2 to 4, characterized in that, The first storage unit is electrically connected to the gate driving circuit and the power supply circuit, and is configured to obtain a reference electrical signal during the process of the first threshold compensation unit obtaining the first compensation data, and to obtain the light emission current data after storing the first compensation data. Based on the difference between the voltage value of the reference electrical signal and the voltage value of the luminous current data, the first compensation data is coupled and adjusted to obtain the target current driving data; The driving transistor is configured to generate a driving signal based on the target current driving data and the second compensation data.

6. The display device according to claim 5, characterized in that, The duration adjustment circuit includes: The data processing unit includes a second threshold compensation unit and a second storage unit, and is electrically connected to the data driving circuit and the gate driving circuit. It is configured to obtain the first light emission control signal and a reference electrical signal, and to control the first light emission control signal to write the reference electrical signal into the second storage unit. The data processing unit is further configured to obtain a second light emission control signal and light emission duration data, and the second light emission control signal controls it to write the threshold-compensated light emission duration data into the second storage unit. Obtain the adjustment electrical signal, and adjust the threshold-compensated emission duration data based on the change in the adjustment electrical signal to obtain the target duration adjustment data; The reference potential input unit is electrically connected to the power supply circuit and the gate drive circuit, and is configured to obtain a first reference electrical signal, a second reference electrical signal and a third light emission control signal, and is controlled by the third light emission control signal to output the first reference electrical signal and the second reference electrical signal to the data processing unit. The second threshold compensation unit includes a second gating transistor, which is electrically connected to the reference potential input unit and the second storage unit. The data processing unit is configured to control the conduction state of the second gating transistor by the target duration adjustment data. When the second selection transistor is turned on, a first control sub-signal is output based on the first reference electrical signal. The first control sub-signal is a signal that controls the control circuit to construct a path. When the second selection transistor is turned off, a second control sub-signal is output based on the second reference electrical signal. The second control sub-signal is a signal that controls the control circuit to turn off the path. The control signal includes either the first control sub-signal or the second control sub-signal.

7. The display device according to claim 6, characterized in that, The display cycle of the sub-pixel includes a charging phase, a compensation phase, a first data writing phase, a second data writing phase, and a display phase. During the charging phase, the first scanning signal and the first light emission control signal are at a first level, the second light emission control signal and the third light emission control signal are at a second level, and the adjustment electrical signal is at a first preset level. The first storage unit obtains the reference electrical signal; The first light-emitting control transistor is turned on based on the first light-emitting control signal, and the first voltage signal obtained at its first terminal is written into the first terminal of the first compensation transistor. The first compensation transistor is turned on based on the first scan signal, and writes the first voltage signal into the first memory cell; The data processing unit writes the reference electrical signal into the second storage unit based on the first scanning signal.

8. The display device according to claim 7, characterized in that, During the compensation phase, the first scanning signal is at a first level, the first light emission control signal, the second light emission control signal, and the third light emission control signal are at a second level, and the adjustment electrical signal is at a first preset level. The first gating transistor is turned on based on the first light-emitting control signal and outputs the first scan signal obtained at its first terminal. The second light-emitting control transistor is turned on based on the first scanning signal to construct a path between the threshold compensation unit and the sub-pixel; The first compensation transistor remains on based on the first scan signal; The driving transistor is turned on based on the first voltage signal, and together with the first compensation transistor, a threshold compensation structure is constructed. The first storage unit discharges to the power supply circuit through the threshold compensation structure, the path, and the sub-pixel until the first compensation data is obtained.

9. The display device according to claim 8, characterized in that, During the first data writing stage, the first scanning signal, the first light emission control signal, the second light emission control signal, and the third light emission control signal are at a second level, and the adjustment electrical signal is at a first preset level. The first storage unit obtains the light-emitting current data, and based on the voltage difference between the light-emitting current data and the reference electrical signal, couples and adjusts the first compensation data to generate the target current driving data; The first gating transistor remains in the on state based on the first light emission control signal and outputs the first scanning signal; The second light-emitting control transistor is turned off based on the first scan signal.

10. The display device according to claim 8, characterized in that, During the second data writing stage, the first light emission control signal and the second light emission control signal are at a first level, the first scan signal and the third light emission control signal are at a second level, and the adjustment electrical signal is at a first preset level; The first gating transistor is turned off based on the first light emission control signal, thus stopping the transmission of the first scan signal; The data processing unit constructs a threshold compensation structure based on the second light emission control signal and the reference electrical signal stored in the second storage unit; The threshold compensation structure performs threshold compensation on the emission duration data obtained by the data processing unit based on its threshold voltage. The second storage unit stores the emission duration data after threshold compensation; The first light-emitting control transistor is turned on based on the first light-emitting control signal and outputs a first voltage signal.

11. The display device according to claim 7, characterized in that, During the display phase, the first light emission control signal and the third light emission control signal are at a first level, the first scanning signal and the second light emission control signal are at a second level, and the adjustment electrical signal is a ramp signal that adjusts from the first preset level to the second preset level. The first light-emitting control transistor is turned on based on the first light-emitting control signal and outputs a first voltage signal; The driving transistor generates a driving signal based on the target duration adjustment data and the first voltage signal; The reference potential input unit is turned on based on the third light emission control signal, and writes the first reference electrical signal and the second reference electrical signal it obtains into the second gating transistor. The second storage unit adjusts the emission duration data for threshold compensation based on the change in the adjustment electrical signal to obtain the target duration adjustment data; The second gating transistor is turned off when the target duration adjustment data is not within its conduction data range; The data processing unit outputs the second reference electrical signal as the second control sub-signal; wherein the second reference electrical signal is at a second level; The second light-emitting control transistor is turned off based on the second modulation sub-signal, and does not transmit the driving signal, so that the sub-pixel does not emit light; The second selection transistor turns on when the target duration adjustment data is within its on-data range; The data processing unit outputs the first reference electrical signal as a first control sub-signal; wherein the first reference electrical signal is at a first level; The second light-emitting control transistor is turned on based on the first reference electrical signal, and transmits the driving signal to the sub-pixel to drive the sub-pixel to emit light.

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