Risk chip repairing method and device

Abstract

The invention discloses a method and a device for repairing a risk chip, which are applied to the technical field of chip assessment, and the method comprises the following steps: assessing a real-time attack parameter set based on a preset risk assessment model, and generating a risk assessment value; acquiring historical attack operation information of the to-be-evaluated chip, and calculating an attack risk threshold value based on the historical attack operation information, a preset reference threshold value and a preset sensitivity coefficient; determining a risk chip based on the risk assessment value and an attack risk threshold, and obtaining a risk type and a risk level corresponding to the risk chip; and performing repair and security verification on the risk chip based on the risk type, and matching a starting scheme based on the risk level, so as to restart the chip passing the security verification based on the starting scheme, thereby completing repair of the risk chip. According to the method, detection, repairing, security verification and hierarchical starting are combined to form a closed loop, so that the automation from detection to recovery is improved, and the service interruption time and the operation and maintenance cost caused by a chip security event are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip security evaluation, and in particular to a risk chip repair method and device. BACKGROUND

[0002] At present, with the rapid development of computer, network, communication and integrated circuit technology, and the general trend of social informatization, chips have been widely used in various environments. As the basis of modern electronic and information systems, the chips may not only lead to personal privacy leakage and enterprise intellectual property loss if they are broken or backdoors are implanted, but also may cause equipment out of control, industrial accidents or key infrastructure paralysis, thereby causing significant life and property risks and national security risks. Since the chip runs through the whole life cycle of design, manufacturing, supply chain and operation, layered protection and strict management must be implemented in architecture design, key management, trusted boot, firmware signature, side channel and physical protection, and supply chain traceability, otherwise any weak link may be exploited, causing irreparable economic and reputation losses. However, with the in-depth study of information security, various bypass attack methods seriously threaten the security features of the chip. In an actual application, the hardware components of the chip inevitably receive security attacks during operation, thereby obtaining sensitive information in the chip. In order to ensure the security of the chip, the chip is usually analyzed and evaluated for security by the manufacturer itself and a security product detection agency before leaving the factory, and the risk chip is repaired.

[0003] The existing risk chip repair method usually uses a fixed threshold or a simple experience threshold, ignores the differences of different chip models, deployment scenarios and historical risk backgrounds, causes high false positive or false negative rates, and at the same time, most of the existing methods are limited to detection or alarm, lack of automatic closed loop with targeted repair, security verification and hierarchical start strategy, and cannot guarantee the security restart of the chip, resulting in low chip security. SUMMARY

[0004] The present application provides a risk chip repair method and device to improve the security of the chip.

[0005] In order to solve the above technical problems, the present application provides a risk chip repair method, comprising:

[0006] Obtaining a real-time attack parameter set of a chip to be evaluated, evaluating the real-time attack parameter set based on a preset risk evaluation model to generate a risk evaluation value; the risk evaluation model is obtained based on LSTM;

[0007] Obtaining historical attack running information of the chip to be evaluated, calculating an attack risk threshold based on the historical attack running information, a preset reference threshold and a preset sensitivity coefficient;

[0008] determine a risk chip based on the risk assessment value and the attack risk threshold value, and obtain a risk type and a risk level corresponding to the risk chip;

[0009] repair and security verification are performed on the risk chip based on the risk type, and a startup scheme is matched based on the risk level, so that the chip that passes the security verification is restarted based on the startup scheme, and the repair of the risk chip is completed.

[0010] The application generates a risk assessment value by obtaining a real-time attack parameter set of a chip to be evaluated and a risk assessment model constructed based on LSTM (Long Short-Term Memory), combines real-time time-series attack information with historical statistical information, considers both current situation and long-term trend in risk identification, uses the LSTM model to model time-series features to improve the detection sensitivity of different attack types, compares the risk assessment value with an attack risk threshold value to determine a risk chip and obtain its risk type and level, and makes a threshold-based comparison and hierarchical decision to make the identification result quantifiable and facilitate priority sorting. Finally, detection, repair, security verification and hierarchical startup are combined in a closed loop to improve the automation, traceability and system usability from detection to recovery, thereby reducing service interruption time and operation and maintenance cost caused by chip security incidents.

[0011] Further, the real-time attack parameter set of the chip to be evaluated is obtained, the real-time attack parameter set is evaluated based on a preset risk assessment model, and an evaluation result is generated, including:

[0012] The real-time attack parameter set of the chip to be evaluated is obtained, and the weight coefficients of each real-time attack parameter in the real-time attack parameter set are calculated;

[0013] The risk assessment model evaluates each real-time attack parameter in the real-time attack parameter set, and obtains an evaluation value corresponding to each real-time attack parameter;

[0014] The weight coefficients and evaluation values of each real-time attack parameter are weighted and summed to obtain a risk assessment value of the chip to be evaluated.

[0015] The application first calculates the weight coefficients of each real-time attack parameter, then outputs evaluation values of each parameter from the risk assessment model, and finally does weighted summation based on the weight and evaluation value to obtain the risk assessment value. By explicitly introducing parameter-level weight distribution, different types of attack indicators can be processed differently according to importance and historical performance, enhancing the discriminability and interpretability of the evaluation. The model evaluation value and weight are fused into a single risk score, which is convenient for subsequent threshold comparison and automatic decision-making, thereby improving the consistency, controllability and engineering implementability of the risk score.

[0016] Further, the historical attack running information of the chip to be evaluated is acquired, and an attack risk threshold is calculated based on the historical attack running information, a preset reference threshold and a preset sensitivity coefficient, including:

[0017] The historical attack running information of the chip to be evaluated is acquired, and a historical risk event proportion is calculated based on the historical attack running information;

[0018] The attack risk threshold of the chip to be evaluated is calculated based on the historical risk event proportion, a preset reference threshold and a preset sensitivity coefficient.

[0019] The present application gives the historical risk event proportion based on the historical attack running information for the calculation of the attack risk threshold, and the proportion is used to generate the targeted threshold in combination with the preset reference threshold and the sensitivity coefficient. By explicitly considering the local historical risk distribution in the threshold determination process, the threshold is no longer a fixed static value, but a dynamic reference responding to the actual running environment, which can adapt to the risk background of different chip models, deployment scenarios and time windows, thereby reducing the false positive and false negative rates and improving the accuracy of the threshold.

[0020] Further, the risk chip is determined based on the risk evaluation value and the attack risk threshold, and the risk type and risk level corresponding to the risk chip are acquired, including:

[0021] The risk evaluation value and the attack risk threshold are compared, and when the risk evaluation value is greater than the attack risk threshold, the chip to be evaluated is determined as a risk chip;

[0022] The risk type of the risk chip is determined based on the attack parameter type of the real-time attack parameter set;

[0023] The risk level of the risk chip is determined based on the historical risk evaluation data and real-time running parameters of the risk chip.

[0024] The present application determines the risk chip by comparing the risk evaluation value and the attack risk threshold, determines the risk type based on the type of the real-time attack parameter, and determines the risk level based on the historical risk evaluation data and real-time running parameters. This technical feature combines numerical evaluation with semantic attack type discrimination, which not only realizes quantitative determination of whether it is a risk chip, but also provides risk source information to support directional disposal; at the same time, the risk level is calculated based on historical and real-time data, so that the disposal priority can be allocated based on evidence driving, improving disposal efficiency and decision accuracy.

[0025] Further, the risk level of the risk chip is determined based on the historical risk evaluation data and real-time running parameters of the risk chip, including:

[0026] Obtain historical risk assessment data and real-time running parameters of the risk chip, the historical risk assessment data including historical risk assessment values, and the real-time running parameters including a current performance value and an affected unit quantity;

[0027] Calculate a risk trend feature of the risk chip based on the historical risk assessment values;

[0028] Calculate a running feature of the risk chip based on the current performance value and a preset benchmark performance value;

[0029] Calculate an influence range feature of the risk chip based on the affected unit quantity and a total unit quantity;

[0030] Calculate a risk level value of the risk chip based on the risk trend feature, the running feature, and the influence range feature;

[0031] Determine a risk level of the risk chip based on the risk level value.

[0032] The present application determines the risk level by determining the multi-dimensional input including the historical risk assessment values, the current performance value, and the affected unit quantity, and calculating the risk level value based on the multi-dimensional input. The multi-dimensional quantification mechanism integrates the three key dimensions of time trend, performance degradation, and influence range into risk assessment, which is beneficial to finely depict the actual damage degree of the attack on the chip and the system, so that the risk level can better reflect the business impact and repair urgency, and support more reasonable resource allocation and recovery strategy selection.

[0033] Further, the risk chip is repaired and security verified based on the risk type, and a start strategy is started based on matching of the risk level, so as to restart the chip after security verification, and complete the risk chip repair, including

[0034] The risk chip is repaired based on the risk type, and the target chip is security verified after the repair is completed, to obtain a chip to be started;

[0035] A start strategy is started based on matching of a preset target level and a risk level of the chip to be started, and the chip to be started is started based on the start strategy.

[0036] The application implements repair based on risk type and performs security verification on the chip after repair, and then starts the strategy according to the preset target level and the risk level of the chip and performs the start to complete the repair closed loop. The combination of targeted repair and independent security verification ensures that the repair measures actually eliminate the identified risks and prevent new vulnerabilities from being introduced by repair; through the risk level driven start strategy matching, the principle of hierarchical disposal according to risk is realized, so that different recovery processes are adopted for different severity events, which can quickly recover in a low-risk scenario and guarantee hierarchical security start in a high-risk scenario, and efficiency and security are considered.

[0037] Further, the start strategy is matched based on the preset target level and the risk level of the to-be-started chip, and the to-be-started chip is started based on the start strategy, including:

[0038] When the risk level of the to-be-started chip is lower than the preset target level, the to-be-started chip is directly started;

[0039] When the risk level of the to-be-started chip is higher than or equal to the preset target level, the to-be-started chip is started based on the preset continuous security start strategy.

[0040] The application directly starts when the risk level of the to-be-started chip is lower than the preset target level, and adopts the preset continuous security start strategy when the risk level is higher than or equal to the target level, and by distinguishing the two paths of direct start and continuous security start, more strict hierarchical verification is adopted in a high-risk scenario, so as to reduce the risk of power-on of the attacked image while allowing quick recovery in a low-risk scenario, so as to realize controllable compromise between security and availability, reduce unnecessary business interruption, and provide stronger security guarantee when necessary.

[0041] Further, when the risk level of the to-be-started chip is higher than or equal to the preset target level, the to-be-started chip is started based on the preset continuous security start strategy, including:

[0042] Obtaining the security start trust chain of the to-be-started chip, and reading the start image of the adjacent lower-level start item based on the adjacent intermediate start item and the upper-level start item in the security start trust chain;

[0043] Performing security verification on each start image of the security start trust chain, and when the security verification of all start images is passed, the start of the to-be-started chip is completed.

[0044] The application uses a "safe boot trust chain" in a high-risk situation, reads a lower-level boot image based on adjacent middle and upper-level boot items, and performs security verification on each image in the trust chain, and only when all images pass the verification, the boot is completed, by establishing a trust chain of step-by-step signature verification and integrity check, the attack of tampering with the image, forging the signature or rolling back the execution can be prevented, the inherent security and traceability during booting are enhanced through step-by-step verification, and the subsequent remote authentication and trusted update mechanism are provided with basic protection.

[0045] Further, the risk assessment model is constructed based on LSTM and includes:

[0046] The historical attack data of the chip to be evaluated is acquired, and the historical attack data includes historical attack parameters, historical repair parameters and attack identification parameters;

[0047] A training data set is constructed based on the historical attack parameters, the historical repair parameters and the attack identification parameters;

[0048] An initial evaluation model is constructed based on LSTM, and the initial evaluation model is trained based on the training data set to obtain a risk assessment model.

[0049] By introducing attack events, repair effects and identification features into the training set at the same time, combining the learning ability of LSTM to time sequence dependence, the obtained evaluation model can capture the time sequence mode, repeatability and time sequence evolution of the influence after the repair of the attack event, and further improve the identification ability and prediction accuracy of the complex dynamic attack; at the same time, the training and data set construction are clear, which is beneficial to model performance verification, repeatable training and engineering deployment.

[0050] In a second aspect, the application provides a risk chip repair device, which includes a risk assessment module, an attack threshold calculation module, a risk screening module and a repair module;

[0051] The risk assessment module is used for acquiring a real-time attack parameter set of a chip to be evaluated, evaluating the real-time attack parameter set based on a preset risk assessment model, and generating a risk assessment value; the risk assessment model is constructed based on LSTM;

[0052] The attack threshold calculation module is used for acquiring historical attack running information of the chip to be evaluated, and calculating an attack risk threshold based on the historical attack running information, a preset reference threshold and a preset sensitivity coefficient;

[0053] The risk screening module is used for determining a risk chip based on the risk assessment value and the attack risk threshold, and acquiring a risk type and a risk level corresponding to the risk chip;

[0054] The repair module is used for repairing and security verification of the risk chip based on the risk type, and starting a scheme based on the risk level matching, so as to restart the chip after security verification based on the starting scheme, and complete the risk chip repair. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 A flowchart of a risk chip repair method provided by an embodiment of the present application is shown in the figure.

[0056] Figure 2 A structural diagram of a risk chip repair device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0057] The specific embodiments of the present application will be further described in detail below in combination with the drawings and embodiments. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0058] The terms "first" and "second" and the like in the specification and claims of the present application and the drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0059] In this document, the term "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0060] Embodiment 1

[0061] Reference Figure 1 , Figure 1 A flowchart of a risk chip repair method provided by an embodiment of the present application is shown in the figure. The present application provides a risk chip repair method, which includes steps 101 to 104, as follows:

[0062] Step 101: Obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk evaluation model, and generate a risk evaluation value; the risk evaluation model is obtained based on LSTM;

[0063] In the embodiment, the risk assessment model is constructed based on LSTM, and includes:

[0064] The historical attack data of the chip to be evaluated is acquired, and the historical attack data includes historical attack parameters, historical repair parameters and attack identification parameters.

[0065] A training data set is constructed based on the historical attack parameters, the historical repair parameters and the attack identification parameters.

[0066] An initial evaluation model is constructed based on LSTM, and the initial evaluation model is trained based on the training data set to obtain a risk assessment model.

[0067] In the embodiment, a time sequence training set is constructed for the historical attack data of the chip to be evaluated, a long short-term memory network (LSTM) is used as a core time sequence modeling unit, a risk assessment model is trained, and a risk assessment value (continuous score or risk probability) is inferred from a real-time attack parameter sequence for subsequent threshold comparison and hierarchical decision-making.

[0068] In the embodiment, the historical attack data is derived from chip local logs, a device management system (DMS), a remote log library and an operation and maintenance audit database. The historical attack parameters include attack event timestamps, attack mode identifiers (such as DDoS, abnormal access, vulnerability exploitation attempts, etc.), attack session duration, attack frequency (number of events per unit time), damage data volume caused by a single attack, source IP and domain name feature statistics, etc. The historical attack parameters are attack event timestamps, attack mode identifiers, attack session duration, attack frequency, damage data volume caused by a single attack, and source IP and domain name feature statistics of a chip of the same type as the chip to be evaluated in the same application scenario.

[0069] In the embodiment, the historical repair parameters include repair start time and end time corresponding to each attack, repair duration, repair strategy type (patch, rollback, configuration correction and isolation), post-repair impact duration, whether complete recovery, etc. The historical repair parameters are used to evaluate the scale and severity of the corresponding attack type, and the preset risk level is determined according to the evaluation result.

[0070] In the embodiment, the attack identification parameters include a feature set for detection, such as error code count, abnormal call rate, resource usage anomaly, session failure rate, etc.

[0071] In this embodiment, the historical data is divided by a fixed sliding window (for example, the sliding window length L = 30 time steps, and the time step can be minutes / hours), each training sample is a time series feature vector sequence with a length of L, and the label is the risk assessment target in a subsequent period of time (for example, the risk score or whether a high-risk event occurs in the next 1 hour). The missing items are filled forward or interpolated based on adjacent time steps; and the obvious outliers are removed or truncated according to a preset rule. More meaningful time series features are constructed from the original logs, for example, the following are calculated at each time step: the number of attack events per unit time, the average attack duration, the cumulative damage data volume, the interval between the last N repairs, the repair success rate, the resource anomaly ratio, and the like; and the category features are one-hot encoded or embedded.

[0072] In this embodiment, the risk assessment model includes an input layer, a hidden layer, a fully connected layer, and an output layer; the input layer receives the normalized attack identification parameters; in the hidden layer, an LSTM layer captures the time series dependence; and the fully connected layer outputs feature mapping.

[0073] In this embodiment, the input layer is used to receive a normalized time series feature matrix, and the input shape is (L, d), where L is the time step length and d is the feature dimension of each time step. The hidden layer includes one or more LSTM units. For example, two layers of stacked LSTM: the first layer of LSTM has 128 units and returns a sequence; and the second layer of LSTM has 64 units and returns the state at the last time. To prevent overfitting, a dropout layer (with a default dropout of 0.2) can be added after the LSTM. The fully connected layer is used to connect the output of the LSTM to one or two layers of fully connected layers, and the activation function uses ReLU. The output layer is used to determine the output form according to the task.

[0074] In this embodiment, by introducing attack events, repair effects, and identification features in the training set at the same time, and combining the learning ability of LSTM on time series dependence, the obtained evaluation model can capture the time series pattern, repeatability of attack events, and time series evolution of the influence after repair, thereby improving the identification ability and prediction accuracy of complex dynamic attacks; and the training and data set construction are clear, which is beneficial to model performance verification, repeatable training, and engineering deployment.

[0075] In this embodiment, the real-time attack parameter set of the chip to be evaluated is obtained, the real-time attack parameter set is evaluated based on a preset risk assessment model, and an evaluation result is generated, including:

[0076] The real-time attack parameter set of the chip to be evaluated is obtained, and the weight coefficients of each real-time attack parameter in the real-time attack parameter set are calculated;

[0077] The risk assessment model is used to evaluate each real-time attack parameter in the real-time attack parameter set, to obtain an evaluation value corresponding to each real-time attack parameter;

[0078] The risk assessment value of the chip to be evaluated is obtained by weighted summation based on the weight coefficient and the evaluation value of each real-time attack parameter.

[0079] In this embodiment, first, a dynamic weight coefficient is calculated for each attack identification parameter of the target chip according to its prior importance index and historical hit performance of the parameter. The prior importance is obtained by expert rules or offline sensitivity analysis, and the historical hit performance is obtained by statistical records of historical detection. The weight distribution is a dynamic mechanism, which can be adjusted online with the changes of historical hit rate and importance index, to ensure reasonable distribution of the relative influence of different types of features at different time sequences. Subsequently, each original attack identification parameter collected is converted into a unified numerical scale (for example, the numerical value is mapped to a standard interval) through preprocessing and normalization, to eliminate dimensional differences and facilitate subsequent comparison. For category or text features, encoding or embedding processing is performed to obtain numerical features. Then, the normalized parameters are organized into a time window as model input and input into the trained network attack assessment model (including an LSTM time sequence layer and a subsequent mapping layer) to obtain the evaluation value or corresponding risk contribution of each attack identification parameter, while recording the model confidence or uncertainty measure. Finally, the system aggregates the evaluation value of each parameter by its dynamic weight to generate the comprehensive risk assessment value of the chip. The risk assessment value, together with the model confidence and parameter details, is written into a log and reported to the risk decision module for comparison with a dynamic threshold, risk classification, and subsequent disposal.

[0080] In this embodiment, the weight distribution is a dynamic mechanism, specifically:

[0081]

[0082] wherein, k i represents the dynamic weight of the i-th attack parameter; I i represents the importance of the i-th attack parameter, reflecting the criticality of the attack parameter to attack detection; H i represents the historical attack hit rate; a represents the importance weight coefficient; b represents the historical hit weight coefficient; n represents the total number of parameters.

[0083] In this embodiment, each attack identification parameter of the chip to be evaluated is evaluated and normalized, as follows:

[0084]

[0085] wherein, w irepresents the original value of the i-th attack identification parameter; min(W) represents the minimum value of the parameter in all samples; max(W) represents the maximum value of the parameter in all samples; w' i represents the normalized parameter value, ranging between [0, 1].

[0086] In this embodiment, finally, the processed evaluation values are weighted and summed to obtain the risk evaluation value S of the chip to be evaluated:

[0087]

[0088] wherein, S represents the comprehensive evaluation value, k i represents the dynamic weight of the i-th attack parameter, w' i represents the parameter value of the normalized attack parameter.

[0089] In this embodiment, first, the weight coefficients of each real-time attack parameter are calculated; second, the risk evaluation model outputs evaluation values for each parameter respectively; finally, the risk evaluation value is obtained by weighted summation based on the weight and the evaluation value. By explicitly introducing parameter-level weight distribution, different types of attack indicators can be processed differently according to importance and historical performance, enhancing the discriminability and interpretability of the evaluation; the model evaluation value and the weight are fused into a single risk score, which is convenient for subsequent threshold comparison and automatic decision-making, thereby improving the consistency, controllability and engineering implementability of the risk score.

[0090] Step 102: obtaining historical attack running information of the chip to be evaluated, calculating an attack risk threshold based on the historical attack running information, a preset reference threshold and a preset sensitivity coefficient;

[0091] In this embodiment, the obtaining historical attack running information of the chip to be evaluated, calculating an attack risk threshold based on the historical attack running information, a preset reference threshold and a preset sensitivity coefficient, comprises:

[0092] obtaining historical attack running information of the chip to be evaluated, calculating a historical risk event proportion based on the historical attack running information;

[0093] calculating an attack risk threshold of the chip to be evaluated based on the historical risk event proportion, a preset reference threshold and a preset sensitivity coefficient.

[0094] In this embodiment, first, the historical data access module retrieves the attack running records and operation and maintenance events of the chip to be evaluated within a preset time window from the local persistent storage, remote log library or audit database, including but not limited to attack type identification, occurrence time, severity annotation, disposal result and repair time length, etc. The retrieved original records are subjected to integrity check, timestamp standardization, repeated elimination and abnormality cleaning to form a historical event set for statistical analysis. Subsequently, the statistical module calculates the proportion index of "high-risk events" based on the historical event set, i.e. the ratio between the number of attack events labeled as high severity or causing significant impact and the total number of events within the time window, i.e. the historical risk event proportion, which can be further grouped by chip model, deployment scenario or time period to obtain a more detailed historical risk profile. Then, the reference threshold value and sensitivity coefficient matching the current chip and deployment context are read from the threshold value library, the sensitivity coefficient is used to control the response intensity of the threshold value to the historical high-risk proportion, and the reference threshold value is dynamically adjusted based on the historical high-risk proportion to generate the final attack risk threshold value for this evaluation; the adjusted threshold value is versioned and saved and written into the audit log for backtracking and reproduction, and is issued to the risk screening and alarm module through a preset interface for subsequent real-time comparison and alarm triggering.

[0095] In this embodiment, the attack risk threshold value is:

[0096] T i = Base i ×(1+γ·H risk ) (4)

[0097] wherein T i represents the attack risk trend threshold value of attack parameter i; Base i represents the reference threshold value; γ represents the sensitivity coefficient, default 0.1; H risk represents the historical risk event proportion.

[0098] In this embodiment, the calculation of the attack risk threshold value gives the steps of calculating the historical risk event proportion based on the historical attack running information, and generating the targeted threshold value by combining the proportion with the preset reference threshold value and sensitivity coefficient. By explicitly considering the local historical risk distribution in the threshold value determination process, the threshold value is no longer a fixed static value, but a dynamic reference responding to the actual running environment, which can adapt to the risk background of different chip models, deployment scenarios and time windows, thereby reducing the false positive and false negative rates and improving the accuracy of the threshold value.

[0099] Step 103: determining a risk chip based on the risk evaluation value and the attack risk threshold value, and obtaining a risk type and a risk level corresponding to the risk chip;

[0100] In the embodiment, the risk chip is determined based on the risk assessment value and the attack risk threshold, and the risk type and risk level corresponding to the risk chip are obtained, including:

[0101] The risk assessment value is compared with the attack risk threshold, and when the risk assessment value is greater than the attack risk threshold, the chip to be evaluated is determined as a risk chip;

[0102] The risk type of the risk chip is determined based on the attack parameter type of the real-time attack parameter set;

[0103] The risk level of the risk chip is determined based on the historical risk assessment data and real-time running parameters of the risk chip.

[0104] In the embodiment, first, the risk assessment value of the risk chip and the attack risk threshold are obtained, and the two are compared; when the risk assessment value is higher than the corresponding threshold, the system marks the chip to be evaluated as a "risk chip".

[0105] In the embodiment, the risk level of the risk chip is determined based on the historical risk assessment data and real-time running parameters of the risk chip, including:

[0106] The historical risk assessment data and real-time running parameters of the risk chip are obtained, the historical risk assessment data including a historical risk assessment value, and the real-time running parameters including a current performance value and an affected unit quantity;

[0107] The risk trend feature of the risk chip is calculated based on the historical risk assessment value;

[0108] The running feature of the risk chip is calculated based on the current performance value and a preset benchmark performance value;

[0109] The impact range feature of the risk chip is calculated based on the affected unit quantity and a total unit quantity;

[0110] The risk level value of the risk chip is calculated based on the risk trend feature, the running feature and the impact range feature;

[0111] The risk level of the risk chip is determined based on the risk level value.

[0112] In the embodiment, firstly, the historical risk assessment data sequence marked as the risk chip and the latest real-time running parameters are acquired, wherein the historical risk assessment data includes a continuous comprehensive assessment value sequence in a period of time, and the real-time running parameters at least include a current performance index, a preset benchmark performance, and a number of affected hardware units and a total number of units. Subsequently, a risk trend feature is calculated according to a sliding window strategy, that is, a weighted average of relative changes of the comprehensive assessment values in the latest several assessments, and the weight is exponentially attenuated with time, so that the recent fluctuations have a greater impact on the trend feature, thereby reflecting the upward or downward trend of the risk; and an influence range feature is calculated in parallel, taking the maximum value of the proportion of the number of affected units to the total number of units to reflect the attack coverage, and a running feature is calculated, quantifying the damage degree of the running state according to the deviation degree of the current performance from the benchmark performance. Then, the comprehensive assessment value, the risk trend feature, the influence range feature, and the running state influence coefficient are summarized to form a total risk value p, and the risk value is used as a quantitative severity index for subsequent risk level determination.

[0113] In the embodiment, the target chip with an attack risk is evaluated in terms of the assessment value, the risk trend feature, the covered influence range, and the influence degree on the running state of the target chip, and a corresponding risk value caused by the potential attack is calculated, as shown in the following formula:

[0114] p = S + h + m + u (5)

[0115] Wherein, p is the risk value, S is the risk assessment value of the target chip, h is the risk trend feature, m is the influence range feature, and u is the running feature.

[0116] In the embodiment, the risk trend feature h is:

[0117]

[0118] Wherein, S t represents the risk assessment value of the tthassessment; S t-1 represents the risk assessment value of the (t-1)thassessment; ω t =e -0.1(T-t) represents the time attenuation weight; and T represents the sliding window size.

[0119] In the embodiment, the influence range feature m is:

[0120]

[0121] In the embodiment, the running feature is:

[0122]

[0123] Wherein, the performance value is a composite performance score (CPS), which is a percentage score of a plurality of key operation indexes after normalization and weighting according to a pre-set weight, and is used to quantify the operation performance of the current chip, and the closer to the reference performance, the higher the CPS.

[0124] In the embodiment, the risk level of the risk chip is determined based on the risk level value. Firstly, the risk value is mapped to a discrete risk level (for example, very low / low / medium / high / very high) according to a pre-defined grading interval, and the risk value, each feature value and its calculation basis are recorded in the audit log and the alarm carrier, so as to drive the repair priority, select the corresponding start strategy and support the post-tracing and manual review.

[0125] In the embodiment, the risk level is determined according to the risk value, wherein the risk level is divided into very low, low, medium, high and very high attack levels. The determination rule of the risk level is as follows:

[0126] When the risk value p is greater than or equal to 80, the risk level is a very high attack level;

[0127] When the risk value p is less than 80 but greater than or equal to 60, the risk level is a high attack level;

[0128] When the risk value p is less than 60 but greater than or equal to 30, the risk level is a medium attack level;

[0129] When the risk value p is less than 30 but greater than or equal to 10, the risk level is a low attack level;

[0130] When the risk value p is less than 10, the risk level is a very low attack level.

[0131] In the embodiment, the risk level is determined after the multi-dimensional input for determining the risk level, including the historical risk evaluation value, the current performance value and the number of affected units, is determined and the risk level value is calculated. The multi-dimensional quantitative mechanism unifies three key dimensions of time trend, performance degradation and influence range into risk assessment, which is beneficial to finely describe the actual damage degree of the attack on the chip and the system, so that the risk level can better reflect the business impact and repair urgency, and support more reasonable resource allocation and recovery strategy selection.

[0132] Step 104: repairing and security verification of the risk chip based on the risk type, and matching a start scheme based on the risk level, so as to restart the chip after security verification based on the start scheme, and complete the risk chip repair.

[0133] In the embodiment, the risk chip is repaired and security verified based on the risk type, and a start strategy is matched based on the risk level, so as to restart the chip after security verification, complete the repair of the risk chip, and the method comprises the following steps:

[0134] The risk chip is repaired based on the risk type, and security verification is performed on the target chip after the repair is completed, and a chip to be started is obtained;

[0135] A start strategy is matched based on a preset target level and a risk level of the chip to be started, and the chip to be started is started based on the start strategy.

[0136] In the embodiment, after the repair work of the chip judged as the risk chip is completed, the repair result is comprehensively security verified to form the chip to be started. Then, the preset target level and the risk level of the chip to be started are compared to match the start strategy.

[0137] In the embodiment, the repair is implemented based on the risk type, and security verification is performed on the chip after the repair. Then, the start strategy is matched based on the preset target level and the risk level of the chip, and the start is performed to complete the repair closed loop. The targeted repair and independent security verification are combined to ensure that the identified risk is actually eliminated by the repair and new vulnerabilities are prevented from being introduced by the repair. Through the start strategy matching driven by the risk level, the principle of layered disposal according to the risk is realized, so that different recovery processes are adopted for different severity events, which can quickly recover in a low-risk scene and guarantee the graded security start in a high-risk scene, and the efficiency and safety are considered.

[0138] In the embodiment, the start strategy is matched based on the preset target level and the risk level of the chip to be started, and the chip to be started is started based on the start strategy, and the method comprises the following steps:

[0139] When the risk level of the chip to be started is lower than the preset target level, the chip to be started is directly started;

[0140] When the risk level of the chip to be started is higher than or equal to the preset target level, the chip to be started is started based on a preset continuous security start strategy.

[0141] In the embodiment, when the risk level of the chip to be started is lower than the preset target level, the chip is directly started; and when the risk level is higher than or equal to the target level, the preset continuous security starting strategy is adopted. By distinguishing the two paths of direct starting and continuous security starting, more strict hierarchical verification is ensured in the high-risk scenario, thereby reducing the risk of power-on of the attacked image while allowing fast recovery in the low-risk scenario, so as to achieve a controllable compromise between security and availability, reduce unnecessary business interruption, and provide stronger security guarantee when necessary.

[0142] In the embodiment, when the risk level of the chip to be started is higher than or equal to the preset target level, the chip is started based on the preset continuous security starting strategy, including:

[0143] obtaining a security starting trust chain of the chip to be started, and reading a starting image of a next lower-level starting item based on a next higher-level starting item and a next lower-level starting item in the security starting trust chain;

[0144] performing security verification on each starting image of the security starting trust chain, and completing starting of the chip to be started when the security verification of all the starting images is passed.

[0145] In the embodiment, when the risk level of the chip to be started is lower than the preset target level, the chip is directly started according to a normal starting process; and when the risk level reaches or is higher than the preset target level, the chip is started according to the preset continuous security starting strategy.

[0146] In the embodiment, the security verification, specifically: first, the verification end sends a verification request containing identity information and target verification information to the chip to be verified, the identity information is used to identify the verification end or the verification subject, and the target verification information is used to indicate the target certificate or verification material of this verification (such as the signature digest of the startup image, the session certificate or the one-time challenge response); after receiving the verification request, the chip reads the preset verification information corresponding to the identity information from the protected security storage area, and the preset verification information is a trusted certificate or reference signature / digest written during manufacturing or configuration and protected by hardware isolation; then, the readout preset verification information is compared with the target verification information from the verification end item by item and consistency checked, including signature verification and freshness check (such as based on random challenge / response or timestamp to prevent replay) as necessary; when the preset verification information and the target verification information are consistent and meet the freshness and integrity requirements, it is considered that the security verification is passed, the chip generates and records the verification pass record (including verification subject identification, verification timestamp and check digest), and at the same time, the protected verification success response can be returned for subsequent startup process; if the check fails, it is considered that the security verification fails, the chip records the failure reason and related metadata and takes subsequent actions (such as increasing the failure count, temporarily locking the verification interface, reporting an alarm or refusing to start) according to the policy to ensure the auditability and security of the verification process.

[0147] In the embodiment, when the risk level of the chip to be started reaches or is higher than the preset target level, the preset continuous security startup strategy is used to start the chip in stages. Specifically, first, the security startup trust chain saved on the chip is obtained and parsed, and each level of the startup image pointed to by each level is read in the order from top to bottom in the trust chain; the security verification operation is performed on each read startup image in turn, including the authenticity verification of the image signature, the integrity comparison of the image digest, the comparison of the image version and the non-rollback counter (to prevent downgrade rollback), and the time / freshness check when necessary; after the verification of each level is passed, the measurement digest of the image of this level is written into the protected measurement register to form an auditable measurement chain, and the next level image is read and verified under the condition that the image of this level is loaded into the controlled execution area and cannot be tampered with; if the verification of any level fails, the verification failure information is recorded and reported according to the preset strategy, and the rollback, isolation or limited recovery mode is triggered to prevent the execution of untrusted images; only when all levels of the startup image in the trust chain have completed the above verification and written the measurement record, the execution permission of the final image is released and the security startup of the chip to be started is completed. After the startup is completed, the complete verification and measurement log should be saved for traceability and remote authentication, and the running state of the chip is monitored in a short period after startup to confirm the trustworthiness and stability of the environment after startup.

[0148] The application uses a "safe boot trust chain" in a high-risk situation, reads a lower-level boot image based on adjacent middle and upper-level boot items, and performs security verification on each image in the trust chain, and only when all images are verified, the boot is completed, by establishing a trust chain of step-by-step signature verification and integrity check, it can prevent attacks such as image tampering, signature forgery or execution rollback, and by step-by-step verification, the inherent security and traceability during boot are enhanced, providing a basic guarantee for subsequent remote authentication and trusted update mechanism.

[0149] In the embodiment, the risk assessment value is generated by acquiring the real-time attack parameter set of the chip to be evaluated and the risk assessment model constructed based on LSTM, the real-time time series attack information is combined with the historical statistical information, the risk identification considers both the current situation and the long-term trend, and the LSTM model is used to model the time series characteristics to improve the detection sensitivity of different attack types, and then the risk assessment value is compared with the attack risk threshold to determine the risk chip and obtain its risk type and level, the threshold-based comparison and hierarchical decision make the identification result quantifiable and facilitate priority sorting, and finally the detection, repair, security verification and hierarchical boot are combined in a closed loop to improve the automation, traceability and system availability from detection to recovery, thereby reducing the service interruption time and operation and maintenance cost caused by chip security incidents.

[0150] Please refer to Figure 2 , Figure 2 A structural schematic diagram of a risk chip repair device provided by the embodiment of the application, comprising: a risk assessment module 201, an attack threshold calculation module 202, a risk screening module 203 and a repair module 204.

[0151] The risk assessment module 201 is configured to acquire a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk assessment model, and generate a risk assessment value; the risk assessment model is constructed based on LSTM.

[0152] The attack threshold calculation module 202 is configured to acquire historical attack running information of the chip to be evaluated, calculate an attack risk threshold based on the historical attack running information, a preset reference threshold and a preset sensitivity coefficient.

[0153] The risk screening module 203 is configured to determine a risk chip based on the risk assessment value and the attack risk threshold, and obtain a risk type and a risk level corresponding to the risk chip.

[0154] The repair module 204 is configured to repair and perform security verification on the risk chip based on the risk type, and start a scheme based on the risk level, so as to restart the chip that passes the security verification based on the scheme, and complete the repair of the risk chip.

[0155] In the embodiment of the present application, a terminal device is also provided, which comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above-mentioned risk chip repair method when executing the computer program.

[0156] In the embodiment of the present application, a computer readable storage medium is also provided, which comprises a stored computer program, wherein the computer readable storage medium controls the device where the computer readable storage medium is located to execute the above-mentioned risk chip repair method when the computer program runs.

[0157] For example, the computer program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present application. One or more modules can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the terminal device.

[0158] The terminal device can be a desktop computer, a notebook computer, a palm computer, a cloud server and the like. The terminal device can include, but is not limited to, a processor, a memory, a display. Those skilled in the art can understand that the above components are only examples of the terminal device and do not constitute a limitation on the terminal device, and can include more or fewer components, or combine certain components, or different components, for example, the terminal device can also include an input / output device, a network access device, a bus and the like.

[0159] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The processor is the control center of the terminal device, and connects all parts of the terminal device through various interfaces and lines.

[0160] The memory can be used to store computer programs and / or modules, and the processor can realize various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and calling data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required for a function (such as a sound playing function, a text conversion function, etc.), etc.; and the data storage area can store data created according to the use of the mobile phone (such as audio data, text message data, etc.), etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory devices.

[0161] Wherein, if the module based on the risk chip repair is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the processes in the above-mentioned embodiment methods, which can also be completed by a computer program instructing related hardware. The computer program can be stored in a computer readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms, etc. The computer readable medium can include any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc. Those skilled in the art can understand and implement without creative labor.

[0162] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above-described specific embodiments are only examples of the present application and are not intended to limit the protection scope of the present application. In particular, any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for repairing a risk chip, characterized in that ,including: obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk evaluation model, and generate a risk evaluation value; the risk evaluation model is constructed based on LSTM; obtain historical attack running information of the chip to be evaluated, calculate an attack risk threshold based on the historical attack running information, a preset reference threshold, and a preset sensitivity coefficient; determine a risk chip based on the risk evaluation value and the attack risk threshold, and obtain a risk type and a risk level corresponding to the risk chip; based on the risk type, repair and security verification are performed on the risk chip, and based on the risk level, a startup scheme is matched to restart the chip after security verification, thereby completing the repair of the risk chip.

2. The method for repairing a risky chip as described in claim 1, characterized in that... ,obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk evaluation model, and generate an evaluation result, including: obtain a real-time attack parameter set of a chip to be evaluated, calculate the weight coefficient of each real-time attack parameter in the real-time attack parameter set; evaluate each real-time attack parameter in the real-time attack parameter set based on the risk evaluation model, and obtain an evaluation value corresponding to each real-time attack parameter; based on the weight coefficient and the evaluation value of each real-time attack parameter, obtain the risk evaluation value of the chip to be evaluated.

3. A method for repairing a risky chip as described in claim 2, characterized in that... ,obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk evaluation model, and generate an evaluation result, including: obtain historical attack running information of the chip to be evaluated, calculate the weight coefficient of each real-time attack parameter in the real-time attack parameter set; based on the historical attack running information, a preset reference threshold, and a preset sensitivity coefficient, calculate the attack risk threshold of the chip to be evaluated.

4. A method for repairing a risky chip as described in claim 3, characterized in that... ,obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk evaluation model, and generate an evaluation result, including: compare the risk evaluation value and the attack risk threshold, and when the risk evaluation value is greater than the attack risk threshold, determine that the chip to be evaluated is a risk chip; determine the risk type of the risk chip based on the attack parameter type of the real-time attack parameter set; based on the historical risk evaluation data and real-time running parameters of the risk chip, determine the risk level of the risk chip.

5. A method for repairing a risky chip as described in claim 3, characterized in that... ,obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk evaluation model, and generate an evaluation result, including: obtain historical risk evaluation data and real-time running parameters of the risk chip, the historical risk evaluation data including a historical risk evaluation value, and the real-time running parameters including a current performance value and a number of affected units; based on the historical risk evaluation value, calculate the risk trend feature of the risk chip; based on the current performance value and a preset reference performance value, calculate the running feature of the risk chip; based on the number of affected units and the total number of units, calculate the impact range feature of the risk chip; Calculate a risk level value of the risk chip based on the risk trend feature, the operation feature and the influence range feature; Determine a risk level of the risk chip based on the risk level value.

6. The method of claim 5, wherein the risk chip is repaired by , the risk chip is repaired and security verified based on the risk type, and a start strategy is matched based on the risk level, so that the chip after security verification is restarted based on the start strategy, and the risk chip repair is completed, including: The risk chip is repaired based on the risk type, and the target chip is security verified after the repair is completed to obtain a chip to be started; A start strategy is matched based on a preset target level and the risk level of the chip to be started, and the chip to be started is started based on the start strategy.

7. A method for repairing a risky chip as described in claim 6, characterized in that... , the start strategy is matched based on a preset target level and the risk level of the chip to be started, and the chip to be started is started based on the start strategy, including: When the risk level of the chip to be started is lower than the preset target level, the chip to be started is directly started; When the risk level of the chip to be started is higher than or equal to the preset target level, the chip to be started is started based on a preset continuous security start strategy.

8. A method for repairing a risky chip as described in claim 7, characterized in that... , when the risk level of the chip to be started is higher than or equal to the preset target level, the chip to be started is started based on a preset continuous security start strategy, including: Obtain a security start trust chain of the chip to be started, and read a start mirror of an adjacent lower level based on an adjacent middle level start item and a higher level start item in the security start trust chain; Security verification is performed on each start mirror of the security start trust chain, and when the security verification of all start mirrors is passed, the start of the chip to be started is completed.

9. A method for repairing a risky chip as described in claim 1, characterized in that... , the risk assessment model is constructed based on LSTM, including: Obtain historical attack data of a chip to be evaluated, the historical attack data including historical attack parameters, historical repair parameters and attack identification parameters; Construct a training data set based on the historical attack parameters, the historical repair parameters and the attack identification parameters; An initial evaluation model is constructed based on LSTM, and the initial evaluation model is trained based on the training data set to obtain a risk assessment model.

10. A device for repairing faulty chips, characterized in that... , including: a risk assessment module, an attack threshold calculation module, a risk screening module and a repair module; The risk assessment module is configured to obtain a real-time attack parameter set of a chip to be evaluated, evaluate the real-time attack parameter set based on a preset risk assessment model, and generate a risk assessment value; The risk assessment model is constructed based on LSTM; The attack threshold calculation module is configured to obtain historical attack operation information of the chip to be evaluated, and calculate an attack risk threshold based on the historical attack operation information, a preset benchmark threshold and a preset sensitivity coefficient; The risk screening module is configured to determine a risk chip based on the risk assessment value and the attack risk threshold, and obtain a risk type and a risk level corresponding to the risk chip; The repair module is configured to perform repair and security verification on the risk chip based on the risk type, and to start a scheme based on the risk level matching, so as to restart the chip after passing the security verification based on the scheme, and complete the repair of the risk chip.

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