PCIe bandwidth allocation methods and devices, storage media and electronic devices

Abstract

This application discloses a PCIe bandwidth allocation method and apparatus, storage medium, and electronic device, relating to the field of computing technology. The method includes: sending a first clock signal to a target PCIe device and receiving a second clock signal returned by the target PCIe device in response to the first clock signal; determining the signal phase difference corresponding to each of the multiple channels based on the first clock signal and the channel clock signals corresponding to each of the multiple channels; determining a channel grouping result for the multiple channels based on the signal phase differences corresponding to each of the multiple channels, wherein the channel grouping result includes at least one channel group, and the channel group includes at least one channel; and determining a bandwidth allocation result matching the target PCIe device based on the channel grouping result. This solves the technical problem of low bandwidth allocation efficiency in related technologies and improves bandwidth allocation efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a PCIe bandwidth allocation method and apparatus, storage medium and electronic device. Background Technology

[0002] Traditional PCIe bandwidth identification schemes typically involve each company defining its own bandwidth allocation table. When a Riser card is manufactured, it is assigned a unique and fixed bandwidth allocation code. When the server powers on, the CPU obtains the Riser card's bandwidth allocation code and allocates bandwidth to it according to predefined rules.

[0003] In the aforementioned PCIe bandwidth allocation methods, the bandwidth allocation table is limited by different server version technologies. Different server versions require different bandwidth allocation tables, resulting in each Riser card being compatible with only a single server version. This creates a significant barrier to Riser card compatibility across different server versions, leading to resource waste. In other words, existing PCIe bandwidth allocation methods suffer from low allocation efficiency.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This application provides a PCIe bandwidth allocation method and apparatus, storage medium and electronic device to at least solve the problem of low PCIe bandwidth allocation efficiency in related technologies.

[0006] According to one aspect of the embodiments of this application, a PCIe bandwidth allocation method is provided, comprising: sending a first clock signal to a target PCIe device and receiving a second clock signal returned by the target PCIe device in response to the first clock signal, wherein the target PCIe device and a current device communicate via a PCIe interface, and the second clock signal includes channel clock signals corresponding to each of a plurality of channels in the PCIe interface; determining signal phase differences corresponding to each of the plurality of channels based on the first clock signal and the channel clock signals corresponding to each of the plurality of channels; determining channel grouping results of the plurality of channels based on the signal phase differences corresponding to each of the plurality of channels, wherein the channel grouping results include at least one channel group, and the channel group includes at least one channel; and determining a bandwidth allocation result matching the target PCIe device based on the channel grouping results.

[0007] According to another aspect of the embodiments of this application, a PCIe bandwidth allocation apparatus is also provided, comprising: a sending unit, configured to send a first clock signal to a target PCIe device and receive a second clock signal returned by the target PCIe device in response to the first clock signal, wherein the target PCIe device and a current device communicate via a PCIe interface, and the second clock signal includes channel clock signals corresponding to each of the plurality of channels in the PCIe interface; a first determining unit, configured to determine the signal phase difference corresponding to each of the plurality of channels based on the first clock signal and the channel clock signals corresponding to each of the plurality of channels; a second determining unit, configured to determine a channel grouping result of the plurality of channels based on the signal phase differences corresponding to each of the plurality of channels, wherein the channel grouping result includes at least one channel group, and the channel group includes at least one channel; and an allocation unit, configured to determine a bandwidth allocation result matching the target PCIe device based on the channel grouping result.

[0008] According to another aspect of the embodiments of this application, a server motherboard is also provided, including a slot on the server motherboard and a chip for any of the above-described PCIe bandwidth allocation methods.

[0009] This application also provides a server, including a server expansion card and a PCIe device connected to the server expansion card, and also includes the aforementioned server motherboard.

[0010] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described PCIe bandwidth allocation methods.

[0011] This application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the PCIe bandwidth allocation method embodiments described above.

[0012] Through the above-described embodiments of this application, by sending a first clock signal to a target PCIe device and receiving a second clock signal returned by the target PCIe device in response to the first clock signal, wherein the target PCIe device and the current device communicate via a PCIe interface, and the second clock signal includes channel clock signals corresponding to each of the multiple channels in the PCIe interface; based on the first clock signal and the channel clock signals corresponding to each of the multiple channels, the signal phase difference corresponding to each of the multiple channels is determined; based on the signal phase difference corresponding to each of the multiple channels, the channel grouping result of the multiple channels is determined, wherein the channel grouping result includes at least one channel group, and the channel group includes at least one channel; based on the channel grouping result, a bandwidth allocation result matching the target PCIe device is determined, thereby realizing automatic grouping of multiple channels based on clock signals, and thus realizing automatic allocation of PCIe bandwidth, solving the technical problem of low efficiency in existing PCIe bandwidth allocation. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is an optional hardware structure block diagram for implementing a PCIe bandwidth allocation method according to an embodiment of this application;

[0015] Figure 2 This is a flowchart of an optional PCIe bandwidth allocation method;

[0016] Figure 3 This is a schematic diagram of a component structure for an optional PCIe bandwidth allocation method;

[0017] Figure 4 This is a flowchart of another optional PCIe bandwidth allocation method;

[0018] Figure 5 This is a schematic diagram of an optional PCIe bandwidth allocation device. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The specific application environment architecture or specific hardware architecture on which the execution of the PCIe bandwidth allocation method depends is described here.

[0023] The following explains the technical terms used in this application:

[0024] PCIe: PCIe is a high-speed computer bus standard used as a high-speed serial communication interface to connect computer motherboards and external devices, such as graphics cards and network cards.

[0025] REFCLK: As the reference clock signal in the PCIe standard, REFCLK is the fundamental clock for the entire PCIe communication. Its frequency is generally 500MHz or 667MHz. Each PCIe slot and connector has a REFCLK differential signal, which is used to synchronize data transmission and other operations, to ensure precise time coordination between various devices, to ensure clock alignment between the transmitting end (Tx) and the receiving end (Rx), to achieve reliable data transmission, and to avoid data sampling errors.

[0026] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of an embodiment of the present application for implementing a PCIe bandwidth allocation method. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor (MCU) or a programmable logic device (FPGA), and may also include a central processing unit (CPU)) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0027] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the PCIe bandwidth allocation method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0028] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0029] The embodiments of this application provide a PCIe bandwidth allocation method. The method is described in detail below in conjunction with the execution flow of the above PCIe bandwidth allocation method.

[0030] This embodiment provides a PCIe bandwidth allocation method that can be applied to servers or terminal devices. Figure 2 This is a flowchart of a PCIe bandwidth allocation method according to an embodiment of this application, such as... Figure 2 As shown, the method includes the following steps:

[0031] S202, send a first clock signal to the target PCIe device and receive a second clock signal returned by the target PCIe device in response to the first clock signal, wherein the target PCIe device and the current device communicate based on the PCIe interface, and the second clock signal includes channel clock signals corresponding to each of the multiple channels in the PCIe interface.

[0032] S204, determine the signal phase difference corresponding to each of the multiple channels based on the first clock signal and the channel clock signals corresponding to each of the multiple channels respectively;

[0033] S206, determine the channel grouping result of multiple channels based on the signal phase difference corresponding to each of the multiple channels, wherein the channel grouping result includes at least one channel group, and the channel group includes at least one channel;

[0034] S208 determines the bandwidth allocation result that matches the target PCIe device based on the channel grouping result.

[0035] In step S202 of this application, the PCIe device can be a hardware device using a PCI Express interface, such as a graphics card, a solid-state drive, a network card, etc.

[0036] Optionally, the first clock signal can be a clock signal emitted by the current device, used to synchronize or trigger the response signal of the target PCIe device. Correspondingly, the second clock signal can be a clock signal returned by the target PCIe device after responding to the first clock signal, containing clock information for each of the multiple channels.

[0037] In one alternative implementation, the first clock signal described above may specifically be a REFCLK differential signal.

[0038] It should be noted that in a PCIe system, the REFCLK differential signals (REFCLK+ / REFCLK-) of a PCIe slot are usually from the same source. REFCLK homogeneity requires that the devices at both ends of the PCIe link (such as the CPU and graphics card, the motherboard and the NVMe SSD) must use the same clock source (or a strictly synchronized clock source) as the reference clock, so as to avoid data sampling errors, link training failures or performance degradation caused by slight differences in clock source frequency or phase.

[0039] Correspondingly, the channel clock signal for each channel (lane) included in the second clock signal can be the response signal returned by each channel based on the aforementioned REFCLK differential signal.

[0040] Furthermore, in step S204, the aforementioned signal phase difference can be used to indicate the relative time delay or advance between the first clock signal and the corresponding channel clock signals of the multiple channels, and can be used to characterize the degree of signal synchronization between different channels.

[0041] It should be noted that when the first clock signal is specifically a REFCLK differential signal, the aforementioned signal phase difference can specifically be a REFCLK phase difference. In the embodiments of this application, the REFCLK phase difference refers to the time offset (PhaseOffset) of the reference clock signals (REFCLK+ / -) of the transmitting end (Tx) and the receiving end (Rx) in the same PCIe link. Ideally, the REFCLKs of Tx and Rx should be perfectly synchronized (phase difference of 0). However, in actual systems, due to hardware design, transmission path, or environmental factors, phase difference is unavoidable, but it must be controlled within the allowable range of the specifications.

[0042] Specifically, the REFCLK phase difference can be caused by the following reasons:

[0043] Reason 1: Clock drift: Temperature changes or voltage fluctuations cause slight changes in the clock source frequency, accumulating phase differences (such as temperature drift of ±50ppm for crystal oscillators).

[0044] Reason 2: Difference in wiring length: The PCIe specification requires that the length difference of the REFCLK signal lines on the motherboard be controlled within 15 inches (approximately 38.1 cm). Since the signal propagation speed is approximately 6 inches per nanosecond, the maximum length difference will cause a transmission delay of approximately 2.5 nanoseconds, resulting in phase shift.

[0045] Reason 3: Impedance discontinuity: Improper placement of vias, connectors, or terminating resistors can cause signal reflection and disrupt phase alignment.

[0046] Reason 4: Clock driver characteristics: Even when using the same clock driver, the inherent delay differences between different output channels (such as differences in the internal path of the chip) will introduce a small phase difference, usually within the range of ±50ps.

[0047] Reason 5: Power supply noise: Power supply noise of the clock generator (such as ripple > 50mV) may cause clock edge jitter, indirectly increasing the phase difference.

[0048] Reason 6: Crosstalk: Electromagnetic coupling from nearby high-speed signal lines (such as PCIe data lines) can interfere with the REFCLK signal edge.

[0049] Reason 7: Temperature gradient: Uneven local temperature on the PCB causes changes in signal propagation speed (dielectric constant changes with temperature).

[0050] For each channel, a small and deterministic phase difference can be used to characterize the similarity of properties of different channels during data transmission, and then to divide different channels into different channel groups, thereby achieving bandwidth allocation to match the target PCIe device.

[0051] Through the above-described embodiments of this application, by accurately measuring the phase difference of the clock signal of the PCIe channel, channels with good synchronization are grouped and each group is allocated an appropriate bandwidth, thereby maximizing the bandwidth utilization of the PCIe interface while ensuring the stability and reliability of data transmission.

[0052] In one optional implementation, determining the channel grouping result of multiple channels based on the signal phase difference corresponding to each of the multiple channels includes:

[0053] S1, determine the relative phase difference between multiple channels based on the signal phase difference corresponding to each of the multiple channels;

[0054] S2, if the relative phase difference between at least two candidate channels among multiple channels satisfies the target grouping condition, at least two candidate channels are determined as a channel group.

[0055] Understandably, if the relative phase difference between at least two channels meets certain grouping conditions (e.g., the phase difference is within an acceptable range), then these two channels are identified as a channel group. The above grouping operation helps with subsequent bandwidth allocation and data transmission optimization.

[0056] The following section will further explain the method for determining the relative phase difference between multiple channels.

[0057] In one optional implementation, determining the relative phase difference between multiple channels based on the signal phase difference corresponding to each of the multiple channels includes:

[0058] S1, Obtain two channels from multiple channels as the current channel pair;

[0059] S2, determine the relative phase difference with the current channel pair based on the signal phase difference between the two current channels in the current channel pair;

[0060] S3, iterate through every channel pair consisting of two channels in multiple channels;

[0061] Repeat the above steps and establish a phase difference matrix based on the relative phase difference between each channel pair, where the phase difference matrix is ​​used to indicate the relative phase difference between multiple channels.

[0062] In the above embodiments of this application, while obtaining the signal phase difference corresponding to each channel, pairwise comparisons can be performed to determine the relative phase difference between each pair of channels, and the relative phase difference between multiple channels can be described by a phase difference matrix.

[0063] Once the relative phase difference between any two channels is determined, the channels can be initially grouped in the following way to obtain candidate channel groups.

[0064] In an optional implementation, before determining at least two candidate channels as a channel group, provided that the relative phase difference between at least two candidate channels among a plurality of channels satisfies the target grouping condition, the method further includes:

[0065] S1, obtain the target phase difference threshold;

[0066] S2, sequentially select one channel from multiple channels as the first channel;

[0067] S3, select one channel from multiple channels except for the first channel as the second channel;

[0068] S4, if the relative phase difference between the first channel and the second channel is less than or waits for the target phase difference threshold, the second channel and the first channel are determined as two candidate channels in the current candidate channel group.

[0069] In this embodiment, a threshold method can be used to initially group multiple channels. For example, a phase difference threshold of 15% UI (0.3ns @ PCIe Gen3) can be preset. Adaptive threshold clustering is used to compare the phase differences of all lanes pairwise using a dynamic grouping algorithm. Lanes with phase differences less than the threshold are marked as "correlated pairs". Based on the related pair information, a clustering algorithm is used to divide the lanes into several groups. The accuracy of this algorithm can reach 0.1 UI.

[0070] It's important to note that UI (Unit Interval) is the fundamental time unit in high-speed digital communication, representing the duration of a single symbol cycle. Its value is equal to the reciprocal of the signal transmission rate. If the PCIe Gen3 rate is 8.0 GT / s, then UI = 1 / 8e9 = 125 picoseconds (ps). In clock offset measurement, 0.1UI represents an accuracy of 12.5ps (in Gen3 scenarios).

[0071] In PCIe links, the UI (Interval Unit) serves two main purposes. First, it acts as a timing calibration benchmark: when reading the clock offset of each lane through IIO registers (such as IIO_PCIEPHY_LANE_OFFSET), the UI serves as a quantization unit to accurately characterize the deviation of physical layer signal alignment. Second, it can be used for jitter tolerance assessment: the PCIe specification requires the total jitter (TJ) of the link to be less than 0.3UI (typical value), and a high-precision measurement of 0.1UI can provide early warning of signal integrity risks.

[0072] It's important to note that there's a further connection between the UI and hardware design: for example, the UI value decreases with each generation of PCIe speed (e.g., UI = 62.5ps for Gen4), but it needs to maintain the same proportional accuracy (0.1UI = 6.25ps) to match tighter timing margins. Furthermore, the Intel SPR platform uses mixed-signal circuitry (such as a time-to-digital converter, TDC) to convert physical layer latency into UI-scaled values ​​and stores them in IIO registers for firmware to read.

[0073] The following is a description of the main algorithmic logic of the above algorithm.

[0074] First, you can initialize an empty list called groups to store the final grouping results.

[0075] Next, an empty set `visited` is initialized to record channels that have already been visited, thus avoiding duplicate processing.

[0076] Further, a traversal operation is performed, specifically, traversing each channel i in the phase_matrix:

[0077] If channel i is not visited, create a new group and add it to the groups list; add channel i to the group and mark it as visited.

[0078] Next, iterate through all channels j after channel i: calculate the phase difference between channels i and j; if the phase difference is less than the preset threshold, add channel j to the current group and mark it as visited.

[0079] Once each channel i has been traversed, the group is sorted by channel index and added to the groups list.

[0080] Repeat the above traversal steps until all channels have been visited.

[0081] Finally, it returns a list of groups containing all the groups.

[0082] Through the above-described embodiments of this application, channel grouping based on phase difference is achieved by comparing the phase differences between channels and grouping channels with phase differences less than a threshold into the same group. This method ensures that channels within the same group exhibit consistent clock synchronization, thereby optimizing bandwidth allocation and data transmission efficiency in PCIe slots.

[0083] In an optional implementation, the above-mentioned method for obtaining the target phase difference threshold can also be a dynamic method, including: adjusting the target phase difference threshold when at least one of the candidate channel groups determined in the previous determination does not meet the target grouping conditions.

[0084] Specifically, if at least one of the candidate channel groups identified in the previous analysis does not meet the target grouping conditions, then the target phase difference threshold needs to be adjusted. Here, the "target grouping conditions" refer to the phase difference within a channel group needing to be within a specific range to ensure the synchronization and stability of data transmission.

[0085] Further, in an optional implementation, if at least one candidate channel group among the previously determined candidate channel groups does not meet the target grouping condition, the target phase difference threshold is adjusted, including:

[0086] Case 1: If the number of candidate channels in the first candidate channel group among the multiple candidate channel groups determined in the previous test is greater than or equal to the first number threshold, and the first candidate channel group does not meet the target grouping conditions, the target phase difference threshold shall be increased.

[0087] Case 2: If the number of candidate channels in the first candidate channel group among the multiple candidate channel groups determined in the previous test is less than or equal to the second number threshold, and the first candidate channel group does not meet the target grouping conditions, reduce the target phase difference threshold.

[0088] Among them, the first quantity threshold is greater than the second quantity threshold.

[0089] In the above implementation, if the number of candidate channels included in the first candidate channel group is greater than or equal to the first quantity threshold, and the group does not meet the target grouping condition, then the target phase difference threshold is increased. This allows for more flexible grouping with larger phase differences when there are many channels in the same channel group, thereby improving bandwidth utilization.

[0090] In the above implementation, if the number of candidate channels included in the first candidate channel group is less than or equal to the second quantity threshold, and the group does not meet the target grouping condition, then the target phase difference threshold is reduced. Therefore, when the number of channels within the same channel group is small, stricter phase difference control is required to ensure the synchronization and stability of data transmission.

[0091] The above embodiments of this application describe a method for dynamically adjusting the PCIe channel packet phase difference threshold to adapt to different channel configurations and performance requirements. This improves the flexibility and efficiency of bandwidth allocation while ensuring the synchronization and stability of data transmission. By dynamically adjusting the threshold, the system can better adapt to changing hardware environments and performance requirements.

[0092] If at least two candidate channels are determined in the candidate channel group through the above implementation method, the method of determining the channel group based on the candidate channel group will be further explained below.

[0093] In one alternative implementation, if the relative phase difference between at least two candidate channels among a plurality of channels satisfies the target grouping condition, at least two candidate channels are determined as a channel group, including at least one of the following:

[0094] Method 1: Obtain the phase difference distribution interval of the signal phase difference corresponding to at least two candidate channels; if the phase difference distribution interval is located within the target interval, determine at least two candidate channels as a channel group;

[0095] Method 2: Obtain the number of channels from at least two candidate channels; if the number of channels is the target value among multiple reference values, determine at least two candidate channels as a channel group;

[0096] Method 3: When the number of channels matches the phase difference distribution range, at least two candidate channels are identified as a channel group.

[0097] In the above embodiments of this application, at least three alternative methods for determining the final channel group based on candidate channel groups are described. These methods aim to ensure that the grouping of PCIe (Peripheral Component Interconnect Express) channels meets both phase difference requirements and specific performance and bandwidth requirements. The following is a detailed description of these three methods:

[0098] Method 1 is a grouping method based on phase difference distribution intervals. First, the phase difference distribution intervals of the signal phase differences for at least two candidate channels are obtained. This interval represents the possible range of phase differences between the two channels. Then, it is determined whether this phase difference distribution interval falls within a preset target interval. The target interval is set according to system performance requirements and PCIe specifications to ensure that the grouped channels meet specific synchronization and performance standards. Finally, if the phase difference distribution interval is within the target interval, then the two candidate channels can be identified as a channel group.

[0099] Method two is a grouping method based on the number of channels. First, the number of channels is obtained: the number of channels for at least two candidate channels is obtained. The number of channels refers to the number of channels considered in the current group. Then, it is determined whether this number of channels is a target value among several reference values. These reference values ​​may be determined according to the PCIe specification and system design, such as x1, x2, x4, x8, x16, etc. Finally, if the number of channels is the target value, then the two candidate channels can be determined as a channel group.

[0100] Method three is a grouping method based on matching the number of channels with the phase difference distribution range. Method three combines the first two methods, considering both the number of channels and the phase difference distribution range. Firstly, it determines whether the number of channels matches the phase difference distribution range. This means that both the number of channels and the phase difference need to meet specific conditions. If the number of channels matches the phase difference distribution range, then the two candidate channels can be identified as a channel group.

[0101] The at least three methods described in this application provide a flexible strategy for determining PCIe channel groups to optimize bandwidth allocation and ensure the synchronization and stability of data transmission. Method one focuses on precise phase difference matching, method two focuses on the standardization of the number of channels, and method three combines both to provide a comprehensive grouping strategy. These methods ensure that bandwidth allocation in the PCIe system is more efficient and adaptable to different application scenarios.

[0102] In a preferred embodiment, determining at least two candidate channels as a channel group when the relative phase difference between at least two candidate channels in the plurality of channels satisfies the target grouping condition further includes:

[0103] S1, In the case that there are N candidate channel groups in multiple channels and the number of candidate channels in the N candidate channel groups is the same, obtain the phase difference distribution interval corresponding to each of the N candidate channel groups.

[0104] S2, if all N phase difference distribution intervals are located within the target interval and the variation pattern of the N phase difference distribution intervals satisfies the target pattern, then the N candidate channel groups are determined as N channel groups.

[0105] The above method will be described below with reference to specific embodiments.

[0106] In this embodiment of the application, the number of lanes in each group can be verified according to the bandwidth and phase difference mapping table to determine whether it conforms to the PCIe specification (such as x1, x4, x8, x16), thereby generating the bandwidth allocation table shown in Table 1 and storing it in the NVRAM non-volatile data storage area of ​​the BIOS FLASH chip.

[0107] Table 1

[0108]

[0109] In Table 1 above, the CPU ports (PE0, PE1, PE2, PE3) determine the bandwidth allocation of each lane based on the phase difference between the identified PCIe slot's REFCLK differential signal and the clock source. For example, if the phase difference between the identified PCIe slot's REFCLK differential signal and the clock source for port PE3 has four stable UI values, and each of the four stable UI values ​​is a continuous lane value change, then the 16 lanes of this PCIe slot are divided into four equal parts, that is, lanes with the same UI value are connected to the same device, divided into x4, x4, x4, x4.

[0110] The following further explains how to determine the signal phase difference of each of the multiple channels based on the first clock signal and the channel clock signals corresponding to each of the multiple channels.

[0111] In one optional implementation, determining the signal phase difference corresponding to each of the multiple channels based on the first clock signal and the channel clock signals corresponding to each of the multiple channels includes:

[0112] S1, determine the arrival time of the channel clock signals corresponding to each of the multiple channels;

[0113] S2, calculate the arrival time difference between the arrival time of each of the multiple channels and the reference arrival time indicated by the first clock signal;

[0114] S3, determine the signal phase difference corresponding to each of the multiple channels based on the arrival time difference.

[0115] Optionally, determining the arrival time of the received channel clock signals for each of the multiple channels includes:

[0116] S1, obtain the channel clock signals corresponding to each of the multiple channels from the second clock signal;

[0117] S2, according to the time-to-digital conversion unit, analyzes the channel clock signals corresponding to each of the multiple channels to obtain the arrival time of the channel clock signals corresponding to each of the multiple channels.

[0118] In one specific implementation, the CPU accurately acquires the clock signals of all lane loopbacks and stores the clock data in the IIO register set (such as IIO_PCIEPHY_LANE_OFFSET on the Intel SPR platform).

[0119] Next, phase difference calculation is performed. The CPU uses a high-precision time-to-digital converter (TDC) to measure the arrival time of the clock signals of all received lanes, and then calculates the phase difference of each lane under each root port relative to the reference clock. This establishes a phase difference matrix and records the relative phase relationship between all lanes.

[0120] The following provides a further explanation of step S202. Before sending the first clock signal to the target PCIe device and receiving the second clock signal returned by the target PCIe device in response to the first clock signal, the method further includes: in response to the current device being in a power-on state, sending a target control command to multiple PCIe devices through the BIOS program, wherein the multiple PCIe devices include the target PCIe device, the target control command is used to trigger the PCIe device to perform a clock loopback test, and the clock loopback test is used to send the first clock signal to the PCIe device and receive the second clock signal returned by the PCIe device in response to the first clock signal.

[0121] It should be noted that, in the embodiments of this application, as Figure 3 The schematic diagram of the component structure for applying the PCIe bandwidth allocation method shown can utilize the existing resources of the server to build a clock loopback mechanism hardware architecture. Specifically, all lanes in the slot are used as physical channels for the clock signal loopback mechanism; the REFCLK differential signal is used as the reference clock signal source for the clock signal loopback mechanism; the path for transmitting the clock signal from the slot back to the CPU is used as the loopback transmission path; and the CPU is used as the calculation unit for phase difference analysis and lane grouping.

[0122] exist Figure 3 In the process, when the server powers on, the clock signal loopback mechanism is activated. Each lane in each PCIe slot receives the CPU's REFCLK differential information. Each lane transmits the received clock signal back to the CPU through a dedicated loopback path (Data Lane). The CPU accurately collects the clock signals from all lane loopbacks and calculates their phase difference. By setting a phase difference threshold (determined based on system clock accuracy and jitter characteristics), the lanes are grouped, and the number of lanes in each group is verified to conform to the PCIe specification (e.g., x1, x4, x8, x16).

[0123] The following provides a further explanation of the clock loop interaction process.

[0124] In one alternative implementation, before sending the target control command to multiple PCIe devices via the BIOS program, at least one of the following is included:

[0125] Method 1: Add the first code of the test instruction for indicating clock loopback test to the first field of the target structure;

[0126] Method 2: Add a second code to the second field of the target structure to indicate the test mode for clock loopback testing;

[0127] Method 3: Add a third code to the third field of the target structure to indicate the trigger control method for clock loopback testing;

[0128] Method 4: Add a fourth code to the fourth field of the target structure to indicate the duration of the loopback test;

[0129] Method 5: Add a fifth code to the fifth field of the target structure to indicate the integrity of the verification command data.

[0130] In this embodiment, a clock loopback protocol can be defined using the above-described implementation: the BIOS program defines the SMBus clock loopback protocol, adds a 0xD2 instruction code (reserving extension bits), and adopts SMBus broadcast mode (address 0x7E); the data structure is as follows:

[0131] struct CLK_LOOPBACK_CMD {

[0132] uint8_t command; / / 0xD2, which is the first code of the test command used to indicate the clock loopback test;

[0133] uint8_t loopback_mode; / / 0x01 = clock loopback, 0x02 = data loopback, which is the second code used to indicate the test mode for clock loopback testing;

[0134] uint8_t loop_mode; / / Single trigger (mode 0) and continuous sampling (mode 1), i.e., the third code used to indicate the trigger control mode for clock loopback testing;

[0135] uint8_t loop_time; / / Loop closure duration, i.e., the fourth encoding used to indicate the duration of the loop closure test;

[0136] uint8_t checksum; / / The first 3 bytes are XORed for verification, which is the fifth encoding used to indicate the integrity of the verification command data.

[0137] In the signal transmission phase of this application embodiment, after the system is powered on, the hardware interaction mechanism triggers the clock loopback mechanism, entering the signal transmission phase. During this phase, each slot's lane receives the REFCLK differential signal and the loopback instruction: loopback_mode=0x01.

[0138] During the loopback transmission phase, after receiving the instruction, the PCIe device transmits the REFCLK clock differential signals of all lanes in this slot back to the CPU through a dedicated loopback path, and sends a data loopback instruction to the CPU: loopback_mode=0x02.

[0139] Next, signal acquisition and phase difference calculation operations can be performed.

[0140] Having determined the channel grouping result through the above embodiments of this application, the bandwidth allocation method is further described below. In an optional embodiment, determining the bandwidth allocation result matching the target PCIe device based on the channel grouping result includes: determining at least one allocation parameter of the bandwidth allocation result based on the number of channel groups indicated by the channel grouping result, wherein the at least one allocation parameter is used to indicate the division of multiple channels in the PCIe interface.

[0141] Optionally, after determining at least one allocation parameter of the bandwidth allocation result based on the number of channel groups indicated by the channel grouping result, the method further includes: storing at least one allocation parameter in a target storage area that matches the BIOS program.

[0142] Optionally, after storing at least one allocation parameter in a target memory area matching the BIOS program, the method further includes:

[0143] S1, read at least one allocation parameter from the target storage area;

[0144] S2, determine the bandwidth allocated to each of the multiple PCIe devices based on at least one allocation parameter.

[0145] In the above embodiments of this application, after verifying whether the number of lanes in each group conforms to the PCIe specification (such as x1, x4, x8, x16), a bandwidth allocation table is generated and stored in the NVRAM non-volatile data storage area (i.e., the target storage area) of the BIOS FLASH chip.

[0146] Next, PCIe transmits the data to the PCH via the SMBUS protocol, notifying the BIOS program to read the bandwidth allocation table for the memory area and complete the bandwidth allocation.

[0147] In one optional implementation, before sending the first clock signal to the target PCIe device and receiving the second clock signal returned by the target PCIe device in response to the first clock signal, the method further includes at least one of the following:

[0148] Scenario 1: The first server expansion card is connected to the first PCIe interface in the current device;

[0149] Scenario 2: Remove the second server expansion card connected to the second PCIe interface of the current device.

[0150] It is understood that, in the above implementation method, when the number of Riser cards is increased / decreased or the type of Riser card is changed in the server, the above implementation method can be used to quickly allocate PCIe bandwidth, thereby improving bandwidth allocation efficiency.

[0151] The following combination Figure 4 This application provides a complete explanation of the PCIe bandwidth allocation method.

[0152] In this embodiment, after the server powers on, the clock signal loopback mechanism is activated. Each lane in each PCIe slot receives the CPU's REFCLK differential information. Each lane transmits the received clock signal back to the CPU via a dedicated loopback path (Data Lane). The CPU accurately collects the loopback clock signals from all lanes and calculates their phase difference. By setting a phase difference threshold (determined based on system clock accuracy and jitter characteristics), the lanes are grouped. The number of lanes in each group is verified to conform to the PCIe specification (e.g., x1, x4, x8, x16). Finally, the actual lane group and its width are identified and mapped to the bandwidth configuration in the PCIe specification (e.g., x4, x8, etc.). A lane bandwidth allocation table is generated and stored in the NVRAM non-volatile data storage area of ​​the BIOS FLASH chip, thus achieving bandwidth identification. Subsequently, the BIOS program is notified to read the bandwidth allocation table in the storage area and complete the bandwidth allocation. The following describes the specific steps in detail.

[0153] S402: The server powers on and the BIOS starts; after the server powers on and starts, the clock signal loopback mechanism is activated.

[0154] S404 defines the clock loopback protocol; the BIOS program defines the SMBus clock loopback protocol, adds the 0xD2 instruction code (reserving extension bits), and adopts the SMBus broadcast mode (address 0x7E).

[0155] S406 triggers the clock loopback mechanism to transmit a signal;

[0156] After the system powers on, the hardware interaction mechanism triggers the clock loopback mechanism, entering the signal transmission phase. During this phase, each slot's lane receives the REFCLK differential signal and the loopback command: loopback_mode=0x01;

[0157] S408, differential signal data loopback transmission;

[0158] After receiving the instruction, the PCIe device transmits the REFCLK clock differential signals of all lanes in this slot to the CPU via a dedicated loopback path, and sends a data loopback instruction to the CPU: loopback_mode=0x02;

[0159] S410, data acquisition and storage;

[0160] The CPU accurately acquires the clock signals of all lane loopbacks and stores the clock data in the IIO register group (such as IIO_PCIEPHY_LANE_OFFSET on the Intel SPR platform).

[0161] S412, Phase difference calculation;

[0162] The CPU accurately acquires the clock signals of all lane loopbacks and stores the clock data in the IIO register group (such as IIO_PCIEPHY_LANE_OFFSET on the Intel SPR platform).

[0163] S414, Threshold grouping;

[0164] The phase difference threshold is preset to 15% UI (0.3ns @ PCIe Gen3). Adaptive threshold clustering is used to compare the phase differences of all lanes pairwise using a dynamic grouping Python algorithm. Lanes with phase differences less than the threshold are marked as "correlated pairs". Based on the related pair information, a clustering algorithm is used to divide the lanes into several groups.

[0165] S416, bandwidth allocation calculation;

[0166] Based on the bandwidth and phase difference mapping table, verify whether the number of lanes in each group conforms to the PCIe specification (such as x1, x4, x8, x16), and generate a bandwidth allocation table to be stored in the NVRAM non-volatile data storage area of ​​the BIOS FLASH chip.

[0167] For example, the phase difference between the REFCLK differential signal of the PCIe slot identified by the PE3 port and the clock source has four stable UI values. Each of the four stable UI values ​​is a continuous lane value change. Therefore, the 16 lanes of this PCIe slot are divided into four equal parts, that is, lanes with the same UI value are connected to the same device, divided into x4, x4, x4, x4.

[0168] S418, bandwidth allocation.

[0169] Finally, PCIe transmits the data to the PCH via the SMBUS protocol, instructing the BIOS program to read the bandwidth allocation table for the memory area and complete the bandwidth allocation.

[0170] The above-described embodiments of this application relate to a method for automatic identification and allocation of server CPU PCIe bandwidth based on a clock signal loopback mechanism. This method utilizes existing hardware resources to construct a clock signal loopback mechanism, and then modifies the software program. Through processes such as differential signal transmission, differential signal propagation, phase difference data acquisition, lane grouping, and bandwidth matching, it achieves automatic identification and allocation of actual server CPU PCIe bandwidth. Therefore, it uses a clock signal loopback circuit to automatically identify bandwidth without prior confirmation of the riser card model, and eliminates the need to maintain BIOS software due to changes in the riser card, making it a universally applicable development method.

[0171] In the above implementation, the clock signal loopback mechanism built using existing hardware resources achieves the upgrade from customized development to general development simply by issuing SMBUS loopback instructions and using the CPU PCIe phase monitoring mechanism to allocate bandwidth, which greatly improves R&D efficiency and saves hardware resources.

[0172] Furthermore, the use of a clock signal loopback mechanism breaks the convention restrictions between different versions of servers and between different manufacturers. It can serve as a standard design scheme for server PCIe slot bandwidth identification and allocation, so that server models with any configuration and topology do not need to redevelop firmware to adapt to their PCIe topology. It can also achieve the effect of universal firmware with bandwidth allocation function, laying the foundation for standardization of this technology in the industry.

[0173] Furthermore, by combining physical layer signal feature analysis with protocol layer intelligent decision-making, a high-precision, low-latency PCIe topology self-identification solution is provided for multi-CPU servers. Compared with traditional GPIO solutions, this eliminates the need for technicians to focus on BIOS software changes due to changes in load devices, reducing firmware adaptation workload by 90%.

[0174] It is clear that the method according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0175] Embodiments of this application also provide a PCIe bandwidth allocation device. Figure 5 This is a structural block diagram of a PCIe bandwidth allocation device according to an embodiment of this application, such as... Figure 5 As shown, the device includes:

[0176] The transmitting unit 502 is used to send a first clock signal to the target PCIe device and receive a second clock signal returned by the target PCIe device in response to the first clock signal. The target PCIe device and the current device communicate with each other based on the PCIe interface. The second clock signal includes channel clock signals corresponding to each of the multiple channels in the PCIe interface.

[0177] The first determining unit 504 is used to determine the signal phase difference corresponding to each of the multiple channels based on the first clock signal and the channel clock signals corresponding to each of the multiple channels respectively.

[0178] The second determining unit 506 is used to determine the channel grouping result of multiple channels based on the signal phase difference corresponding to each of the multiple channels, wherein the channel grouping result includes at least one channel group, and the channel group includes at least one channel.

[0179] Allocation unit 508 is used to determine the bandwidth allocation result that matches the target PCIe device based on the channel grouping result.

[0180] The above device sends a first clock signal to the target PCIe device and receives a second clock signal returned by the target PCIe device in response to the first clock signal. The target PCIe device and the current device communicate via a PCIe interface. The second clock signal includes channel clock signals corresponding to multiple channels in the PCIe interface. Based on the first clock signal and the channel clock signals corresponding to each channel, the phase difference of each channel is determined. Based on the phase difference of each channel, a channel grouping result is determined, where the channel grouping result includes at least one channel group, and each channel group includes at least one channel. Based on the channel grouping result, a bandwidth allocation result matching the target PCIe device is determined. This achieves automated grouping of multiple channels based on clock signals, thereby achieving automated allocation of PCIe bandwidth and solving the technical problem of low efficiency in existing PCIe bandwidth allocation methods.

[0181] Optionally, the PCIe bandwidth allocation device described above is used to: determine the relative phase difference between multiple channels based on the signal phase difference corresponding to each of the multiple channels; and determine at least two candidate channels as a channel group if the relative phase difference between at least two candidate channels among the multiple channels satisfies the target grouping condition.

[0182] Optionally, the PCIe bandwidth allocation device described above is configured to: obtain two channels from multiple channels as current channel pairs; determine the relative phase difference between the current channel pairs and the current channel pairs based on the signal phase difference between the two current channels in the current channel pairs; traverse each channel pair consisting of two channels in the multiple channels, repeat the above steps, and establish a phase difference matrix based on the relative phase difference between each channel pair, wherein the phase difference matrix is ​​used to indicate the relative phase difference between multiple channels.

[0183] Optionally, the PCIe bandwidth allocation device described above is used to: determine the arrival time of the channel clock signals corresponding to each of the multiple channels; calculate the arrival time difference between the arrival time of each of the multiple channels and the reference arrival time indicated by the first clock signal; and determine the signal phase difference corresponding to each of the multiple channels based on the arrival time difference.

[0184] Optionally, the PCIe bandwidth allocation device described above is used to: obtain the channel clock signals corresponding to each of the multiple channels from the second clock signal; and parse the channel clock signals corresponding to each of the multiple channels according to the time-to-digital conversion unit to obtain the arrival time of the channel clock signals corresponding to each of the multiple channels.

[0185] Optionally, the PCIe bandwidth allocation device described above is used for at least one of the following: obtaining the phase difference distribution interval of the signal phase difference corresponding to at least two candidate channels; determining at least two candidate channels as a channel group when the phase difference distribution interval is located within a target interval; obtaining the number of channels of at least two candidate channels; determining at least two candidate channels as a channel group when the number of channels is a target value among multiple reference values; and determining at least two candidate channels as a channel group when the number of channels matches the phase difference distribution interval.

[0186] Optionally, the PCIe bandwidth allocation device described above is further configured to: when there are N candidate channel groups in multiple channels, and the number of candidate channels included in the N candidate channel groups is the same, obtain the phase difference distribution intervals corresponding to each of the N candidate channel groups; and when all N phase difference distribution intervals are located in the target interval, and the variation law of the N phase difference distribution intervals satisfies the target law, determine the N candidate channel groups as N channel groups.

[0187] Optionally, the PCIe bandwidth allocation device described above is further configured to: obtain a target phase difference threshold; sequentially obtain one channel from multiple channels as a first channel; sequentially obtain one channel from multiple channels other than the first channel as a second channel; and, if the relative phase difference between the first channel and the second channel is less than or waits for the target phase difference threshold, determine the second channel and the first channel as two candidate channels in the current candidate channel group.

[0188] Optionally, the PCIe bandwidth allocation device described above is used to: adjust the target phase difference threshold when at least one of the candidate channel groups determined in the previous determination does not meet the target grouping conditions.

[0189] Optionally, the PCIe bandwidth allocation device described above is configured to: increase the target phase difference threshold when the number of candidate channels included in the first candidate channel group among the multiple candidate channel groups determined in the previous determination is greater than or equal to a first quantity threshold, and the first candidate channel group does not meet the target grouping conditions; and decrease the target phase difference threshold when the number of candidate channels included in the first candidate channel group among the multiple candidate channel groups determined in the previous determination is less than or equal to a second quantity threshold, and the first candidate channel group does not meet the target grouping conditions; wherein the first quantity threshold is greater than the second quantity threshold.

[0190] Optionally, the aforementioned PCIe bandwidth allocation device is further configured to: in response to the current device being powered on, send a target control command to multiple PCIe devices through a BIOS program, wherein the multiple PCIe devices include a target PCIe device, the target control command is used to trigger the PCIe device to perform a clock loopback test, the clock loopback test is used to send a first clock signal to the PCIe device, and receive a second clock signal returned by the PCIe device in response to the first clock signal.

[0191] Optionally, the PCIe bandwidth allocation device described above is used to: add a first code for indicating a test command for clock loopback testing to a first field of the target structure; add a second code for indicating a test mode for clock loopback testing to a second field of the target structure; add a third code for indicating a trigger control mode for clock loopback testing to a third field of the target structure; add a fourth code for indicating the duration of loopback testing to a fourth field of the target structure; and add a fifth code for indicating the integrity of verification command data to a fifth field of the target structure.

[0192] Optionally, the PCIe bandwidth allocation device described above is used to: determine at least one allocation parameter of the bandwidth allocation result based on the number of channel groups indicated by the channel grouping result, wherein the at least one allocation parameter is used to indicate the division of multiple channels in the PCIe interface.

[0193] Optionally, the PCIe bandwidth allocation device described above is further configured to: store at least one allocation parameter in a target storage area that matches the BIOS program.

[0194] Optionally, the PCIe bandwidth allocation device described above is configured to: read at least one allocation parameter from a target storage area; and determine the bandwidth allocated to each of the multiple PCIe devices based on the at least one allocation parameter.

[0195] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the PCIe bandwidth allocation method embodiments described above.

[0196] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the PCIe bandwidth allocation method embodiments described above when running.

[0197] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0198] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the PCIe bandwidth allocation method embodiments described above.

[0199] According to another aspect of the embodiments of this application, a server motherboard is also provided, including a slot on the server motherboard, and an input / output system chip for any of the above-described PCIe bandwidth allocation methods.

[0200] This application also provides a server, including a server expansion card and a PCIe device connected to the server expansion card, and also includes the aforementioned server motherboard.

[0201] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described PCIe bandwidth allocation methods.

[0202] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0203] The foregoing has provided a detailed description of a PCIe bandwidth allocation method, apparatus, storage medium, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A PCIe bandwidth allocation method, characterized by, Comprising: sending a first clock signal to a target PCIe device, and receiving a second clock signal returned by the target PCIe device in response to the first clock signal, wherein the target PCIe device is communicatively connected with a current device based on a PCIe interface, and the second clock signal comprises a plurality of lane clock signals each corresponding to a plurality of lanes in the PCIe interface; determining a signal phase difference corresponding to each of the plurality of lanes based on the first clock signal and the lane clock signal corresponding to each of the plurality of lanes; determining a lane grouping result of the plurality of lanes based on the signal phase difference corresponding to each of the plurality of lanes, wherein the lane grouping result comprises at least one lane group, and the lane group comprises at least one of the plurality of lanes; determining a bandwidth allocation result matched with the target PCIe device based on the lane grouping result.

2. The method of claim 1, wherein the determining the lane grouping result of the plurality of lanes based on the signal phase difference corresponding to each of the plurality of lanes comprises: determining a relative phase difference between the plurality of lanes based on the signal phase difference corresponding to each of the plurality of lanes; and determining at least two candidate lanes in the plurality of lanes as the lane group when the relative phase difference between the at least two candidate lanes satisfies a target grouping condition.

3. The method of claim 2, wherein the determining the relative phase difference between the plurality of lanes based on the signal phase difference corresponding to each of the plurality of lanes comprises: obtaining two lanes in the plurality of lanes as a current lane pair; determining the relative phase difference between the current lane pair based on the signal phase difference corresponding to each of the two lanes in the current lane pair; and iterating the above steps for each lane pair formed by two lanes in the plurality of lanes, and establishing a phase difference matrix based on the relative phase difference between each lane pair, wherein the phase difference matrix is used to indicate the relative phase difference between the plurality of lanes.

4. The method of claim 2, wherein the determining the signal phase difference corresponding to each of the plurality of lanes based on the first clock signal and the lane clock signal corresponding to each of the plurality of lanes comprises: determining an arrival time of receiving the lane clock signal corresponding to each of the plurality of lanes; calculating an arrival time difference between a reference arrival time indicated by the first clock signal and the arrival time corresponding to each of the plurality of lanes based on the arrival time corresponding to each of the plurality of lanes; and determining the signal phase difference corresponding to each of the plurality of lanes based on the arrival time difference.

5. The method of claim 4, wherein the determining the arrival time of receiving the lane clock signal corresponding to each of the plurality of lanes comprises: obtaining the lane clock signal corresponding to each of the plurality of lanes from the second clock signal. ​ ​ ​ ​ The time-to-digital conversion unit resolves the channel clock signal corresponding to each of the plurality of channels to obtain the time of arrival of the channel clock signal corresponding to each of the plurality of channels.

6. The method of claim 2, wherein, in a case where the relative phase difference between at least two candidate channels of the plurality of channels satisfies a target grouping condition, the at least two candidate channels are determined as the channel group, including at least one of: obtaining a phase difference distribution interval of the signal phase difference corresponding to each of the at least two candidate channels; and in a case where the phase difference distribution interval is located in a target interval, determining the at least two candidate channels as the channel group; obtaining a number of channels of the at least two candidate channels; in a case where the number of channels is a target value in a plurality of reference values, determining the at least two candidate channels as the channel group; and in a case where the number of channels matches the phase difference distribution interval, determining the at least two candidate channels as the channel group.

7. The method of claim 6, wherein, in a case where the relative phase difference between at least two candidate channels of the plurality of channels satisfies a target grouping condition, the at least two candidate channels are determined as the channel group, further including: in a case where the plurality of channels include N candidate channel groups and the number of candidate channels included in the N candidate channel groups is the same, obtaining the phase difference distribution interval corresponding to each of the N candidate channel groups; in a case where the N phase difference distribution intervals are all located in the target interval and a variation rule of the N phase difference distribution intervals satisfies a target rule, determining the N candidate channel groups as the N channel groups.

8. The method of claim 2, wherein, before the at least two candidate channels are determined as the channel group in a case where the relative phase difference between at least two candidate channels of the plurality of channels satisfies a target grouping condition, the method further includes: obtaining a target phase difference threshold value; sequentially obtaining one channel from the plurality of channels as a first channel; sequentially obtaining one channel from the channels of the plurality of channels other than the first channel as a second channel; in a case where the relative phase difference between the first channel and the second channel is less than or equal to the target phase difference threshold value, determining the second channel and the first channel as two candidate channels in a current candidate channel group.

9. The method of claim 8, wherein the obtaining a target phase difference threshold value includes: in a case where at least one candidate channel group of a plurality of candidate channel groups determined last time does not satisfy the target grouping condition, adjusting the target phase difference threshold value.

10. The method of claim 9, wherein, in the case where at least one candidate channel group of a plurality of candidate channel groups determined last time does not satisfy the target grouping condition, the target phase difference threshold value is adjusted, including: ​ ​ ​ ​ ​ in a case that a number of the candidate lanes included in a first candidate lane group in the plurality of candidate lane groups determined last time is greater than or equal to a first number threshold and the first candidate lane group does not satisfy the target grouping condition, increasing the target phase difference threshold; in a case that the number of the candidate lanes included in the first candidate lane group in the plurality of candidate lane groups determined last time is less than or equal to a second number threshold and the first candidate lane group does not satisfy the target grouping condition, decreasing the target phase difference threshold; wherein the first number threshold is greater than the second number threshold.

11. The method of claim 1, wherein the sending the first clock signal to the target PCIe device and receiving the second clock signal returned by the target PCIe device in response to the first clock signal further comprises: in response to the current device being in a power-on state, sending a target control instruction to a plurality of PCIe devices through a BIOS program, wherein the plurality of PCIe devices includes the target PCIe device, and the target control instruction is used to trigger the PCIe devices to perform a clock loopback test, and the clock loopback test is used to send the first clock signal to the PCIe devices and receive the second clock signal returned by the PCIe devices in response to the first clock signal.

12. The method of claim 11, wherein the sending the target control instruction to the plurality of PCIe devices through the BIOS program further comprises at least one of: adding a first encoding for indicating a test instruction of the clock loopback test in a first field of a target structure; adding a second encoding for indicating a test mode of the clock loopback test in a second field of the target structure; adding a third encoding for indicating a trigger control mode of the clock loopback test in a third field of the target structure; adding a fourth encoding for indicating a duration of the loopback test in a fourth field of the target structure; and adding a fifth encoding for indicating integrity of a check command data in a fifth field of the target structure.

13. The method of claim 1, wherein the determining the bandwidth allocation result matched with the target PCIe device according to the lane grouping result comprises: determining at least one allocation parameter of the bandwidth allocation result according to a number of lane groups indicated by the lane grouping result, wherein the at least one allocation parameter is used to indicate a division of the plurality of lanes in the PCIe interface.

14. The method of claim 13, wherein the determining the at least one allocation parameter of the bandwidth allocation result according to the number of lane groups indicated by the lane grouping result further comprises storing the at least one allocation parameter in a target storage area matched with a BIOS program.

15. The method of claim 14, wherein the storing the at least one allocation parameter in the target storage area matched with the BIOS program further comprises: ​ ​ ​ ​ ​ reading at least one of the allocation parameters from the target storage area; determining a bandwidth allocated to each of the plurality of PCIe devices according to the at least one of the allocation parameters.

16. The method of claim 13, wherein, before the sending a first clock signal to a target PCIe device and receiving a second clock signal returned by the target PCIe device in response to the first clock signal, the method further comprises at least one of: accessing a first server expansion card via a first PCIe interface in a current device; removing a second server expansion card accessed via a second PCIe interface in the current device.

17. A PCIe bandwidth allocation apparatus, characterized by, comprises: a sending unit configured to send a first clock signal to a target PCIe device and receive a second clock signal returned by the target PCIe device in response to the first clock signal, wherein the target PCIe device is communicatively connected to a current device via a PCIe interface, and the second clock signal comprises a plurality of lane clock signals each corresponding to a lane in the PCIe interface; a first determining unit configured to determine a signal phase difference corresponding to each of the plurality of lanes according to the first clock signal and the plurality of lane clock signals; a second determining unit configured to determine a lane grouping result of the plurality of lanes according to the signal phase difference corresponding to each of the plurality of lanes, wherein the lane grouping result comprises at least one lane group, and each of the lane group comprises at least one of the plurality of lanes; an allocating unit configured to determine a bandwidth allocation result matched with the target PCIe device according to the lane grouping result.

18. A server motherboard comprising a socket on the server motherboard, wherein, a chip for performing the PCIe bandwidth allocation method as claimed in any one of claims 1 to 16.

19. A server comprising a server expansion card and a PCIe device connected with the server expansion card, characterized in that, a server mainboard as claimed in claim 18.

20. A computer-readable storage medium, characterized in that, a computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the steps of the PCIe bandwidth allocation method as claimed in any one of claims 1 to 16.

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