Complementary ring channel MOS (Metal Oxide Semiconductor) transistor, preparation method thereof, semiconductor device and electronic equipment

Abstract

The invention relates to a complementary ring channel MOS transistor and a preparation method thereof, a semiconductor device and electronic equipment. The complementary ring channel MOS transistor comprises a first MOS transistor and a second MOS transistor, wherein the first MOS transistor comprises a gate structure and a first surrounding structure, and the second MOS transistor comprises a gate structure and a second surrounding structure. According to the invention, the first surrounding structure and the second surrounding structure surround the outer surface of the gate structure, so that the circuit density is greatly improved, and the chip area in the subsequent process is greatly saved; meanwhile, the preparation process is simple, the production cost is low, the floating body effect does not exist, and batch production is facilitated.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a complementary ring channel MOSFET and its fabrication method, semiconductor devices, and electronic devices. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, and traditional planar complementary metal-oxide-semiconductor (CMOS) technology has reached its limits. Three-dimensional gate-around transistor structures have attracted widespread attention, as they help to fabricate as many device cells as possible on a limited substrate.

[0003] However, gate-around transistors have technical problems such as complex fabrication processes, high production costs, significant floating body effect, and difficulty in mass production. Summary of the Invention

[0004] The purpose of this disclosure is to provide a complementary ring-channel MOSFET and its fabrication method, semiconductor device, and electronic device, which solves the technical problems of complex fabrication process, high production cost, obvious floating body effect, and difficulty in mass production of ring-channel transistors, and can at least improve circuit density and performance.

[0005] To achieve the objectives of this disclosure, the following technical solutions are provided:

[0006] In a first aspect, this disclosure provides a complementary ring-channel MOSFET, comprising: a first MOSFET and a second MOSFET; wherein,

[0007] The first MOS transistor includes a gate structure and a first surrounding structure. The first surrounding structure includes a first channel layer of a first conductivity type, a first source layer of a second conductivity type, and a first drain layer of a second conductivity type. The first source layer, the first channel layer, and the first drain layer all surround the outer surface of the gate structure and are arranged adjacent to each other in sequence along the extension direction of the gate structure.

[0008] The second MOS transistor includes a gate structure and a second surrounding structure. The second surrounding structure includes a second channel layer of a second conductivity type, a second source layer of a first conductivity type, and a second drain layer of a first conductivity type. The second drain layer, the second source layer, and the second channel layer all surround the outer surface of the gate structure and are sequentially adjacent to each other along the extension direction of the gate structure, and are arranged at intervals from the first surrounding structure.

[0009] The complementary ring-channel MOSFET disclosed herein, with a first and a second surrounding structure encircling the outer surface of the gate structure, greatly improves circuit density and significantly saves chip area in subsequent processes. Simultaneously, the fabrication process is simple, production costs are low, and there is no floating body effect, facilitating mass production. Furthermore, the first channel layer of the first conductivity type in the first surrounding structure and the second channel layer of the second conductivity type in the second surrounding structure are electrically complementary, effectively improving the structure's performance.

[0010] In one embodiment, the complementary ring-channel MOSFET further includes:

[0011] Substrate;

[0012] The bottom dielectric layer is located on the upper surface of the substrate; the first MOS transistor and the second MOS transistor are both located above the bottom dielectric layer.

[0013] In one embodiment, the first conductivity type includes N-type and the second conductivity type includes P-type; or the first conductivity type includes p-type and the second conductivity type includes N-type.

[0014] In one embodiment, the complementary ring-channel MOSFET further includes:

[0015] An annular dielectric layer is located between the first and second surrounding structures and surrounds the outer surface of the gate structure.

[0016] In one embodiment, the complementary ring-channel MOSFET further includes:

[0017] A first annular back gate structure surrounds the outer surface of a first channel layer. The first annular back gate structure includes: a first annular back gate dielectric layer surrounding the outer surface of the first channel layer; and a first annular back gate electrode surrounding the outer surface of the first annular back gate dielectric layer.

[0018] The second annular back gate structure surrounds the outer surface of the second channel layer. The second annular back gate structure includes: a second annular back gate dielectric layer surrounding the outer surface of the second channel layer; and a second annular back gate electrode surrounding the outer surface of the second annular back gate dielectric layer.

[0019] In a second aspect, this disclosure also provides a semiconductor device, comprising: a complementary ring-channel MOSFET as described in any one of the first aspects; the semiconductor device further comprising a first interconnect pillar, a first interconnect layer, a second interconnect layer, a third interconnect layer, a second interconnect pillar, and a fourth interconnect layer; wherein,

[0020] The first connection post is connected to the gate structure;

[0021] The first drain layer of the first MOSFET and the second drain layer of the second MOSFET are connected via a second interconnect layer, a third interconnect layer and a second connecting post;

[0022] The first source layer of the first MOSFET is connected to the power supply voltage via the first interconnect layer;

[0023] The second source layer of the second MOSFET is grounded via the fourth interconnect layer.

[0024] The semiconductor device disclosed herein forms a complementary MOS circuit by setting complementary ring channel MOS transistors, which greatly improves the circuit density, significantly saves chip area in subsequent processes, and effectively improves the performance of the semiconductor device; at the same time, the fabrication process is simple, the production cost is low, there is no floating body effect, and it is conducive to mass production.

[0025] Thirdly, this disclosure also provides a semiconductor device, comprising: a first MOS transistor structure and a second MOS transistor structure, both the first MOS transistor structure and the second MOS transistor structure comprising a complementary ring-channel MOS transistor as described in any one of the first aspects; the semiconductor device further comprises: a third interconnect pillar, a fourth interconnect pillar, a fifth interconnect layer, a sixth interconnect layer, a seventh interconnect layer, an eighth interconnect layer, a ninth interconnect layer, and the fifth interconnect pillar; wherein,

[0026] The third connection post is connected to the gate structure of the first MOS transistor structure;

[0027] The fourth connection post is connected to the gate structure of the second MOS transistor structure;

[0028] The first source layer in the first MOS transistor structure and the first source layer in the second MOS transistor structure are connected to the power supply voltage via the fifth interconnect layer;

[0029] The first drain layer in the first MOS transistor structure is connected to the first drain layer in the second MOS transistor structure via the sixth interconnect layer, and then connected to the second source layer in the second MOS transistor structure via the fifth connecting pillar and the ninth interconnect layer.

[0030] The second drain layer in the first MOS transistor structure is connected to the second drain layer in the second MOS transistor structure via the seventh interconnect layer;

[0031] In the first MOS transistor structure, the second source layer is grounded via the eighth interconnect layer.

[0032] The semiconductor device disclosed herein forms a complementary MOS circuit by setting complementary ring channel MOS transistors, which greatly improves the circuit density, significantly saves chip area in subsequent processes, and effectively improves the performance of the semiconductor device; at the same time, the fabrication process is simple, the production cost is low, there is no floating body effect, and it is conducive to mass production.

[0033] Fourthly, this disclosure also provides a semiconductor device, comprising: a first MOS transistor structure and a second MOS transistor structure, both the first MOS transistor structure and the second MOS transistor structure comprising a complementary ring-channel MOS transistor as described in any one of the first aspects; the semiconductor device further comprises: a sixth interconnecting pillar, a seventh interconnecting pillar, a tenth interconnecting layer, an eleventh interconnecting layer, a twelfth interconnecting layer, a thirteenth interconnecting layer, a fourteenth interconnecting layer, and an eighth interconnecting pillar; wherein,

[0034] The sixth connection post is connected to the gate structure of the first MOS structure;

[0035] The seventh connecting pillar is connected to the gate structure of the second MOS structure;

[0036] In the first MOS transistor structure, the first source layer is connected to the power supply voltage via the tenth interconnect layer;

[0037] The first drain layer in the first MOS transistor structure is connected to the first drain layer in the second MOS transistor structure via the eleventh interconnect layer;

[0038] The second drain layer in the first MOS transistor structure is connected to the second drain layer in the second MOS transistor structure via the twelfth interconnect layer, and then connected to the first source layer in the second MOS transistor structure via the eighth connecting pillar and the fourteenth interconnect layer.

[0039] The second source layer in the first MOSFET structure is connected to the second source layer in the second MOSFET structure via the thirteenth interconnect layer, and both are grounded.

[0040] The semiconductor device disclosed herein forms a complementary MOS circuit by setting complementary ring channel MOS transistors, which greatly improves the circuit density, significantly saves chip area in subsequent processes, and effectively improves the performance of the semiconductor device; at the same time, the fabrication process is simple, the production cost is low, there is no floating body effect, and it is conducive to mass production.

[0041] Fifthly, this disclosure also provides a method for fabricating a complementary ring-channel MOSFET, comprising:

[0042] Provide substrate;

[0043] A first surrounding structure and a second surrounding structure are formed on the substrate at intervals from top to bottom; gate holes that communicate with each other are formed in both the first surrounding structure and the second surrounding structure.

[0044] A gate structure is formed within the gate hole.

[0045] The disclosed method for fabricating a complementary ring-channel MOSFET, by having a first and a second ring structure surrounding the outer surface of the gate structure, significantly improves circuit density and greatly reduces chip area in subsequent processes. Simultaneously, the fabrication process is simple, production costs are low, and there is no floating body effect, facilitating mass production. Furthermore, the first channel layer of the first ring structure with a first conductivity type and the second channel layer of the second ring structure with a second conductivity type are electrically complementary, effectively improving the structure's performance.

[0046] In one embodiment, before forming the first and second surrounding structures arranged at intervals from top to bottom on the substrate, the method further includes: forming a first sacrificial layer on the upper surface of the substrate;

[0047] A second sacrificial layer is also formed between the first and second surrounding structures;

[0048] After forming the gate structure within the gate aperture, the method further includes: removing the first sacrificial layer and the second sacrificial layer to form a first sacrificial gap and a second sacrificial gap; forming a bottom dielectric layer within the first sacrificial gap and forming an annular dielectric layer within the second sacrificial gap.

[0049] In one embodiment, after forming the gate structure within the gate via, the method further includes:

[0050] A first annular back gate structure and a second annular back gate structure are formed; the first annular back gate structure surrounds the outer surface of the first channel layer; the second annular back gate structure surrounds the outer surface of the second channel layer.

[0051] Sixthly, embodiments of this disclosure also provide an electronic device comprising the complementary ring-channel MOS transistor described in any embodiment of this disclosure.

[0052] In a seventh aspect, embodiments of this disclosure also provide an electronic device, including the semiconductor device described in any of the embodiments of this disclosure.

[0053] Eighthly, embodiments of this disclosure also provide an electronic device, including a complementary ring channel MOSFET fabricated by the method described in any embodiment of this disclosure.

[0054] The electronic device disclosed herein, by having a first surrounding structure and a second surrounding structure surrounding the outer surface of the gate structure, greatly improves circuit density and significantly saves chip area in subsequent processes. Simultaneously, the fabrication process is simple, production costs are low, and there is no floating body effect, facilitating mass production. Furthermore, the first channel layer of the first conductivity type in the first surrounding structure and the second channel layer of the second conductivity type in the second surrounding structure are electrically complementary, effectively improving the performance of the complementary ring-channel MOSFET, thereby enhancing the performance of the electronic device. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of a cross-sectional structure of a complementary ring-channel MOS transistor provided in one embodiment;

[0057] Figure 2 This is a graph showing the total drain current versus back gate voltage for different thicknesses of the first channel layer in a complementary ring channel MOSFET provided in one embodiment.

[0058] Figure 3 This is a diagram illustrating the leakage current distribution of the first channel layer in a complementary ring-channel MOSFET, as provided in one embodiment.

[0059] Figure 4 This is a diagram illustrating the leakage current distribution of the first channel layer in a complementary ring-channel MOSFET, provided in another embodiment.

[0060] Figure 5 This is a graph showing the total drain current of the first MOS transistor as a function of the back gate voltage of the first annular back gate structure in a complementary ring-channel MOS transistor provided in one embodiment.

[0061] Figure 6 This is a graph showing the total drain current versus back gate voltage for different lengths of the first channel layer in a complementary ring channel MOSFET provided in one embodiment.

[0062] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment;

[0063] Figure 8 This is a circuit diagram of a semiconductor device provided in another embodiment;

[0064] Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment;

[0065] Figure 10 This is a circuit diagram of a semiconductor device provided in another embodiment;

[0066] Figure 11 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment;

[0067] Figure 12This is a circuit diagram of a semiconductor device provided in another embodiment;

[0068] Figure 13 This is a flowchart of a method for fabricating a complementary ring channel MOS transistor provided in another embodiment;

[0069] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S11 of a method for fabricating a complementary ring channel MOS transistor provided in another embodiment;

[0070] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S13 of a method for fabricating a complementary ring channel MOS transistor provided in another embodiment;

[0071] Figure 16 This is a schematic cross-sectional view of the structure obtained in step S14 of a method for fabricating a complementary ring channel MOS transistor provided in another embodiment;

[0072] Figure 17 This is a cross-sectional schematic diagram of the first and second annular back gate structures formed in a method for fabricating a complementary annular channel MOS transistor according to another embodiment.

[0073] Explanation of reference numerals in the attached figures

[0074] 10. First MOS transistor; 101. First surround structure; 1011. First channel layer; 1012. First source layer; 1013. First drain layer; 20. Second MOS transistor; 201. Second surround structure; 2011. Second channel layer; 2012. Second source layer; 2013. Second drain layer; 30. Gate structure; 301. Gate conductive layer; 302. Annular gate oxide layer; 40. Substrate; 50. Bottom dielectric layer; 60. Annular dielectric layer; 70. First annular back gate structure; 701. First annular back gate dielectric layer; 702. First annular back gate electrode; 80. Second annular back gate structure; 801. Second annular back gate dielectric layer; 802. Second annular back gate electrode;

[0075] 90. Semiconductor device; 901. First interconnect post; 902. First interconnect layer; 903. Second interconnect layer; 904. Third interconnect layer; 905. Second interconnect post; 906. Fourth interconnect layer;

[0076] 100. Semiconductor device; 1001. First MOSFET structure; 1002. Second MOSFET structure; 1003. Third interconnect pillar; 1004. Fourth interconnect pillar; 1005. Fifth interconnect layer; 1006. Sixth interconnect layer; 1007. Seventh interconnect layer; 1008. Eighth interconnect layer; 1009. Ninth interconnect layer; 1010. Fifth interconnect pillar;

[0077] 110. Semiconductor device; 1101. First MOSFET structure; 1102. Second MOSFET structure; 1103. Sixth interconnect pillar; 1104. Seventh interconnect pillar; 1105. Tenth interconnect layer; 1106. Eleventh interconnect layer; 1107. Twelfth interconnect layer; 1108. Thirteenth interconnect layer; 1109. Fourteenth interconnect layer; 1110. Eighth interconnect pillar;

[0078] 120. Gate hole. Detailed Implementation

[0079] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0081] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0082] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0083] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0084] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0085] Please see Figure 1This disclosure provides a complementary ring-channel MOSFET, comprising a first MOSFET 10 and a second MOSFET 20. The first MOSFET 10 includes a gate structure 30 and a first surrounding structure 101. The first surrounding structure 101 includes a first channel layer 1011 of a first conductivity type, a first source layer 1012 of a second conductivity type, and a first drain layer 1013 of a second conductivity type. The first source layer 1012, the first channel layer 1011, and the first drain layer 1013 all surround the outer surface of the gate structure 30. The second MOS transistor 20 includes a gate structure 30 and a second surrounding structure 201. The second surrounding structure 201 includes a second channel layer 2011 of a second conductivity type, a second source layer 2012 of a first conductivity type, and a second drain layer 2013 of a first conductivity type. The second drain layer 2013, the second source layer 2012, and the second channel layer 2011 all surround the outer surface of the gate structure 30 and are arranged adjacent to each other in sequence along the extending direction of the gate structure 30, and are spaced apart from the first surrounding structure 101.

[0086] The complementary ring-channel MOSFET disclosed herein, with a first and a second surrounding structure encircling the outer surface of the gate structure, greatly improves circuit density and significantly saves chip area in subsequent processes. Simultaneously, the fabrication process is simple, production costs are low, and there is no floating body effect, facilitating mass production. Furthermore, the first channel layer of the first conductivity type in the first surrounding structure and the second channel layer of the second conductivity type in the second surrounding structure are electrically complementary, effectively improving the structure's performance.

[0087] It should be noted that the first conductivity type includes N-type and the second conductivity type includes P-type; or the first conductivity type includes p-type and the second conductivity type includes N-type; specifically, in one example, the first conductivity type is P-type and the second conductivity type is N-type. In another example, the first conductivity type is N-type and the second conductivity type is P-type; more specifically, in this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0088] As an example, the first MOS transistor 10 may include, but is not limited to, a PMOS transistor or an NMOS transistor; the second MOS transistor 20 may include, but is not limited to, an NMOS transistor or a PMOS transistor; specifically, in this embodiment, the first MOS transistor 10 is a PMOS transistor and the second MOS transistor 20 is an NMOS transistor.

[0089] As an example, the first channel layer 1011 of the first conductivity type may include, but is not limited to, an N-type channel layer or a P-type channel layer. The channel layer material includes, but is not limited to, silicon, silicon-germanium, and metal oxide materials such as IGZO. Specifically, in this embodiment, the first channel layer 1011 is an N-type channel layer. The first channel layer 1011 may include, but is not limited to, a semiconductor layer. For example, the first channel layer 1011 may be at least one of a silicon layer or a germanium-silicon layer. The thickness of the first channel layer 1011 may include, but is not limited to, less than 20 nm. For example, the thickness of the first channel layer 1011 may be 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 14 nm, 16 nm, or 18 nm.

[0090] As an example, the first source layer 1012 of the second conductivity type may include, but is not limited to, a P-type source layer or an N-type source layer. Specifically, in this embodiment, the first source layer 1012 is a P-type source layer, and the first source layer 1012 may include, but is not limited to, a single-crystal silicon layer; the first drain layer 1013 of the second conductivity type may include, but is not limited to, a P-type drain layer; the first drain layer 1013 may include, but is not limited to, a single-crystal silicon layer.

[0091] As an example, the second channel layer 2011 of the second conductivity type may include, but is not limited to, a P-type channel layer or an N-type channel layer. The channel layer material includes, but is not limited to, silicon, silicon-germanium, and metal oxide materials such as IGZO. Specifically, in this embodiment, the second channel layer 2011 is a P-type channel layer. The second channel layer 2011 may include, but is not limited to, a semiconductor layer. For example, the second channel layer 2011 may be at least one of a silicon layer or a germanium-silicon layer. The thickness of the second channel layer 2011 may include, but is not limited to, less than 20 nm. For example, the thickness of the second channel layer 2011 may be 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 14 nm, 16 nm, or 18 nm.

[0092] It should be noted that when the thickness of the first channel layer 1011 and the thickness of the second channel layer 2011 are controlled to be less than 20 nm, leakage current generated by the structure can be suppressed. Taking the thickness of the first channel layer 1011 as an example, for instance... Figure 2 , Figure 3 and Figure 4 As shown, Figure 2 This shows the variation of the total drain current with the back gate voltage for different thicknesses of the first channel layer 1011. Figure 3The leakage mode when the thickness of the first channel layer 1011 is 22.5nm is as follows: there are gate-induced drain leakage current (GIDL) and drain-induced barrier lowering (DIBL) phenomena, and the channel can penetrate to a distance. Figure 4 The leakage current mode when the thickness of the first channel layer 1011 is 10nm is only GIDL phenomenon, which greatly reduces leakage current.

[0093] As an example, the second source layer 2012 of the first conductivity type may include, but is not limited to, an N-type source layer or a P-type source layer. Specifically, in this embodiment, the second source layer 2012 is an N-type source layer, and the second source layer 2012 may include, but is not limited to, a single-crystal silicon layer. The second drain layer 2013 of the first conductivity type may include, but is not limited to, an N-type drain layer or a P-type drain layer. Specifically, in this embodiment, the second drain layer 2013 is an N-type drain layer, and the second drain layer 2013 may include, but is not limited to, a single-crystal silicon layer.

[0094] As an example, the gate structure 30 may include a gate conductive layer 301 and an annular gate oxide layer 302. The gate conductive layer 301 may include, but is not limited to, a columnar structure, and the annular gate oxide layer 302 surrounds the outer surface of the gate conductive layer 301. The gate conductive layer 301 may include, but is not limited to, conductive layers, such as at least one of a polysilicon gate conductive layer or a metal gate conductive layer. The annular gate oxide layer 302 may include a single-layer structure, or it may include a stacked structure. The annular gate oxide layer 302 may include silicon dioxide, hafnium monoxide, silicon fluoride, silicon nitride, or a stacked layer of the above layers. The gate oxide layer 302 may also include, but is not limited to, a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), or any combination thereof. In this embodiment, the annular gate oxide layer 302 is a hafnium monoxide layer and a silicon dioxide layer sequentially stacked from the gate conductive layer 301.

[0095] In some embodiments, please continue reading Figure 1 The complementary ring channel MOSFET may further include: a substrate 40; a bottom dielectric layer 50 located on the upper surface of the substrate 40; and a first MOSFET 10 and a second MOSFET 20 both located above the bottom dielectric layer 50.

[0096] As an example, substrate 40 may include, but is not limited to, at least one of silicon substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, sapphire substrate, silicon on insulator (SOI) substrate, silicon on diamond (SOD) substrate, and strained silicon substrate deposited on germanium-silicon wafer.

[0097] As an example, the bottom dielectric layer 50 may include, but is not limited to, an insulating layer. For example, the bottom dielectric layer 50 may be a silicon nitride layer, a silicon carbonitride layer, a silicon carbon oxide layer, or a fluorosilicate glass layer, etc.; the bottom dielectric layer 50 may also be a stacked structure of the above layers.

[0098] In some embodiments, please continue reading Figure 1 The complementary ring channel MOSFET may further include: an annular dielectric layer 60, located between the first surrounding structure 10 and the second surrounding structure 20, and surrounding the outer surface of the gate structure 30.

[0099] As an example, the annular dielectric layer 60 may include, but is not limited to, an insulating layer. For example, the annular dielectric layer 60 may be a silicon nitride layer, a silicon carbonitride layer, a silicon carbon oxide layer, or a fluorosilicate glass layer, etc.; the bottom dielectric layer 50 may also be a stacked structure of the above layers.

[0100] In some embodiments, please continue reading Figure 1 The complementary ring-channel MOSFET may further include: a first ring-shaped back gate structure 70 surrounding the outer surface of the first channel layer 1011; the first ring-shaped back gate structure 70 may include: a first ring-shaped back gate dielectric layer 701 surrounding the outer surface of the first channel layer 1011; a first ring-shaped back gate electrode 702 surrounding the outer surface of the first ring-shaped back gate dielectric layer 701; and a second ring-shaped back gate structure 80 surrounding the outer surface of the second channel layer 2011; the second ring-shaped back gate structure 80 may include: a second ring-shaped back gate dielectric layer 801 surrounding the outer surface of the second channel layer 2011; and a second ring-shaped back gate electrode 802 surrounding the outer surface of the second ring-shaped back gate dielectric layer 801.

[0101] As an example, the first annular back gate dielectric layer 701 may include, but is not limited to, an oxide layer, a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), or any combination thereof, such as a silicon dioxide layer, a hafnium monoxide layer, a silicon fluoride layer, a silicon nitride layer, or a superposition of the above layers; the first annular back gate electrode 702 may include, but is not limited to, a conductive layer, such as at least one of a polysilicon gate conductive layer or a metal gate conductive layer.

[0102] As an example, the second annular back gate dielectric layer 801 may include, but is not limited to, an oxide layer, a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), or any combination thereof, such as a silicon dioxide layer, a hafnium monoxide layer, a silicon fluoride layer, a silicon nitride layer, or a superposition of the above layers; the second annular back gate electrode 802 may include, but is not limited to, a conductive layer, such as at least one of a polysilicon gate conductive layer or a metal gate conductive layer.

[0103] It should be noted that the first annular back gate structure 70 can adjust the threshold voltage of the first MOSFET 10, optimizing the speed and power consumption of the first MOSFET 10 according to actual needs; the second annular back gate structure 80 can adjust the threshold voltage of the second MOSFET 20, optimizing the speed and power consumption of the second MOSFET 20 according to actual needs. Specifically, taking the first annular back gate structure 70 as an example, the total drain current of the first MOSFET 10 changes with the back gate voltage of the first annular back gate structure 70 as follows: Figure 5 As shown, when the voltage value of the first annular back gate structure 70 is negative, the smaller the voltage value, the larger the corresponding transistor threshold current. When the voltage value of the gate structure 30 is 0V and the voltage value of the first annular back gate structure 70 is -1V, the current of the first MOS transistor can be reduced to about 1e-11A.

[0104] It should be noted that the lengths of the first channel layer 1011 and the second channel layer 2011 also affect the threshold voltages of the first MOSFET 10 and the second MOSFET 20. Specifically, taking the first channel layer 1011 as an example, please refer to [link to relevant documentation]. Figure 6 The total drain current of the first MOSFET 10 varies with the back gate voltage of the first annular back gate structure 70 under different thicknesses and lengths of the first channel layer 1011. When the length of the first channel layer 1011 is short, the negative value of the threshold voltage of the first MOSFET 10 is more pronounced. Please continue reading. Figure 6 The optimal value is when the thickness of the first channel layer 1011 is 10nm and the length is 40nm.

[0105] This disclosure also provides a semiconductor device 90, please refer to... Figure 7 and Figure 8 The semiconductor device 90 may include: a complementary ring channel MOSFET of any of the above embodiments; wherein, the first drain layer 1013 of the first MOSFET 10 is connected to the second drain layer 2013 of the second MOSFET 20; the first source layer 1012 of the first MOSFET 10 is connected to the power supply voltage VDD; and the second source layer 2012 of the second MOSFET 20 is grounded.

[0106] The semiconductor device disclosed herein forms a complementary MOS circuit by setting complementary ring channel MOS transistors, which greatly improves the circuit density, significantly saves chip area in subsequent processes, and effectively improves the performance of the semiconductor device; at the same time, the fabrication process is simple, the production cost is low, there is no floating body effect, and it is conducive to mass production.

[0107] Please continue reading. Figure 7 and Figure 8 The semiconductor device 90 may further include a first connection post 901 connected to the gate structure 30; a first interconnect layer 902 connecting the first source layer 1012 of the first MOSFET 10 to the power supply voltage VDD; a second interconnect layer 903 connecting to the first drain layer 1013 of the first MOSFET 10; a third interconnect layer 904 connecting to the second drain layer 2013 of the second MOSFET 20; a second connection post 905 connecting to both the second interconnect layer 903 and the third interconnect layer 904; and a fourth interconnect layer 906 grounding the second source layer 2012 of the second MOSFET 20.

[0108] Specifically, the semiconductor device 90 may include any of the complementary ring-channel MOSFETs in the above embodiments; the semiconductor device 90 may also include a first connection post 901, a first interconnect layer 902, a second interconnect layer 903, a third interconnect layer 904, a second connection post 905, and a fourth interconnect layer 906; wherein, the first connection post 901 is connected to the gate structure 30; the first drain layer 1013 of the first MOSFET 10 and the second drain layer 2013 of the second MOSFET 20 are connected via the second interconnect layer 903, the third interconnect layer 904, and the second connection post 905; the first source layer 1012 of the first MOSFET 10 is connected to the power supply voltage VDD via the first interconnect layer 902; the second source layer 2012 of the second MOSFET 20 is grounded via the fourth interconnect layer 906.

[0109] This disclosure also provides a semiconductor device 100, please refer to... Figure 9 and Figure 10The semiconductor device 100 may include: a first MOS transistor structure 1001 and a second MOS transistor structure 1002, both of which include a complementary ring-channel MOS transistor as described in any of the above embodiments; wherein, the first source layer 1012 in the first MOS transistor structure 1001 and the first source layer 1012 in the second MOS transistor structure 1002 are connected to the power supply voltage VDD; the first drain layer 1013 in the first MOS transistor structure 1001 and the first drain layer 1013 in the second MOS transistor structure 1002 are connected to the second source layer 2012 in the second MOS transistor structure 1002; the second drain layer 2013 in the first MOS transistor structure 1001 and the second drain layer 2013 in the second MOS transistor structure 1002 are connected; and the second source layer 2012 in the first MOS transistor structure 1001 is grounded.

[0110] The semiconductor device disclosed herein forms a complementary MOS circuit by setting complementary ring channel MOS transistors, which greatly improves the circuit density, significantly saves chip area in subsequent processes, and effectively improves the performance of the semiconductor device; at the same time, the fabrication process is simple, the production cost is low, there is no floating body effect, and it is conducive to mass production.

[0111] Please continue reading. Figure 9 and Figure 10 The semiconductor device 100 may further include: a third connection post 1003 connected to the gate structure 30 of the first MOS transistor structure 1001; a fourth connection post 1004 connected to the gate structure 30 of the second MOS transistor structure 1002; a fifth interconnect layer 1005 connecting the first source layer 1012 of the first MOS transistor 10 of the first MOS transistor structure 1001 and the first source layer 1012 of the first MOS transistor 10 of the second MOS transistor structure 1002 to the power supply voltage VDD; and a sixth interconnect layer 1006 connecting the first drain layer 1013 of the first MOS transistor 10 of the first MOS transistor structure 1001 and the first drain layer 1012 of the second MOS transistor structure 1002. The first drain layer 1013 of the first MOSFET 10 is connected; the seventh interconnect layer 1007 is connected to the second drain layer 2013 of the second MOSFET 20 of the first MOSFET structure 1001 and the second drain layer 2013 of the second MOSFET 20 of the second MOSFET structure 1002; the eighth interconnect layer 1008 grounds the second source layer 2012 of the second MOSFET 20 of the first MOSFET structure 1001; the ninth interconnect layer 1009 is connected to the second source layer 2012 of the second MOSFET 20 of the second MOSFET structure 1002; and the fifth connecting post 1010 is connected to both the sixth interconnect layer 1006 and the ninth interconnect layer 1009.

[0112] Specifically, the semiconductor device 100 may include: a first MOS transistor structure 1001 and a second MOS transistor structure 1002, both of which include complementary ring-channel MOS transistors as described in any of the above embodiments; the semiconductor device 100 may further include: a third interconnecting post 1003, a fourth interconnecting post 1004, a fifth interconnecting layer 1005, a sixth interconnecting layer 1006, a seventh interconnecting layer 1007, an eighth interconnecting layer 1008, a ninth interconnecting layer 1009, and a fifth interconnecting post 1010; wherein, the third interconnecting post 1003 is connected to the gate structure 30 of the first MOS transistor structure 1001; the fourth interconnecting post 1004 is connected to the gate structure 30 of the second MOS transistor structure 1002; the first MOS transistor structure 1001... The first source layer 1012 and the first source layer 1012 in the second MOS transistor structure 1002 are connected to the power supply voltage VDD via the fifth interconnect layer 1005; the first drain layer 1013 in the first MOS transistor structure 1001 is connected to the first drain layer 1013 in the second MOS transistor structure 1002 via the sixth interconnect layer 1006, and is then connected to the second source layer 2012 in the second MOS transistor structure 1002 via the fifth connecting post 1010 and the ninth interconnect layer 1009; the second drain layer 2013 in the first MOS transistor structure 1001 is connected to the second drain layer 2013 in the second MOS transistor structure 1002 via the seventh interconnect layer 1007; the second source layer 2012 in the first MOS transistor structure 1001 is grounded via the eighth interconnect layer 1008.

[0113] This disclosure also provides a semiconductor device 110, please refer to... Figure 11 and Figure 12 The semiconductor device 110 may include a first MOS transistor structure 1101 and a second MOS transistor structure 1102, both of which include a complementary ring-channel MOS transistor according to any of the above embodiments; wherein, the first source layer 1012 in the first MOS transistor structure 1101 is connected to the power supply voltage VDD; the first drain layer 1013 in the first MOS transistor structure 1101 is connected to the first drain layer 1013 in the second MOS transistor structure 1102; after the second drain layer 2013 in the first MOS transistor structure 1101 and the second drain layer 2013 in the second MOS transistor structure 1102 are connected, they are both connected to the first source layer 1012 in the second MOS transistor structure 1102; after the second source layer 2012 in the first MOS transistor structure 1101 and the second source layer 2012 in the second MOS transistor structure 1102 are connected, they are both grounded.

[0114] The semiconductor device disclosed herein forms a complementary MOS circuit by setting complementary ring channel MOS transistors, which greatly improves the circuit density, significantly saves chip area in subsequent processes, and effectively improves the performance of the semiconductor device; at the same time, the fabrication process is simple, the production cost is low, there is no floating body effect, and it is conducive to mass production.

[0115] Please continue reading. Figure 11 and Figure 12 The semiconductor device 110 may further include: a sixth connection post 1103 connected to the gate structure 30 of the first MOS transistor structure 1101; a seventh connection post 1104 connected to the gate structure 30 of the second MOS transistor structure 1102; a tenth interconnect layer 1105 connecting the first source layer 1012 of the first MOS transistor 10 of the first MOS transistor structure 1101 to the power supply voltage VDD; an eleventh interconnect layer 1106 connecting the first drain layer 1013 of the first MOS transistor 10 of the first MOS transistor structure 1101 and the first drain layer 1013 of the first MOS transistor 10 of the second MOS transistor structure 1102; and a twelfth interconnect layer 1107 connected to the first MOS transistor 10 of the first MOS transistor structure 1102. The second drain layer 2013 of the second MOSFET 20 in the S-MOSFET structure 1101 and the second drain layer 2013 of the second MOSFET 20 in the second MOSFET structure 1102 are connected together; the thirteenth interconnect layer 1108 connects the second source layer 2012 of the second MOSFET 20 in the first MOSFET structure 1101 and the second source layer 2012 of the second MOSFET 20 in the second MOSFET structure 1102 to ground; the fourteenth interconnect layer 1109 is connected to the first source layer 1012 of the first MOSFET 10 in the second MOSFET structure 1102; the eighth connecting post 1110 is connected to both the fourteenth interconnect layer 1109 and the twelfth interconnect layer 1107.

[0116] Specifically, the semiconductor device 110 may include: a first MOS transistor structure 1101 and a second MOS transistor structure 1102, both of which include complementary ring-channel MOS transistors as described in any of the above embodiments; the semiconductor device 110 may further include: a sixth interconnecting post 1103, a seventh interconnecting post 1104, a tenth interconnecting layer 1105, an eleventh interconnecting layer 1106, a twelfth interconnecting layer 1107, a thirteenth interconnecting layer 1108, a fourteenth interconnecting layer 1109, and an eighth interconnecting post 1110; wherein, the sixth interconnecting post 1103 is connected to the gate structure 30 of the first MOS transistor structure 1101; the seventh interconnecting post 1104 is connected to the gate structure 30 of the second MOS transistor structure 1102; the first interconnecting post 1105 in the first MOS transistor structure 1101 is connected to the gate structure 30 of the second MOS transistor structure 1102; the seventh interconnecting post 1106 in the first MOS transistor structure 1105 is connected to the gate structure 30 of the second MOS transistor structure 1102; the seventh interconnecting post 1107 in the first MOS transistor structure 1108 is connected to the gate structure 30 of the second MOS transistor structure 1102; the seventh interconnecting post 1108 in the first MOS transistor structure 1109 is connected to the gate structure 30 of the second MOS transistor structure 1102; the seventh interconnecting post 1104 in the first MOS transistor structure 1105 is connected to the gate structure 30 of the second MOS transistor structure 1102; the seventh interconnecting post 1105 in the first MOS transistor structure 1106 is connected to the gate structure 30 of the second MOS transistor structure 1102; the seventh interconnecting post 1106 A source layer 1012 is connected to the power supply voltage VDD via a tenth interconnect layer 1105; a first drain layer 1013 in a first MOSFET structure 1101 is connected to a first drain layer 1013 in a second MOSFET structure 1102 via an eleventh interconnect layer 1106; a second drain layer 2013 in a first MOSFET structure 1101 is connected to a second drain layer 2013 in a second MOSFET structure 1102 via a twelfth interconnect layer 1107, and then connected to a first source layer 1012 in a second MOSFET structure 1102 via an eighth connecting post 1110 and a fourteenth interconnect layer 1109; a second source layer 2012 in a first MOSFET structure 1101 is connected to a second source layer 2012 in a second MOSFET structure 1102 via a thirteenth interconnect layer 1108, and then grounded.

[0117] This disclosure also provides a method for fabricating a complementary ring-channel MOSFET. Please refer to [link to relevant documentation]. Figure 13 The fabrication method of complementary ring channel MOSFETs may include:

[0118] S11: Provides a substrate.

[0119] S13: A first surrounding structure and a second surrounding structure are formed on the substrate at intervals from top to bottom; gate holes that communicate with each other are formed in both the first surrounding structure and the second surrounding structure.

[0120] S14: A gate structure is formed within the gate hole.

[0121] The disclosed method for fabricating a complementary ring-channel MOSFET, by having a first and a second ring structure surrounding the outer surface of the gate structure, significantly improves circuit density and greatly reduces chip area in subsequent processes. Simultaneously, the fabrication process is simple, production costs are low, and there is no floating body effect, facilitating mass production. Furthermore, the first channel layer of the first ring structure with a first conductivity type and the second channel layer of the second ring structure with a second conductivity type are electrically complementary, effectively improving the structure's performance.

[0122] In some embodiments, prior to step S13, the method for fabricating a complementary ring channel MOS transistor may include the following step: S12.

[0123] S12: A first sacrificial layer is formed on the upper surface of the substrate. A second sacrificial layer is also formed between the first surrounding structure and the second surrounding structure.

[0124] In some embodiments, after step S14, the method for fabricating a complementary ring channel MOS transistor may further include the following step: S15.

[0125] S15: Remove the first sacrificial layer and the second sacrificial layer to form a first sacrificial gap and a second sacrificial gap; form a bottom dielectric layer in the first sacrificial gap and form an annular dielectric layer in the second sacrificial gap.

[0126] It should be understood that, although Figure 13 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 13 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages does not have to be sequential, but can be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0127] To more clearly illustrate the fabrication methods of the semiconductor devices in the above embodiments, please refer to the following embodiments. Figures 14-17 I understand.

[0128] In step S11, please refer to Figure 14 Substrate 40 is provided.

[0129] As an example, substrate 40 may include, but is not limited to, at least one of silicon substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, sapphire substrate, silicon on insulator (SOI) substrate, silicon on diamond (SOD) substrate, and strained silicon substrate deposited on germanium-silicon wafer.

[0130] In step S12, a first sacrificial layer (not shown) is formed on the upper surface of the substrate 40.

[0131] As an example, a first sacrificial layer may be formed on the upper surface of the substrate 40 using, but not limited to, molecular beam epitaxy (MBE); the first sacrificial layer may include, but is not limited to, a germanium-silicon layer.

[0132] In step S13, please refer to Figure 15 A first surrounding structure 101 and a second surrounding structure 201 are formed on the substrate 40 at intervals from top to bottom; gate holes 120 are formed in both the first surrounding structure 101 and the second surrounding structure 201.

[0133] As an example, a first surrounding structure 101 and a second surrounding structure 201 arranged from top to bottom can be formed on a substrate 40 using molecular beam epitaxy, but not limited to this process; and gate holes 120 that are interconnected can be formed in the first surrounding structure 101 and the second surrounding structure 201 using wet etching or dry etching, but not limited to this process.

[0134] In some embodiments, a second sacrificial layer (not shown) is further formed between the first surrounding structure 101 and the second surrounding structure 201.

[0135] As an example, a second sacrificial layer may be formed on the upper surface of the first surrounding structure 101 using, but not limited to, molecular beam epitaxy; the second sacrificial layer may include, but is not limited to, a germanium-silicon layer.

[0136] In step S14, please refer to Figure 16 A gate structure 30 is formed within the gate aperture 120.

[0137] As an example, step S14 may include steps S141 to S142.

[0138] S141: Please continue reading Figure 16 An annular gate oxide layer 302 is formed within the gate aperture 120. For example, the annular gate oxide layer 302 can be formed within the gate aperture 120 using, but not limited to, atomic layer deposition (ALD) technology. Specifically, the annular gate oxide layer 302 can include a single-layer structure or a stacked structure. The annular gate oxide layer 302 can include, but is not limited to, oxide layers, such as silicon dioxide, hafnium oxide, or a stack of the above layers. Specifically, in this embodiment, the annular gate oxide layer 302 is a hafnium oxide layer and a silicon dioxide layer stacked sequentially from the gate conductive layer 301.

[0139] S142: Please continue reading Figure 16A gate conductive material layer (not shown) is formed within the annular gate oxide layer 302, and the annular gate oxide layer 302 surrounds the outer surface of the gate conductive layer 301. For example, the gate conductive material layer can be formed within the annular gate oxide layer 302 using, but not limited to, molecular beam epitaxy, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. The gate conductive material layer may include, but is not limited to, a conductive layer, such as at least one of a polysilicon gate conductive layer or a metal gate conductive layer.

[0140] S143: Please continue reading Figure 16 A patterned mask layer (not shown) is formed on the upper surface of the gate conductive material layer; for example, a patterned mask layer may be formed on the upper surface of the gate conductive material layer 3011 using, but not limited to, spin coating, molecular beam epitaxy, physical vapor deposition, chemical vapor deposition or atomic layer deposition processes; the patterned mask layer may include, but is not limited to, a photoresist layer or a hard mask layer (e.g., a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer or a spin-coated carbon layer, etc.).

[0141] S144: Please continue reading Figure 16 The gate conductive material layer is etched based on a patterned mask layer to form the gate conductive layer 301; for example, the gate conductive material layer can be etched using, but is not limited to, wet etching or dry etching processes to form the gate conductive layer 301.

[0142] S145: Remove the patterned mask layer; for example, the patterned mask layer may be removed using, but is not limited to, ashing, grinding or etching processes.

[0143] In step S15, please continue reading. Figure 16 Remove the first sacrificial layer and the second sacrificial layer to form a first sacrificial gap (not shown) and a second sacrificial gap (not shown); form a bottom dielectric layer 50 in the first sacrificial gap and form an annular dielectric layer 60 in the second sacrificial gap.

[0144] As an example, the first sacrificial layer and the second sacrificial layer can be removed using, but not limited to, wet etching or dry etching processes to form the first sacrificial gap and the second sacrificial gap; the bottom dielectric layer 50 can be formed within the first sacrificial gap and the annular dielectric layer 60 can be formed within the second sacrificial gap using, but not limited to, molecular beam epitaxy, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes; the bottom dielectric layer 50 can include, but is not limited to, an insulating layer, for example, a silicon nitride layer, a silicon carbonitride layer, a silicon carbon oxide layer, or a fluorosilicate glass layer, etc.; the bottom dielectric layer 50 can also be a stacked structure of the above layers; the annular dielectric layer 60 can include, but is not limited to, an insulating layer, for example, a silicon nitride layer, a silicon carbonitride layer, a silicon carbon oxide layer, or a fluorosilicate glass layer, etc.; the bottom dielectric layer 50 can also be a stacked structure of the above layers.

[0145] In some embodiments, after step S15, please refer to Figure 17 The fabrication method of the complementary ring channel MOSFET may further include: forming a first ring back gate structure 70 and a second ring back gate structure 80; the first ring back gate structure 70 surrounds the outer surface of the first channel layer 1011; and the second ring back gate structure 80 surrounds the outer surface of the second channel layer 2011.

[0146] As an example, the first annular back gate structure 70 may include a first annular back gate dielectric layer 701 and a first annular back gate electrode 702; the first annular back gate dielectric layer 701 may include, but is not limited to, an oxide layer, a low dielectric constant (low K) material dielectric layer and a high dielectric constant (high K) material, such as a silicon dioxide layer, a hafnium monoxide layer, a silicon fluoride layer, a silicon nitride layer, or a superposition of the above layers; the first annular back gate electrode 702 may include, but is not limited to, a conductive layer, such as at least one of a polysilicon gate conductive layer or a metal gate conductive layer; the first annular back gate structure 70 can adjust the threshold voltage of the first MOSFET to optimize the speed and power consumption of the first MOSFET according to actual needs.

[0147] As an example, the second annular back gate structure 80 may include a second annular back gate dielectric layer 801 and a second annular back gate electrode 802; the second annular back gate dielectric layer 801 may include, but is not limited to, a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), or any combination thereof, such as a silicon dioxide layer, a hafnium monoxide layer, a silicon fluoride layer, a silicon nitride layer, or a superposition of the above layers; the first annular back gate electrode 802 may include, but is not limited to, a conductive layer, such as at least one of a polysilicon gate conductive layer or a metal gate conductive layer. The second annular back gate structure 80 can adjust the threshold voltage of the second MOSFET, optimizing the speed and power consumption of the second MOSFET according to actual needs.

[0148] For example, the material of the metal gate conductive layer is selected from indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloys, titanium, titanium nitride, tantalum nitride, tantalum nitride, and combinations thereof.

[0149] This disclosure also provides an electronic device including any of the complementary ring-channel MOS transistors described in the above embodiments.

[0150] In some embodiments, an electronic device is provided, including the semiconductor device described in any of the embodiments of this disclosure.

[0151] In some embodiments, an electronic device is provided, including a complementary ring channel MOSFET fabricated by the method described in any embodiment of this disclosure.

[0152] For example, electronic devices can be storage devices, mobile phones, computers, tablets, televisions, artificial intelligence devices, etc.

[0153] The electronic device disclosed herein, by having a first surrounding structure and a second surrounding structure encircling the outer surface of the gate structure, greatly improves circuit density and significantly saves chip area in subsequent processes. Simultaneously, the fabrication process is simple, production costs are low, and there is no floating body effect, facilitating mass production. Furthermore, the first channel layer of the first conductivity type in the first surrounding structure and the second channel layer of the second conductivity type in the second surrounding structure are electrically complementary, effectively improving the performance of the complementary ring-channel MOSFET, thereby enhancing the performance of the electronic device.

[0154] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A complementary toroidal MOSFET, characterized in that, include: The first MOSFET and the second MOSFET; where... The first MOS transistor includes a gate structure and a first surrounding structure. The first surrounding structure includes a first channel layer of a first conductivity type, a first source layer of a second conductivity type, and a first drain layer of a second conductivity type. The first source layer, the first channel layer, and the first drain layer all surround the outer surface of the gate structure and are arranged adjacent to each other in sequence along the extension direction of the gate structure. The second MOS transistor includes: the gate structure and the second surrounding structure. The second surrounding structure includes a second channel layer of a second conductivity type, a second source layer of a first conductivity type, and a second drain layer of a first conductivity type. The second drain layer, the second source layer, and the second channel layer all surround the outer surface of the gate structure and are sequentially adjacent to each other along the extension direction of the gate structure, and are arranged at intervals from the first surrounding structure.

2. The complementary ring-channel MOSFET according to claim 1, characterized in that, The complementary ring-channel MOSFET also includes: Substrate; The bottom dielectric layer is located on the upper surface of the substrate; the first MOS transistor and the second MOS transistor are both located above the bottom dielectric layer.

3. The complementary ring-channel MOSFET according to claim 2, characterized in that, The first conductivity type includes N-type, and the second conductivity type includes P-type; or The first conductivity type includes P-type, and the second conductivity type includes N-type.

4. The complementary ring-channel MOSFET according to claim 1, characterized in that, The complementary ring-channel MOSFET also includes: An annular dielectric layer is located between the first surrounding structure and the second surrounding structure, and surrounds the outer surface of the gate structure.

5. The complementary ring-channel MOS transistor according to claim 1, characterized in that, Complementary ring channel MOSFETs also include: A first annular back gate structure surrounds the outer surface of the first channel layer. The first annular back gate structure includes: a first annular back gate dielectric layer surrounding the outer surface of the first channel layer; and a first annular back gate electrode surrounding the outer surface of the first annular back gate dielectric layer. A second annular back gate structure surrounds the outer surface of the second channel layer. The second annular back gate structure includes: a second annular back gate dielectric layer surrounding the outer surface of the second channel layer; and a second annular back gate electrode surrounding the outer surface of the second annular back gate dielectric layer.

6. A semiconductor device, characterized in that, include: The semiconductor device further comprises a first interconnect pillar, a first interconnect layer, a second interconnect layer, a third interconnect layer, a second interconnect pillar, and a fourth interconnect layer, as described in any one of claims 1 to 5; wherein, The first connecting post is connected to the gate structure; The first drain layer of the first MOS transistor and the second drain layer of the second MOS transistor are connected via the second interconnect layer, the third interconnect layer and the second connecting post; The first source layer of the first MOSFET is connected to the power supply voltage via the first interconnect layer; The second source layer of the second MOS transistor is grounded via the fourth interconnect layer.

7. A semiconductor device, characterized in that, include: The first MOSFET structure and the second MOSFET structure, both comprising a complementary ring-channel MOSFET as described in any one of claims 1 to 5; the semiconductor device further comprises: a third interconnect pillar, a fourth interconnect pillar, a fifth interconnect layer, a sixth interconnect layer, a seventh interconnect layer, an eighth interconnect layer, a ninth interconnect layer, and a fifth interconnect pillar; wherein, The third connecting post is connected to the gate structure of the first MOS transistor structure; The fourth connecting post is connected to the gate structure of the second MOS transistor structure; The first source layer in the first MOS transistor structure and the first source layer in the second MOS transistor structure are connected to the power supply voltage via the fifth interconnect layer; After the first drain layer in the first MOS transistor structure is connected to the first drain layer in the second MOS transistor structure via the sixth interconnect layer, both drain layers are connected to the second source layer in the second MOS transistor structure via the fifth connecting post and the ninth interconnect layer. The second drain layer in the first MOS transistor structure is connected to the second drain layer in the second MOS transistor structure via the seventh interconnect layer; The second source layer in the first MOS transistor structure is grounded via the eighth interconnect layer.

8. A semiconductor device, characterized in that, include: The first MOSFET structure and the second MOSFET structure, both comprising a complementary ring-channel MOSFET as described in any one of claims 1 to 5; the semiconductor device further comprising: a sixth interconnect pillar, a seventh interconnect pillar, a tenth interconnect layer, an eleventh interconnect layer, a twelfth interconnect layer, a thirteenth interconnect layer, a fourteenth interconnect layer, and an eighth interconnect pillar; wherein, The sixth connecting post is connected to the gate structure of the first MOS structure; The seventh connecting post is connected to the gate structure of the second MOS structure; The first source layer in the first MOS transistor structure is connected to the power supply voltage via the tenth interconnect layer; The first drain layer in the first MOS transistor structure is connected to the first drain layer in the second MOS transistor structure via the eleventh interconnect layer; After the second drain layer in the first MOS transistor structure is connected to the second drain layer in the second MOS transistor structure via the twelfth interconnect layer, both are connected to the first source layer in the second MOS transistor structure via the eighth connecting pillar and the fourteenth interconnect layer; The second source layer in the first MOS transistor structure is connected to the second source layer in the second MOS transistor structure via the thirteenth interconnect layer, and both are grounded.

9. A method for fabricating a complementary ring-channel MOSFET, characterized in that, include: Provide substrate; A first surrounding structure and a second surrounding structure are formed on the substrate at intervals from top to bottom; gate holes that communicate with each other are formed in both the first surrounding structure and the second surrounding structure. A gate structure is formed within the gate hole.

10. The method for fabricating a complementary ring-channel MOS transistor according to claim 9, characterized in that, Before forming the first and second surrounding structures arranged at intervals from top to bottom on the substrate, the method further includes: forming a first sacrificial layer on the upper surface of the substrate; A second sacrificial layer is also formed between the first surrounding structure and the second surrounding structure; After forming the gate structure in the gate hole, the method further includes: removing the first sacrificial layer and the second sacrificial layer to form a first sacrificial gap and a second sacrificial gap; forming a bottom dielectric layer in the first sacrificial gap and forming an annular dielectric layer in the second sacrificial gap.

11. The method for fabricating a complementary ring-channel MOS transistor according to claim 9, characterized in that, After forming the gate structure within the gate aperture, the method further includes: A first annular back gate structure and a second annular back gate structure are formed; the first annular back gate structure surrounds the outer surface of the first channel layer; the second annular back gate structure surrounds the outer surface of the second channel layer.

12. An electronic device, characterized in that, Includes any one of the following features: The complementary ring-channel MOS transistor according to any one of claims 1-5; The semiconductor device according to claim 6; The semiconductor device according to claim 7; The semiconductor device according to claim 8; A complementary ring channel MOSFET fabricated using the method described in any one of claims 9-11.

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