Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a bottom semiconductor layer; the buried dielectric layer is located on the bottom semiconductor layer; the transistor structure is located on the buried dielectric layer; the insulation isolation structure is located on the side face of the transistor structure, and the insulation isolation structure extends downwards to the buried dielectric layer; the side surface of the conductive structure is surrounded by the insulating isolation structure, the bottom of the conductive structure penetrates through the buried dielectric layer so as to be electrically connected with the bottom semiconductor layer, and the conductive structure extends upwards to lead out the potential of the bottom semiconductor layer. The electric potential of the bottom semiconductor layer is led out to the upper surface of the semiconductor device through the conductive structure, so that the influence of the floating body effect is eliminated. And the conductive structure is surrounded by the insulating isolation structure arranged on the side surface of the transistor structure, so that the influence of the conductive structure on the isolation effect is reduced, and the withstand voltage of the device is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device, and also to a method for manufacturing a semiconductor device. Background Technology

[0002] SOI (Silicon On Insulator) technology, due to its unique structure, has advantages such as good isolation performance, low leakage current, high speed, radiation resistance and low power consumption. It fully leverages the potential of silicon integrated circuit technology and is gradually becoming the mainstream technology and application for manufacturing high-speed, low-power, highly integrated and highly reliable integrated circuits.

[0003] Power field-effect transistors mainly come in two types: vertical double-diffused MOSFETs (VDMOS) and lateral double-diffused MOSFETs (LDMOS).

[0004] Research has revealed that SOI LDMOS transistors exhibit a floating effect relative to the underlying silicon layer, which affects the electrical performance of SOI LDMOS. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor device and its manufacturing method that can eliminate the buoyancy effect.

[0006] A semiconductor device includes: a bottom semiconductor layer; a buried dielectric layer located on the bottom semiconductor layer; a transistor structure located on the buried dielectric layer; an insulating isolation structure located on the side of the transistor structure, the insulating isolation structure extending downward to the buried dielectric layer; and a conductive structure whose side is surrounded by the insulating isolation structure, and whose bottom extends through the buried dielectric layer to be electrically connected to the bottom semiconductor layer, the conductive structure extending upward to draw out the potential of the bottom semiconductor layer.

[0007] The aforementioned semiconductor device uses a conductive structure to bring the potential of the bottom semiconductor layer to the upper surface of the semiconductor device, thereby eliminating the effects of the floating body effect. Furthermore, an insulating isolation structure located on the side of the transistor structure surrounds the conductive structure, reducing the impact of the conductive structure on the isolation effect and ensuring the device's withstand voltage (reverse breakdown voltage).

[0008] In one embodiment, the semiconductor device is an SOI device.

[0009] In one embodiment, the semiconductor device further includes a bottom lead region located in the bottom semiconductor layer, the conductive structure being connected to the bottom semiconductor layer through the bottom lead region, the bottom lead region having the same conductivity type as the bottom semiconductor layer, and the doping concentration of the bottom lead region being greater than the doping concentration of the bottom semiconductor layer.

[0010] In one embodiment, the semiconductor device is an SOI LDMOSFET, the buried dielectric layer is a buried oxide layer, the bottom semiconductor layer is a bottom silicon layer, and the transistor structure includes: a source region having a first conductivity type; a drain region having a first conductivity type; a drift region having a first conductivity type and at least partially located between the source region and the drain region; and a gate disposed above the region between the source region and the drain region.

[0011] In one embodiment, the transistor structure further includes: a first conductivity type well region connected to the drift region, wherein the drain region is located in the first conductivity type well region; a second conductivity type well region connected to the drift region, wherein the source region is located in the second conductivity type well region; a field oxide layer located on the drift region, wherein the gate extends from the edge of the source region to the field oxide layer.

[0012] In one embodiment, the bottom of the second conductivity type well region extends to the surface of the buried dielectric layer.

[0013] In one embodiment, the semiconductor device further includes an interlayer dielectric layer on the transistor structure and a bottom silicon lead-out on the interlayer dielectric layer. The semiconductor device has a bottom silicon contact hole that penetrates the interlayer dielectric layer and extends from the bottom to the top of the conductive structure. The bottom silicon contact hole is filled with a conductive material to electrically connect the conductive structure to the bottom silicon lead-out.

[0014] In one embodiment, the semiconductor device is an N-channel semiconductor device, in which the bottom semiconductor layer is connected to a lower potential than the drain region through the conductive structure during operation; or the semiconductor device is a P-channel semiconductor device, in which the bottom semiconductor layer is connected to a higher potential than the drain region through the conductive structure during operation.

[0015] A method for manufacturing a semiconductor device includes: obtaining a wafer having a bottom semiconductor layer, a buried dielectric layer on the bottom semiconductor layer, and a transistor structure on the buried dielectric layer; a portion of the transistor structure being formed in a top semiconductor layer on the buried dielectric layer; etching to form a deep trench penetrating the top semiconductor layer and the buried dielectric layer, and forming an insulating isolation structure on the sidewalls of the deep trench; the bottom of the deep trench reaching the bottom semiconductor layer; and filling the deep trench with a conductive material to form a conductive structure that draws out the potential of the bottom semiconductor layer.

[0016] The aforementioned semiconductor device manufacturing method utilizes a conductive structure to extract the potential of the bottom semiconductor layer, thereby eliminating the effects of the floating body effect. Furthermore, by surrounding the conductive structure with an insulating isolation structure located on the side of the transistor structure, the influence of the conductive structure on the isolation effect is reduced, ensuring the device's withstand voltage (reverse breakdown voltage).

[0017] In one embodiment, the wafer further forms an interlayer dielectric layer on the top semiconductor layer. The step of etching to form a deep trench penetrating the top semiconductor layer and the buried dielectric layer, and forming an insulating isolation structure on the sidewall of the deep trench, includes: forming a hard mask on the interlayer dielectric layer; photolithographically etching the hard mask and the interlayer dielectric layer to form a bottom silicon contact hole; using the hard mask as an etch stop layer, etching the top semiconductor layer downwards along the bottom silicon contact hole; forming an insulating layer on the sidewall of the deep trench as an insulating isolation structure; using the hard mask as an etch stop layer, etching the buried dielectric layer downwards along the deep trench to etch through the buried dielectric layer.

[0018] In one embodiment, the step of forming a hard mask on the interlayer dielectric layer includes forming a nitrided layer and an oxide layer on the nitrided layer.

[0019] In one embodiment, prior to the step of filling the deep trench with conductive material, the method further includes the step of implanting ions of the same conductivity type as the bottom semiconductor layer at the bottom of the deep trench to form a bottom lead-out region; the doping concentration of the bottom lead-out region is greater than the doping concentration of the bottom semiconductor layer. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a schematic diagram of the structure of a semiconductor device in one embodiment of this application.

[0022] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the semiconductor device structure after step S210 is completed in one embodiment of this application.

[0024] Figure 4 This is a schematic diagram of the semiconductor device structure after step S223 is completed in one embodiment of this application.

[0025] Figure 5 This is a schematic diagram of the semiconductor device structure after step S225 is completed in one embodiment of this application.

[0026] Figure 6 This is a schematic diagram of the semiconductor device structure after step S229 is completed in one embodiment of this application.

[0027] Figure 7 This is a schematic diagram of the semiconductor device structure after step S230 is completed in one embodiment of this application.

[0028] Figure 8 This is a flowchart of a sub-step of step S220 in one embodiment of this application.

[0029] Figure 9 This is a flowchart of a semiconductor device manufacturing method following step S230 in one embodiment of this application. Detailed Implementation

[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0036] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0037] Research has revealed that in SOI LDMOS, the LDMOS transistor formed on the buried oxide layer constitutes a capacitor relative to the underlying silicon layer. Charge accumulates on this capacitor, resulting in a floating body effect. Taking N-channel LDMOS as an example, the specific mechanism is as follows: the strong electric field at the drain accelerates channel electrons. After gaining sufficient energy, these accelerated electrons undergo collisional ionization, generating new electron-hole pairs. These new electron-hole pairs separate under the influence of the electric field; electrons are collected at the drain, while holes accumulate in the buried oxide layer near the source. As the number of accumulated holes increases, the local body potential also rises, causing a decrease in the gate turn-on voltage at that location, resulting in a sudden increase in the drain output current. Furthermore, the increase in body potential lowers the source-drain breakdown voltage of the LDMOS.

[0038] This application proposes a semiconductor device capable of drawing the potential of a substrate to the device surface, thereby eliminating the floating body effect. Figure 1This is a schematic diagram of a semiconductor device structure according to an embodiment of this application, including a bottom semiconductor layer 101, a buried dielectric layer 102, a transistor structure, an insulating isolation structure 109, and a conductive structure 110. The buried dielectric layer 102 is located on the bottom semiconductor layer 101. The transistor structure is located on the buried dielectric layer 102. The insulating isolation structure 109 is located on the side of the transistor structure, i.e., on the outside of the transistor structure, providing electrical isolation to the transistor structure. The insulating isolation structure 109 extends downwards to the buried dielectric layer 102. The conductive structure 110 is surrounded on its side by the insulating isolation structure 109. The bottom of the conductive structure 110 extends downwards through the buried dielectric layer 102 to electrically connect with the bottom semiconductor layer 101. The conductive structure 110 extends upwards to bring the potential of the bottom semiconductor layer 101 to the upper surface of the device.

[0039] The aforementioned semiconductor device uses a conductive structure 110 to bring the potential of the bottom semiconductor layer 101 to the upper surface of the semiconductor device, thereby eliminating the effect of the floating body effect. Furthermore, the conductive structure 110 is surrounded by an insulating isolation structure 109 located on the side of the transistor structure, reducing the impact of the conductive structure 110 on the isolation effect and ensuring the device's withstand voltage (reverse breakdown voltage).

[0040] In one embodiment of this application, the semiconductor device is an SOI LDMOSFET, the buried dielectric layer 102 is a buried oxide layer, the bottom semiconductor layer 101 is a bottom silicon layer, and the transistor structure includes a source region 117, a drain region 106, and a drift region 103 formed in the top silicon layer on the buried dielectric layer 102. The transistor structure also includes a gate 118 disposed above the region between the source region 117 and the drain region 106. The source region 117, the drain region 106, and the drift region 103 have a first conductivity type, and at least a portion of the drift region 103 is located between the source region 117 and the drain region 106. In one embodiment of this application, the gate 118 is made of polysilicon; in other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 118. In one embodiment of this application, the doping concentration of the source region 117 and the drain region 106 is greater than the doping concentration of the drift region 103.

[0041] exist Figure 1In the illustrated embodiment, the semiconductor device is an N-channel SOI LDMOS, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the semiconductor device can also be a P-channel device, with P-type as the first conductivity type and N-type as the second conductivity type. For an N-channel SOI LDMOS, during operation, the bottom semiconductor layer 101 is connected to a lower potential than the drain region 106 via the conductive structure 110. When the drain region 106 is connected to a high level, the bottom semiconductor layer 101 is connected to a low level. For a P-channel SOI LDMOS, during operation, the bottom semiconductor layer 101 is connected to a higher potential than the drain region 106 via the conductive structure 110. When the drain region 106 is connected to a low level, the bottom semiconductor layer 101 is connected to a high level.

[0042] exist Figure 1 In the illustrated embodiment, the transistor structure further includes a first conductivity type well region 105, a second conductivity type well region 104, and a field oxide layer 114. The first conductivity type well region 105 is connected to the drift region 103, and the drain region 106 is located in the first conductivity type well region 105. The second conductivity type well region 104 is connected to the drift region 103, and the source region 117 is located in the second conductivity type well region 104. The field oxide layer 114 is located on the drift region 103, and the gate 118 extends from the edge of the source region 117 to the field oxide layer 114. In one embodiment of this application, the gate 118 extends above the source region 117 or to the edge of the source region 117, that is, it overlaps with or is tangential to the edge of the source region 117, to ensure that the surface of the second conductivity type well region 104 between the source region 117 and the drift region 103 is inverted, thus ensuring the continuity of the conductive channel. The second conductivity type well region 104 is the channel formation region of the device, and its concentration will also affect the depletion of the drift region and the on-state voltage. The first conductivity type well region 105 serves as a drain drift region buffer layer to improve the on-state breakdown voltage of the device during forward operation. In one embodiment of this application, the doping concentration of the first conductivity type well region 105 is greater than the doping concentration of the drift region 103, and the doping concentration of the drain region 106 is greater than the doping concentration of the first conductivity type well region 105.

[0043] exist Figure 1 In the illustrated embodiment, the transistor structure further includes a body lead-out region 116 located in the second conductivity type well region 104. The body lead-out region 116 has a second conductivity type. In one embodiment of this application, the doping concentration of the body lead-out region 116 is greater than the doping concentration of the second conductivity type well region 104.

[0044] exist Figure 1 In the embodiment shown, the bottom of the second conductivity type well region 104 extends to the upper surface of the buried dielectric layer 102.

[0045] exist Figure 1In the illustrated embodiment, the semiconductor device further includes a bottom lead-out region 111 located in the bottom semiconductor layer 101. The conductive structure 110 is connected to the bottom semiconductor layer 101 through the bottom lead-out region 111. The bottom lead-out region 111 has the same conductivity type as the bottom semiconductor layer 101, and the doping concentration of the bottom lead-out region 111 is greater than that of the bottom semiconductor layer 101. The bottom lead-out region 111 is used to reduce the contact resistance between the conductive structure 110 and the bottom semiconductor layer 101.

[0046] In one embodiment of this application, the conductive structure 110 is a tungsten plug.

[0047] exist Figure 1 In the illustrated embodiment, the semiconductor device further includes an interlayer dielectric layer 115 located on the top silicon layer and a metal layer located on the interlayer dielectric layer 115. The metal layer includes a bottom silicon lead-out 112, a source lead-out 107, a drain lead-out 113, and a gate lead-out 108. The semiconductor device is provided with contact holes penetrating the interlayer dielectric layer 115, including a bottom silicon contact hole extending to the top of the conductive structure 110, a source contact hole extending to the source region 117, a body contact hole extending to the body lead-out region 116, a gate contact hole extending to the gate 118, and a drain contact hole extending to the drain region 106. Each contact hole is filled with a conductive material to electrically connect the bottom structure to the corresponding lead-out region; for example, the bottom silicon contact hole electrically connects the conductive structure to the bottom silicon lead-out 112. In one embodiment of this application, each contact hole is filled with a tungsten plug.

[0048] In one embodiment of this application, potential lead-out structures of the bottom semiconductor layer are formed on both sides of the SOI LDMOS, that is, conductive structures 110 and insulating isolation structures 109 are formed on both sides of the SOI LDMOS. Figure 1 In the illustrated embodiment, on one side of the SOI LDMOS, the deep trench containing the conductive structure 110 and the insulating isolation structure 109 extends downward into the second conductivity type well region 104; on the other side of the SOI LDMOS, the deep trench containing the conductive structure 110 and the insulating isolation structure 109 extends downward into the first conductivity type well region 105. The source region 117, drain region 106, body lead-out region 116, and other structures of the SOI LDMOS are located between the conductive structures 110 on both sides.

[0049] exist Figure 1 In the embodiment shown, the bottom semiconductor layer 101 is a P-type substrate, the bottom lead-out region 111 is a P-type bottom lead-out region, the first conductivity type well region 105 is an N-well, the second conductivity type well region 104 is a P-well, the drift region 103 is an N-type drift region, the source region 117 is an N+ region, the drain region 106 is an N+ region, and the body lead-out region 116 is a P+ region.

[0050] This application provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device described in any of the foregoing embodiments. Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application, including the following steps:

[0051] S210, Obtain a wafer with a bottom semiconductor layer, a buried dielectric layer and a transistor structure formed.

[0052] A portion of the transistor structure is formed in a top semiconductor layer on top of the buried dielectric layer. In one embodiment of this application, the wafer also has an interlayer dielectric layer 115 formed on top of the top semiconductor layer. Figure 3 In the illustrated embodiment, transistor structures and interlayer dielectric layers 115 can be fabricated on an SOI substrate (including a bottom semiconductor layer 101, a buried dielectric layer 102 on the bottom semiconductor layer 101, and a top semiconductor layer on the buried dielectric layer 102) in accordance with methods known in the art.

[0053] In one embodiment of this application, the transistor structure includes a source region 117, a drain region 106, and a drift region 103 formed in a top semiconductor layer. The transistor structure also includes a gate 118 disposed above the region between the source region 117 and the drain region 106. The source region 117, the drain region 106, and the drift region 103 have a first conductivity type, and at least a portion of the drift region 103 is located between the source region 117 and the drain region 106. In one embodiment of this application, the gate 118 is made of polysilicon; in other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material for the gate 118. In one embodiment of this application, the doping concentration of the source region 117 and the drain region 106 is greater than the doping concentration of the drift region 103.

[0054] exist Figure 3 In the illustrated embodiment, the semiconductor device is an N-channel SOI LDMOS with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the semiconductor device may also be a P-channel device, with P-type as the first conductivity type and N-type as the second conductivity type.

[0055] exist Figure 3In the illustrated embodiment, the transistor structure further includes a first conductivity type well region 105, a second conductivity type well region 104, and a field oxide layer 114. The first conductivity type well region 105 is connected to the drift region 103, and the drain region 106 is located in the first conductivity type well region 105. The second conductivity type well region 104 is connected to the drift region 103, and the source region 117 is located in the second conductivity type well region 104. The field oxide layer 114 is located on the drift region 103, and the gate 118 extends from the edge of the source region 117 to the field oxide layer 114. In one embodiment of this application, the gate 118 extends above the source region 117 or to the edge of the source region 117, that is, it overlaps with or is tangential to the edge of the source region 117, to ensure that the surface of the second conductivity type well region 104 between the source region 117 and the drift region 103 is inverted, thus ensuring the continuity of the conductive channel. The second conductivity type well region 104 is the channel formation region of the device, and its concentration will also affect the depletion of the drift region and the on-state voltage. The first conductivity type well region 105 serves as a drain drift region buffer layer to improve the on-state breakdown voltage of the device during forward operation. In one embodiment of this application, the doping concentration of the first conductivity type well region 105 is greater than the doping concentration of the drift region 103, and the doping concentration of the drain region 106 is greater than the doping concentration of the first conductivity type well region 105.

[0056] exist Figure 3 In the illustrated embodiment, the transistor structure further includes a body lead-out region 116 located in the second conductivity type well region 104. The body lead-out region 116 has a second conductivity type. In one embodiment of this application, the doping concentration of the body lead-out region 116 is greater than the doping concentration of the second conductivity type well region 104.

[0057] exist Figure 3 In the embodiment shown, the bottom of the second conductivity type well region 104 extends to the upper surface of the buried dielectric layer 102.

[0058] S220, etching to form a deep trench, and forming an insulating isolation structure on the sidewall of the deep trench.

[0059] In one embodiment of this application, a deep trench 121 is etched to successively penetrate the interlayer dielectric layer 115, the top semiconductor layer, and the buried dielectric layer 102, and an insulating isolation structure 109 is formed on the sidewall of the deep trench 121. The bottom of the deep trench 121 reaches the bottom semiconductor layer 101. The structure after step S220 can be referred to Figure 6 .

[0060] S230, fill the deep trench with conductive material to form a conductive structure that draws out the potential of the bottom semiconductor layer.

[0061] In one embodiment of this application, first in deep groove 121 ( Figure 7Ti and / or TiN are formed on the inner surface of the wafer (not shown in the image), and then tungsten plugs are filled into the deep trench 121. Ti and / or TiN serve as a buffer layer between the tungsten plugs and the surrounding material of the deep trench 121. After filling with tungsten plugs, the wafer surface is planarized (CMP) to remove excess tungsten plugs and other structures, resulting in the conductive structure 110. The structure after step S230 can be referred to... Figure 7 .

[0062] The above-described semiconductor device manufacturing method uses a conductive structure 110 to bring the potential of the bottom semiconductor layer 101 to the upper surface of the semiconductor device, thereby eliminating the effect of the floating body effect. Furthermore, the conductive structure 110 is surrounded by an insulating isolation structure 109 located on the side of the transistor structure, reducing the impact of the conductive structure 110 on the isolation effect and ensuring the device's withstand voltage (reverse breakdown voltage).

[0063] See Figure 8 In one embodiment of this application, step S220 includes:

[0064] S221, forming a hard mask on the interlayer dielectric layer.

[0065] In one embodiment of this application, the hard mask includes a nitride layer 131 and an oxide layer 132 on the nitride layer 131. In one embodiment of this application, the nitride layer 131 may be made of silicon nitride, such as silicon nitride. In one embodiment of this application, the oxide layer 132 may be made of silicon oxide, such as silicon dioxide.

[0066] S223, photolithography and etching of the hard mask and the interlayer dielectric layer to form bottom silicon contact holes.

[0067] In one embodiment of this application, after coating photoresist on a hard mask, exposure is performed using a corresponding photomask. After development, the photoresist exposes an etching window. Through the etching window, the oxide layer 132, the nitride layer 131, and the interlayer dielectric layer 115 are etched sequentially downwards to complete the etching of the bottom silicon contact hole 121a. (Refer to...) Figure 4 .

[0068] S225 uses a hard mask as an etch barrier layer to etch the top semiconductor layer downwards along the bottom silicon contact hole.

[0069] In one embodiment of this application, using oxide layer 132 as an etching barrier layer, the top semiconductor layer is etched downwards along the bottom silicon contact hole 121a to etch a deep trench 121. Oxide layer 132 is consumed during the etching process in step S225, and the etching in step S225 stops at the buried dielectric layer 102. (Refer to...) Figure 5 In one embodiment of this application, bottom silicon contact holes 121a and deep trenches 121 are etched on both sides of the SOI LDMOS. Figure 5In the embodiment shown, the deep trenches 121 on both sides of the SOI LDMOS pass downward through the second conductivity type well region 104 and the first conductivity type well region 105, respectively.

[0070] S227, an insulating layer is formed on the sidewall of the deep trench as an insulating isolation structure.

[0071] In one embodiment of this application, an oxide layer can be formed on the sidewall of the deep trench 121 as an insulating layer by thermal oxidation or deposition processes to obtain an insulating isolation structure 109.

[0072] S229 uses a hard mask as an etching barrier layer to etch the buried medium layer downwards along the deep trench.

[0073] Reference Figure 6 In one embodiment of this application, the nitride layer 131 is used as an etching barrier layer, and the buried medium layer 102 is etched downward along the deep trench to etch through the buried medium layer 102.

[0074] In one embodiment of this application, after step S229 and before step S230, the method further includes implanting ions of the same conductivity type as the bottom semiconductor layer 101 at the bottom of the deep trench 121 to form a bottom lead-out region 111. The doping concentration of the bottom lead-out region 111 is greater than the doping concentration of the bottom semiconductor layer 101.

[0075] Reference Figure 9 In one embodiment of this application, the method further includes the following after step S230:

[0076] S241, patterned interlayer dielectric layer, forming each contact hole.

[0077] In one embodiment of this application, photoresist is coated on the interlayer dielectric layer 115, and the photoresist is exposed using a contact hole photomask. After development, etching windows for each contact hole are formed. The interlayer dielectric layer 115 is etched through the etching windows to form each contact hole. Specifically, it may include source contact holes extending to the source region 117, body contact holes extending to the body lead-out region 116, gate contact holes extending to the gate 118, and drain contact holes extending to the drain region 106, etc.

[0078] S243, a metal layer is formed on the interlayer dielectric layer.

[0079] A metal layer is formed on the interlayer dielectric layer 115 by sputtering or a process known in the art for forming metal films.

[0080] S245, a patterned metal layer, forms various lead-out structures.

[0081] In one embodiment of this application, photoresist is coated on a metal layer, and the photoresist is exposed using a metal layer photomask. After development, corresponding etching windows are formed. The metal layer is then etched through the etching windows to form various lead-out structures. Specifically, these may include a bottom silicon lead-out 112, a source lead-out 107, a drain lead-out 113, and a gate lead-out 108, etc. The device structure after step S245 can be found in [reference needed]. Figure 1 .

[0082] The semiconductor device manufacturing method of this application is based on the same inventive concept as the semiconductor device. For details not specifically described in the semiconductor device manufacturing method, please refer to the above introduction of the semiconductor device.

[0083] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0084] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Bottom semiconductor layer; A buried dielectric layer is located on the bottom semiconductor layer; A transistor structure is located on the buried dielectric layer; An insulating isolation structure is located on the side of the transistor structure, and the insulating isolation structure extends downward to the buried dielectric layer; The conductive structure is surrounded on the sides by the insulating isolation structure, and its bottom extends through the buried dielectric layer to be electrically connected to the bottom semiconductor layer. The conductive structure extends upward to bring out the potential of the bottom semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, It also includes a bottom lead-out region located in the bottom semiconductor layer, through which the conductive structure is connected to the bottom semiconductor layer. The bottom lead-out region has the same conductivity type as the bottom semiconductor layer, and the doping concentration of the bottom lead-out region is greater than that of the bottom semiconductor layer.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device is an SOI LDMOSFET, the buried dielectric layer is a buried oxide layer, the bottom semiconductor layer is a bottom silicon layer, and the transistor structure includes: The source region has the first type of conductivity. The drain region has the first conductivity type; The drift region has a first conductivity type and is at least partially located between the source region and the drain region; The gate is located above the region between the source region and the drain region.

4. The semiconductor device according to claim 3, characterized in that, The transistor structure also includes: A first conductivity type well region is connected to the drift region, and the drain region is located in the first conductivity type well region; A second conductivity type well region is connected to the drift region, and the source region is located in the second conductivity type well region; A field oxide layer is located on the drift region, and the gate extends from the edge of the source region to the field oxide layer.

5. The semiconductor device according to claim 4, characterized in that, The bottom of the second conductivity type well region extends to the surface of the buried dielectric layer; and / or The semiconductor device further includes an interlayer dielectric layer on the transistor structure and a bottom silicon lead-out on the interlayer dielectric layer. The semiconductor device has a bottom silicon contact hole that penetrates the interlayer dielectric layer and extends from the bottom to the top of the conductive structure. The bottom silicon contact hole is filled with a conductive material, thereby electrically connecting the conductive structure to the bottom silicon lead-out.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The semiconductor device is an N-channel semiconductor device, and during operation, the bottom semiconductor layer is connected to a potential lower than that of the drain region through the conductive structure; or The semiconductor device is a P-channel semiconductor device, and during operation, the bottom semiconductor layer is connected to a higher potential than the drain region through the conductive structure.

7. A method for manufacturing a semiconductor device, comprising: Obtain a wafer having a bottom semiconductor layer, a buried dielectric layer on the bottom semiconductor layer, and a transistor structure on the buried dielectric layer; A portion of the transistor structure is formed in the top semiconductor layer on the buried dielectric layer; A deep trench is formed by etching, penetrating the top semiconductor layer and the buried dielectric layer, and an insulating isolation structure is formed on the sidewall of the deep trench; the bottom of the deep trench reaches the bottom semiconductor layer; The deep trench is filled with conductive material to form a conductive structure that draws out the potential of the bottom semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The wafer also has an interlayer dielectric layer formed on the top semiconductor layer. The step of etching to form a deep trench penetrating the top semiconductor layer and the buried dielectric layer, and forming an insulating isolation structure on the sidewall of the deep trench includes: A hard mask is formed on the interlayer dielectric layer; Photolithography and etching are performed on the hard mask and the interlayer dielectric layer to form bottom silicon contact holes; Using the hard mask as an etching barrier layer, the top semiconductor layer is etched downwards along the bottom silicon contact hole; An insulating layer is formed on the sidewall of the deep trench as an insulating isolation structure; Using the hard mask as an etching barrier layer, the buried medium layer is etched downwards along the deep trench, thus penetrating the buried medium layer.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The step of forming a hard mask on the interlayer dielectric layer includes forming a nitrided layer and an oxide layer on the nitrided layer.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Before the step of filling the deep trench with conductive material, the method further includes the step of injecting ions of the same conductivity type as the bottom semiconductor layer at the bottom of the deep trench to form a bottom lead-out region; the doping concentration of the bottom lead-out region is greater than the doping concentration of the bottom semiconductor layer.

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