Discontinuous pulse signal frequency acquisition system and method

Abstract

The invention provides a discontinuous pulse signal frequency acquisition system and method, and the system comprises an attenuation unit, a filtering unit, an impedance matching unit, a first comparator, a second comparator and a main control unit, and the attenuation unit is used for reducing the amplitude value of an input pulse signal; the filtering unit is used for filtering the signal after the amplitude value is reduced; the main control unit is connected with the first comparator and the second comparator. According to the invention, the discontinuous pulse signal is attenuated and subjected to filtering impedance matching and then is input into the first comparator and the second comparator at the same time, the main control module triggers the first comparator to count when detecting the rising edge output by the second comparator, and the first comparator calculates the period of two continuous square waves, so that the frequency of the discontinuous pulse signal is obtained; effective and rapid acquisition of discontinuous pulse signal frequency is realized.

Description

Technical Field

[0001] This invention relates to the field of discontinuous pulse signal frequency acquisition technology, and specifically to a discontinuous pulse signal frequency acquisition system and method. Background Technology

[0002] Discontinuous pulse signals refer to pulse signals that are not continuous and are discrete in state. The signal has clear intervals between "present" and "absent" states, and is not a continuous fluctuation (e.g., ...). Figure 1 (As shown). Discontinuous pulse signals are frequently used in some detection fields. Once the discontinuous signal becomes continuous, it can easily burn out cascaded components. Generally, cascaded components are high-power, high-value components; burnout results in severe losses and the system will be unable to function. Real-time monitoring of discontinuous pulse signals is crucial. If malfunction occurs, control strategies can be implemented to protect cascaded components, making this monitoring particularly important. Discontinuous pulse signals are susceptible to various interferences, making frequency identification difficult. Conventional methods require measurement with a standard oscilloscope. However, standard oscilloscopes are bulky and require manual parameter adjustment, which does not meet the requirements of detection applications. Detection equipment generally requires small size, high intelligence, and fast testing speed. Therefore, a discontinuous pulse signal frequency acquisition method is proposed to achieve the purpose of acquisition and monitoring. Summary of the Invention

[0003] To address the above problems, this invention provides a discontinuous pulse signal frequency acquisition system and method, which can achieve rapid acquisition of discontinuous pulse signal frequencies.

[0004] Specifically, the present invention is implemented as follows: According to a first aspect, the present invention provides a discontinuous pulse signal frequency acquisition system, comprising: The attenuation unit is used to reduce the amplitude of the input pulse signal; The filtering unit is used to filter the signal after the amplitude value has been reduced; Impedance matching unit, connected to the filter unit; The first comparator is connected to the impedance matching unit; The second comparator is connected to the impedance matching unit; The main control unit is connected to the first comparator and the second comparator; The processed signal is simultaneously input to the first comparator and the second comparator. When the main control unit detects the rising edge of the output of the second comparator, it triggers the first comparator to count. The first comparator calculates the period of two consecutive square waves, thereby obtaining the frequency of the discontinuous pulse signal.

[0005] Furthermore, the attenuation unit includes: Resistors R2, R3, R4 and R9 are connected in series on the input path of the discontinuous pulse signal. One end of resistor R9 is connected between resistors R2 and R3, and the other end is grounded.

[0006] Furthermore, the filtering unit includes: Input coupling capacitor C1, capacitor C3, capacitor C5, output coupling capacitor C11, and operational amplifier U1; The signal is input to operational amplifier U1 after passing through resistors R3 and R4; One end of the input coupling capacitor C1 is connected to the power input terminal of the operational amplifier U1, and the other end is grounded; One end of capacitor C3 is connected to the connection node of resistors R3 and R4, and the other end is connected to operational amplifier U1. One end of capacitor C5 is connected between resistor R4 and operational amplifier U1, and the other end is grounded; One end of the output coupling capacitor C11 is connected to the power output terminal of the operational amplifier U1, and the other end is grounded.

[0007] Furthermore, the impedance matching unit includes: A first impedance matching circuit and a second impedance matching circuit are connected in parallel, with the first impedance matching circuit connected to a first comparator and the second impedance matching circuit connected to a second comparator.

[0008] Furthermore, the first impedance matching circuit includes: Operational amplifier U2, resistors R1, R5, R6, R7, R8, input coupling capacitors C2, C6, and C7; One end of resistor R5 is connected to operational amplifier U2, and the other end is grounded; One end of resistor R1 is connected between resistor R5 and operational amplifier U2, and the other end is connected to the power output terminal of operational amplifier U2. One end of the resistor R6 is connected to the filter unit, and the other end is connected to the input terminal of the operational amplifier U2; One end of the input coupling capacitor C2 is connected to the power input terminal of the operational amplifier U2, and the other end is grounded; One end of the capacitor C7 is connected between the resistor R6 and the operational amplifier U2, and the other end is grounded; The resistors R7 and R8 are connected to the output of the operational amplifier U2. One end of the resistor R7 is connected to the output of the operational amplifier U2, and the other end is connected to the resistor R8. The other end of the resistor R8 is grounded. One end of capacitor C6 is connected to resistor R7, and the other end is grounded. Resistor R8 is located between resistor R7 and capacitor C6.

[0009] Furthermore, the second impedance matching circuit includes: Operational amplifier U40, resistors R274, R284, R285, R286, R287, R288, input coupling capacitors C278, C276, C277, and C279; One end of the resistor R286 is connected to the operational amplifier U40, and the other end is grounded; One end of the resistor R288 is connected between the resistor R5 and the operational amplifier U40, and the other end is connected to the power output terminal of the operational amplifier U40. One end of resistor R274 is connected to the filter unit, and the other end is connected in series with resistor R287 and then connected to the input terminal of operational amplifier U40. One end of the input coupling capacitor C278 is connected to the power input terminal of the operational amplifier U40, and the other end is grounded; One end of the capacitor C279 is connected between resistors R274 and R287, and the other end is grounded. One end of the capacitor C276 is connected between the resistor R287 and the operational amplifier U2, and the other end is grounded; The resistors R285 and R284 are connected to the output of the operational amplifier U40. One end of the resistor R285 is connected to the output of the operational amplifier U40, and the other end is connected to the resistor R284. The other end of the resistor R284 is grounded. One end of capacitor C277 is connected to resistor R285, and the other end is grounded. Resistor R284 is located between resistor R7 and capacitor C6.

[0010] Furthermore, the discontinuous pulse signal frequency acquisition system also includes: The communication unit, connected to the main control unit, is used to send the frequency of the discontinuous pulse signal calculated by the main control unit to other control systems for display.

[0011] According to a second aspect, the present invention also provides a method for acquiring the frequency of discontinuous pulse signals, comprising: Step 1: Acquire the input pulse signal; Step 2: The attenuation unit reduces the amplitude of the input pulse signal; Step 3: The filtering unit filters the signal after reducing the amplitude value to remove noise; Step 4: After passing through the impedance matching unit, the filtered signal is simultaneously input to the first comparator and the second comparator. After passing through the first comparator and the second comparator, the signal is a square wave signal. Step 5: When the main control unit detects the rising edge of the output of the second comparator, it triggers the first comparator to count. The first comparator calculates the period of two consecutive square waves, thereby obtaining the frequency of the discontinuous pulse signal.

[0012] Further, in step 5, the second comparator is connected to the MCU's external interrupt extiX, and the first comparator is connected to the MCU's timer / counter TIM_CHX. The MCU's external interrupt extiX and timer / counter TIM_CHX are set to rise-falling edge trigger. When extiX detects a rising edge, TIM_CHX is enabled to enable input capture. TIM_CHX captures the rising edge and then waits for the rising edge interrupt to arrive. When a rising edge interrupt is captured, the capture state is marked as a falling edge, and the current timer count value is T0. When a falling edge interrupt is captured, the capture state is marked as a rising edge, and the current timer count value is T1. Then, the high-level time of the pulse signal is calculated as Th = T1 - T0. When another rising edge trigger occurs, the capture state is marked as a falling edge, and the current timer count value is T2. Then, the high-level time of the pulse signal is calculated as Tl = T2 - T1. The total period of the effective signal in the pulse is Th + Tl = T, where 1 / T is the frequency of the effective signal in the pulse. The above capture operation is repeated until the falling edge of extiX is triggered, at which point the capture stops.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention processes discontinuous pulse signals and simultaneously inputs them to a first comparator and a second comparator. When the main control module detects the rising edge of the output of the second comparator, it triggers the first comparator to count. The first comparator calculates the period of two consecutive square waves, thereby obtaining the frequency of the discontinuous pulse signal, achieving effective and rapid acquisition of the frequency of the discontinuous pulse signal. Attached Figure Description

[0014] Figure 1 The waveform diagram is for a discontinuous pulse signal. Figure 2 This is a block diagram of the discontinuous pulse signal frequency acquisition system in Example 1; Figure 3 The circuit diagrams for the attenuation unit, filtering unit, and impedance matching unit in Example 1 are shown below. Figure 4 This is a schematic diagram of RS485 serial communication in Example 1; Figure 5 is a block diagram of the internal principle of the RS485 communication IC in Example 1; Figure 6 The output waveforms of the first comparator and the second comparator in Example 1 are shown. Detailed Implementation

[0015] The present invention will be further described in detail below through specific embodiments. Example

[0016] like Figure 2 As shown, this embodiment provides a discontinuous pulse signal frequency acquisition system, including: an attenuation unit, a filtering unit, an impedance matching unit, a first comparator, a second comparator, a main control unit, a communication unit, and a power management unit. The attenuation unit, filtering unit, and impedance matching unit together form a signal conditioning unit. The attenuation unit attenuates the amplitude of the discontinuous analog voltage signal to within the power supply voltage range, facilitating subsequent signal processing. The filtering unit filters the attenuated signal to remove noise. The impedance matching unit uses a follower operational amplifier; the output signal is converted into a discontinuous square wave signal after passing through the first and second comparators. The acquisition board uses a TI TLV3501 rail-to-rail high-speed comparator to convert the input analog signal into a digital signal. The frequency signal first undergoes second-order filtering, then comparison, and the output digital signal is sent to the main control MCU for timing and counting to achieve frequency acquisition.

[0017] Specifically, such as Figure 3 As shown, the attenuation unit includes: Resistors R2, R3, R4, and R9 are connected in series in the input path of the discontinuous pulse signal. One end of resistor R9 is connected between resistors R2 and R3, and the other end is grounded. The signal is input to operational amplifier U1 after passing through resistors R3 and R4. This attenuation unit attenuates the signal amplitude through the voltage division effect of resistors R2 and R9. Simultaneously, the resistor network formed by resistors R3 and R4 matches the input impedance of the signal source (the attenuated node) with that of operational amplifier U1, providing a suitable amplitude input signal for subsequent operational amplifiers U1.

[0018] The filtering unit includes: input coupling capacitor C1, capacitor C3, capacitor C5, output coupling capacitor C11, and operational amplifier U1 (THS4631). One end of the input coupling capacitor C1 is connected to the power input terminal (+15V) of operational amplifier U1, and the other end is grounded; one end of the output coupling capacitor C11 is connected to the power output terminal (-15V) of operational amplifier U1, and the other end is grounded. This filters out high-frequency interference on the power line, provides decoupling filtering for the power supply of operational amplifier U1, and ensures stable power supply to operational amplifier U1.

[0019] One end of capacitor C3 is connected to the connection node of resistors R3 and R4, and the other end is connected to operational amplifier U1; one end of capacitor C5 is connected between resistor R4 and operational amplifier U1, and the other end is grounded; capacitors C3 and C5 act as filter capacitors to filter out noise.

[0020] The impedance matching unit includes a first impedance matching circuit and a second impedance matching circuit, which are connected in parallel. The signal filtered by the filtering unit is simultaneously input to both the first and second impedance matching circuits from the output of operational amplifier U1. The first impedance matching circuit includes: operational amplifier U2 (TLV3501), resistors R1, R5, R6, R7, and R8, and input coupling capacitors C2, C6, and C7.

[0021] Resistor R5 is connected at one end to operational amplifier U2 and at the other end to ground. Resistor R1 is connected at one end between resistor R5 and operational amplifier U2 and at the other end to the power output terminal of operational amplifier U2. Resistors R5 and R1 form a threshold voltage divider circuit, which sets the inverted threshold voltage of the first comparator. Resistor R6 is connected at one end to the filter unit and at the other end to the input terminal of operational amplifier U2. Capacitor C7 is connected at one end between resistor R6 and operational amplifier U2 and at the other end to ground. Together, they suppress input noise, making the triggering of the first comparator more stable.

[0022] One end of the input coupling capacitor C2 is connected to the power input terminal (+5V) of the operational amplifier U2, and the other end is grounded to filter out power supply interference.

[0023] Resistors R7 and R8 are connected to the output of operational amplifier U2. One end of resistor R7 is connected to the output of operational amplifier U2, and the other end is connected to resistor R8. The other end of resistor R8 is grounded. One end of capacitor C6 is connected to resistor R7, and the other end is grounded. Resistor R8 is located between resistor R7 and capacitor C6. Impedance matching at the output is used to condition the digital signal output by the first comparator, which is then finally output to the first comparator.

[0024] Similarly, the second impedance matching circuit includes: operational amplifier U40 (TLV3501), resistors R274, R284, R285, R286, R287, R288, input coupling capacitors C278, C276, C277, and C279. One end of resistor R286 is connected to operational amplifier U40, and the other end is grounded; one end of resistor R288 is connected between resistor R5 and operational amplifier U40, and the other end is connected to the power output terminal of operational amplifier U40; one end of resistor R274 is connected to the filter unit, and the other end is connected in series with resistor R287 and then connected to the input terminal of operational amplifier U40; one end of input coupling capacitor C278 is connected to the power input terminal of operational amplifier U40, and the other end is grounded; one end of capacitor C279 is connected between resistor R274 and resistor R285. Between resistor R287, the other end is grounded; one end of capacitor C276 is connected between resistor R287 and operational amplifier U2, and the other end is grounded; resistors R285 and R284 are connected to the output of operational amplifier U40, one end of resistor R285 is connected to the output of operational amplifier U40, and the other end is connected to resistor R284, and the other end of resistor R284 is grounded; one end of capacitor C277 is connected to resistor R285, and the other end is grounded, and resistor R284 is located between resistor R7 and capacitor C6.

[0025] The main control unit uses a 1-piece Beijing GigaDevice GD32F407ZGT6 processor, whose main functions and performance parameters are as follows: a) Kernel (1) 32-bit high-performance ARM Cortex-M4 processor; (2) Clock: up to 168MHz; (3) Supports FPU (floating-point arithmetic) and DSP instructions.

[0026] b) I / O ports (1) GD32F407ZGT6: TQFP144 pins, 114 I / O ports; (2) Debugging support: serial cable and JTAG.

[0027] c) Memory (1) Memory capacity: 1024K FLASH, 192K SRAM.

[0028] d) Clock, reset, and power management (1) 2.6V~3.6V power supply and IO voltage; (2) Power-on reset, power-off reset and programmable voltage monitoring; (3) A powerful clock system; a) External high-speed crystal oscillator of 4~32MHz b) Internal 48MHz high-speed RC oscillator c) Internal phase-locked loop (PLL, frequency multiplier): Generally, the system clock is obtained by multiplying an external or internal high-speed clock using a PLL. d) An external low-speed 32.768K crystal oscillator, mainly used as the RTC clock source. e) Low power consumption (1) Three low-power modes: sleep, stop, and standby; (2) The RTC and backup registers can be powered by a battery.

[0029] f) ADC (1) Three 12-bit AD converters [up to 19 external test channels]; (2) The internal channel can be used for internal temperature measurement; (3) Built-in reference voltage.

[0030] g) DAC (1) Two 12-bit DAs.

[0031] h) Ethernet (1) Ethernet Media Access Controller (MAC) compliant with IEEE 802.3 standard; (2) 10M / 100Mbit / s rate with dedicated DMA controller and SRAM; (3) Supports hardware PTP (precision time protocol) protocol, which conforms to IEEE 1588.

[0032] i) DMA (1) 16 DMA channels with FIFO and burst support; (2) Supports peripherals: timers, ADCs, DACs, SDIO, I2S, SPI, I2C and USART.

[0033] j) Up to 17 timers (1) 10 general purpose timers (TM1 and TM4 are 32-bit); (2) Two basic timers; (3) Two advanced timers (TM0 and TM7); (4) One system timer; (5) Two watchdog timers; k) Up to 17 communication interfaces (1) Three I2C interfaces; (2) 6 serial ports; (3) Three SPI interfaces; (4) Two CAN2.0 ports; (5) Two USB OTG ports; (6) One SDIO; l) Operating temperature: -40℃ to +85℃.

[0034] The system clock is the primary clock for the MCU main control unit. A clock reference is input to the MCU, and then the clock is multiplied internally to reach the MCU's maximum operating frequency of 168MHz. In this embodiment, a 25MHz passive crystal oscillator and a 32.768kHz passive crystal oscillator are used.

[0035] The communication unit uses an RS485 communication unit to realize communication between the acquisition board and external devices. For example... Figure 4-5 As shown, the integrated board can realize one-channel isolated RS485 serial communication. The RS485 transceiver interface chip is the MAX3485ESA from MAXIM. The isolation optocoupler is the TLP2362 from TOSHIBA. The performance parameters of the RS485 interface chip MAX3485ESA are as follows: 3.3V power supply Compatible with +5V logic level Delay time 8ns 2nA standby current Built-in current limiting and overheat protection half-duplex 10Mbps transmission rate Operating temperature: -40~+85℃.

[0036] The main function of the power management unit is to supply power to the MCU, AD acquisition, signal conditioning, RMS-to-DC circuit, RS485 communication, and other units. Required power voltages include +15V, -15V, +5V, and +3.3V.

[0037] The +27VDC input from the connector is converted to +3.3V using a 1-piece TI LM63625-Q1 DC-DC power management chip to supply power to the MCU circuit. A 1-piece SUCW102415 power module converts the 27V to ±15V to supply power to the analog signal section circuit. The RS485 communication isolation power supply is provided by a 1-piece PDL02-24S33 module power supply. The isolation operational amplifier's power supply is provided by a 1-piece PDL02-24D12 module power supply.

[0038] When the signal is input from the left end of resistor R2, the right end of resistor R7 will output the original waveform, and the right end of resistor R285 will output the trigger signal, as shown in the figure. When the MCU receives the trigger signal from comparator 2, the MCU's timer counter will start the input capture frequency test.

[0039] The second comparator is connected to the MCU's external interrupt extiX, and the first comparator is connected to the MCU's timer / counter TIM_CHX. Both the external interrupt extiX and the timer / counter TIM_CHX are set to rise-edge and falling-edge triggering. When the external interrupt extiX detects a rising edge, the timer / counter TIM_CHX is enabled to capture input. The timer / counter TIM_CHX captures the rising edge and waits for a rising edge interrupt. When a rising edge interrupt is captured, the capture state is marked as a falling edge, and the current timer count is T0. When a falling edge interrupt is captured, the capture state is marked as a rising edge, and the current timer count is T1. Then, the high-level time of the pulse signal is calculated as Th = T1 - T0. When another rising edge trigger occurs, the capture state is marked as a falling edge, and the current timer count is T2. Then, the high-level time of the pulse signal is calculated as Tl = T2 - T1. The total period of the effective signal in the pulse is Th + Tl = T, where 1 / T is the frequency of the effective signal in the pulse. The above capture operation is repeated until the external interrupt extiX falling edge is triggered, at which point the capture stops.

[0040] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A non-continuous pulsed signal frequency acquisition system, characterized by, The application relates to a signal processing device for a non-continuous pulse signal, which comprises: a damping unit, a filter unit and an impedance matching unit connected in sequence; a first comparator connected with the impedance matching unit; a second comparator connected with the impedance matching unit; a master control unit connected with the first comparator and the second comparator; the processed signal is simultaneously input into the first comparator and the second comparator, the master control unit triggers the first comparator to start counting when detecting the rising edge output by the second comparator, and the first comparator calculates the period of two continuous square waves to obtain the frequency of the non-continuous pulse signal.

2. The noncontinuous pulsed signal frequency acquisition system of claim 1, wherein, The damping unit is used for reducing the amplitude value of the input pulse signal, and comprises: a resistance R2, a resistance R3, a resistance R4 and a resistance R9, the resistance R2, the resistance R3 and the resistance R4 are connected in series on the non-continuous pulse signal input path, and one end of the resistance R9 is connected between the resistance R2 and the resistance R3 and the other end is grounded.

3. The noncontinuous pulsed signal frequency acquisition system of claim 2, wherein, The filter unit is used for filtering the signal after the amplitude value is reduced, and comprises: an input coupling capacitor C1, a capacitor C3, a capacitor C5, an output coupling capacitor C11 and an operational amplifier U1; the signal is input into the operational amplifier U1 after passing through the resistance R3 and the resistance R4; one end of the input coupling capacitor C1 is connected with the power input end of the operational amplifier U1 and the other end is grounded; one end of the capacitor C3 is connected with the connection node of the resistance R3 and the resistance R4 and the other end is connected with the operational amplifier U1; one end of the capacitor C5 is connected between the resistance R4 and the operational amplifier U1 and the other end is grounded; one end of the output coupling capacitor C11 is connected with the power output end of the operational amplifier U1 and the other end is grounded.

4. The noncontinuous pulsed signal frequency acquisition system of claim 1, wherein, The impedance matching unit comprises: a first impedance matching circuit and a second impedance matching circuit, the first impedance matching circuit and the second impedance matching circuit are connected in parallel, the first impedance matching circuit is connected with the first comparator, and the second impedance matching circuit is connected with the second comparator.

5. The noncontinuous pulsed signal frequency acquisition system of claim 4, wherein, The first impedance matching circuit comprises: an operational amplifier U2, a resistance R1, a resistance R5, a resistance R6, a resistance R7, a resistance R8, an input coupling capacitor C2, a capacitor C6 and a capacitor C7; one end of the resistance R5 is connected with the operational amplifier U2 and the other end is grounded; one end of the resistance R1 is connected between the resistance R5 and the operational amplifier U2 and the other end is connected with the power output end of the operational amplifier U2; one end of the resistance R6 is connected with the filter unit and the other end is connected with the input end of the operational amplifier U2; one end of the input coupling capacitor C2 is connected with the power input end of the operational amplifier U2 and the other end is grounded; one end of the capacitor C7 is connected between the resistance R6 and the operational amplifier U2 and the other end is grounded; the resistance R7 and the resistance R8 are connected with the output end of the operational amplifier U2, one end of the resistance R7 is connected with the output end of the operational amplifier U2 and the other end is connected with the resistance R8, and the other end of the resistance R8 is grounded; one end of the capacitor C6 is connected with the resistance R7 and the other end is grounded, and the resistance R8 is located between the resistance R7 and the capacitor C6.

6. The noncontinuous pulsed signal frequency acquisition system of claim 4, wherein, The second impedance matching circuit comprises: An operational amplifier U40, a resistor R274, a resistor R284, a resistor R285, a resistor R286, a resistor R287, a resistor R288, an input coupling capacitor C278, a capacitor C276, a capacitor C277 and a capacitor C279; One end of the resistor R286 is connected with the operational amplifier U40, and the other end is grounded; One end of the resistor R288 is connected between the resistor R5 and the operational amplifier U40, and the other end is connected with the power output end of the operational amplifier U40; One end of the resistor R274 is connected with the filter unit, and the other end is connected with the resistor R287 in series and then connected with the input end of the operational amplifier U40; One end of the input coupling capacitor C278 is connected with the power input end of the operational amplifier U40, and the other end is grounded; One end of the capacitor C279 is connected between the resistor R274 and the resistor R287, and the other end is grounded; One end of the capacitor C276 is connected between the resistor R287 and the operational amplifier U2, and the other end is grounded; The resistor R285 and the resistor R284 are connected with the output end of the operational amplifier U40, one end of the resistor R285 is connected with the output end of the operational amplifier U40, and the other end is connected with the resistor R284, and the other end of the resistor R284 is grounded; One end of the capacitor C277 is connected with the resistor R285, and the other end is grounded, and the resistor R284 is located between the resistor R7 and the capacitor C6.

7. The noncontinuous pulsed signal frequency acquisition system of claim 1, wherein, Further comprising: A communication unit connected with the master control unit, used for sending the frequency of the discontinuous pulse signal calculated by the master control unit to other control systems for display.

8. A method for frequency acquisition of a non-continuous pulsed signal, characterized by, Comprising: Step 1: obtaining the input pulse signal; Step 2: the attenuation unit reduces the amplitude value of the input pulse signal; Step 3: the filter unit filters the signal after reducing the amplitude value, filtering the clutter; Step 4: the filtered signal is input into the first comparator and the second comparator after passing through the impedance matching unit, and the signal after passing through the first comparator and the second comparator is a square wave signal; Step 5: when the master control unit detects the rising edge output by the second comparator, the first comparator is triggered to count, and the first comparator calculates the period of two consecutive square waves, thereby obtaining the frequency of the discontinuous pulse signal.

9. The method of claim 8, wherein, In the step 5, The second comparator is connected to the external interrupt extiX of the MCU, the first comparator is connected to the timing counter TIM_CHX of the MCU, and the external interrupt extiX of the MCU and the timing counter TIM_CHX of the MCU are set to trigger on the rising and falling edges, when the external interrupt extiX detects the rising edge, the timing counter TIM_CHX starts input capture, the timing counter TIM_CHX captures the rising edge, and then waits for the rising edge interrupt to come, when the rising edge interrupt is captured, the capture state is marked as the falling edge, and the current timing count value is T0, when the falling edge interrupt is captured, the capture state is marked as the rising edge, and the current timing count value is T1, and then the high level time of the pulse signal is calculated as Th=T1-T0; When the rising edge is triggered again, the capture state is marked as falling edge, the current timing count value is T2, then the high level time of the pulse signal is calculated as T1=T2-T1, the total period of the effective signal in the pulse is Th+T1=T, and 1 / T is the frequency of the effective signal in the pulse; The above capture operation is calculated in a loop until the capture is stopped after the falling edge of the external interrupt extiX is triggered.

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