A time-to-digital conversion circuit and conversion method

Abstract

The application belongs to the technical field of time-to-digital conversion, and discloses a time-to-digital conversion circuit and a conversion method. The circuit comprises a time counting module, a first data buffer module and an arithmetic logic module. The time counting module comprises a ring oscillator, a coarse value counter, a latch unit, an XOR unit, a decoder, a multiplier and an adder. The ring oscillator comprises a NAND gate and a plurality of inverters connected in sequence. The output end of the last inverter is connected with the input end of the coarse value counter and the first input end of the NAND gate respectively. The second input end of the NAND gate is used for receiving a counting enable signal. The latch unit is connected with each inverter in the ring oscillator. The XOR unit is connected with the decoder. The application can realize time-to-digital conversion of a signal by using unified conversion logic through fewer circuit devices, and the conversion speed is faster.

Description

Technical Field

[0001] This application relates to the field of time-to-digital conversion technology, and in particular to a time-to-digital conversion circuit and conversion method. Background Technology

[0002] Existing time-to-digital conversion methods based on ring oscillators mainly use a single rising edge as the clock edge to count the counter. At this point, it is necessary to determine whether the current ring oscillator has completed one cycle or two cycles. Then, based on the determination result, an operation is performed on the final counter value. Depending on the number of cycles, it is determined whether half a cycle time needs to be added to the output result. In other words, the existing technology requires designing two different calculation algorithms for the output value of the ring oscillator based on the number of cycles, which makes the operation logic relatively complex and the corresponding logic circuit structure more complex. Summary of the Invention

[0003] This application provides a time-to-digital conversion circuit and conversion method, which can achieve time-to-digital conversion of signals with fewer circuit components and a unified conversion logic, and the conversion speed is faster.

[0004] In a first aspect, embodiments of this application provide a time-to-digital conversion circuit, including:

[0005] The module consists of a time counting module, a first data cache module, and an arithmetic logic module.

[0006] The time counting module includes a ring oscillator, a coarse value counter, a latch unit, an XOR unit, a decoder, a multiplier, and an adder; the ring oscillator includes NAND gates and multiple inverters connected in sequence.

[0007] The output of the last inverter is connected to the input of the coarse counter and the first input of the NAND gate, respectively; the second input of the NAND gate is used to receive the counting enable signal; the coarse counter is used to count the rising and falling edges of the output signal of the last inverter to obtain the first value and send it to the multiplier.

[0008] The latch unit is connected to each inverter in the ring oscillator; the latch unit is used to send the output signal of each inverter to the XOR unit in response to the first edge signal or the second edge signal.

[0009] The XOR unit is connected to the decoder; the XOR unit is used to perform XOR processing on the output signals of two adjacent inverters to obtain multiple output values ​​and send them to the decoder.

[0010] The decoder is used to decode each output value to obtain a second value and send it to the adder;

[0011] The multiplier is used to convert the first value into a third value in units of inverter delay and send it to the adder;

[0012] The adder is used to add the second value and the third value to obtain the first conversion result corresponding to the first edge signal or the second conversion result corresponding to the second edge signal, and send it to the first data buffer module;

[0013] The arithmetic logic module is used to read the first conversion result and the second conversion result from the first data cache module; and to calculate the numerical arithmetic result based on the difference between the first conversion result and the second conversion result.

[0014] Furthermore, the latch unit includes multiple latches; the XOR unit includes multiple XOR gates;

[0015] The latch, the XOR gate, and the inverter of the ring oscillator are in one-to-one correspondence;

[0016] The data input terminal of the latch is connected to the output terminal of the corresponding inverter; the output terminals of the latch and the previous latch are respectively connected to the two input terminals of the corresponding XNOR gate; when the enable input terminal of the latch receives the first edge signal or the second edge signal, it sends the output signal of the corresponding inverter to the corresponding XNOR gate.

[0017] The XOR gate is used to perform XOR operation on two output signals to obtain the output value, which is then sent to the decoder.

[0018] Furthermore, the circuit also includes:

[0019] The system includes a read / write control module, an edge detection module, and a pulse generator. The read / write control module receives pulse configuration commands and sends them to the pulse generator, as well as receives edge extraction commands and sends them to the edge detection module.

[0020] The pulse generator is used to generate pulse signals according to pulse configuration instructions;

[0021] The edge detection module is used to extract the rising edge or falling edge of the pulse signal according to the edge extraction instruction to obtain the first edge signal, and to extract the rising edge or falling edge of the echo signal after the pulse signal is reflected to obtain the second edge signal, and send it to the latch unit of the time counting module.

[0022] Furthermore, the circuit also includes a signal filtering module;

[0023] The signal filtering module is located before the edge detection module and is used to filter the reflected echo signal.

[0024] Furthermore, the circuit also includes a crystal oscillator start-up module for starting the crystal oscillator, generating a measurement clock signal and sending it to the time counting module; the time counting module also includes a crystal oscillator counter;

[0025] The read / write control module is also used to receive mode configuration information, generate a first mode instruction or a second mode instruction based on the mode configuration information, and send it to the time counting module and the arithmetic logic module.

[0026] The time counting module is also used to respond to the first mode command and output the first conversion result and the second conversion result to the first data buffer module according to the received first edge signal and second edge signal;

[0027] The time counting module is also used to respond to the second mode command, output a first conversion result based on the first edge signal, output a second conversion result based on the measurement clock signal after the first edge signal, output a third conversion result based on the second edge signal, and output a fourth conversion result based on the measurement clock signal after the second edge signal; and send the first conversion result, the second conversion result, the third conversion result, and the fourth conversion result to the first data buffer module;

[0028] The crystal counter is used to respond to the second mode command, count the measurement clock signal between the first edge signal and the second edge signal, obtain the clock count result and send it to the first data buffer module;

[0029] The arithmetic logic module is also used to respond to the first mode instruction to obtain a digital arithmetic result based on the difference between the first conversion result and the second conversion result; and to respond to the second mode instruction to obtain a digital arithmetic result based on the first conversion result, the second conversion result, the third conversion result, the fourth conversion result and the clock count result.

[0030] Furthermore, the circuit also includes a self-calibration module for clock calibration of the crystal oscillator starting module according to a preset period.

[0031] Furthermore, the self-calibration module is connected to the read / write control module;

[0032] The read / write control module is also used to receive calibration commands and send them to the self-calibration module;

[0033] The self-calibration module is also used to perform clock calibration on the crystal oscillator starting module in response to calibration commands.

[0034] Furthermore, the arithmetic logic module is specifically used to obtain the crystal clock period of the clock signal of the crystal oscillator starting module; the difference between the first conversion result and the second conversion result is divided by the crystal clock period to obtain the digital arithmetic result.

[0035] Furthermore, the arithmetic logic module is specifically used to obtain the crystal clock period of the clock signal of the crystal oscillator starting module; calculate the first difference between the first conversion result and the second conversion result, calculate the second difference between the third conversion result and the fourth conversion result, subtract the second difference from the first difference, divide by the crystal clock period, and then add it to the clock counting result to obtain the digital arithmetic result.

[0036] Furthermore, the circuit also includes a second data buffer module;

[0037] The arithmetic logic module is also used to send the obtained numerical arithmetic results to the second data cache module;

[0038] The read / write control module is also used to read the numerical arithmetic results from the second data cache module.

[0039] Furthermore, the read / write control module is also used to send crystal oscillator measurement commands to the time counting module and the arithmetic logic module;

[0040] The time counting module is also used to respond to crystal oscillator measurement commands, and output the first conversion result and the second conversion result to the first data buffer module according to the two edge signals corresponding to one cycle of the measurement clock signal;

[0041] The arithmetic logic module is also used to respond to crystal oscillator measurement commands, read the first conversion result and the second conversion result in the first data buffer module and calculate the difference to obtain the crystal oscillator clock cycle in units of inverter delay.

[0042] Furthermore, the self-calibration module is specifically used to extract the system clock signal, obtain the first edge signal and the second edge signal, and send them to the time counting module under the second mode command;

[0043] The system reads the second data cache module to obtain the digital arithmetic result and uses it as the system measurement result; it calculates the ratio between the system measurement result and the preset standard result; and it performs clock calibration on the crystal oscillator starting module based on the ratio.

[0044] Furthermore, the decoder is specifically used to combine the received output values ​​to obtain the XOR output code; determine the position of the 1 code in the XOR output code, and convert the position of the 1 code in the XOR output code into a second value.

[0045] Secondly, embodiments of this application provide a time-to-digital conversion method, applied to a time-to-digital conversion circuit as described in any of the above embodiments, the time-to-digital conversion method comprising:

[0046] Each inverter of the ring oscillator obtains its output signal based on a counting enable signal;

[0047] The latch unit responds to the first edge signal or the second edge signal and sends the output signals of each inverter to the XOR unit;

[0048] The XOR unit performs XOR processing on the output signals of two adjacent inverters to obtain multiple output values, which are then sent to the decoder.

[0049] The coarse counter counts the rising and falling edges of the output signal of the last inverter to obtain the first value;

[0050] The decoder decodes each output value to obtain the second value and sends it to the adder;

[0051] The multiplier obtains the first value, converts it into a third value in units of inverter delay, and sends it to the adder;

[0052] The adder adds the second and third values ​​to obtain the first conversion result corresponding to the first edge signal or the second conversion result corresponding to the second edge signal, and sends it to the first data buffer module.

[0053] The arithmetic logic module reads the first conversion result and the second conversion result from the first data cache module; it calculates the arithmetic result based on the difference between the first conversion result and the second conversion result.

[0054] Furthermore, the method also includes:

[0055] The read / write control module receives pulse configuration commands and sends them to the pulse generator;

[0056] The read / write control module receives the edge extraction command and sends it to the edge detection module;

[0057] The pulse generator generates pulse signals according to the pulse configuration command;

[0058] The edge detection module extracts the rising edge or falling edge of the pulse signal according to the edge extraction instruction to obtain the first edge signal, and extracts the rising edge or falling edge of the echo signal after the pulse signal is reflected to obtain the second edge signal, which is then sent to the latch unit.

[0059] Furthermore, the method also includes:

[0060] The signal filtering module filters the reflected echo signal and then sends it to the edge detection module.

[0061] Furthermore, the method also includes:

[0062] The crystal oscillator startup module starts the crystal oscillator, generates a measurement clock signal, and sends it to the time counting module.

[0063] The read / write control module receives mode configuration information, generates a first mode instruction or a second mode instruction based on the mode configuration information, and sends it to the time counting module and the arithmetic logic module.

[0064] The time counting module responds to the first mode command and outputs the first conversion result and the second conversion result based on the received first edge signal and second edge signal; or, responds to the second mode command and outputs the first conversion result based on the first edge signal, the second conversion result based on the measurement clock signal after the first edge signal, the third conversion result based on the second edge signal, and the fourth conversion result based on the measurement clock signal after the second edge signal.

[0065] The crystal counter responds to the second mode command and counts the measurement clock signal between the first edge signal and the second edge signal to obtain the clock count result;

[0066] The arithmetic logic module responds to the first mode instruction and obtains a digital arithmetic result based on the difference between the first conversion result and the second conversion result; or, responds to the second mode instruction and obtains a digital arithmetic result based on the first conversion result, the second conversion result, the third conversion result, the fourth conversion result, and the clock count result.

[0067] Furthermore, the method also includes:

[0068] The self-calibration module performs clock calibration on the crystal oscillator starting module according to a preset cycle.

[0069] Furthermore, the method also includes:

[0070] The read / write control module receives calibration commands and sends them to the self-calibration module;

[0071] The self-calibration module responds to the calibration command from the read / write control module and performs clock calibration on the crystal oscillator starting module.

[0072] Furthermore, the decoder above decodes each output value to obtain a second value, including:

[0073] Combine the received output values ​​to obtain the XOR output code;

[0074] Determine the position of the 1 code in the XOR output code and convert it to the second value.

[0075] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0076] This application provides a time-to-digital conversion circuit. After the counting enable signal is input to the ring oscillator of the time counting module, a coarse counter connected to the output of the last inverter uses both the rising and falling edges of the received output signal as valid clock edges for counting. At this time, each edge count corresponds to the time it takes for the counting enable signal to propagate half a revolution in the ring oscillator. Therefore, the first value obtained by the coarse counter from edge counting is converted into a third value in units of inverter delay, which can represent the coarse digital conversion result of the current time. After receiving the first edge signal or the second edge signal, the latch unit immediately latches the output signal of the inverter at the current moment to the XOR unit, so that the XOR unit can locate the flip point of the ring oscillator through the output value and output it in the form of a second value through the decoder. This second value is the fine conversion result of time within a short range. The coarse third value is added to the fine second value in the adder to obtain the accurate first / second conversion result. The difference between these two conversion results can be regarded as the time difference between the first edge signal and the second edge signal. The aforementioned time-to-digital conversion circuit does not require different time conversion algorithms for different numbers of cycles of the ring oscillator. It has only one time conversion logic, which is simpler than the conversion logic of existing technologies, requires simpler logic circuits, and has a faster conversion speed. Attached Figure Description

[0077] Figure 1 A block diagram of a time-to-digital conversion circuit is provided for an exemplary embodiment of this application.

[0078] Figure 2 This is a structural diagram of a time counting module provided for an exemplary embodiment of this application.

[0079] Figure 3 A block diagram of a time-to-digital conversion circuit is provided as another exemplary embodiment of this application.

[0080] Figure 4 A flowchart of a time-to-digital conversion method provided as an exemplary embodiment of this application. Detailed Implementation

[0081] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0082] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0083] Please see Figure 1This application provides a time-to-digital conversion circuit, including a time counting module, a first data buffer module, and an arithmetic logic module.

[0084] Please see Figure 2 The time counting module includes a ring oscillator, a coarse value counter, a latch unit, an XOR unit, a decoder, a multiplier, and an adder; the ring oscillator includes NAND gates and multiple inverters connected in sequence.

[0085] Specifically, the input of the first inverter is connected to the output of the NAND gate, and subsequent inverters are connected in sequence.

[0086] The output of the last inverter is connected to the input of the coarse counter and the first input of the NAND gate, respectively; the second input of the NAND gate is used to receive the counting enable signal; the coarse counter is used to count the rising and falling edges of the output signal of the last inverter to obtain the first value and send it to the multiplier.

[0087] Specifically, the coarse-value counter takes the rising and falling edges of the output signal of the last inverter of the ring oscillator as the effective clock edges of the counter, so the clock period of the coarse-value counter is N*Td.

[0088] Where N is the number of inverters in the ring oscillator, and Td is the delay between the input and output of each inverter, also known as inverter delay or counting precision; for accuracy, the smaller the value of Td, the better.

[0089] If the first value output by the coarse counter is recorded as CNT, then the time it represents is Tc = CNT * N * Td.

[0090] The latch unit is connected to each inverter in the ring oscillator; the latch unit is used to send the output signal of each inverter to the XOR unit in response to the first edge signal or the second edge signal; the XOR unit is connected to the decoder; the XOR unit is used to perform XOR processing on the output signals of two adjacent inverters to obtain multiple output values ​​and send them to the decoder.

[0091] The latch unit includes multiple latches; the XOR unit includes multiple XOR gates.

[0092] The latches, XOR gates, and inverters of the ring oscillator correspond one-to-one.

[0093] The data input terminal of the latch is connected to the output terminal of the corresponding inverter; the output terminals of the latch and the previous latch are respectively connected to the two input terminals of the corresponding XNOR gate; when the enable input terminal of the latch receives the first edge signal or the second edge signal, it sends the output signal of the corresponding inverter to the corresponding XNOR gate.

[0094] The XOR gate is used to perform XOR operation on two output signals to obtain the output value, which is then sent to the decoder.

[0095] like Figure 2 As shown, the number of latches and XOR gates is N, the same as the number of inverters in a ring oscillator. The latches are used to latch the current output value of the inverters in the ring oscillator. The N latches are not connected to each other, that is, each latch has only two inputs (the corresponding inverter output and the input of the edge of the signal under test) and one output (the corresponding XOR gate).

[0096] The XNOR gate is used to compare whether the output logic of two adjacent latches is consistent, thereby obtaining the current toggle point position of the ring oscillator and outputting "1". Specifically, the input of the first XNOR gate is the output of the last latch and the output of the first latch, the input of the second XNOR gate is the output of the first latch and the output of the second latch, the input of the third XNOR gate is the output of the second latch and the output of the third latch, and so on for the connection of N XNOR gates.

[0097] The outputs of each XOR gate are connected to the inputs of the decoder; the output value of this group of XOR gates is denoted as D1.

[0098] The decoder is used to decode each output value to obtain a second value and send it to the adder.

[0099] The decoder is specifically used to combine the received output values ​​to obtain the XOR output code; determine the position of the 1 in the XOR output code, and convert the position of the 1 in the XOR output code into a second value.

[0100] For example, taking N=5, if the XNOR gate output value is D1=10000, it can be seen that the 1 code is in the 0th position from the left, so the decoder records the second output value D2 as 0; if the XNOR gate output is 01000, that is, the 1 code is in the 1st position from the left, so the decoder records the second output value D2 as 1; if the XNOR gate output is 00100, the 1 code is in the 2nd position from the left, so the decoder records the second output value D2 as 2. At this time, the time represented by D2 is Tf=D2*Td.

[0101] The multiplier is used to convert the first value into a third value in units of inverter delay and send it to the adder.

[0102] Specifically, the multiplier is used to convert the first value CNT output by the coarse value counter into a value in units of inverter delay Td. If the third value of the multiplier is recorded as H, then H = CNT * N.

[0103] The adder is used to add the second value and the third value to obtain the first conversion result corresponding to the first edge signal or the second conversion result corresponding to the second edge signal, and then send it to the first data buffer module.

[0104] Specifically, the adder adds the third value of the multiplier and the second value of the decoder to obtain the first / second conversion result T=Tc+Tf= CNT*N*Td+Tf= CNT*N*Td+D2*Td=(H+D2)*Td.

[0105] It can be considered that the combination of the third and second values ​​in this application is actually a combination of "coarse counting" and "fine counting". The third value records the total number of "steps" the counting enable signal traverses the ring oscillator chain during the entire measured time interval (from the start of the input counting enable signal EN to the receipt of the first edge signal). This is a coarse measurement, but it covers a long time range. The second value indicates which position (which stage of inverter) the counting enable signal has propagated to in the ring oscillator at the current moment. Combining these two results yields the time length expressed in digital terms.

[0106] The arithmetic logic module is used to read the first conversion result and the second conversion result from the first data cache module; and to calculate the numerical arithmetic result based on the difference between the first conversion result and the second conversion result.

[0107] Specifically, the arithmetic logic module reads the two conversion results from the first data buffer module, calculates the difference ΔT between the first and second conversion results as a multiple of the crystal oscillator period Tref as tx = ΔT / Tref, and uses tx as the digital arithmetic result. This digital arithmetic result represents the digital quantization result of the time difference between the first edge signal and the second edge signal.

[0108] Taking N=4 as an example, the ring oscillator consists of one NAND gate and four inverters. The output delay of each inverter is Td, and the outputs are defined as I1, I2, I3, I4, and I5, respectively.

[0109] Before the counting enable signal EN arrives, the ring oscillator outputs as follows: I1=1, I2=0, I3=1, I4=0, I5=1, and the first value CNT of the coarse counter outputs is 0. After EN arrives, the ring oscillator outputs as shown in the table below, with 10 Td cycles, A=D1+D2. After the first / second edge signal arrives, the ring oscillator stops working, and the latch instantly latches the current state of each node on the ring oscillator. The conversion result no longer changes and is output to the first data buffer module. Based on the circuit structure and algorithm of the time counting module of this application, the correct first / second conversion result T1 / T2 can be calculated.

[0110]

[0111] The above embodiment provides a time-to-digital conversion circuit. After the counting enable signal is input to the ring oscillator of the time counting module, the coarse counter connected to the output of the last inverter uses both the rising and falling edges of the received output signal as valid clock edges for counting. At this time, each edge count corresponds to the time it takes for the counting enable signal to propagate half a revolution in the ring oscillator. Therefore, the first value obtained by the coarse counter from edge counting is converted into a third value in units of inverter delay, which can represent the coarse digital conversion result of the current time. After receiving the first edge signal or the second edge signal, the latch unit immediately latches the output signal of the inverter at the current time to the XOR unit, so that the XOR unit can locate the flip point of the ring oscillator through the output value and output it in the form of a second value through the decoder. This second value is the fine conversion result of time within a short range. The coarse third value is added to the fine second value in the adder to obtain the accurate first / second conversion result. The difference between these two conversion results can be regarded as the time difference between the first edge signal and the second edge signal. The aforementioned time-to-digital conversion circuit does not require different time conversion algorithms for different numbers of cycles of the ring oscillator. It has only one time conversion logic, which is simpler than the conversion logic of existing technologies, requires simpler logic circuits, and has a faster conversion speed.

[0112] In some embodiments, the circuit further includes a signal filtering module.

[0113] The signal filtering module is located before the edge detection module and is used to filter the reflected echo signal.

[0114] The circuit also includes a read / write control module, an edge detection module, and a pulse generator; the read / write control module is used to receive pulse configuration instructions and send them to the pulse generator, and to receive edge extraction instructions and send them to the edge detection module.

[0115] The pulse generator is used to generate pulse signals according to the pulse configuration instruction; the edge detection module is used to extract the rising edge or falling edge of the pulse signal according to the edge extraction instruction to obtain the first edge signal, and to extract the rising edge or falling edge of the echo signal after the pulse signal is reflected to obtain the second edge signal, and send it to the latch unit of the time counting module.

[0116] Specifically, the edge detection module is connected to the enable input of each latch in the time counting module.

[0117] It is worth noting that since the second edge signal comes from the pulse signal after reflection and echo, the time counting module after the edge detection module must receive the first edge signal first and then the second edge signal. That is, the first edge signal comes first and the second edge signal comes later. The time counting module and the arithmetic logic module are used to convert the time difference between the two signal edges of the first edge signal and the second edge signal into a digital arithmetic result.

[0118] However, the pulse signal may be affected by environmental interference during propagation. Therefore, this application uses a signal filtering module to filter out the interference in the echo signal after the pulse signal is reflected before sending it to the edge detection module.

[0119] Please see Figure 3 In some embodiments, the circuit further includes a crystal oscillator startup module for starting the crystal oscillator, generating a measurement clock signal, and sending it to the time counting module. The time counting module also includes a crystal counter.

[0120] The read / write control module is also used to receive mode configuration information, generate a first mode instruction or a second mode instruction based on the mode configuration information, and send them to the time counting module and the arithmetic logic module.

[0121] The time counting module is also used to respond to the first mode command and output the first conversion result and the second conversion result to the first data buffer module according to the received first edge signal and second edge signal.

[0122] The time counting module is also used to respond to the second mode command, output the first conversion result according to the first edge signal, output the second conversion result according to the measurement clock signal after the first edge signal, output the third conversion result according to the second edge signal, and output the fourth conversion result according to the measurement clock signal after the second edge signal; and send the first conversion result, the second conversion result, the third conversion result and the fourth conversion result to the first data buffer module.

[0123] The crystal counter is used to respond to the second mode command, count the measurement clock signal between the first edge signal and the second edge signal, obtain the clock count result and send it to the first data buffer module.

[0124] It can be considered that the aforementioned ring oscillator, coarse value counter, latch unit, XOR unit, decoder, multiplier and adder constitute the time-to-digital conversion unit in the time counting module.

[0125] Specifically, the time-to-digital converter in the time counting module is used to convert the difference between the moment the edge signal is received and the moment the count enable signal is received into a time conversion result. However, the time-to-digital converter responds to different edge signals in different measurement time ranges, and the object of the output time conversion result has different definitions.

[0126] When the time difference between the pulse signal and the echo signal after reflection is small, there is no need for a crystal counter to participate in the counting. Only the time conversion result of the time conversion unit triggered by the two edge signals of the pulse signal and the echo signal after reflection can be directly calculated by the difference.

[0127] When the time difference between the pulse signal and the echo signal after the pulse signal is reflected is large, it may exceed the conversion range of the time-to-digital converter unit, so a crystal counter is required to participate in the counting. At this time, the first edge signal from the pulse signal, the edge of the most recent measurement clock signal after the first edge signal, the second edge signal from the echo signal, and the edge of the most recent measurement clock signal after the second edge signal will all trigger the time-to-digital converter unit to output the time conversion result.

[0128] The arithmetic logic module is also used to respond to the first mode instruction to obtain a digital arithmetic result based on the difference between the first conversion result and the second conversion result; and to respond to the second mode instruction to obtain a digital arithmetic result based on the first conversion result, the second conversion result, the third conversion result, the fourth conversion result and the clock count result.

[0129] In general, when the time difference between the first edge signal and the second edge signal is long, it may exceed the counting range of the time-to-digital conversion unit. To address this, this application further adds a crystal counter. When the edge time difference between the pulse signal and the pulse signal echo signal is large, the crystal counter is used to convert most of the time difference. The time difference between the two edge signals is calculated by combining the time difference between the two edge signals and the most recent measurement clock signal.

[0130] Under the first mode instruction, the arithmetic logic module is specifically used to obtain the crystal clock period of the clock signal of the crystal oscillator starting module; the difference between the first conversion result and the second conversion result is divided by the crystal clock period to obtain the digital arithmetic result.

[0131] Under the second mode instruction, the arithmetic logic module is specifically used to obtain the crystal clock period of the clock signal of the crystal oscillator starting module; calculate the first difference between the first conversion result and the second conversion result, calculate the second difference between the third conversion result and the fourth conversion result, subtract the second difference from the first difference, divide by the crystal clock period, and then add it to the clock counting result to obtain the digital arithmetic result.

[0132] Specifically, when the time difference between the pulse signal and the echo signal after reflection is small, the crystal counter is not required to participate in the counting. One cycle of the clock signal of the crystal oscillator module is recorded as Tref. The arithmetic logic module first reads the two conversion results T1 and T2 from the first data buffer module, calculates the difference between T1 and T2 ΔT = T2 - T1, and calculates the multiple of one cycle of the measured clock signal Tref as tx = ΔT / Tref. tx is then used as the digital arithmetic result.

[0133] When the time difference between the pulse signal and the echo signal after reflection is large, a crystal counter is required for counting. The arithmetic logic module first reads the first conversion result T1, the second conversion result T2, the third conversion result T3, and the fourth conversion result T4 from the first data buffer module. It calculates the first difference between T1 and T2, ΔT1 = T2 - T1, and the second difference between T3 and T4, ΔT2 = T4 - T3. At this time, the multiple of the time difference between the pulse signal and the echo signal and one period Tref of the measurement clock signal is tx = (ΔT1 - ΔT2) / Tref + time count result. tx is used as the digital arithmetic result.

[0134] It is worth noting that since the pulse signal is generally generated by the pulse generator configured by the MCU through the read / write control module, the MCU can determine whether the measurement range of the time counting module is large or small. Therefore, the working mode of the time counting module and the arithmetic logic module can also be controlled by the MCU through the read / write control module.

[0135] The above embodiments expand the measurement range of the time counting module through mode switching and the design of the calculation algorithm in the arithmetic logic module, enabling the time-to-digital conversion circuit of this application to measure two signal edges with a large conversion time difference.

[0136] Please see Figure 3 In some embodiments, the circuit further includes a self-calibration module and a second data buffer module.

[0137] The arithmetic logic module is also used to send the obtained numerical arithmetic results to the second data cache module.

[0138] The read / write control module is also used to read the numerical arithmetic results from the second data cache module.

[0139] The self-calibration module is used to perform clock calibration on the crystal oscillator starting module according to a preset cycle.

[0140] Specifically, the crystal oscillator starting module may experience clock offset during application, which reduces the accuracy of the time-to-digital conversion process in the second mode based on the clock signal. In order to obtain a more accurate time value, this application adds a self-calibration module to calibrate the crystal oscillator starting module that generates the clock signal.

[0141] Furthermore, the self-calibration module is connected to the read / write control module.

[0142] The read / write control module is also used to receive calibration commands and send them to the self-calibration module.

[0143] The self-calibration module is also used to perform clock calibration on the crystal oscillator starting module in response to calibration commands.

[0144] The self-calibration module can trigger the clock calibration operation of the crystal oscillator module in two ways: one is to control it through the read / write control module, which calibrates the crystal oscillator clock by issuing calibration commands; the other is to use the system clock signal to perform a timing operation, and then perform the crystal oscillator clock calibration when the timing reaches a preset period.

[0145] It should be noted that the time-to-digital conversion circuit of this application requires two crystal oscillators. One crystal oscillator is used to generate a system clock signal to support the operation of other circuit modules in this application, except for the time counting module. The other crystal oscillator is the crystal oscillation module mentioned above, which generates a measurement clock signal to supply the time counting module for operation.

[0146] The self-calibration module is specifically used to extract the system clock signal, obtain the first edge signal and the second edge signal, and send them to the time counting module under the second mode command; read the second data buffer module to obtain the digital arithmetic result and use it as the system measurement result; calculate the ratio of the system measurement result and the preset standard result; and perform clock calibration on the crystal oscillator starting module according to the ratio.

[0147] Specifically, the calibration process involves using the time counting module under the second mode command to measure the system clock signal. Because the time counting module needs to operate based on the measured clock signal under the second mode command, a longer time interval between the first and second edge signals is required. Therefore, the self-calibration module typically uses the edges of multiple consecutive cycles of the system clock signal as the first and second edge signals, and takes the digital arithmetic result output by the arithmetic logic module as the system measurement result, i.e., Tosc1. Theoretically, if the crystal oscillator startup module is accurate, the output measurement clock signal must also be accurate. Therefore, the preset standard result of the system measurement should be Tosc2. If Tosc1 is not equal to Tosc2, it indicates that the crystal oscillator startup module needs calibration. In this case, the ratio tosc = Tosc1 / Tosc2 can be calculated, which is the calibration result.

[0148] Furthermore, in addition to storing the numerical arithmetic results of the arithmetic logic module, the second data cache module can also be connected to the self-calibration module to store the calibration results (tosc) of each self-calibration module.

[0149] In some embodiments, the read / write control module is also used to send crystal oscillator measurement commands to the time counting module and the arithmetic logic module.

[0150] The time counting module is also used to respond to crystal oscillator measurement commands, and output the first conversion result and the second conversion result to the first data buffer module according to the two edge signals corresponding to one cycle of the measurement clock signal.

[0151] The arithmetic logic module is also used to respond to crystal oscillator measurement commands, read the first conversion result and the second conversion result in the first data buffer module and calculate the difference to obtain the crystal oscillator clock cycle in units of inverter delay.

[0152] It should be noted that in the specific implementation process, the inverter delay Td is easily affected by the temperature or process of the circuit components, resulting in slight differences in Td at different times or between different products. If a uniform crystal oscillator clock period is used, the accuracy of the conversion result may be inconsistent. Therefore, in order to eliminate the influence of Td, this application has the time counting module measure the two edges of the measurement clock signal of one cycle. At this time, the time counting module operates in the first mode, that is, the two edges of the measurement clock signal will trigger the output of the latch unit once, respectively, to obtain the first conversion result and the second conversion result. Then, the corresponding digital arithmetic result is further calculated as the period calculation result of the measurement clock signal, thereby obtaining the crystal oscillator clock period Tref = period calculation result * Td. Since the results output by the time counting module are all in Td units, when the arithmetic logic module calculates the digital arithmetic results corresponding to the other two edge signals according to the above embodiment, it eliminates the unit Td by comparing it with the crystal oscillator clock period, thereby eliminating the influence of the fluctuation of the inverter delay Td.

[0153] Please see Figure 4 Another embodiment of this application provides a time-to-digital conversion method, applied to a time-to-digital conversion circuit as described in any of the above embodiments, the time-to-digital conversion method comprising:

[0154] In step S11, each inverter of the ring oscillator obtains its output signal based on the counting enable signal.

[0155] In step S12, the latch unit responds to the first edge signal or the second edge signal by sending the output signals of each inverter to the XOR unit.

[0156] In step S13, the XOR unit performs XOR processing on the output signals of two adjacent inverters to obtain multiple output values ​​and sends them to the decoder.

[0157] In step S14, the coarse value counter counts the rising and falling edges of the output signal of the last inverter to obtain the first value.

[0158] In step S15, the decoder decodes each output value to obtain the second value and sends it to the adder.

[0159] In step S16, the multiplier obtains the first value, converts it into a third value in units of inverter delay, and sends it to the adder.

[0160] In step S17, the adder adds the second value and the third value to obtain the first conversion result corresponding to the first edge signal or the second conversion result corresponding to the second edge signal, and sends it to the first data buffer module.

[0161] Step S18: The arithmetic logic module reads the first conversion result and the second conversion result from the first data cache module; and calculates the arithmetic result based on the difference between the first conversion result and the second conversion result.

[0162] Furthermore, the method also includes:

[0163] The read / write control module receives pulse configuration commands and sends them to the pulse generator.

[0164] The read / write control module receives the edge extraction command and sends it to the edge detection module.

[0165] The pulse generator generates pulse signals according to the pulse configuration instructions.

[0166] The edge detection module extracts the rising edge or falling edge of the pulse signal according to the edge extraction instruction to obtain the first edge signal, and extracts the rising edge or falling edge of the echo signal after the pulse signal is reflected to obtain the second edge signal, which is then sent to the latch unit.

[0167] Furthermore, the method also includes:

[0168] The signal filtering module filters the reflected echo signal and then sends it to the edge detection module.

[0169] Furthermore, the method also includes:

[0170] The crystal oscillator startup module starts the crystal oscillator, generates a measurement clock signal, and sends it to the time counting module.

[0171] The read / write control module receives the mode configuration information, generates a first mode instruction or a second mode instruction based on the mode configuration information, and sends it to the time counting module and the arithmetic logic module.

[0172] The time counting module responds to the first mode command and outputs the first conversion result and the second conversion result based on the received first edge signal and second edge signal; or, responds to the second mode command and outputs the first conversion result based on the first edge signal, the second conversion result based on the measurement clock signal after the first edge signal, the third conversion result based on the second edge signal, and the fourth conversion result based on the measurement clock signal after the second edge signal.

[0173] The crystal counter responds to the second mode command and counts the measurement clock signal between the first edge signal and the second edge signal to obtain the clock count result.

[0174] The arithmetic logic module responds to the first mode instruction and obtains a digital arithmetic result based on the difference between the first conversion result and the second conversion result; or, responds to the second mode instruction and obtains a digital arithmetic result based on the first conversion result, the second conversion result, the third conversion result, the fourth conversion result, and the clock count result.

[0175] Furthermore, the method also includes:

[0176] The self-calibration module performs clock calibration on the crystal oscillator starting module according to a preset cycle.

[0177] Furthermore, the method also includes:

[0178] The read / write control module receives calibration instructions and sends them to the self-calibration module.

[0179] The self-calibration module responds to the calibration command from the read / write control module and performs clock calibration on the crystal oscillator starting module.

[0180] Furthermore, the decoder above decodes each output value to obtain a second value, including:

[0181] Combine the received output values ​​to obtain the XOR output code.

[0182] Determine the position of the 1 code in the XOR output code and convert it to the second value.

[0183] The specific limitations of the time-to-digital conversion method provided in this embodiment can be found in the embodiment of the time-to-digital conversion circuit described above, and will not be repeated here.

[0184] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0185] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A time-to-digital conversion circuit, characterized by, The application relates to a time counting module, a first data buffer module and an arithmetic logic module. The time counting module comprises a ring oscillator, a coarse value counter, a latch unit, an exclusive OR unit, a decoder, a multiplier and an adder; the ring oscillator comprises a NAND gate and a plurality of inverters connected in sequence; an output end of the last inverter is connected with an input end of the coarse value counter and a first input end of the NAND gate; a second input end of the NAND gate is used for receiving a counting enable signal; the coarse value counter is used for counting rising edges and falling edges of an output signal of the last inverter to obtain a first value and send the first value to the multiplier; the latch unit is connected with each inverter in the ring oscillator; the latch unit is used for sending output signals of each inverter to the exclusive OR unit in response to a first edge signal or a second edge signal; the exclusive OR unit is connected with the decoder; the exclusive OR unit is used for performing exclusive OR processing on output signals of two adjacent inverters to obtain a plurality of output values and send the output values to the decoder; the decoder is used for decoding each output value to obtain a second value and send the second value to the adder; the decoder is specifically used for combining each received output value to obtain an exclusive OR output code; the position of a 1 code in the exclusive OR output code is determined; the position of the 1 code in the exclusive OR output code is converted into the second value; the multiplier is used for converting the first value into a third value in units of inverter delay and sending the third value to the adder; the adder is used for adding the second value and the third value to obtain a first conversion result corresponding to the first edge signal or a second conversion result corresponding to the second edge signal and send the first conversion result or the second conversion result to the first data buffer module; the arithmetic logic module is used for reading the first conversion result and the second conversion result in the first data buffer module; a digital arithmetic result is obtained by calculating a difference value of the first conversion result and the second conversion result. The latch unit comprises a plurality of latches; the exclusive OR unit comprises a plurality of exclusive OR gates; the latches, the exclusive OR gates and the inverters of the ring oscillator are in one-to-one correspondence; a data input end of the latch is connected with an output end of the corresponding inverter; the output ends of the latch and the previous latch are respectively connected with two input ends of the corresponding exclusive OR gate; when the enabled input end of the latch receives the first edge signal or the second edge signal, the output signal of the corresponding inverter is sent to the corresponding exclusive OR gate; the exclusive OR gate is used for performing exclusive OR processing on two output signals to obtain an output value and send the output value to the decoder. The application further relates to a read-write control module, an edge detection module and a pulse generator. The read-write control module is used for receiving a pulse configuration instruction and sending the pulse configuration instruction to the pulse generator, and receiving an edge extraction instruction and sending the edge extraction instruction to the edge detection module; the pulse generator is used for generating a pulse signal according to the pulse configuration instruction; ​ ​ ​ ​ ​ 2. The time-to-digital conversion circuit of claim 1, wherein, ​ ​ ​ 3. The time-to-digital conversion circuit of claim 2, wherein, ​ ​ ​ ​ The edge detection module is configured to perform rising edge extraction or falling edge extraction on the pulse signal according to the edge extraction instruction to obtain the first edge signal, perform rising edge extraction or falling edge extraction on the echo signal after reflection of the pulse signal to obtain the second edge signal, and send the second edge signal to a latch unit of the time counting module.

4. The time-to-digital conversion circuit of claim 3, wherein, The signal filtering module is further configured to filter the echo signal after reflection.

5. The time-to-digital conversion circuit of claim 4, wherein, The crystal oscillator starting module is further configured to start the crystal oscillator, generate a measurement clock signal, and send the measurement clock signal to the time counting module. The time counting module further comprises a crystal oscillator counter. The read-write control module is further configured to receive mode configuration information, generate a first mode instruction or a second mode instruction according to the mode configuration information, and send the first mode instruction or the second mode instruction to the time counting module and the arithmetic logic module. The time counting module is further configured to, in response to the first mode instruction, output a first conversion result and a second conversion result to the first data buffer module according to the first edge signal and the second edge signal. The time counting module is further configured to, in response to the second mode instruction, output a first conversion result according to the first edge signal, output a second conversion result according to the measurement clock signal after the first edge signal, output a third conversion result according to the second edge signal, and output a fourth conversion result according to the measurement clock signal after the second edge signal; and send the first conversion result, the second conversion result, the third conversion result, and the fourth conversion result to the first data buffer module. The crystal oscillator counter is further configured to, in response to the second mode instruction, count the measurement clock signal between the first edge signal and the second edge signal to obtain a clock count result and send the clock count result to the first data buffer module. The arithmetic logic module is further configured to, in response to the first mode instruction, obtain a digital arithmetic result according to a difference between the first conversion result and the second conversion result; and in response to the second mode instruction, obtain a digital arithmetic result according to the first conversion result, the second conversion result, the third conversion result, the fourth conversion result, and the clock count result.

6. The time-to-digital conversion circuit of claim 5, wherein, The self-calibration module is further configured to calibrate the crystal oscillator starting module according to a preset period.

7. The time-to-digital conversion circuit of claim 6, wherein, The self-calibration module is connected to the read-write control module, and the read-write control module is further configured to receive a calibration instruction and send the calibration instruction to the self-calibration module. The self-calibration module is further configured to, in response to the calibration instruction, calibrate the crystal oscillator starting module.

8. The time-to-digital conversion circuit of claim 7, wherein, The arithmetic logic module is specifically configured to obtain a crystal oscillator clock period of the clock signal of the crystal oscillator starting module; and divide a difference between the first conversion result and the second conversion result by the crystal oscillator clock period to obtain the digital arithmetic result.

9. The time-to-digital conversion circuit of claim 8, wherein, The arithmetic logic module is specifically configured to obtain a crystal clock period of a clock signal of the crystal oscillator starting module; calculate a first difference value of the first conversion result and the second conversion result, a second difference value of the third conversion result and the fourth conversion result, and subtract the second difference value from the first difference value, divide the result by the crystal clock period, and add a clock counting result to obtain the digital arithmetic result.

10. The time-to-digital conversion circuit of claim 9, wherein, Further comprising a second data buffer module; The arithmetic logic module is further configured to send the obtained digital arithmetic result to the second data buffer module; The read-write control module is further configured to read the digital arithmetic result in the second data buffer module.

11. The time-to-digital conversion circuit of claim 10, wherein, The read-write control module is further configured to send a crystal measurement instruction to the time counting module and the arithmetic logic module; The time counting module is further configured to, in response to the crystal measurement instruction, output a first conversion result and a second conversion result to the first data buffer module according to two edge signals corresponding to one period of the measurement clock signal; The arithmetic logic module is further configured to, in response to the crystal measurement instruction, read the first conversion result and the second conversion result in the first data buffer module and calculate a difference value to obtain the crystal clock period in inverter delay units.

12. The time-to-digital conversion circuit of claim 11, wherein, The self-calibration module is specifically configured to extract a system clock signal to obtain a first edge signal and a second edge signal and send them to the time counting module in the second mode instruction; Read the second data buffer module to obtain a digital arithmetic result as a system measurement result; calculate a ratio of the system measurement result and a preset standard result; and calibrate a clock of the crystal oscillator starting module according to the ratio.

13. A time-to-digital conversion method, characterized by, The time-to-digital conversion method is applied to the time-to-digital conversion circuit according to any one of claims 1-12, and the time-to-digital conversion method comprises: Each inverter of the ring oscillator obtains an output signal based on the counting enable signal; The latch unit sends the output signal of each inverter to the exclusive OR unit in response to the first edge signal or the second edge signal; The exclusive OR unit performs exclusive OR processing on the output signals of two adjacent inverters to obtain a plurality of output values and send them to the decoder; The coarse value counter counts rising and falling edges of the output signal of the last inverter to obtain a first value; The decoder decodes each of the output values to obtain a second value and send it to the adder; specifically, the decoder combines each of the received output values to obtain an exclusive OR output code; determines the position of the 1 code in the exclusive OR output code and converts it into the second value; The multiplier obtains the first value, converts it into a third value in inverter delay units, and sends it to the adder; The adder adds the second value and the third value to obtain the first conversion result corresponding to the first edge signal or the second conversion result corresponding to the second edge signal, and sends it to the first data buffer module; The arithmetic logic module reads the first conversion result and the second conversion result in the first data buffer module; calculates according to a difference value of the first conversion result and the second conversion result to obtain a digital arithmetic result.

14. The time-to-digital conversion method of claim 13, wherein, Further comprising: The read-write control module receives the pulse configuration instruction and sends it to the pulse generator. The read-write control module receives the edge extraction instruction and sends it to the edge detection module. The pulse generator generates a pulse signal according to the pulse configuration instruction. The edge detection module extracts the rising edge or falling edge of the pulse signal according to the edge extraction instruction to obtain the first edge signal, and extracts the rising edge or falling edge of the echo signal after reflection to obtain the second edge signal, and sends it to the latch unit.

15. The time-to-digital conversion method of claim 14, wherein, Further comprising: The signal filtering module filters the reflected echo signal and sends it to the edge detection module.

16. The time-to-digital conversion method of claim 15, wherein, Further comprising: The crystal oscillator starts to oscillate, generates a measurement clock signal and sends it to the time counting module; The read-write control module receives mode configuration information, generates a first mode instruction or a second mode instruction according to the mode configuration information, and sends it to the time counting module and the arithmetic logic module; The time counting module responds to the first mode instruction, outputs a first conversion result and a second conversion result according to the received first edge signal and second edge signal; or, in response to the second mode instruction, outputs a first conversion result according to the first edge signal, a second conversion result according to the measurement clock signal after the first edge signal, a third conversion result according to the second edge signal, and a fourth conversion result according to the measurement clock signal after the second edge signal; The crystal oscillator responds to the second mode instruction and counts the measurement clock signal between the first edge signal and the second edge signal to obtain a clock count result; The arithmetic logic module responds to the first mode instruction and obtains a digital arithmetic result according to the difference between the first conversion result and the second conversion result; or, in response to the second mode instruction, obtains a digital arithmetic result according to the first conversion result, the second conversion result, the third conversion result, the fourth conversion result and the clock count result.

17. The time-to-digital conversion method of claim 16, wherein, Further comprising: The self-calibration module performs clock calibration on the crystal oscillator start module according to a preset period.

18. The time-to-digital conversion method of claim 17, wherein, Further comprising: The read-write control module receives the calibration instruction and sends it to the self-calibration module; The self-calibration module responds to the calibration instruction of the read-write control module and performs clock calibration on the crystal oscillator start module.

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