SOC chip and electronic device

Abstract

A SOC chip and an electronic device are used for outputting a reset signal meeting system requirements. The SOC chip comprises a power supply circuit and a reset circuit; the power supply circuit is connected with the reset circuit; the power supply circuit is connected with a first power supply; according to preset reset parameters, a control signal is generated and sent to the reset circuit; the reset circuit is connected with a second power supply; when the second power supply is powered on and the control signal is received, the time for charging the internal capacitor by the second power supply and the charging current amplitude of the capacitor are adjusted; when the capacitor is charged to a set value, a reset signal is generated and output to other circuits in the SOC chip; wherein the power-on time of the first power supply is earlier than that of the second power supply. When the reset signal generated by the SOC chip does not meet the system requirements, the charging time and the charging current amplitude of the capacitor can be adjusted by controlling the control signal generated by the power supply circuit to adjust the charging speed of the capacitor, so as to output the reset signal meeting the system requirements.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a SOC chip and electronic device. Background Technology

[0002] The Power On Reset (POR) circuit generates a reset signal when the chip is powered on. The generated reset signal enables the internal digital and analog modules to complete the initialization and startup, ensuring that the internal circuitry of the chip can start safely within the acceptable power supply voltage range.

[0003] Currently, power-on reset circuits generally employ RC charging reset circuits. The reset threshold of an RC charging reset circuit is typically the inversion voltage of an inverter. Its architecture is simple, with low area and power consumption, and it can achieve a relatively fast response speed during power-on. However, due to chip manufacturing or other reasons, a mismatch may occur between the capacitor charging speed and the rise speed of the power supply voltage. This can lead to the reset signal triggering timing and amplitude not meeting requirements, and in severe cases, even preventing the generation of a reset signal, thus affecting the normal startup of the chip. Summary of the Invention

[0004] This application provides a SOC chip and electronic device for outputting a reset signal that meets system requirements.

[0005] In a first aspect, embodiments of this application provide a SOC chip, which includes a power supply circuit and a reset circuit.

[0006] The power supply circuit is connected to the reset circuit. The power supply circuit connects to a first power supply, generates a control signal based on preset reset parameters, and sends it to the reset circuit. The reset circuit connects to a second power supply. When the second power supply powers on and receives the control signal, it controls the timing of charging the internal capacitor and adjusts the charging current amplitude of the capacitor. When the capacitor is charged to a set value, it generates a reset signal and outputs the reset signal to other circuits within the SOC chip. The power-on time of the first power supply is earlier than that of the second power supply.

[0007] Using the aforementioned SOC chip, the power supply circuit and reset circuit within the SOC chip are used to generate the reset signal. The power supply circuit can be powered on before the second power supply connected to the reset circuit. After the second power supply powers on and successfully starts the power supply circuit, a control signal is generated according to the system's requirements for the reset signal and the preset reset parameters. After the second power supply powers on and receives the control signal, the reset circuit adjusts the charging timing and charging current amplitude of the capacitor, thereby adjusting the capacitor's charging speed and consequently adjusting the timing and amplitude of the generated reset signal. Therefore, in practical applications, when the reset signal generated internally by the SOC chip does not meet the system requirements, the above circuit can be used to adjust the capacitor's charging speed to output a reset signal that meets the system requirements.

[0008] In one possible design, the reset circuit includes a current regulation circuit, a capacitor, and a reset signal generation circuit.

[0009] The current regulation circuit is connected to the capacitor and is used to connect to the second power supply. When the second power supply is powered on and receives the control signal, it controls the timing of the second power supply charging the capacitor and adjusts the charging current amplitude of the capacitor. The reset signal generation circuit is connected to the capacitor and is used to generate the reset signal when the capacitor is charged to the set value, and send the reset signal to other circuits in the SOC chip.

[0010] In one possible design, the current regulation circuit includes a current mirror, multiple impedance modules, and multiple switches.

[0011] The first end of the current mirror is grounded through the plurality of impedance modules, the second end of the current mirror is used to connect to the second power supply, and the third end of the current mirror is grounded through the capacitor; the plurality of impedance modules are connected in series; the plurality of switches correspond one-to-one with the plurality of impedance modules, each switch is connected in parallel with the corresponding impedance module, and the control terminal of each switch is connected to the power supply circuit.

[0012] With the above design, based on the characteristics of the current mirror, the charging time and current amplitude of the capacitor are determined by the generation time and amplitude of the current in the branch where the impedance module is located. Therefore, the power supply circuit can control the on and off of multiple switches by controlling the control signal to control the timing of the current mirror connecting to the impedance module and the number of impedance modules connected, thereby controlling the generation time and current amplitude of the current in the branch where the impedance module is located, so as to adjust the charging time and charging speed of the capacitor, and further adjust the generation time and amplitude of the reset signal.

[0013] In one possible design, the current mirror includes a first current transmission tube and a second current transmission tube.

[0014] In this configuration, the source of the first current transmission transistor is connected to the second power supply, the drain of the first current transmission transistor is grounded through the plurality of impedance modules, and the gate of the first current transmission transistor is connected to the drain of the first current transmission transistor; the source of the second current transmission transistor is connected to the second power supply, the drain of the second current transmission transistor is grounded through the capacitor, and the gate of the second current transmission transistor is connected to the gate of the first current transmission transistor.

[0015] In one possible design, each impedance module includes an NMOS transistor, the gate of which is connected to the drain of the NMOS transistor.

[0016] In one possible design, each impedance module includes a PMOS transistor, the gate of which is connected to the drain of the PMOS transistor.

[0017] In one possible design, each impedance module includes a resistor.

[0018] In one possible design, the control signal includes multiple sub-control signals, each of which is a voltage signal and each sub-control signal is used to control the on and off of a switch.

[0019] In one possible design, the reset signal generation circuit includes an inverter, a delay circuit, and an XOR gate circuit.

[0020] The inverter's input terminal is connected to the capacitor, and its output terminal is connected to the input terminal of the delay circuit and the first input terminal of the XOR gate circuit. The output terminal of the delay circuit is connected to the second input terminal of the XOR gate circuit. The output terminal of the XOR gate circuit is used to output the reset signal.

[0021] Secondly, embodiments of this application provide an electronic device that may include a printed circuit board and a System-on-a-Chip (SOC) chip provided in the first aspect of this application and any possible design thereof. The SOC chip is mounted on the printed circuit board.

[0022] Furthermore, the technical effects of the second aspect and any of its possible designs can be found in the technical effects of different designs in the first aspect of the embodiments of this application, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of an RC charging reset circuit provided for related technologies;

[0025] Figure 2 A waveform diagram of a reset signal and power supply voltage provided for an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the structure of a SOC chip provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 1 ;

[0028] Figure 5 This is a schematic diagram of a current regulation circuit provided in an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the structure of a current mirror provided in an embodiment of this application;

[0030] Figure 7 A schematic diagram of the structure of an impedance module provided in this application embodiment. Figure 1 ;

[0031] Figure 8 A schematic diagram of the structure of an impedance module provided in this application embodiment. Figure 2 ;

[0032] Figure 9 A schematic diagram of the structure of an impedance module provided in this application embodiment. Figure 3 ;

[0033] Figure 10 A schematic diagram of a reset circuit provided in an embodiment of this application. Figure 2 . Detailed Implementation

[0034] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0036] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0038] Traditional power-on reset circuits often use RC charging reset circuits, see [link / reference]. Figure 1 The diagram shown is a schematic of a traditional RC charging reset circuit. Figure 1 As shown, the RC charging reset circuit mainly consists of a capacitor C, a resistor R, an inverter Z1, a delay circuit, and an XOR gate Z2. The working principle of the RC charging reset circuit is as follows: after the power supply voltage VDD is initially powered on, VDD gradually increases. VDD charges capacitor C through resistor R. When the voltage of capacitor C reaches the flip threshold of inverter Z1, inverter Z1 outputs a high-level signal. Due to the delay characteristic of the delay circuit, the input terminal of XOR gate Z2 connected to the delay circuit maintains a low-level signal state. At this time, the signal states of the two input terminals of XOR gate Z2 are different, and XOR gate Z2 outputs a high-level reset signal to other functional devices within the SOC chip, causing multiple functional circuits within the SOC chip to perform initialization operations. The corresponding waveforms of the power supply voltage VDD and the reset signal can be found in [reference needed]. Figure 2 As shown.

[0039] In practical applications, the timing of the reset signal output by the RC charging reset circuit is mainly controlled by the charging speed of capacitor C. The charging speed of capacitor C is related to the rise rate of the power supply voltage VDD, the resistance value of resistor R, and the parameters of capacitor C. When the charging speed of capacitor C does not match the rise rate of the power supply voltage VDD due to manufacturing or application environment, the timing and amplitude of the reset signal may not meet the requirements. In severe cases, the reset signal may not be generated at all, affecting the normal startup of the SOC chip.

[0040] Based on this, this application provides a SOC chip and an electronic device. The SOC chip has a built-in reset circuit and a power supply circuit to realize the reset function of the SOC chip. It can also adjust the charging time and charging current amplitude of the capacitor in the reset circuit according to the trigger time of the reset voltage of the SOC chip, so that the reset circuit generates a reset signal that meets the requirements at the power supply amplitude time required by the system.

[0041] See Figure 3 The diagram shown is a structural schematic of a SOC chip provided in an embodiment of this application. Figure 3 As shown, the SOC chip includes a power supply circuit and a reset circuit.

[0042] It should be noted that, Figure 3 The SOC chip structure shown is only an example. Figure 3 The power supply circuit and reset circuit of the SOC chip shown are only used to implement the reset function of the SOC chip. In actual applications, according to the functional requirements of the SOC chip, other functional devices, such as memory and protection circuits, may also be included in the SOC chip. This application does not impose any restrictions here.

[0043] The SOC chip can be any one of the following: CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose Graphics Processing Unit).

[0044] Specifically, the power supply circuit is connected to the reset circuit. The power supply circuit connects to the first power supply, generates a control signal based on preset reset parameters, and sends it to the reset circuit. The reset circuit connects to the second power supply. When the second power supply is powered on and receives the control signal, it controls the timing of charging the internal capacitor and adjusts the capacitor's charging current amplitude. When the capacitor is charged to a set value, it generates a reset signal and outputs it to other circuits within the SOC chip. The first power supply powers on earlier than the second power supply. The set value can be configured according to the structure of the reset circuit. For example, if the device connected to the capacitor's downstream end is an inverter, the set value is the inverter's inverting voltage. If the device connected to the capacitor's downstream end is a Schmitt trigger, the set value is the Schmitt trigger's toggling voltage. Of course, depending on the reset circuit's structure, other values ​​can also be used for the set value; this application does not impose further limitations on this.

[0045] Using the SOC chip provided in this application embodiment, the power supply circuit prioritizes the reset circuit startup, meaning the first power supply powers on before the second power supply. Furthermore, the power supply circuit pre-stores reset parameters. Therefore, before the second power supply powers on, the power supply circuit can generate a control signal using the pre-stored reset parameters, and control the operation of the reset circuit using the aforementioned control signal during the second power supply's power-on process. The reset parameters may include the amplitude of the capacitor C charging current and the charging time corresponding to the reset signal being triggered at different power supply voltages. For example, if the system requires the SOC chip to trigger a reset signal when the second power supply voltage rises to 50%, then based on the aforementioned reset parameters, the amplitude of the capacitor C charging current and the charging time corresponding to the reset signal being triggered when the second power supply voltage rises to 50% are determined. The aforementioned parameters are used to generate a control signal, and this control signal controls the charging time and the amplitude of the charging current of capacitor C in the reset circuit, causing capacitor C to charge to the set value when the second power supply voltage rises to 50%, thus triggering the reset signal.

[0046] It should be noted that the method of triggering the reset signal when the second power supply rises to 50% is only an example. In actual applications, depending on system requirements, the reset circuit can also be controlled to trigger the reset signal at other times by configuring control signals. The reset parameters can be pre-stored by the SOC chip or set by the host computer of the SOC chip; this application does not impose further limitations on this.

[0047] The generation process of the reset signal will be explained in detail below, taking into account the structure of the reset circuit.

[0048] In some embodiments, see Figure 4As shown, the reset circuit may include a current regulation circuit, a capacitor C, and a reset signal generation circuit. The current regulation circuit is connected to the capacitor C and a second power supply. When the second power supply is powered on and receives a control signal, the current regulation circuit controls the timing of the second power supply charging the capacitor C and adjusts the charging current amplitude of the capacitor C. The reset signal generation circuit is connected to the capacitor C and generates a reset signal when the capacitor C is charged to a set value, and sends the reset signal to other devices within the SOC chip.

[0049] In some implementations, see Figure 5 As shown, the current regulation circuit includes a current mirror, multiple impedance modules, and multiple switches K. The first terminal of the current mirror is grounded through the multiple impedance modules, the second terminal of the current mirror is connected to a second power supply, and the third terminal of the current mirror is grounded through a capacitor; the multiple impedance modules are connected in series. Each switch K corresponds one-to-one with a specific impedance module, and each switch K is connected in parallel with its corresponding impedance module. The control terminal of each switch K is connected to the power supply circuit.

[0050] In practical applications, each impedance module is connected in parallel with a switch K. When the switch K is turned on, the parallel impedance modules can be short-circuited. Therefore, by controlling the on and off of multiple switches K, the number of impedance modules connected in series at the first input terminal of the current mirror can be controlled.

[0051] Specifically, the first terminal of the current mirror serves as its current input terminal, and the third terminal serves as its current output terminal. The current in capacitor C, connected to the third terminal, is determined by the current amplitude at the first terminal. Therefore, the timing of current generation at the current input terminal can be controlled by turning switch K on and off, thus controlling the timing of capacitor C's charging. Similarly, the number of impedance modules connected to the first terminal of the current mirror can be controlled by turning switch K on and off, thereby controlling the current amplitude at the current input terminal and further controlling the charging current amplitude of capacitor C. Thus, by adjusting the charging timing and charging current threshold of capacitor C, the timing of capacitor C charging to a set value can be controlled, further controlling the timing and amplitude of the reset signal trigger, and outputting a reset signal that meets system requirements.

[0052] In this application, the two ends of each switch K in the current regulation circuit are connected to the two ends of the corresponding impedance module. The control terminal of each switch K can be connected to the power supply circuit through an independent line. Therefore, the control signal generated by the power supply circuit can be a level signal, and the power supply circuit can use the above-mentioned level signal to control the conduction and cutoff of each switch K. It should be understood that there are multiple switches K in the current regulation circuit. Therefore, in order to accurately control the conduction and cutoff of each switch K, the control signal includes multiple sub-control signals, each of which can control the conduction and cutoff of one switch K. Among them, each switch K can be turned on when receiving a high-level signal and turned off when receiving a low-level signal. Each switch K can also be turned on when receiving a low-level signal and turned off when receiving a high-level signal, depending on the device type of the switch K. This application does not make specific limitations here.

[0053] The following section details the process of adjusting the charging timing and charging current amplitude of capacitor C, taking into account the structure of the current mirror, impedance module, and reset signal generation circuit.

[0054] In some embodiments, the current mirror includes a first current transmission tube T1 and a second current transmission tube T2. See also Figure 6 As shown, the source of the first current transmission transistor T1 is connected to the second power supply VCC, the drain of the first current transmission transistor T1 is grounded through multiple impedance modules, and the gate of the first current transmission transistor T1 is connected to the drain of the first current transmission transistor T1; the source of the second current transmission transistor T2 is connected to the second power supply VCC, the drain of the second current transmission transistor T2 is grounded through capacitor C, and the gate of the second current transmission transistor T2 is connected to the gate of the first current transmission transistor T1.

[0055] It should be noted that, Figure 6 The current mirror shown is a structural example when the current transmission transistor is an NMOS transistor. In practical applications, the current mirror can also use other switching transistors or other circuit topologies. For example, the current transmission transistor in the current mirror can be a PMOS transistor. This application does not impose any further restrictions here.

[0056] In some implementations, each impedance module includes an NMOS transistor, see [link to relevant documentation]. Figure 7 As shown, the gate of the NMOS transistor is connected to the drain of the NMOS transistor.

[0057] See Figure 7 As shown, a switch K is connected in parallel across the drain and source terminals of each NMOS transistor. The control terminal of the switch K can be connected to the power supply circuit via an independent transmission line and receive the sub-control signal sent by the power supply circuit.

[0058] In practical applications, an NMOS transistor will only conduct when the voltage at its control terminal meets the turn-on voltage Vth. Different NMOS transistors can have different turn-on voltages Vth depending on their model, allowing multiple impedance modules to be configured with NMOS transistors using different turn-on voltages Vth. The power supply circuit can generate a voltage signal with a specific turn-on voltage Vth amplitude (i.e., a sub-control signal) based on the system's reset signal requirements and stored reset parameters. This sub-control signal is then output to the switch K connected in parallel with the corresponding impedance module to control the number of NMOS transistors connected to the first terminal of the current mirror, further controlling the current amplitude at the current input terminal of the current mirror, thereby adjusting the charging current amplitude of capacitor C. Furthermore, the current mirror can only mirror the current in the series path of the impedance modules proportionally to the branch containing capacitor C after current has been established, further adjusting the charging current amplitude of capacitor C. Therefore, the power supply circuit can also adjust the charging timing of capacitor C by controlling the timing of the sub-control signal transmission.

[0059] It should be noted that, Figure 7 The impedance module structure shown is for illustrative purposes only. In practical applications, other components can also be used for the impedance module.

[0060] See one example. Figure 8 As shown, the impedance module can use a PMOS transistor, with the gate and drain of the PMOS transistor connected together. It should be noted that the process of controlling the current at the first terminal of the current mirror using a PMOS transistor is the same as that using an NMOS transistor, only the startup voltage amplitude is different; this will not be repeated here.

[0061] In another example, see Figure 9 As shown, the impedance module can be a resistor.

[0062] In practical applications, the resistance values ​​in each impedance module can be the same or different. The power supply circuit can generate multiple sub-control signals based on the system's requirements for the reset signal and the stored reset parameters. These sub-control signals control the number of resistors connected to the first terminal of the current mirror. When the number of input resistors changes, the current amplitude at the first terminal of the current mirror also changes, thereby controlling the charging current amplitude of capacitor C. Furthermore, the aforementioned sub-control signals can be pulse signals. By controlling the duty cycle of the pulse signals, the timing of connecting the resistors to the first terminal of the current mirror can be adjusted, further controlling the charging timing of capacitor C.

[0063] It should be noted that, Figures 7 to 9 The impedance module structure shown is only an example. In actual applications, the impedance module can also use other devices with the above functions. This application does not impose any restrictions here.

[0064] See Figure 10As shown, the structure of the reset signal generation circuit can adopt the industry-standard reset circuit structure. For example, the reset signal generation circuit includes an inverter Z1, a delay circuit, and an XOR gate circuit Z2. The input terminal of the inverter Z1 is connected to the capacitor C, and the output terminal of the inverter Z1 is connected to the input terminal of the delay circuit and the first input terminal of the XOR gate circuit Z2. The output terminal of the delay circuit is connected to the second input terminal of the XOR gate circuit Z2. The output terminal of the XOR gate circuit Z2 is used to output the reset signal.

[0065] It should be noted that, Figure 10 The reset signal generation circuit structure shown is only an example. In actual applications, the reset circuit can also adopt other circuit topologies commonly used in the industry. This application does not impose any restrictions on it.

[0066] See also Figure 10 As shown, when the second power supply VDD is powered on, the first terminal of the current mirror is connected to the impedance module and generates current. Based on the working characteristics of the current mirror, the current at the first terminal of the current mirror is mirrored proportionally to the third terminal connected to capacitor C and charges capacitor C. Furthermore, the current amplitude in the branch where capacitor C is located is independent of the rise rate of the second power supply VDD. Therefore, the problem of the reset signal not meeting the requirements due to the mismatch between the charging speed of capacitor C and the rise rate of the second power supply VDD can be effectively eliminated. As the charging time increases, the voltage across capacitor C gradually increases. When capacitor C is charged to the set value, the voltage at the input terminal of inverter Z1 reaches the inversion voltage, and the output of inverter Z1 is inverted from a low level to a high level. At this time, the first input terminal of the XOR gate Z2 is in a high level state, while the second input terminal of the XOR gate Z2 remains in a low level state due to the delay characteristics of the delay circuit. The different states of the two input terminals of the XOR gate Z2 result in the output of a high-level reset signal, which is then output to other devices in the SOC chip to control the initialization operation of these devices.

[0067] In conjunction with the above description, this application also provides an electronic device, which may include a printed circuit board (PCB) and the aforementioned SOC chip, wherein the SOC chip is mounted on the PCB. The structure of the SOC chip can be found in the foregoing description and will not be repeated here.

[0068] In one example, the SOC chip can be soldered onto the PCB.

[0069] In another example, to reduce the maintenance cost of electronic devices, a socket for mounting a SOC chip is soldered onto the PCB, and the SOC chip can be plugged into the socket.

[0070] It should be noted that other components are also provided on the PCB. For example, the peripheral circuit of the SOC chip is soldered on the PCB, and other chips, such as power chips, can also be soldered on the PCB. This application does not make specific settings here.

[0071] In some implementations, if the electronic device includes multiple components, the electronic device may also include multiple PCBs, each PCB having a connector, and the multiple PCBs can be connected through the connectors.

[0072] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0073] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A SOC chip, characterized by, The application relates to a power supply circuit and a reset circuit. The power supply circuit is connected with the reset circuit, the power supply circuit is used for being connected with a first power supply, a control signal is generated according to preset reset parameters and is sent to the reset circuit. The reset circuit is used for being connected with a second power supply, when the second power supply is powered on and the control signal is received, the time for charging an internal capacitor by the second power supply and the amplitude of the charging current of the capacitor are adjusted, a reset signal is generated when the capacitor is charged to a set value, and the reset signal is output to other circuits in the SOC chip. The reset circuit comprises a current adjusting circuit, a capacitor and a reset signal generating circuit. The current adjusting circuit is connected with the capacitor, the current adjusting circuit is used for being connected with the second power supply, when the second power supply is powered on and the control signal is received, the time for charging the capacitor by the second power supply and the amplitude of the charging current of the capacitor are adjusted. The reset signal generating circuit is connected with the capacitor, and is used for generating the reset signal when the capacitor is charged to the set value and sending the reset signal to other circuits in the SOC chip. The current adjusting circuit comprises a current mirror, a plurality of impedance modules and a plurality of switches. The first end of the current mirror is grounded through the plurality of impedance modules, the second end of the current mirror is used for being connected with the second power supply, and the third end of the current mirror is grounded through the capacitor. The plurality of impedance modules are connected in series. The plurality of switches correspond to the plurality of impedance modules one by one, each switch is connected in parallel with a corresponding impedance module, and the control end of each switch is connected with the power supply circuit. The control signal comprises a plurality of sub-control signals, each sub-control signal is a voltage signal, and each sub-control signal is used for controlling the conduction and turn-off of one switch. The current mirror comprises a first current transmission tube and a second current transmission tube.

2. The SOC chip of claim 1, wherein, The source of the first current transmission tube is used for being connected with the second power supply, the drain of the first current transmission tube is grounded through the plurality of impedance modules, and the gate of the first current transmission tube is connected with the drain of the first current transmission tube. The source of the second current transmission tube is used for being connected with the second power supply, the drain of the second current transmission tube is grounded through the capacitor, and the gate of the second current transmission tube is connected with the gate of the first current transmission tube. Each impedance module comprises an NMOS tube, and the gate of the NMOS tube is connected with the drain of the NMOS tube.

3. The SOC chip of claim 1, wherein, Each impedance module comprises a PMOS tube, and the gate of the PMOS tube is connected with the drain of the PMOS tube.

4. The SOC chip of claim 1, wherein, Each impedance module comprises a resistor.

5. The SOC chip of claim 1, wherein, The reset signal generating circuit comprises an inverter, a delay circuit and an XOR gate circuit.

6. The SOC chip of claim 1, wherein, The input end of the inverter is connected with the capacitor, the output end of the inverter is connected with the input end of the delay circuit and the first input end of the XOR gate circuit. The output end of the delay circuit is connected with the second input end of the XOR gate circuit. The output end of the XOR gate circuit is used for outputting the reset signal. ​ 7. An electronic device, comprising: A printed circuit board including the SOC chip according to any one of claims 1 to 6 mounted on the printed circuit board.

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