Multi-cycle path synchronization circuit

Abstract

The invention belongs to the technical field of digital chip system design, and provides a multi-cycle path synchronization circuit which comprises at least one multi-cycle path synchronization sub-circuit. Each multi-cycle path synchronization sub-circuit comprises a counter, combinational logic, a first-class trigger group, a second-class trigger group located in front of a clock gate, the clock gate and a plurality of second-class trigger groups located in hard cores, and a chip is subjected to hard core division to obtain a plurality of hard cores; and each multi-cycle path synchronization sub-circuit is provided with a second type trigger group in each hard core. And a trigger group is inserted into a related path, so that the time sequence is optimized without influencing the area and the performance.

Description

Technical Field This disclosure belongs to the field of digital chip system design technology, and in particular relates to a multi-cycle path synchronization circuit. Background Technology

[0001] In chip architecture design, the chip is divided into multiple different modules based on its functions. Because different modules have different requirements for performance, power consumption, and timing, they operate at different frequencies, necessitating clock division. Two common frequency division methods in chip design are register division and Integrated Clock Gating (ICG) division.

[0002] The following explanation uses frequency division by two as an example: When frequency division is implemented through a register, the relevant circuitry and timing are as follows: Figure 1 and Figure 2 As shown: Figure 1 This is a frequency divider circuit diagram related to a two-way frequency divider. Figure 2 This is a timing diagram related to a 2:1 divide-by-2 clock. In this divide-by-2 mode, the source clock (clk_src) and the 2:1 divide-by-2 clock (clk_div2) in the system design are usually asynchronous. Therefore, when registers in these two different clock domains exchange data, clock domain crossing (CDC) signal processing must be performed.

[0003] When using ICG to implement frequency division by two, the corresponding circuit diagram and timing diagram are as follows: Figure 3 and Figure 4 As shown: Figure 3 This is a circuit diagram for a frequency divider ICG circuit. Figure 4 This is the timing diagram for the ICG divide-by-2 clock. With this circuit design, the source clock (clk_src) and the divide-by-2 clock (clk_div2) can be synchronized. To ensure that data at different frequencies does not affect normal functionality or disrupt timing stability during interaction, a clock division enable signal (clk_en) is used as a data sampling point and to control the data hold time.

[0004] When sampling data from a low-frequency clock using a high-frequency clock, each sampling requires an interval of multiple clock cycles (the specific number of intervals is determined by the division ratio, which is determined by the periodic characteristics of the clock division enable signal clk_en). This sampling method is called multi-cycle path sampling.

[0005] When data exchange occurs at different clock frequencies, this multi-cycle path synchronous sampling method offers significant advantages over conventional asynchronous sampling: 1) Reduced power consumption: After ICG processing, the power consumption of the clock tree on the relevant path is significantly reduced when the clock signal is transmitted to the clock terminals of all registers in the clock domain, thereby effectively reducing the overall power consumption of the chip. 2) Improved performance: In conventional asynchronous sampling scenarios between different frequencies, CDC processing is necessary; especially in multi-bit bus interactions, asynchronous FIFO memory is required to achieve cross-clock domain processing, and asynchronous FIFO often requires multiple clock cycles to complete a single data exchange. However, in this multi-cycle path synchronous circuit design, different clock frequencies are synchronous, and the appropriate sampling point can be determined simply by using the clock division enable signal (clk_en). Taking a 2-fold division as an example, only one additional high-frequency clock cycle is needed to complete multi-bit data exchange between different clock frequencies. Therefore, the multi-cycle path synchronous circuit can significantly improve the performance of data exchange to a certain extent.

[0006] Although multi-cycle path synchronization circuit design can significantly improve the power consumption and performance of the entire chip, the clock divider enable signal (clk_en) needs to be generated from the source clock (clk_src) and sampled by registers in the same clock domain. This poses a certain challenge to the overall timing of the chip, especially in application scenarios with large chip area and high maximum operating frequency. Summary of the Invention

[0007] To address the aforementioned issues, this disclosure provides a multi-cycle path synchronization circuit that divides the hard core and inserts flip-flop groups on the corresponding paths, thereby resolving the timing problems introduced by the need for high-frequency clock sampling for frequency division enable.

[0008] This invention provides a multi-cycle path synchronization circuit, comprising at least one multi-cycle path synchronization sub-circuit; each multi-cycle path synchronization sub-circuit includes: The chip consists of a counter, combinational logic, a first-type flip-flop group, a second-type flip-flop group located before the clock gating, a clock gating, and multiple second-type flip-flop groups located within the hard core. The chip is divided into multiple hard cores. Each multi-cycle path synchronization sub-circuit has a second-type flip-flop group within each hard core. The counter has its input connected to the source clock clk_src and its output connected to the input of combinational logic. Combinational logic whose output is connected to the input of the first type of flip-flop group; The first type of flip-flop group has its clock input connected to the source clock clk_src, and its output connected to the input of the second type of flip-flop group located before the clock gating and the input of the second type of flip-flop group located inside the hard core, respectively. The second type of flip-flop group, located before the clock gating, has its clock input connected to the source clock clk_src and its output connected to the gating enable terminal of the clock gating. The clock gating has its clock input connected to the source clock clk_src and its output output is the frequency divider signal clk_div. The second type of flip-flop group located inside the hard core has its clock input connected to the source clock clk_src, and its output output is a clock divider enable signal.

[0009] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the number of flip-flops inside the second type of flip-flop group located before the clock gate is the same as the number of flip-flops inside the second type of flip-flop group located inside the hard core.

[0010] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the number of internal flip-flops in any two second-type flip-flop groups located inside the hard core is the same.

[0011] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the specific number of flip-flops in the first type of flip-flop group is determined based on the total number of hard cores in the chip and the timing of the corresponding paths of these hard cores.

[0012] Furthermore, the maximum total number of flip-flops in the first type of flip-flop group is N = A(A+1) / 2, where A is the number of hard cores.

[0013] Furthermore, if multiple hard cores are placed at a distance less than a pre-defined distance, a set of triggers is reused.

[0014] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the number of flip-flops in the second type of flip-flop group located inside the hard core is determined according to the timing situation inside the hard core.

[0015] Furthermore, the number of triggers inside the second type of trigger group located inside the hard core is 1 or 2.

[0016] Furthermore, within the same multi-cycle path synchronization sub-circuit, the chip is hard-core divided according to function or area, and it is necessary to ensure that all flip-flops operating at the highest clock frequency and having multi-cycle path interaction are covered by each hard core.

[0017] Furthermore, each multi-cycle path synchronization sub-circuit corresponds to a frequency division ratio.

[0018] Compared with the prior art, this disclosure has the following advantages: 1. Because of the accurate insertion of the first type of flip-flop group / second type of flip-flop group, the sampling path of the high-frequency clock inside the hard core to the clock division enable signal clk_en is shortened, thereby optimizing the timing problem. Therefore, the timing problem introduced by the need for high-frequency clock sampling for the division enable in the multi-cycle path synchronous circuit structure is solved. For example, originally the high-frequency clock inside each hard core A0 / A1 / ... / An needed to sample clk_en0, but after sampling this invention, the high-frequency clock inside each hard core only needs to sample clk_en2b0 / clk_en2b1 / ... / clk_en2bn. 2. When using this architecture for large-scale chip design, the presence of Clock Gating (ICG) eliminates the dynamic power consumption introduced by the clock tree when the clock enable is low, thereby reducing the overall dynamic power consumption of the chip. Specifically, the divider signal clk_div drives tens of thousands of flip-flops throughout the chip, and the connection of clk_div to each flip-flop also forms tens of thousands of clock trees. ICG can eliminate a portion of the dynamic power consumption of the clock tree itself (when the clock enable is low). 3. When using this architecture for large-scale chip design, the structure of the multi-cycle synchronous circuit means that data sampling between different frequencies does not require complex CDC operations, which reduces data path delay and thus improves the overall performance of the chip.

[0019] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 The circuit for dividing the frequency by two when using a register is shown; Figure 2 The timing diagram for frequency division by two is shown; Figure 3 This illustrates a divide-by-two circuit for clock-gated frequency division; Figure 4 The timing diagram for clock-gated frequency division by two is shown; Figure 5 A schematic diagram of a multi-cycle path synchronization circuit according to an embodiment of the present disclosure is shown; Figure 6 A first type of trigger group according to an embodiment of the present disclosure is shown; Figure 7 A schematic diagram of another multi-cycle path synchronization circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] like Figure 5 As shown, this is a multi-cycle path synchronization circuit provided in an embodiment of this disclosure, comprising a multi-cycle path synchronization sub-circuit corresponding to one clock path; the multi-cycle path synchronization sub-circuit includes: The chip comprises a counter, combinational logic, a first type of flip-flop group, a second type of flip-flop group located before the clock gating, a clock gating, and multiple second type of flip-flop groups located within a hard core. Multiple hard cores are obtained after hard core partitioning of the chip. Each multi-cycle path synchronization sub-circuit has one second type of flip-flop group within each hard core. In this application, the first type of flip-flop group and the second type of flip-flop group are used for distinction; the first type of flip-flop group is equivalent to the first flip-flop group, and the second type of flip-flop group is equivalent to the second flip-flop group.

[0024] The counter has its input connected to the source clock clk_src and its output connected to the input of combinational logic. Combinational logic whose output is connected to the input of the first type of flip-flop group; The first type of flip-flop group has its clock input connected to the source clock clk_src, and its output connected to the input of the second type of flip-flop group located before the clock gating and the input of the second type of flip-flop group located inside the hard core, respectively. The second type of flip-flop group, located before the clock gating, has its clock input connected to the source clock clk_src and its output connected to the gating enable terminal of the clock gating. The clock gating has its clock input connected to the source clock clk_src and its output output is the frequency divider signal clk_div. The second type of flip-flop group located inside the hard core has its clock input connected to the source clock clk_src, and its output output is a clock divider enable signal.

[0025] The first / second type of trigger group operates normally, meaning the output of the previous stage trigger is connected to the input of the next stage trigger.

[0026] The reasons for this difference compared to the first type of trigger group in the prior art are explained below: If the clock division enable signal (clk_en0) output by the counter is directly sent to each hard core, then... Figure 5 Due to the limited area of ​​the chip, the placement of each hard core in the chip is random, and the counter may be composed of multiple flip-flops. Therefore, there will be many paths from the flip-flops in the counter to each hard core, and it is impossible to ensure that the timing of each path is satisfied. In order to ensure that the timing of each path is satisfied, a first type of flip-flop group needs to be added.

[0027] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the specific number of flip-flops in the first type of flip-flop group is determined based on the total number of hard cores in the chip and the timing of the corresponding paths of these hard cores.

[0028] Here, the number of hard cores depends entirely on the overall chip area and functional division. If the chip area is large, resulting in a large number of hard cores, then without type I flip-flops, then... Figure 5 In combinational logic, a single clock enable signal needs to be connected to various hard cores. Since each hard core is located differently, the path length varies, resulting in inconsistent timing across paths. This makes it difficult to ensure that the timing of each path meets expectations. Introducing a first-type flip-flop group allows adjusting the path length by changing the position of the flip-flops, thus ensuring that each path meets timing expectations. Different numbers of first-type flip-flops provide different movement points, facilitating timing adjustments during static timing analysis (STA).

[0029] As above Figure 6 As shown, the area within the dashed box represents the first type of flip-flop group. The different physical distances between the three hard cores A0 / A1 / A2 and the combinational logic that generates the clock divider enable signal clk_en result in varying transmission path lengths for the clk_en signal, ultimately causing differences in the timing performance of each hard core. Introducing the first type of flip-flop group ensures that each hard core A0 / A1 / A2 has a corresponding flip-flop, effectively shortening the transmission path of the clk_en signal for each hard core and improving timing consistency.

[0030] Furthermore, it is necessary to ensure that the combinational logic generating the clock divider enable signal clk_en has the same number of flip-flops across all hard cores. The maximum total number of flip-flops in the first type of flip-flop group is N = A + (A-1) + (A-2) + ... + 1 = A(A+1) / 2, where A is the number of hard cores. If multiple hard cores are placed very close together (less than a pre-defined distance), a set of flip-flops can be reused, such as... Figure 6 The hard cores A0 and B in the system reuse a set of triggers.

[0031] The following explains why a second type of flip-flop group is added inside the hard core compared to existing technologies, and a second type of register group is also added before the external clock gating: The second type of flip-flop group inside the hard block is used to solve timing problems caused by path delays and combinational logic delays within the hard block. This allows the backend Place and Route (PR) to place the second type of flip-flop group as close as possible to the clock divider enable signal (clk_en1) output by the external first type of flip-flop group during physical implementation, thereby reducing path delays outside the hard block. The number of flip-flops in the second type of flip-flop group depends on the timing characteristics within the hard block. Another set of second type flip-flops placed before the clock gating ensures that the clock divider enable signal (clk_en2a) entering the clock gating is completely synchronized with the final clock divider enable signal (clk_en2b0…clk_en2bn) generated internally by the hard block, thus guaranteeing the correctness of the function when modules in two different clock domains perform multi-cycle path sampling. Furthermore, the number of second type flip-flop groups within multiple hard blocks must be exactly the same to ensure functional consistency and correctness.

[0032] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the number of flip-flops inside the second type of flip-flop group located before the clock gate is the same as the number of flip-flops inside the second type of flip-flop group located inside the hard core.

[0033] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the number of internal flip-flops in any two second-type flip-flop groups located inside the hard core is the same.

[0034] Furthermore, in the same multi-cycle path synchronizing sub-circuit, the number of flip-flops in the second type of flip-flop group located inside the hard core is determined according to the timing situation inside the hard core.

[0035] The function of the second type of flip-flop group is similar to that of the first type. Many flip-flops within the hard core need to sample the clock divider enable signal clk_en. The path length of this clock divider enable signal clk_en to each flip-flop varies, resulting in varying timing characteristics. The existence and number of second-type flip-flop groups can be flexibly rearranged to resolve timing issues along each path. Because the hard core itself is relatively small compared to the entire chip, and the arrangement of each flip-flop is limited, the second-type flip-flop group typically contains only 1-2 flip-flops.

[0036] Specifically, in the chip design flow, hard cores typically perform DC (design compiler) synthesis and place-and-route implementation independently. For timing optimization, inserting one flip-flop can be tried first: if the timing of the relevant paths converges after insertion, the design requirements are met; if timing violations still exist in some related paths, two flip-flops can be inserted to further verify the timing convergence effect by increasing the timing margin. Furthermore, in the same multi-cycle path synchronization sub-circuit, the chip is divided into hard cores according to function or area, and it is necessary to ensure that all flip-flops operating at the highest clock frequency and with multi-cycle path interactions are covered by each hard core.

[0037] like Figure 7 As shown, it is a multi-cycle path synchronization circuit provided in the embodiment of this disclosure, which includes two multi-cycle path synchronization sub-circuits, corresponding to two clocks respectively divided by 2 and 3 of the source clock clk_src; one multi-cycle path synchronization sub-circuit corresponds to one division ratio; when there are at least two multi-cycle path synchronization sub-circuits, any two multi-cycle path synchronization sub-circuits work independently.

[0038] In practical applications, it is only necessary to ensure Figure 7 The number of flip-flops in a second-type flip-flop group of the same color must be exactly the same. The number of registers in a second-type flip-flop group of different colors can be adjusted according to the actual situation.

[0039] In actual use, the chip may have multiple clock paths internally. For specific multi-cycle path synchronization circuits, please refer to [reference needed]. Figure 5 and Figure 7 You can get it immediately.

[0040] In the embodiments of this disclosure, the chip is hard-partitioned and trigger groups are inserted on the relevant paths, which can optimize the timing without affecting the chip area and performance.

[0041] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A multi-cycle path synchronization circuit, characterized in that, The multi-cycle path synchronization circuit comprises at least one multi-cycle path synchronization sub-circuit, and each multi-cycle path synchronization sub-circuit comprises: a counter, combinational logic, a first type of flip-flop group, a second type of flip-flop group before a clock gate, the clock gate and a plurality of second type of flip-flop groups inside the hard cores, wherein the chip is divided into a plurality of hard cores after hard core division; each multi-cycle path synchronization sub-circuit has a second type of flip-flop group inside each hard core; a counter, whose input end is connected to a source clock clk_src, and whose output end is connected to the input end of the combinational logic; combinational logic, whose output end is connected to the input end of the first type of flip-flop group; the first type of flip-flop group, whose clock input end is connected to the source clock clk_src, and whose output end is connected to the input end of the second type of flip-flop group before the clock gate and the input end of each second type of flip-flop group inside the hard cores, respectively; the second type of flip-flop group before the clock gate, whose clock input end is connected to the source clock clk_src, and whose output end is connected to the gate enable end of the clock gate; the clock gate, whose clock input end is connected to the source clock clk_src, and whose output end outputs a divided clock signal clk_div; the second type of flip-flop group inside the hard cores, whose clock input end is connected to the source clock clk_src, and whose output end outputs a clock division enable signal.

2. The multi-cycle path synchronization circuit of claim 1, wherein, In the same multi-cycle path synchronization sub-circuit, the number of flip-flops inside the second type of flip-flop group before the clock gate is the same as the number of flip-flops inside the second type of flip-flop group inside the hard cores.

3. The multi-cycle path synchronous circuit of claim 1, wherein, In the same multi-cycle path synchronization sub-circuit, the number of flip-flops inside any two second type of flip-flop groups inside the hard cores is the same.

4. The multi-cycle path synchronization circuit of claim 1, wherein, In the same multi-cycle path synchronization sub-circuit, the specific number of flip-flops in the first type of flip-flop group is determined according to the number of hard cores of the whole chip and the timing conditions of the paths corresponding to the hard cores.

5. The multi-cycle path synchronous circuit of claim 1, wherein, The maximum total number of flip-flops in the first type of flip-flop group is N=A(A+1) / 2, where A is the number of hard cores.

6. The multi-cycle path synchronization circuit of claim 1, wherein, If the placement positions of the plurality of hard cores are less than a pre-set distance, a set of flip-flops is reused.

7. The circuit of claim 1, wherein, In the same multi-cycle path synchronization sub-circuit, the number of flip-flops inside the second type of flip-flop group inside the hard cores is determined according to the timing conditions inside the hard cores.

8. The multi-cycle path synchronization circuit of claim 7, wherein, The number of flip-flops inside the second type of flip-flop group inside the hard cores is 1 or 2.

9. The circuit of claim 1, wherein, In the same multi-cycle path synchronization sub-circuit, the chip is divided into hard cores according to functions or areas, and it is necessary to ensure that all flip-flops working at the highest clock frequency and having multi-cycle path interactions are covered by each hard core.

10. The multi-cycle path synchronous circuit of claim 1, wherein, One multi-cycle path synchronization sub-circuit corresponds to one division ratio.

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