Dynamic clamping for power level ground bomb protection in single layer modulation

Abstract

The invention relates to dynamic clamping for power level earth spring protection in single layer modulation. In one example, an apparatus includes a transistor (604), a switch (602), and a control circuit (610). The transistor (604) has a first current connection (604c), a second current connection (604b), and a transistor control connection (604a). The switch (602) is coupled between the transistor control terminal (604a) and a reference terminal (606), the switch (602) having a switch control input (602a). The control circuit (610) has a control input and a control output, the control output coupled to the switch control input (602a), and the control input coupled to at least one of the transistor control terminal (604a), the first current terminal (604c), or the second current terminal (604b).

Description

[0001] Cross-reference to related applications

[0002] This non-provisional application is a continuation to U.S. Patent Application No. 63 / 666,730, filed July 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application generally relates to electronic devices, and more specifically, to dynamic clamping for power level ground spring protection in single-layer modulation. Background Technology

[0004] Electronic devices may include high-speed electronic components with high-frequency switching events and low-speed electronic components that do not have high-frequency switching events or otherwise operate at lower frequencies. Switching noise can couple from high-speed electronic components to low-speed electronic components, and switching noise may adversely affect the operation of low-speed electronic components. Summary of the Invention

[0005] In one example, a device includes a transistor, a switch, and a control circuit. The transistor has a first current terminal, a second current terminal, and a transistor control terminal. The switch is coupled between the transistor control terminal and a reference terminal, and the switch has a switch control input. The control circuit has a control input and a control output, the control output being coupled to the switch control input, and the control input being coupled to at least one of the transistor control terminal, the first current terminal, or the second current terminal.

[0006] In one example, a device includes an amplifier, a first power stage, a second power stage, a modulator, and a clamping circuit. The amplifier has an amplifier input and an amplifier output. The first power stage has a first power stage input and a first power stage output, the first power stage input being coupled to the amplifier output. The clamping circuit is coupled between the first power stage input and a reference terminal, the clamping circuit having a clamping control input coupled to the first power stage. The modulator has a modulator input and a modulator output, the modulator input being coupled to the amplifier input. The second power stage has a second power stage input and a second power stage output, the second power stage input being coupled to the modulator output. Attached Figure Description

[0007] Figure 1A and 1B This is a schematic diagram illustrating an example of an audio system.

[0008] Figure 2 and 3 It is shown Figure 1A and 1B A schematic diagram of an additional example of an audio system.

[0009] Figure 4 This is a schematic diagram illustrating an example of switching noise coupled into an audio system.

[0010] Figure 5A and 5B The graph includes examples illustrating the effects of switching noise coupled into an audio system.

[0011] Figure 6 This is a schematic diagram illustrating an example of a clamping circuit used to mitigate the effects of switching noise.

[0012] Figure 7 It is shown Figure 6 A schematic diagram illustrating an example of the internal components of the clamping circuit.

[0013] Figure 8 and 9 This is a schematic diagram illustrating an example of a clamping circuit used to mitigate the effects of switching noise.

[0014] Figure 10A , 10B Figures 1 and 10C are schematic diagrams illustrating an example of a clamping circuit used to mitigate the effects of switching noise.

[0015] Figure 11 It is shown Figure 6-10C A schematic diagram illustrating an example of the internal components of the clamping circuit.

[0016] Figure 12 Includes showing Figure 6-10C A graph illustrating an example of the operation of the clamping circuit.

[0017] Figure 13 This is a flowchart illustrating an example method for clamping a transistor. Detailed Implementation

[0018] Figure 1A An example audio system 100 is shown. As illustrated, system 100 includes a first amplifier (labeled Amplifier A) and a second amplifier (labeled Amplifier B) that drive a speaker 102. Amplifier A may be coupled to terminal 104 of speaker 102, and amplifier B may be coupled to terminal 106 of speaker 102. Amplifiers A and B may be of different types and have different control schemes. For example, amplifier A may be a non-switching type, while amplifier B may be a switching type.

[0019] A switching amplifier includes a power stage that generates multi-level signals (e.g., binary, tri-level, etc.) by selectively connecting its output to one of a plurality of voltage sources. In some examples, the switching amplifier can be used as a Class D amplifier. The switching amplifier may be driven by a modulation circuit that receives a sinusoidal audio signal and generates a pulse width modulation (PWM) signal, a pulse density signal, and / or any other type of modulated control signal to control the power stage to also generate modulated signals (e.g., binary, tri-level, etc.) with discrete signal levels. The modulated signals provided by the power stage may have timing characteristics, such as duty cycle, pulse width, etc., which are modulated / varied to reflect the instantaneous amplitude of the audio signal. The modulated signals generated by the power stage may be filtered (e.g., through a low-pass filter, or through the inductance of a speaker) to produce an amplified version of the sinusoidal audio signal, and the amplified sinusoidal audio signal may be fed to a speaker. The low-pass filter may include an LC filter comprising a series inductor coupled between the output of the switching amplifier and the speaker, and a shunt capacitor coupled between the speaker and ground. The low-pass filter may also include a capacitor that is coupled across the speaker terminals.

[0020] A non-switching amplifier may include another power stage driven by control circuitry comprising a linear amplifier. The control circuitry may receive a sinusoidal audio signal and provide the non-switching amplifier with a control signal having an amplitude that varies according to the instantaneous amplitude change of the audio signal (e.g., linearly or nearly linearly). In response to the control signal, the non-switching amplifier may also generate an analog signal with an amplitude that can track the audio signal when the non-switching amplifier operates in linear mode, wherein the analog signal voltage level is lower than the supply voltage of the power stage. Where the analog signal voltage level is higher than the supply voltage, the non-switching amplifier may operate in saturation mode, wherein the analog signal is clipped and limited to the supply voltage. In some examples, the non-switching amplifier may be used as a Class A amplifier, a Class B amplifier, a Class AB amplifier, etc. The output of the non-switching amplifier may also be filtered (e.g., through another low-pass filter) to attenuate high-frequency components (e.g., noise) and distortion, such as those caused by saturation / clipping, nonlinear effects (e.g., distortion from conduction angle hand-over), etc. However, because the signal output of the non-switching amplifier is analog and continuous, the low-pass filter may have fewer components. For example, an audio system can include a capacitor at the output of a non-switching amplifier to perform filtering, instead of an LC filter.

[0021] Figure 1B Show Figure 1A Examples of internal components of System 100. Figure 1BThe system 100 includes a first power stage PS1 having a first output terminal 108 and a second power stage PS2 having a second output terminal 110. The first power stage PS1 can represent Figure 1A Amplifier A (or a portion thereof), and the second power stage PS2 can be represented as Figure 1A Amplifier B (or a portion thereof). First output terminal 108 and second output terminal 110 are coupled to LC filter circuit 112. The two speaker terminals 104 and 106 of LC filter circuit 112 (also related to...) Figure 1A (To be described) Coupled to speaker 102.

[0022] Power stage PS1 includes a first transistor S1 and a second transistor S2 connected in series between a power terminal 116a (e.g., receiving power supply PVDD) and a ground terminal. For example, a first current terminal of transistor S1 is coupled to the power terminal 116a, and a second current terminal of transistor S1 is coupled to the output terminal 108. A first current terminal of transistor S2 is coupled to the output terminal 108, and a second current terminal of transistor S2 is coupled to the ground terminal.

[0023] Transistor S1 further includes a control terminal coupled to a first power stage input that receives a control signal CS1 from driver D1, and transistor S2 includes a control terminal coupled to a second power stage input that receives a control signal CS2 from another driver D2. Transistors S1 and S2 can set the VN voltage at the output terminal 108 of power stage PS1 in response to control signals CS1 and CS2. Figure 1B In this configuration, power stage PS1 can be controlled as a non-switching amplifier (e.g., Class AB, Class A, etc.), where CS1 and CS2 can each have amplitudes that vary according to the instantaneous amplitude changes of the audio signal (e.g., linearly or nearly linearly). For example, during the first half-cycle of the audio signal, transistor S1 is turned on or off, and transistor S2 is turned off or off. Transistor S1 can change the amplitude of the VN voltage based on the amplitude of CS1, thereby reflecting / tracking the instantaneous amplitude of the audio signal during the first half-cycle (if operating in linear mode). Furthermore, during the second half-cycle of the audio signal, transistor S1 is turned off or off, and transistor S2 is turned on or off, and transistor S2 can change the amplitude of the VN voltage based on the amplitude of CS2, thereby also reflecting / tracking the instantaneous amplitude of the audio signal during the second half-cycle (if operating in linear mode). Where the audio signal is a sinusoidal signal, the VN voltage can be (or nearly) an amplified version of the sinusoidal signal, and the VN voltage can have the same frequency as the audio signal. On the other hand, the audio signal can also saturate the power stage PS1. In this case, the VN voltage can be clipped at the PVDD voltage or at the ground voltage.

[0024] Furthermore, power stage PS2 includes a third transistor S3 and a fourth transistor S4 connected in series between power terminal 116b (e.g., receiving power supply PVDD) and ground terminal. In one example, power terminals 116a and 116b may be the same power terminal shared by both power stages PS1 and PS2 (or power terminals 116a and 116b may be coupled to a common power terminal), while in another example, power terminals 116a and 116b may be coupled to different voltage sources.

[0025] As shown, the first current terminal of transistor S3 is coupled to the power terminal 116b, and the second current terminal of transistor S3 is coupled to the output terminal 110 having a voltage VY. The first current terminal of transistor S4 is coupled to the output terminal 110, and the second current terminal of transistor S4 is coupled to the ground terminal.

[0026] Transistor S3 further includes a control terminal coupled to a third power stage input that receives a control signal CS3 from driver D3, and transistor S4 further includes a control terminal coupled to a fourth power stage input that receives a control signal CS4 from another driver D4. Transistors S3 and S4 can set the voltage VY at the output terminal 110 of power stage PS2 in response to control signals CS3 and CS4.

[0027] exist Figure 1B In this configuration, power stage PS2 can be controlled as a switching amplifier (e.g., Class D), where control signals CS3 and CS4 are pulse-width modulated signals, pulse-density signals, and / or any other type of modulated control signal with binary amplitude. Depending on the amplitude of the audio signal, one of transistors S3 or S4 can be turned on to connect either power terminal 116b or ground terminal to output terminal 110. In response to CS3 and CS4, power stage PS2 can also generate a modulated signal. The modulated signal provided by the power stage can have timing characteristics, such as duty cycle, pulse width, etc., which are modulated / varied to reflect the instantaneous amplitude of the audio signal. Transistors S3 and S4 can provide VY as the modulated signal at output terminal 110 in response to CS4. The modulated signal VY at output terminal 110 can have a frequency much higher than the audio signal and the signal VN at output terminal 108.

[0028] exist Figure 1BIn the diagram, transistors S1, S2, S3, and S4 are shown as n-channel metal-oxide-semiconductor (NMOS) field-effect transistors (FETs). In other examples, transistors S1, S2, S3, and S4 can be other types of transistors, such as p-channel MOSFETs (PMOS), laterally diffused metal-oxide-semiconductor (LDMOS) FETs, gallium nitride (GaN) FETs, NPN or PNP bipolar junction transistors (BJTs), etc.

[0029] The LC filter circuit 112 includes an inductor L1 coupled between the output terminal 110 and the speaker terminal 106, a capacitor C1 coupled between the speaker terminals 104 and 106, and another capacitor C2 coupled between the speaker terminal 104 and the ground terminal. The inductor L1 and capacitor C1 filter the modulated signal VY provided at the output terminal 110 into a sinusoidal signal VP at the speaker terminal 106, which is then output to the speaker 102 to output the corresponding audio signal. The capacitor C2 can also filter the signal VN to further suppress nonlinearity in the signal VN and provide a relatively low impedance virtually to the ground. Capacitor C2 can be relatively large (e.g., 200 nF or more) to provide a low-impedance virtual ground and reduce electromagnetic interference (EMI) and harmonic distortion in signal VN (e.g., harmonic distortion caused by nonlinear conduction angle switching in the power stage), as explained in the related application, namely, Methods and Apparatus to Modulate Signals Using a Multi-Class Modulation Circuitry, U.S. Application No. 18 / 385,848, entitled "METHODS AND APPARATUS TO MODULATESIGNALS USING MULTI-CLASS MODULATION CIRCUITRY" and Attorney General's Case No. T103189US01. The power stage can drive current from a few microamps to a few amps to charge capacitor C2.

[0030] System 100 also includes a control circuit that generates control signals (in Figure 1B(Not shown in the image), the control signals drive driver circuits D1, D2, D3, and D4 respectively based on the audio signal. Example operation of system 100 is described in related U.S. Application No. 17 / 402,264, filed August 13, 2021, entitled "Methods and Apparatus to Generate a Modulation Protocol to Output Audio," and in related U.S. Application No. 17 / 491,133, filed September 30, 2021, entitled "Switching amplifier having linear transition totem pole modulation," all of which are incorporated herein by reference in their entirety as described above.

[0031] Figure 2 Examples of internal components of system 100 are shown. Figure 2 The system 100 is shown to include, in addition to power stages PS1 and PS2, control circuit 202 providing control signals CS1 and CS2 to power stages PS1, and control circuit 204 providing control signals CS3 and CS4 to power stages PS2. During startup and shutdown, both control circuits 202 and 204 may not receive audio signal 206. During normal operation, control circuits 202 and 204 may receive audio signal 206.

[0032] exist Figure 2 In one example, control circuitry 202 can control power stage PS1 as a non-switching amplifier (e.g., a Class AB amplifier). Control circuitry 202 may include a linear amplifier for generating control signals CS1 and CS2 by amplifying audio signal 206 (if present). Power stage PS1 may provide a VN voltage at a first output terminal 108 that tracks the amplitude of audio signal 206. The VN voltage may also be saturated / clamped if the amplitude of audio signal 206 exceeds a certain threshold. Furthermore, control circuitry 204 can control power stage PS2 as a switching amplifier (e.g., a Class D amplifier). Control circuitry 204 may include a modulated signal generator for generating control signals CS3 and CS4 as modulated signals. In some examples, control circuitry 204 may include a pulse width modulation (PWM) signal generator for generating control signals CS3 and CS4 as PWM signals, wherein the pulse widths of CS3 and CS4 may be modulated based on the instantaneous amplitude of audio signal 206. After VN and VP are filtered by LC filter circuit 112, the difference between VN and VP can be transformed into an amplified audio signal.

[0033] like Figure 2 As shown, to further improve the matching between the common-mode voltages of VN and VP, the PS1 control circuit 202 and the PS2 control circuit 204 can operate in a master-slave configuration. In the master-slave configuration, the PS1 control circuit 202 and the power stage PS1 are the master devices, and the PS2 control circuit 204 and the power stage PS2 are the slave devices. Specifically, the PS1 control circuit can drive the power stage PS1 based on an audio signal 206 (if present) or other signals. On the other hand, the PS2 control circuit 204 may include a subtraction circuit 210 (e.g., an amplifier) ​​that receives VN and VP (or a filtered version of VY) as feedback signals and generates a difference signal 212 representing the difference between VN and VP. The PS2 control circuit 204 can adjust control signals CS3 and CS4 (and VY / VP) based on the difference signal 212. For example, the PS2 control circuit 204 can adjust control signals CS3 and CS4 to minimize (or reduce) the difference signal 212, thereby improving the matching between the common-mode voltages of VN and VP. The PS2 control circuit 204 may have a higher bandwidth than the PS1 control circuit 202, thereby allowing the PS2 control circuit 204 to adjust CS3 and CS4 in response to both the audio signal 206 and the difference signal 212.

[0034] Figure 3 Show Figure 2 Examples of internal components of System 100. (See reference) Figure 3 System 100 may include audio driver circuitry 300 having driver inputs 302a, 302b and driver outputs 304a, 304b. Driver outputs 304a and 304b are coupled to the inputs of power stages PS1 and PS2, respectively. Audio driver circuitry 300 includes PS1 control circuitry 202 and PS2 control circuitry 204. System 100 also includes audio inputs 306a and 306b for receiving differential audio signals 206a (also labeled VINP) and 206b (also labeled VINM) of a sinusoidal audio signal 206. In some examples, system 100 may also include audio signal generation circuitry 305 for providing differential audio signals 206a / 206b to audio inputs 306a and 306b. Audio signal generation circuitry 306 may include a digital-to-analog converter (DAC) for converting a series of digital signals into differential audio signals 206a / 206b.

[0035] PS1 control circuit 202 includes amplifier 308 coupled to audio inputs 306a and 306b. In some examples, amplifier 308 may be a linear differential amplifier 308. Amplifier 308 may receive differential audio signals 206a and 206b and provide control signals CS1 and CS2 by amplifying audio signals 206a and 206b to set the VN voltage at the first output terminal 106.

[0036] Furthermore, the PS2 control circuit 204 includes a filter 320 (e.g., a loop filter), subtraction circuits 322 and 324, a periodic ramp generator 326, a comparator 328, and a voltage scaler circuit 329. Subtraction circuits 322, 324, and 329 are collectively part of a signal combination circuit 325. In some examples, filter 320 may include a multi-stage loop filter. Voltage scaler circuit 329 provides a reduced version of the VN voltage as feedback signal 330. Voltage scaler circuit 329 may also remove the common-mode / DC bias component of the VN voltage and provide a reduced version of the AC component of the VN voltage. Additionally, subtraction circuit 322 may generate a difference signal 332 representing the difference between the filtered audio signals 206a and 206b and the feedback signal through resistors 350b and 352b, wherein the difference signal 332 may have the opposite polarity to the VN voltage (and feedback signal 330). Furthermore, the subtraction circuit 324 can generate another difference signal 334 representing the difference between signals 330 and 332. The signal combination circuit 325 can represent... Figure 2 The subtraction circuit 210, and the difference signal 334 can represent Figure 2 The difference signal 212. System 100 may also include a common-mode regulator 327, which is coupled to driver inputs 302a and 302b to define the same input common-mode voltage for driver inputs 302a and 302b.

[0037] Furthermore, comparator 328 can generate control signals CS3 and CS4 by comparing the difference signal 334 with a periodic ramp signal provided by periodic ramp generator 326 and based on the duty cycle / pulse width of the difference modulation CS3 and CS4. Periodic ramp generator 326 can receive a clock signal (denoted as CLK) and generate a periodic ramp signal synchronized with the clock signal and having a cycle period defined by the clock signal. The difference signal 334 may have a component representing the audio signal 206 and a corrective component representing, for example, the difference between VP and VN caused by the aforementioned asymmetry and nonlinear effects. Therefore, the duty cycle / pulse width of CS3 and CS4 can reflect the instantaneous amplitude of the audio signals 206a and 206b (denoted as difference signal 332) and the difference between VP and VN (as part of a master-slave configuration), and control circuit 204 can adjust CS3 and CS4 to reduce / minimize the aforementioned difference between VP and VN caused by asymmetry and nonlinear effects.

[0038] In addition, system 100 may include a pair of resistor networks 350 and 352 for setting the overall amplification gain of the system. The overall amplification gain can be between the differential output voltage VP-VN (or VY-VN) and the differential input voltage VINP-VINM. System 100 may include resistor network 350 for the signal path from VINP to VY, and resistor network 352 for the signal path from VINM to VN. Resistor network 350 may include an input resistor 350a coupled between audio input 306a and driver input 302a, and a feedback resistor 350b coupled between driver input 302a and output terminal 110. In addition, resistor network 352 may include an input resistor 352a coupled between audio input 306b and driver input 302b, and a feedback resistor 352b coupled between driver input 302b and output terminal 108. Resistor networks 350 and 352 are matched, with input resistors 350a and 352a having the same resistance (e.g., RIN) and feedback resistors 350b and 352b having the same resistance (e.g., RFB) to remove the component of the differential output voltage VP-VN (or VY-VN) caused by the output common-mode voltage VCM and to provide amplification gain for the differential input voltage VINP-VINM.

[0039] In the audio system 100, the output of power stage PS2 is coupled to inductor L1, which can discharge to provide current to speaker 102 via terminal 106, thereby driving terminal 106 at voltage VP. Therefore, power stage PS2 can provide current to charge inductor L1, which also improves the power efficiency of power stage PS2. In contrast, the output of power stage PS1 is coupled to capacitor C2 and output terminal 108, which is coupled to terminal 104 of speaker 102. Power stage PS1 can provide current to charge / discharge capacitor C2 and provide current to speaker 102 via terminals 104 / 108, thereby driving terminals 104 / 108 at voltage VN.

[0040] As described above, in the audio system 100, the PS1 control circuit 202, including amplifier 308, uses power stage PS1 as a non-switching amplifier, while the PS2 control circuit 204, including periodic ramp generator 326 and comparator 328, uses power stage PS2 as a switching amplifier. The PS2 control circuit 204 provides control signals CS3 and CS4 that switch between the supply rails of power stage PS1 (e.g., PVDD and ground) at high frequencies (e.g., the frequency of periodic ramp generator 326) higher than CS1 and CS2. On the other hand, amplifier 308 provides control signals CS1 and CS2 that are at lower frequencies (e.g., the frequency of the audio signal), at lower slew rates, and have reduced voltage swings, for example limited by the output voltage range of amplifier 308, wherein the transistor arrangement of amplifier 308 remains saturated.

[0041] The high-frequency switching of power stage PS2 can generate switching noise, which can be coupled to the control terminals (gates) of transistors S1 and S2 of power stage PS1 via power supply, ground, capacitor C1 and inductor L1, or any other metal interconnects shared between power stages PS1 and PS2. Switching noise from other sources can also couple to the gates of transistors S1 and S2 of power stage PS1, which may adversely affect the operation of power stage PS1. Furthermore, due to the relatively low bandwidth and low slew rate of amplifier 308, amplifier 308 alone may not be able to adjust the gate voltages of transistors S1 and S2 to compensate for the effects of switching noise.

[0042] Figure 4 An example of a mechanism for generating and coupling switching noise in an audio system 100 is shown. (Reference) Figure 4The power terminals 116a of power stage PS1 and 116b of power stage PS2 are coupled to a power interconnect 402 (e.g., a power plane), which may have a distributed network of parasitic inductances 402a, 402b, 402c, and 402d. Parasitic inductance 402a is between the power supply PVDD and the power terminal 116b of power stage PS2; parasitic inductance 402b is between PVDD and the power terminal 116a of power stage PS1; parasitic inductance 402c is between power terminals 116a and 116b; and parasitic inductance 402d is between power terminal 116a and other systems, such as the power stage PS2 of another audio channel, a clock generator, a high-frequency digital system, etc. Furthermore, power stages PS1 and PS2 are coupled to a ground interconnect 404 (e.g., a ground plane), which may also have a distributed network of parasitic inductances 404a, 404b, 404c, 404d, 404e, and 404f. Parasitic inductance 404a is between power stage PS2 and ground, parasitic inductance 404b is between power stage PS1 and ground, parasitic inductance 404c is between capacitor C2 and ground, parasitic inductances 404d and 404e are between power stages PS1 and PS2, and parasitic inductance 404f is between power stage PS1 and the aforementioned other systems. Additionally, a parasitic inductance 406 may exist between speaker 102 and the output terminal 108 of power stage PS1.

[0043] Switching noise can couple to the gates of transistors S1 and S2 from various sources. For example, when power stage PS2 is used as a switching amplifier, a very large switching current can flow through parasitic inductors 402a and 404a. The switching current can cause voltage transition events 410a and 410b across parasitic inductors 402a and 404a, respectively. Voltage transition event 410a, in the form of switching noise, can couple to the gate of transistor S1 via parasitic inductor 402c and the gate-drain parasitic capacitance Cgd1 of transistor S1, causing voltage transition event 412 at the gate of transistor S1. Furthermore, voltage transition event 410b, in the form of switching noise, can couple to the gate of transistor S2 via parasitic inductors 404e and 404d and the gate-source parasitic capacitance Cgs2 of transistor S2, causing voltage transition event 414 at the gate of transistor S2. Voltage transition events 410c and 410d can also be coupled to the gates of transistors S1 and S2, respectively, and facilitate voltage transition events 412 and 414 via parasitic inductances 402d and 404f. For example, voltage transition events 410c and 410d can be caused by switching noise from other parts of the integrated circuit containing power stages PS1 and PS2 (e.g., adjacent channels), switching noise from other components outside the integrated circuit, or switching noise from other components within the integrated circuit coupled through the power plane of the printed circuit board (PCB) and parasitic inductances 402a / b. The initiation and coupling of these voltage transition events can be an example of ground bounce events. Additionally, in cases where the speaker 102 generates switching noise, and / or where the power stage PS1 drives a load that generates switching noise, other sources of switching noise, such as the switching of other power stages PS1 / PS2, may be present. In all these cases, the switching noise (represented by voltage transition event 412) can also be coupled to the gates of transistors S1 and S2 via output terminal 108.

[0044] As described above, due to the relatively low bandwidth and slew rate of amplifier 308, amplifier 308 alone may not be able to adjust the gate voltages of transistors S1 and S2 to compensate for the effects of switching noise. When transistors S1 and S2 are to be turned off, the aforementioned voltage events may inadvertently turn them on or otherwise leave transistors S1 and S2 in an indeterminate state, which may adversely affect the operation of power stage PS1 and audio system 100.

[0045] Figure 5A and Figure 5B Includes a graph illustrating an example effect of switching noise on the operation of power stage PS1. Figure 5AThis includes graphs 502, 504, 506, 508, 510, and 512. Graph 502 shows an example change in the gate voltage of transistor S1 relative to time. Graph 504 shows an example change in the current conducted by transistor S1 relative to time. Graph 506 shows an example change in the gate voltage of transistor S2 relative to time. Graph 508 shows an example change in the current conducted by transistor S2 relative to time. Graph 510 shows an example change in the power dissipation (or power loss) at transistor S2 relative to time. Graph 512 shows an example change in the power dissipation (or power loss) at transistor S1 relative to time. Figure 5B Include Figure 5A Enlarged views of graphs 502-512.

[0046] refer to Figure 5A During an interval T0 corresponding to half a cycle of the audio signal, amplifier 308 can provide a high voltage V0 (e.g., approximately 5V, or PVDD voltage) at the gate of transistor S1 to turn on transistor S1, and a low voltage V1 (e.g., below or approximately Vth of transistor S2) at the gate of transistor S2 to turn off transistor S2. The gate voltage of transistor S1 can also track the audio signal until the gate voltage reaches V0. Furthermore, during an interval T1 corresponding to the other half cycle of the audio signal, amplifier 308 can provide a low voltage V1 (e.g., below or approximately Vth of transistor S1) to turn off transistor S1, and a high voltage V0 (at the gate of transistor S2) to turn off transistor S2. Figure 5A and 5B The voltage is approximately 5V to turn on transistor S2.

[0047] Graphs 502 and 506 also illustrate voltage transition events caused by coupling from switching noise from power stage PS2, such as events 502a and 506a. These voltage transition events and switching noise can have frequencies similar to the switching of power stage PS2, much higher than the frequency of an audio signal. Due to these voltage transition events, when transistor S1 is to be turned off, the gate voltage of transistor S1 can become higher than V1 for most of the interval T1. Similarly, when transistor S2 is to be turned off, the gate voltage of transistor S2 can also become higher than V1 for most of the interval T0.

[0048] When transistor S2 is on and transistor S1 is off, the on-time of transistor S1 during interval T1, and the on-time of transistor S2 during interval T0, when transistor S1 is on and transistor S2 is off, may create a short circuit between PVDD and ground via power stage PS1. This can lead to a large current being conducted through power stage PS1. Furthermore, due to limited bandwidth and slew rate, amplifier 308 may not be able to quickly set the gate voltages of transistors S1 and S2 back to V1, and short circuits may occur for most of intervals T0 and T1, resulting in significant energy loss. For example, refer to... Figure 5B The diagram shows an enlarged version of graphs 502-512 within interval T0, where switching noise causes a voltage transition event at the gate of transistor S2 at time T2, and the gate voltage increases from 0V to 2.6V. Amplifier 308 takes approximately 30 nanoseconds (ns) to reduce the gate voltage of transistor S2 back to V1 (below or approximately the Vth of transistor S2). During these 30 ns, a short circuit is formed between PVDD and ground via power stage PS1, resulting in a very large short-circuit current pulse. With a peak power loss of 650 watts (W), a significant amount of energy may be wasted / lost at power stage PS1 within 30 ns. This short circuit can occur even when power stage PS1 is operating in idle mode and is not actively driven by an audio signal. For example, power stage PS1 in an idle channel may be affected by a ground bounce event from an adjacent channel. The very large short-circuit current pulse can also be caused by… Figure 4 The parasitic inductance shown generates ultra-large current transient events, which can cause additional ground bounce events.

[0049] High-frequency voltage transitions at the gates of transistors S1 and S2 can degrade the performance of the audio system 100 in various ways. Specifically, voltage transitions can lead to significant power losses, reducing the overall power efficiency of the audio system 100 and generating considerable heat, which can pose safety hazards or at least degrade the user experience. Thermal management to mitigate such significant heat can also be substantial and expensive for the user. Furthermore, the large currents conducted through transistors S1 and S2 due to short circuits can shorten transistor lifespan. Additionally, in the example where power stage PS1 is coupled to an overcurrent detection circuit, a large current can trigger the overcurrent detection circuit to shut down power stage PS1 and interrupt its operation. Moreover, high-frequency voltage transitions increase the electromagnetic interference (EMI) characteristics of the audio system 100, which can interfere with the operation of other electronic devices in the vicinity of the audio system 100.

[0050] One possible way to mitigate switching noise is to provide separate power and ground planes for power stage PS1 and power stage PS2. Such an arrangement can reduce the coupling of switching noise from power stage PS2 to power stage PS1 via a shared power plane and / or a shared ground plane, such as... Figure 4As shown. In the example where power stages PS1 and PS2 are within the same integrated circuit package, additional package interconnects (e.g., pins, pads, etc.) and / or a larger integrated circuit package can be provided to connect separate power planes and separate ground planes to different power supplies, which increases package complexity and cost. Furthermore, the bandwidth of amplifier 308 can be increased to shorten the time it takes for amplifier 308 to reduce the gate voltage, which can reduce power loss due to voltage transition events. However, the bandwidth and slew rate of amplifier 308 can be increased several times to effectively shorten the time. Because the power stage PS1 driven by amplifier 308 can be large, the power consumption of amplifier 308 can become very high. The peripheral circuitry driving amplifier 308, such as charge pump circuitry, can also become large and contain more expensive external components.

[0051] Figure 6 Examples of circuits are shown that can solve at least some of the problems described above. References Figure 6 The audio system 100 may include clamping circuitry 600. Clamping circuitry 600 includes a switch 602 (e.g., a transistor) coupled between a control terminal / gate 604a of transistor 604 (which may be one of transistors S1 / S2 of power stage PS1) and a reference terminal 606. Reference terminal 606 may receive a reference voltage. When enabled, switch 602 may connect the gate of transistor 604 to reference terminal 606 to adjust the gate voltage by clamping / setting the gate voltage to the reference voltage. As described below, in some examples, the reference voltage may be the voltage at which transistor 604 is turned off (e.g., ground voltage, a reference voltage based on the voltage at a current terminal of transistor 604, such as the source 604b of transistor 604, etc.). In some examples, the reference voltage may track the average value of the gate voltage of transistor 604 (in the off state), where voltage transition events are removed or at least attenuated. This arrangement reduces the duration of short circuits via power stage PS1 caused by voltage transition events, thereby reducing power losses (and the resulting heat dissipation), improving the reliability of the transistor configuration in power stage PS1, and reducing the EMI characteristics of audio system 100. Furthermore, switch 602 can be significantly smaller than transistor 604 (and power stage PS1), reducing the amount of power required to drive switch 602. Therefore, clamping circuit 600 can have a much higher bandwidth than amplifier 308 in clamping the gate voltage of transistor 604 while consuming a limited amount of power. It also avoids the aforementioned problems of providing separate power and ground planes for power stages PS1 and PS2, and of increasing the bandwidth / slew rate of amplifier 308.

[0052] The clamping circuit 600 also includes control circuitry 610 for enabling / disabling switch 602. Control circuitry 610 can provide control signal 611 to enable switch 602 based on the detection of a voltage transition event at the gate 604a of transistor 604, and to disable switch 602 if no voltage transition event is detected. Control circuitry 610 may include voltage transition detection circuitry 612 for detecting voltage transition events. As described below, control circuitry 610 can detect voltage transition events in various ways, such as by detecting that the instantaneous gate voltage of transistor 604 exceeds the average value of the gate voltage over a short time window, by detecting that the edge rate of the gate voltage exceeds a voltage threshold, or by detecting that the current conducted by transistor 604 exceeds a current threshold indicating a short circuit. Therefore, voltage transition detection circuitry 612 has input 612a coupled to the gate 604a of transistor 604 or a current terminal of transistor 604 (e.g., drain terminal 604c and / or source terminal 604b) to sense the gate voltage and / or current of transistor 604. The voltage transition detection circuit 612 also has an output 612b for providing a voltage transition detection signal 614 to set the state of switch 602.

[0053] Furthermore, the control circuit 610 includes a maximum voltage detection circuit 622. The maximum voltage detection circuit 622 can detect whether the output voltage of the amplifier 308 and the gate voltage of the transistor 604 are at or near their maximum values ​​(e.g., in...). Figure 5A (V0 voltage is shown in the image). If the gate voltage of transistor 604 is at or near its maximum value, then transistor 604 will be turned on, and the clamping of clamping circuit 600 can be deactivated / stopped to avoid clamping the gate voltage of transistor 604 and thus disrupting its operation. Therefore, maximum voltage detection circuit 622 has an input 622a coupled to the gate 604a of transistor 604 and provides a maximum voltage detection signal 624 at output 622b.

[0054] The control circuit 610 further includes a control signal generation circuit 632. The control signal generation circuit 632 has an input 632a coupled to output 622b, an input 632b coupled to output 612b, and an output 632c coupled to switch control input 602a of switch 602. The control signal generation circuit 632 can receive a voltage transition detection signal 614 at input 632a, a maximum voltage detection signal 624 at input 632b, and provide a control signal 611 at output 632c based on the voltage transition detection signal 614 and the maximum voltage detection signal 624. Specifically, the control signal generation circuit 632 can provide the control signal 611 in a first state (e.g., a high voltage state) to turn on switch 602 when the voltage transition detection signal 614 indicates a voltage transition event and the maximum voltage detection signal 624 indicates that the gate voltage of transistor 604 is not at or near its maximum value. The control signal generation circuit 632 may also provide a control signal 611 in a second state (e.g., a low voltage state) to turn off the switch 602 when the voltage transition detection signal 614 indicates no voltage transition event or the maximum voltage detection signal 624 indicates that the gate voltage of the transistor 604 is at or near its maximum value. The control signal generation circuit 632 may also include circuitry for accelerating the transition of the control signal 611 between the first and second states to accelerate the activation and / or deactivation of the switch 602. This can improve the responsiveness of the clamping circuit 600 to voltage transition events, thereby reducing the duration of the short-circuit interval and also reducing interruptions to the normal operation of the transistor 604 caused by clamping operations.

[0055] Figure 7 An example of the internal components of the clamping circuit 600 is shown. Figure 7In the example, reference terminal 606 is coupled to ground, and input 612a of voltage transition detection circuit 612 is coupled to gate 604a of transistor 604. Voltage transition detection circuit 612 includes low-pass filter 702 coupled to input 612a to receive the instantaneous gate voltage of transistor 604 that may rise due to a voltage transition event, and to generate a time-averaged version (or average gate voltage) of the gate voltage, wherein the voltage transition event is removed or at least attenuated. Voltage transition detection circuit 612 also includes transistor 704 having a gate coupled to input 612a to receive the instantaneous gate voltage of transistor 604, and a source coupled to low-pass filter 702 to receive the time-averaged version of the gate voltage. Transistor 704 is coupled between output 612b and the output of low-pass filter 702. Transistor 704 is configured as a comparator and provides a voltage transition detection signal 614 based on a comparison between an instantaneous gate voltage and a time-averaged version of the gate voltage, such that the voltage transition detection signal 614 can indicate whether a voltage transition event has been detected at the gate 604a of transistor 604. Bias circuitry 706 is coupled between output 612b and power supply terminal 708. Bias circuitry 706 includes capacitor 706a for filtering noise (including switching noise) at the power supply terminal and providing bias current and bias voltage with reduced interference to transistor 704. With this arrangement, the voltage transition detection signal 614 and the decision regarding the on / off switch 602 to clamp the gate voltage of transistor 604 are generated based on whether the voltage transition event occurs at the gate 604a of transistor 604 and not elsewhere (e.g., power terminal 708).

[0056] Transistor 704 is configured as a comparator and provides a voltage transition detection signal 614 based on a comparison between a transient gate voltage and a time-averaged version of the gate voltage. For example, if, due to a voltage transition event, the transient gate voltage exceeds the average gate voltage by at least one threshold voltage of transistor 704, then transistor 704 can be turned on to reduce the voltage of output 612b to, for example, the average gate voltage. Furthermore, if, at the end of the voltage transition event, the difference between the transient gate voltage and the average gate voltage is less than the threshold voltage, or the transient gate voltage drops below the average gate voltage, then transistor 704 can be turned off, and bias circuit 706 can pull the output of output 612b to the supply voltage. Therefore, transistor 704 can provide a voltage transition detection signal 614 that tracks / indicates a voltage transition event at gate 604a.

[0057] Furthermore, the control signal generation circuit 632 includes an AC capacitor 710 (or AC coupling capacitor 710), a metastable buffer 712, and a switching network 714. The AC capacitor 710 can perform high-pass filtering on the voltage transition detection signal 614 and provide the filtered signal 614 to the metastable buffer 712. The metastable buffer 712 includes fast-triggered metastable circuits 712a and 712b, which can be triggered on the rising and falling edges of the detection signal 614 to generate a control signal 611 based on the filtered signal 614 with reduced delay, improving the responsiveness of the clamping circuit 600 when enabling / disabling the switch 602. Additionally, the metastable buffer 712 drives the switch 602 (directly or indirectly), which can be small compared to the transistor 604 described above. Therefore, the metastable buffer 712 can consume a small amount of power while operating the switch 602 at high speed. In some examples, the metastable buffer 712 may include one of circuits 712a or 712b triggered based on the rising or falling edge of the detection signal 614, followed by a timer for setting a predetermined pulse width for the control signal 611, which can further reduce the power consumption of the control signal generation circuit 632.

[0058] In addition, the switch network 714 can receive the maximum voltage detection signal 624 and can forward the control signal 611 provided by the metastable buffer 712 at the output 632c if no maximum voltage is detected at the gate 604a, or pull the voltage of the output 632c down to ground to disable the switch 602 if a maximum voltage is detected at the gate 604a.

[0059] Figure 8 and Figure 9 Additional examples of the internal components of the clamping circuit 600 are shown. For example... Figure 8As shown, the voltage transition detection circuit 612 may include a dv / dt circuit 804 coupled to an input 612a coupled to the gate 604a of transistor 604, and a comparator 802 coupled between the dv / dt circuit 804 and the output 612b. The dv / dt circuit 804 may generate a voltage signal representing the absolute edge rate (for both rising and falling edges) of the gate voltage of transistor 604. In some examples, the dv / dt circuit 804 may include an AC capacitor providing current based on the edge rate of the gate voltage, and a current-to-voltage converter converting the current into a voltage signal. The comparator 802 may generate a voltage transition detection signal 614 by comparing the voltage signal with a voltage threshold 806. The comparator 802 may set the voltage transition detection signal 614 to a first state if the voltage signal exceeds the voltage threshold 806, which may indicate the presence of a voltage transition event caused by the coupling of switching noise. Comparator 802 can also set voltage transition detection signal 614 to a second state, which can indicate that there is no voltage transition event (or the voltage transition event has ended).

[0060] In addition, such as Figure 9 As shown, the voltage transition detection circuit 612 may include a current sensor 904 coupled to an input 612a coupled to one or more current terminals (e.g., source terminal 604b, drain terminal 604c) of transistor 604, and a comparator 902 coupled between the current sensor 904 and the output 612b. The current sensor 904 can provide a current sensing signal (which may be a voltage signal) representing the amount of current conducted by transistor 604. The comparator 902 can generate a voltage transition detection signal 614 by comparing the output of the current sensor 904 with a current threshold 906, which may be based on the amount of current conducted by transistor 604 when power stage PS1 provides a short circuit between PVDD and ground. The comparator 902 can set the voltage transition detection signal 614 to a first state if the current sensing signal exceeds the current threshold 906, which may indicate the presence of a short circuit in power stage PS1 caused by a voltage transition event at the gate 604a of transistor 604. Comparator 902 can also set voltage transition detection signal 614 to a second state, which can indicate that there is no short circuit in power stage PS1, and can also indicate that there is no voltage transition event at gate 604a (or the voltage transition event has ended).

[0061] Figure 10A , 10B Figure 10C shows an example of the connection of reference terminal 606, which can provide a reference voltage to which the gate voltage of transistor 604 is clamped when switch 602 is enabled. Figure 10AAs shown, reference terminal 606 can be coupled to ground, such that when switch 602 is enabled, the gate voltage of transistor 604 is set to ground voltage to turn off transistor 604.

[0062] In addition, such as Figure 10B As shown, reference terminal 606 can be coupled to the source terminal 604c of transistor 604 via diode-connected transistor 1000, which can track the threshold voltage of transistor 604 across process variations and different temperatures to provide a reference voltage equal to or higher than the source voltage of transistor 604. This arrangement can reduce the voltage difference between the gate and source of transistor 604 during clamping, thereby reducing voltage stress and interference and improving the reliability of transistor 604. Furthermore, because the gate-source voltage difference of transistor 604 remains below the threshold voltage, transistor 604 can be turned off during clamping to remove short-circuit current paths within power stage PS1. Additionally, due to the reduced gate-source voltage difference, less power is consumed by the driver of amplifier 308 to charge the gate of transistor 604 back to its previous voltage state. This reduces the power handling rating of any peripheral devices supplying power to the driver of amplifier 308.

[0063] In addition, such as Figure 10C As shown, reference terminal 606 can be coupled to average value generator circuit 1002, which can be similar to... Figure 7 A low-pass filter 702 is provided and may be coupled to the gate 604a of transistor 604 to generate a time-averaged version of the gate voltage, wherein voltage transition events are removed or at least attenuated. Switch 602 may clamp the gate 604a of transistor 604 to the average gate voltage, enabling transistor 604 to operate (e.g., to provide current for tracking audio signals) instead of turning off transistor 604. Furthermore, through... Figure 10C The arrangement of the gate 604a, which can be clamped to the average gate voltage of the tracking system dynamics, reduces interference to the operation of amplifier 308. As interference to amplifier 308 is reduced, the signal quality of amplifier 308 is also improved.

[0064] Figure 11 An example of the internal components of the maximum voltage detection circuit 622 is shown. (Reference) Figure 11 In some examples, the maximum voltage detection circuit 622 includes a comparator 1102 with a negative input coupled to an input 622a coupled to the gate 604a of transistor 604 and the output of amplifier 308. The positive input of comparator 1102 receives a threshold representing the maximum output voltage of amplifier 308. In some examples, such as Figure 11As shown, the maximum voltage detection circuit 622 may include a voltage drop circuit 1104 for generating a reference voltage. The reference voltage may be relative to the source voltage of transistor 604 to track changes in the threshold voltage of transistor 604 (e.g., due to PVT variations). The voltage drop circuit 1104 may be coupled between the supply voltage of amplifier 308 (e.g., AVDD, as shown) and the positive input of comparator 1102. The reference voltage generated by the voltage drop circuit 1104 may represent the gate voltage of transistor 604 when transistor 604 is fully turned on, and the output terminal 108 saturates at the PVDD supply voltage of power stage PS1.

[0065] Figure 12 A graph containing an example of the operation of the clamping circuit 600. Figure 12 Includes graphs 1202, 1204, 1206, 1208, 1210, and 1212. Graph 1202 shows an example change in the gate voltage of transistor S1 relative to time. Graph 1204 shows an example change in the current conducted by transistor S1 relative to time. Graph 1206 shows an example change in the gate voltage of transistor S2 relative to time. Graph 1208 shows an example change in the current conducted by transistor S2 relative to time. Graph 1210 shows an example change in the power dissipation (or power loss) at transistor S2 relative to time. Graph 1212 shows an example change in the power dissipation (or power loss) at transistor S1 relative to time. Reference Figure 12 The clamping circuit 600 detects a voltage transition event at time T2. At time T3', approximately 7 ns later than T2, the clamping circuit 600 clamps the gate voltage of transistor S2, thereby disabling the short circuit in power stage PS1 and stopping the short-circuit current. Although Figure 12 The peak power loss is also 650W, similar to Figure 5B As shown, however, due to the shortened duration of the short-circuit interval (from 30 ns to 7 ns), the energy loss (and resulting heat dissipation) caused by switching noise can be significantly reduced. EMI characteristics can also be significantly reduced by decreasing the duration of voltage transition events.

[0066] Figure 13 A flowchart illustrating an example method 1300 for operating a transistor, such as a transistor in the power stage PS1 of an audio system 100 or any transistor in a high switching noise environment, is shown. Method 1300 can be performed by a clamping circuit, for example... Figure 6-11 The clamping circuit 600.

[0067] In operation 1302, clamping circuit 600 can detect voltage transition events at the control terminal of the transistor. Voltage transition events can be caused by coupling from switching noise from other devices. Detection can be performed by voltage transition detection circuit 612 and can be based, for example, comparing instantaneous gate voltage with average gate voltage (e.g., ...). Figure 7 As shown), the edge rate of the gate voltage is measured (e.g. Figure 8 (as shown), and / or measure the current through the transistor (e.g. Figure 9 (As shown).

[0068] In operation 1304, the clamping circuit 600 can perform a clamping operation in response to the detection of a voltage transition event by setting the voltage at the control terminal to a reference voltage. The reference voltage can be ground voltage, a threshold voltage higher than the transistor's source voltage to disable the transistor, or the average gate voltage of the transistor used to maintain its operation, such as... Figures 10A-10C As shown in the diagram. In some examples, if the gate voltage of the transistor is at the maximum voltage provided by the transistor's driver (e.g., amplifier 308), which indicates that the transistor will be turned on and not turned off by the clamping circuit 600, then the clamping circuit 600 can disable / interrupt the clamping operation.

[0069] In this specification, the term "coupled" may cover a connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by control signals generated by device A.

[0070] A device “configured” to perform a task or function can be configured (e.g., programmed and / or hardwired) at the time of manufacture to perform the function, and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0071] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless explicitly stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0072] The circuits or devices described herein as containing specific components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some passive elements and / or sources during or after manufacturing, for example, by an end user and / or a third party, to form the described structure.

[0073] Although this document describes the use of specific transistors, other transistors (or equivalent devices) can actually be used. For example, a p-channel field-effect transistor (PFET) can be used instead of an n-channel field-effect transistor (NFET) with almost no change to the circuitry. Furthermore, other types of transistors can be used, such as laterally diffused metal-oxide-semiconductor (LDMOS) FETs and bipolar junction transistors (BJTs). Additionally, the device can be implemented on / on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0074] In this article, "FET on" refers to the presence of a conduction path in the FET, allowing drain current to flow through it. "FET off" refers to the absence of a conduction path, preventing drain current from flowing through the FET. However, an off-state FET can still have a body diode through which current flows.

[0075] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0076] The use of the phrase "ground" in the foregoing description includes chassis ground, earth, floating ground, virtual ground, digital ground, public ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter indicates a difference from the parameter within + / - 10%.

[0077] Modifications are possible in the described embodiments and examples, and other embodiments and examples are possible within the scope of the claims, such as those hereinafter.

Claims

1. An apparatus comprising: a transistor having a first current terminal, a second current terminal, and a transistor control terminal; and a switch coupled between the transistor control terminal and a reference terminal, the switch having a switch control input; and a control circuit having a control input and a control output, the control output coupled to the switch control input, and the control input coupled to at least one of the transistor control terminal, the first current terminal, or the second current terminal.

2. The apparatus of claim 1, wherein the control circuit is configured to: receive a first signal at the control input; in response to the first signal indicating a transition event at the transistor control terminal, provide a second signal at the output to enable the switch.

3. The apparatus of claim 2, wherein the input of the control circuit is coupled to the transistor control terminal.

4. The apparatus of claim 3, wherein the control circuit includes an average value generation circuit, the average value generation circuit coupled to the transistor control terminal and configured to provide a third signal representing an average value of the first signal over time; and wherein the control circuit is configured to provide the second signal in response to the first signal exceeding the third signal.

5. The apparatus of claim 3, wherein the control circuit includes a rate measurement circuit, the rate measurement circuit coupled to the transistor control terminal and configured to provide a third signal representing a rate of change of the first signal; and wherein the control circuit is configured to provide the second signal in response to the third signal exceeding a threshold value.

6. The apparatus of claim 2, wherein the input of the control circuit is coupled to a current sensor, the current sensor coupled to at least one of the first current terminal or second current terminal, and the first signal is indicative of an amount of current through the transistor; and wherein the control circuit is configured to provide the second signal in response to the first signal exceeding a threshold value.

7. The apparatus of claim 1, wherein the reference terminal is coupled to one of the first current terminal or second current terminal.

8. The apparatus of claim 7, wherein the transistor is a first transistor, and the apparatus further comprises a diode-connected second transistor coupled between the reference terminal and the one of the first current terminal or second current terminal.

9. The apparatus of claim 1, further comprising an average value generation circuit having an input and an output, the input of the average value generation circuit coupled to the transistor control terminal, and the output of the average value generation circuit coupled to the reference terminal, the average value generation circuit configured to provide a time-averaged version of a voltage of the transistor control terminal at the output.

10. The apparatus of claim 1, wherein the control circuit is configured to disable the switch in response to a voltage at the transistor control terminal exceeding a threshold value.

11. The apparatus of claim 10, wherein the transistor is a first transistor; wherein the apparatus further comprises an amplifier having an output coupled to the transistor control terminal; and wherein the control circuit includes a second diode-connected transistor coupled to a power supply of the amplifier to provide the threshold.

12. The apparatus of claim 1, wherein the transistor is part of a first power stage having a first power stage input and a first power stage output, the transistor control terminal is coupled to the first power stage input, and the apparatus further comprises: a linear amplifier having a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input coupled to a first audio input, the second amplifier input coupled to a second audio input, and the amplifier output coupled to the first power stage input; a low pass filter having a first filter input, a second filter input, a first filter output, and a second filter output; a modulator circuit having a first modulator input, a second modulator input, a third modulator input, and a modulator output, the first modulator input coupled to the first filter output, the second modulator input coupled to the second filter output, the third modulator input coupled to the amplifier output; and a second power stage having a second power stage input and a second power stage output, the second power stage input coupled to the modulator output.

13. The apparatus of claim 12, further comprising: a first resistor coupled between the first audio input and the first filter input; a second resistor coupled between the second audio input and the second filter input; a third resistor coupled between the first audio input and the second power stage output; and a fourth resistor coupled between the second audio input and the first power stage output.

14. The apparatus of claim 12, wherein the first power stage output is coupled to a first audio output, and the apparatus further comprises: a first capacitor coupled between the first audio output and a ground terminal; a second capacitor coupled between the first audio output and a second audio output; and an inductor coupled between the second power stage output and the second audio output.

15. An apparatus comprising: an amplifier having an amplifier input and an amplifier output; a first power stage having a first power stage input and a first power stage output, the first power stage input coupled to the amplifier output; a clamp circuit coupled between the first power stage input and a reference terminal, the clamp circuit having a clamp control input coupled to the first power stage; a modulator having a modulator input and a modulator output, the modulator input coupled to the amplifier input; and a second power stage having a second power stage input and a second power stage output, the second power stage input coupled to the modulator output. ​ ​ ​ 16. The apparatus of claim 15, wherein the first power stage includes a transistor having a first current terminal, a second current terminal, and a transistor control terminal, the transistor control terminal coupled to the first power stage input; and wherein the clamp circuit includes: a switch coupled between the transistor control terminal and the reference terminal, the switch having a switch control input; and a control circuit having a control input and a control output, the control output coupled to the switch control input, the control input coupled to at least one of the transistor control terminal, the first current terminal, or the second current terminal via the clamp control input.

17. The apparatus of claim 16, wherein the control circuit is configured to: receive a first signal at the control input; in response to the first signal indicating a transition event at the transistor control terminal, provide a second signal at the output to enable the switch.

18. A method comprising: detecting a voltage transition event at a control terminal of a transistor; and in response to detecting the voltage transition event, setting the control terminal to a reference voltage.

19. The method of claim 18, wherein detecting a voltage transition event at a control terminal of a transistor includes at least one of detecting that a voltage of the control terminal exceeds a time-averaged version of the voltage of the control terminal, detecting that a rate of change of the voltage exceeds a voltage threshold, or detecting that a current through the transistor exceeds a current threshold.

20. The method of claim 18, wherein setting the control terminal to a reference voltage includes at least one of directly connecting the control terminal to a current terminal of the transistor, connecting the control terminal to the current terminal of the transistor via another diode-connected transistor, or connecting the control terminal to an average value generation circuit that generates a time-averaged version of the voltage of the control terminal.

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