A pulse-triggered level shifter

Abstract

The present application relates to the field of integrated circuit technology, and provides a pulse trigger type level shift circuit, which comprises a double pulse current generating circuit, a high-low level shift conversion holding circuit, a high voltage domain output shaping filter circuit and an RS flip-flop connected in sequence. The double pulse current generating circuit generates a short double pulse current signal in response to a jump edge of a low voltage domain input signal; the high-low level shift conversion holding circuit combines the current signal with the input signal to generate a complementary pulse voltage signal in a high voltage domain; the shaping filter circuit shapes and filters the pulse voltage; and the RS flip-flop finally latches the logic state and outputs a stable high voltage domain signal without glitches. The present application generates an extremely short pulse only when the signal jumps by means of pulse current trigger, eliminates the static current path, and has low static power consumption. Meanwhile, the pulse driving is used to realize fast level inversion under high voltage difference, and the input signal driving capability requirement is low, so that the high speed and low power consumption characteristics are taken into account.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and other technical fields, and in particular to a pulse-triggered level shifting circuit. Background Technology

[0002] Level shifting circuits are key modules in integrated circuits, responsible for converting signals from one voltage domain to another. For example, they convert low-voltage logic signals from the core processor into high-voltage gate signals capable of driving power devices. As semiconductor technology advances to more advanced process nodes, circuit systems often need to transmit signals between different power domains with significant voltage differences (e.g., 1.2V versus 5V, 12V, or even higher), posing a significant challenge to the performance of level shifting circuits. Traditional level shifting circuits, such as those employing cross-coupled structures, rely on establishing a continuous conduction path on the high-voltage side to achieve level switching and holding. However, during level holding, these circuits have a static current path from the high-voltage power supply to ground, resulting in high static power consumption, a significant drawback in modern electronic devices that emphasize low power consumption. Furthermore, when the voltage difference between the high and low voltage domains is large, the signal switching speed is severely limited due to the low carrier mobility of high-voltage devices and the large parasitic capacitance of circuit nodes, making it difficult to meet the demands of high-speed applications. To overcome speed bottlenecks, it is sometimes necessary to increase the driving capability of the input signal or adopt a more complex circuit structure, but this will further increase the power consumption, area, and load requirements of the overall circuit.

[0003] Therefore, there is an urgent need in this field for a level shifting circuit that can simultaneously achieve low static power consumption and high transmission speed, fundamentally eliminate static current paths, and realize fast and reliable signal conversion under high voltage differences, while avoiding excessive requirements on the driving capability of the input signal. Summary of the Invention

[0004] To address the shortcomings of the existing technology, this invention provides a pulse-triggered level shifting circuit that can simultaneously achieve low static power consumption and high transmission speed level shifting, fundamentally eliminating static current paths and enabling fast and reliable signal conversion under high voltage differences, while avoiding excessive demands on the driving capability of the input signal.

[0005] The pulse-triggered level shifting circuit provided by this invention includes:

[0006] A dual-pulse current generating circuit, wherein the input terminal of the dual-pulse current generating circuit receives a low-voltage domain input signal and is used to generate a dual-pulse current signal in response to the rising and falling edges of the low-voltage domain input signal;

[0007] A high-low level shift-conversion and holding circuit is provided. The first input terminal of the high-low level shift-conversion and holding circuit is connected to the output terminal of the dual-pulse current generation circuit to receive the dual-pulse current signal. Its second input terminal simultaneously receives the low-voltage domain input signal. The high-low level shift-conversion and holding circuit receives the dual-pulse current signal and the low-voltage domain input signal, and converts the dual-pulse current signal into a complementary pulse voltage signal in the high-voltage domain according to the low-voltage domain input signal for output.

[0008] A high-voltage domain output shaping and filtering circuit is provided, the input of which is connected to the output of the high-low level shift-conversion and holding circuit. The circuit is used to shape and filter the complementary pulse voltage signal to obtain the processed complementary pulse voltage signal.

[0009] The RS flip-flop is connected to the output terminal of the high-voltage domain output shaping filter circuit. It is used to latch the logic state represented by the processed complementary pulse voltage signal and output a stable and glitch-free high-voltage domain output signal.

[0010] Furthermore, the dual-pulse current generation circuit includes a first pulse generation circuit and a second pulse generation circuit. The first pulse generation circuit responds to the low-voltage domain input signal Vin to generate one pulse current signal in the dual-pulse current signal. The second pulse generation circuit responds to the complementary signal of the low-voltage domain input signal Vin. To generate one pulse current signal in the dual-pulse current signal. .

[0011] Furthermore, the first pulse generation circuit includes a first delay module delay, which is used to delay the low-voltage domain input signal Vin to generate a delayed signal; the first pulse generation circuit is configured to generate a pulse current when the low-voltage domain input signal Vin and its delayed signal are both at an active level.

[0012] Furthermore, the second pulse generation circuit includes a second delay module, delay, which is used to generate a complementary signal of the low-voltage domain input signal Vin. Delay to generate a delayed signal; the second pulse generation circuit is configured to input a complementary signal of the signal Vin in the low-voltage domain. When both the delayed signal and the active level are present, a pulse current is generated.

[0013] Furthermore, the first pulse generation circuit includes a first transistor M1, a third transistor M3, a fifth transistor M5, and a seventh transistor M7; the gate of the first transistor M1 receives the low-voltage domain input signal Vin, the gate of the third transistor M3 receives the delay signal generated by the first delay module delay according to the low-voltage domain input signal Vin, the gate of the fifth transistor M5 is connected to the low-voltage domain power supply VCC, the source of the fifth transistor M5 is electrically connected to the drain of the third transistor M3, the source of the third transistor M3 is electrically connected to the drain of the first transistor M1, the source of the first transistor M1 is grounded, the drain of the fifth transistor M5 is electrically connected to the drain of the seventh transistor M7, and the source of the seventh transistor M7 is connected to the high-voltage domain power supply POW.

[0014] Furthermore, the gate of the seventh transistor M7 is the output terminal of the first pulse generation circuit, used to output one pulse current signal from the dual-pulse current signal. .

[0015] Furthermore, the first transistor M1 and the third transistor M3 are low-voltage transistors in the low-voltage domain, the fifth transistor M5 is a high-voltage transistor, and the seventh transistor M7 is a low-voltage transistor in the high-voltage domain.

[0016] Furthermore, the second pulse generation circuit includes a second transistor M2, a fourth transistor M4, a sixth transistor M6, and an eighth transistor M8; the gate of the second transistor M2 receives a complementary signal to the low-voltage domain input signal Vin. The gate of the fourth transistor M4 receives the complementary signal of the second delay module delay based on the low-voltage domain input signal Vin. The generated delayed signal has its gate connected to the low-voltage power supply VCC, its source connected to the drain of the fourth transistor M4, its source connected to the drain of the second transistor M2, its source grounded, its drain connected to the drain of the eighth transistor M8, and its source connected to the high-voltage power supply POW.

[0017] Furthermore, the second transistor M2 and the fourth transistor M4 are low-voltage transistors in the low-voltage domain, the sixth transistor M6 is a high-voltage transistor, and the eighth transistor M8 is a low-voltage transistor in the high-voltage domain.

[0018] Furthermore, the gate of the eighth transistor M8 is the output terminal of the second pulse generation circuit, used to output one pulse current signal from the dual-pulse current signal. .

[0019] Compared with the prior art, the beneficial effects of this invention are as follows:

[0020] This invention provides a pulse-triggered level shifting circuit, including a dual-pulse current generating circuit, a high-low level shift-conversion and holding circuit, a high-voltage domain output shaping and filtering circuit, and an RS flip-flop. The input terminal of the dual-pulse current generating circuit receives a low-voltage domain input signal and generates a dual-pulse current signal in response to the rising and falling edges of the low-voltage domain input signal. The first input terminal of the high-low level shift-conversion and holding circuit is connected to the output terminal of the dual-pulse current generating circuit and receives the dual-pulse current signal; its second input terminal simultaneously receives the low-voltage domain input signal. The high-low level shift-conversion and holding circuit receives the output signal... The invention utilizes a dual-pulse current signal and a low-voltage domain input signal. Based on the low-voltage domain input signal, the dual-pulse current signal is converted into a complementary pulse voltage signal in the high-voltage domain for output. The input of the high-voltage domain output shaping and filtering circuit is connected to the output of the high-low level shift-and-hold circuit, used to shape and filter the complementary pulse voltage signal to obtain a processed complementary pulse voltage signal. The RS flip-flop is connected to the output of the high-voltage domain output shaping and filtering circuit, used to latch the logic state represented by the processed complementary pulse voltage signal, and output a stable and glitch-free high-voltage domain output signal. This invention simultaneously achieves low static power consumption and high transmission speed level shifting, fundamentally eliminating static current paths and realizing fast and reliable signal conversion under high voltage differences, while avoiding excessive demands on the input signal's driving capability. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. Some specific embodiments of the invention will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0022] Figure 1 This is a schematic diagram of a circuit structure of a pulse-triggered level shifting circuit according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a circuit structure for a dual-pulse current generation circuit according to an embodiment of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] See Figures 1-2 This invention provides a pulse-triggered level shifting circuit, comprising:

[0026] A dual-pulse current generating circuit, wherein the input terminal of the dual-pulse current generating circuit receives a low-voltage domain input signal and is used to generate a dual-pulse current signal in response to the rising and falling edges of the low-voltage domain input signal;

[0027] A high-low level shift-conversion and holding circuit is provided. The first input terminal of the high-low level shift-conversion and holding circuit is connected to the output terminal of the dual-pulse current generation circuit to receive the dual-pulse current signal. Its second input terminal simultaneously receives the low-voltage domain input signal. The high-low level shift-conversion and holding circuit receives the dual-pulse current signal and the low-voltage domain input signal, and converts the dual-pulse current signal into a complementary pulse voltage signal in the high-voltage domain according to the low-voltage domain input signal for output.

[0028] A high-voltage domain output shaping and filtering circuit is provided, the input of which is connected to the output of the high-low level shift-conversion and holding circuit. The circuit is used to shape and filter the complementary pulse voltage signal to obtain the processed complementary pulse voltage signal.

[0029] The RS flip-flop is connected to the output terminal of the high-voltage domain output shaping filter circuit. It is used to latch the logic state represented by the processed complementary pulse voltage signal and output a stable and glitch-free high-voltage domain output signal.

[0030] In this embodiment, by setting up a dual-pulse current generation circuit and limiting its generation of dual-pulse current signals in response to the rising and falling edges of the low-voltage domain input signal, the circuit generates a brief pulse current only at the moment the input signal changes direction. During the majority of the signal's stable holding period, there is no continuous current path, thereby reducing the circuit's static power consumption. The high-low level shift-conversion and holding circuit receives the dual-pulse current signal and the low-voltage domain input signal, and converts them into a complementary pulse voltage signal in the high-voltage domain. The pulse current can rapidly charge and discharge the parasitic capacitance of subsequent circuit nodes at an extremely high speed, thereby achieving rapid level switching. The switching speed is reduced due to the influence of the high-voltage device mobility. The instantaneous pulse current provided by the dual-pulse current generation circuit serves to drive the high-voltage domain circuit and charge the parasitic capacitance, relaxing the driving capability requirements of the preceding low-voltage domain input signal. The preceding circuit no longer needs to be designed to be excessively large to drive large-size high-voltage devices, thus simplifying the overall power consumption of the circuit. The high-voltage domain output shaping and filtering circuit shapes and filters the complementary pulse voltage signal. The RS flip-flop latches the logic state of the shaped and filtered complementary pulse voltage signal, outputting a stable and glitch-free high-voltage domain output signal. This effectively suppresses noise introduced by the pulse and ensures that the output level remains stable after the pulse ends, achieving a glitch-free and logically reliable high-voltage domain output and guaranteeing the stability of the entire circuit.

[0031] Preferably, the dual-pulse current generation circuit includes a first pulse generation circuit and a second pulse generation circuit. The first pulse generation circuit responds to the low-voltage input signal Vin to generate one pulse current signal in the dual-pulse current signal. The second pulse generation circuit responds to the complementary signal of the low-voltage domain input signal Vin. To generate one pulse current signal in the dual-pulse current signal. .

[0032] In this embodiment, by having the first pulse generation circuit and the second pulse generation circuit respond to the original signal Vin and its complementary signal respectively, independent and precise response to the rising and falling edges of the input signal can be achieved. This ensures that regardless of whether the input signal transitions from low to high or from high to low, a corresponding pulse current signal with a clear direction can be generated, fundamentally guaranteeing the correctness and integrity of the level shifting operation.

[0033] Preferably, the first pulse generation circuit includes a first delay module `delay`, which delays the low-voltage input signal Vin to generate a delayed signal; the first pulse generation circuit is configured to generate a pulse current when both the low-voltage input signal Vin and its delayed signal are at active levels. The second pulse generation circuit includes a second delay module `delay`, which delays the complementary signal of the low-voltage input signal Vin. Delay to generate a delayed signal; the second pulse generation circuit is configured to input a complementary signal of the signal Vin in the low-voltage domain. When both the delayed signal and the active level are present, a pulse current is generated.

[0034] In this embodiment, by setting a first delay module in the first pulse generation circuit and configuring the first pulse generation circuit to generate a pulse current when the low-voltage domain input signal Vin and its delay signal are both at an effective level, precise generation and control of the pulse width can be achieved. The pulse is generated only within a very short time (i.e., within the delay time) after the original signal transition is completed, ensuring that the generated pulse current signal has a fixed and narrow width, thereby limiting the pulse duration, effectively reducing dynamic power consumption, avoiding interference to the subsequent circuit state that may be caused by an excessively wide pulse, and improving the circuit's noise immunity and stability. By setting a second delay module in the second pulse generation circuit and configuring the second pulse generation circuit to generate a pulse current when the complementary signal of the low-voltage domain input signal Vin and its delay signal are both at an effective level, symmetrical and precise complementary pulse control with the first pulse path can be achieved. This allows the two pulse currents to achieve good matching and symmetry in timing characteristics and pulse shape, providing balanced driving capability for subsequent circuits, ensuring consistent switching speed of the output signal during the rise and fall processes, and optimizing the quality of the output waveform.

[0035] Preferably, the first pulse generation circuit includes a first transistor M1, a third transistor M3, a fifth transistor M5, and a seventh transistor M7. The gate of the first transistor M1 receives the low-voltage input signal Vin. The gate of the third transistor M3 receives a delay signal generated by the first delay module delay based on the low-voltage input signal Vin. The gate of the fifth transistor M5 is connected to the low-voltage power supply VCC. The source of the fifth transistor M5 is electrically connected to the drain of the third transistor M3. The source of the third transistor M3 is electrically connected to the drain of the first transistor M1. The source of the first transistor M1 is grounded. The drain of the fifth transistor M5 is electrically connected to the drain of the seventh transistor M7. The source of the seventh transistor M7 is connected to the high-voltage power supply POW. The gate of the seventh transistor M7 is the output terminal of the first pulse generation circuit, used to output one pulse current signal from the dual-pulse current signals. The first transistor M1 and the third transistor M3 are low-voltage transistors in the low-voltage domain, the fifth transistor M5 is a high-voltage transistor, and the seventh transistor M7 is a low-voltage transistor in the high-voltage domain.

[0036] In this embodiment, the first pulse generation circuit includes a first transistor M1, a third transistor M3, a fifth transistor M5, and a seventh transistor M7, enabling efficient and reliable pulse current generation. The series connection of M1 and M3 forms the core unit for implementing logic functions, jointly controlling pulse formation. M5, as a high-voltage transistor, works in conjunction with M7, undertaking the crucial task of converting low-voltage domain logic control into high-voltage domain pulse current output. The gate of the seventh transistor M7 is the output terminal of the first pulse generation circuit, utilizing the voltage control characteristics of the transistor gate to simplify the signal transmission path within the circuit. The first transistor M1 and the third transistor M3 are low-voltage transistors in the low-voltage domain, the fifth transistor M5 is a high-voltage transistor, and the seventh transistor M7 is a low-voltage transistor in the high-voltage domain, enabling reliable operation and performance optimization of the circuit under high-voltage environments. M1 and M3 use low-voltage transistors to ensure fast switching and low response delay in the low-voltage domain; M5, as a high-voltage transistor, withstands most of the voltage drop between the high-voltage power supply (POW) and the low-voltage logic circuit, protecting M1 and M3 from breakdown; M7, as a low-voltage transistor in the high-voltage domain, has a gate oxide layer that can withstand high voltage, ensuring the reliability of the output node.

[0037] Preferably, the second pulse generation circuit includes a second transistor M2, a fourth transistor M4, a sixth transistor M6, and an eighth transistor M8; the gate of the second transistor M2 receives a complementary signal to the low-voltage input signal Vin. The gate of the fourth transistor M4 receives the complementary signal of the second delay module delay based on the low-voltage domain input signal Vin. The generated delayed signal has the gate of the sixth transistor M6 connected to the low-voltage domain power supply VCC, the source of the sixth transistor M6 electrically connected to the drain of the fourth transistor M4, the source of the fourth transistor M4 electrically connected to the drain of the second transistor M2, the source of the second transistor M2 grounded, and the drain of the sixth transistor M6 electrically connected to the drain of the eighth transistor M8. The source of the eighth transistor M8 is connected to the high-voltage domain power supply POW. The second transistor M2 and the fourth transistor M4 are low-voltage transistors in the low-voltage domain, the sixth transistor M6 is a high-voltage transistor, and the eighth transistor M8 is a low-voltage transistor in the high-voltage domain. The gate of the eighth transistor M8 is the output terminal of the second pulse generation circuit, used to output one pulse current signal from the dual-pulse current signal. .

[0038] In this embodiment, the second pulse generation circuit includes a second transistor M2, a fourth transistor M4, a sixth transistor M6, and an eighth transistor M8, enabling a complementary signal processing path that is completely symmetrical with the first pulse generation circuit. The second pulse generation circuit and the first pulse generation circuit form a mirror image symmetry, ensuring consistent response characteristics to positive and negative transitions, thereby guaranteeing the accuracy of the duty cycle of the final output signal and simplifying circuit design and layout. The second transistor M2 and the fourth transistor M4 are low-voltage transistors in the low-voltage domain, the sixth transistor M6 is a high-voltage transistor, and the eighth transistor M8 is a low-voltage transistor in the high-voltage domain. This ensures that the complementary path matches the main path in terms of electrical performance and reliability, ensuring that the second pulse generation circuit maintains functional symmetry with the first pulse generation circuit while also possessing the same level of withstand voltage and switching speed. This allows the entire dual-pulse generation circuit to operate stably and harmoniously under high voltage differential environments. The gate of the eighth transistor M8 is the output terminal of the second pulse generation circuit, enabling the output and control of the complementary path pulse signal, maintaining a mechanism consistent with the main path. The second pulse signal is also output in voltage form. It is the same as the first output (the gate of M7) in terms of signal type and control mechanism, which facilitates the design of subsequent high-low level shift conversion and holding circuits. This allows the circuit to use a symmetrical or similar structure to receive and process these two control signals, simplifying the overall circuit architecture.

[0039] It should be noted that the above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pulse-triggered level shifting circuit, characterized in that, include: A dual-pulse current generating circuit, wherein the input terminal of the dual-pulse current generating circuit receives a low-voltage domain input signal and is used to generate a dual-pulse current signal in response to the rising and falling edges of the low-voltage domain input signal; A high-low level shift-conversion and holding circuit is provided. The first input terminal of the high-low level shift-conversion and holding circuit is connected to the output terminal of the dual-pulse current generation circuit to receive the dual-pulse current signal. Its second input terminal simultaneously receives the low-voltage domain input signal. The high-low level shift-conversion and holding circuit receives the dual-pulse current signal and the low-voltage domain input signal, and converts the dual-pulse current signal into a complementary pulse voltage signal in the high-voltage domain according to the low-voltage domain input signal for output. A high-voltage domain output shaping and filtering circuit is provided, the input of which is connected to the output of the high-low level shift-conversion and holding circuit. The circuit is used to shape and filter the complementary pulse voltage signal to obtain the processed complementary pulse voltage signal. RS flip-flop, which is connected to the output terminal of the high-voltage domain output shaping filter circuit, is used to latch the logic state represented by the processed complementary pulse voltage signal and output a stable and glitch-free high-voltage domain output signal. The dual-pulse current generation circuit includes a first pulse generation circuit and a second pulse generation circuit. The first pulse generation circuit responds to the low-voltage input signal Vin to generate one pulse current signal in the dual-pulse current signal. The second pulse generation circuit responds to the complementary signal of the low-voltage domain input signal Vin. To generate one pulse current signal in the dual-pulse current signal. The first pulse generation circuit includes a first delay module delay, which is used to delay the low-voltage domain input signal Vin to generate a delayed signal. The first pulse generation circuit is configured to generate a pulse current when the low-voltage domain input signal Vin and its delayed signal are both at an active level.

2. The pulse-triggered level shifting circuit as described in claim 1, characterized in that, The second pulse generation circuit includes a second delay module, delay, which is used to generate a complementary signal of the low-voltage domain input signal Vin. Delay to generate a delayed signal; the second pulse generation circuit is configured to input a complementary signal of the signal Vin in the low-voltage domain. When both the delayed signal and the active signal are at the same level, a pulse current is generated.

3. The pulse-triggered level shifting circuit as described in claim 2, characterized in that, The first pulse generation circuit includes a first transistor M1, a third transistor M3, a fifth transistor M5, and a seventh transistor M7. The gate of the first transistor M1 receives the low-voltage input signal Vin. The gate of the third transistor M3 receives the delay signal generated by the first delay module delay according to the low-voltage input signal Vin. The gate of the fifth transistor M5 is connected to the low-voltage power supply VCC. The source of the fifth transistor M5 is electrically connected to the drain of the third transistor M3. The source of the third transistor M3 is electrically connected to the drain of the first transistor M1. The source of the first transistor M1 is grounded. The drain of the fifth transistor M5 is electrically connected to the drain of the seventh transistor M7. The source of the seventh transistor M7 is connected to the high-voltage power supply POW.

4. The pulse-triggered level shifting circuit as described in claim 3, characterized in that, The gate of the seventh transistor M7 is the output terminal of the first pulse generation circuit, used to output one pulse current signal from the dual-pulse current signal. .

5. The pulse-triggered level shifting circuit as described in claim 3, characterized in that, The first transistor M1 and the third transistor M3 are low-voltage transistors in the low-voltage domain, the fifth transistor M5 is a high-voltage transistor, and the seventh transistor M7 is a low-voltage transistor in the high-voltage domain.

6. The pulse-triggered level shifting circuit as described in claim 3, characterized in that, The second pulse generation circuit includes a second transistor M2, a fourth transistor M4, a sixth transistor M6, and an eighth transistor M8; the gate of the second transistor M2 receives a complementary signal to the low-voltage input signal Vin. The gate of the fourth transistor M4 receives the complementary signal of the second delay module delay based on the low-voltage domain input signal Vin. The generated delayed signal has its gate connected to the low-voltage power supply VCC, its source connected to the drain of the fourth transistor M4, its source connected to the drain of the second transistor M2, its source grounded, its drain connected to the drain of the eighth transistor M8, and its source connected to the high-voltage power supply POW.

7. The pulse-triggered level shifting circuit as described in claim 6, characterized in that, The second transistor M2 and the fourth transistor M4 are low-voltage transistors in the low-voltage domain, the sixth transistor M6 is a high-voltage transistor, and the eighth transistor M8 is a low-voltage transistor in the high-voltage domain.

8. The pulse-triggered level shifting circuit as described in claim 7, characterized in that, The gate of the eighth transistor M8 is the output terminal of the second pulse generation circuit, used to output one pulse current signal from the dual-pulse current signal. .

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