Floating gate type flash memory structure, forming method and electronic device
By forming a gradient floating gate structure through multiple deposition and etching processes, the problem of difficulty in adjusting the height and length of the floating gate in traditional floating gate flash memory structures under the requirements of miniaturization and high performance is solved. This optimizes the electrical characteristics of the memory cell and improves the reliability and read/write speed of the flash memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-03-10
Smart Images
Figure CN121284966B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a floating gate type flash memory structure, a method for forming it, and an electronic device. Background Technology
[0002] With the ever-increasing demands for storage performance and reliability in modern electronic devices, embedded flash memory has become a core storage solution for various consumer electronics products. Floating-gate flash memory cells, with their excellent non-volatility, high integration, and low power consumption, are widely used in smartphones, tablets, smart home devices, and other devices, and have significant advantages in high-speed data access, persistent storage, and miniaturized design.
[0003] However, with the increase in storage capacity and data transfer rate, the performance bottleneck of traditional floating-gate flash memory has gradually become apparent. Specifically, the size and shape of the floating gate in existing technologies are usually fixed, which limits the space for fine-tuning and optimization of flash memory cells. Especially with the increasing demands for miniaturization and high performance, the height and length of the floating gate often cannot be flexibly varied, making it difficult to further optimize the electrical characteristics of the floating-gate memory cells (such as programming voltage, erase voltage, read current, etc.). This not only affects the read and write speed of the memory cells but may also accelerate the leakage of floating gate charge, reducing the long-term reliability of the memory. In addition, the floating gate structure in existing technologies usually adopts a gate design with fixed thickness and length. This design scheme is prone to problems such as insufficient space layout and mutual interference between memory cells when facing high-density storage requirements, thus affecting the performance of the entire storage system. More importantly, as the size of memory cells continues to shrink, the control precision of charge injection and removal in traditional floating-gate structures gradually decreases, making it difficult to guarantee the stability and reliability of high-density flash memory cells under high-frequency read and write operations.
[0004] Therefore, there is an urgent need for a new floating-gate flash memory cell structure that can provide greater design flexibility while maintaining or improving storage performance. This allows the height and length of the floating gate to be flexibly adjusted as needed, thereby optimizing the electrical characteristics of the storage cell and improving the reliability, durability, and read / write speed of the flash memory. Summary of the Invention
[0005] This application provides a floating gate type flash memory structure, a method for forming it, and an electronic device to at least solve the above-mentioned problems existing in the related art.
[0006] To solve the above-mentioned technical problems, the technical solution of this application is as follows:
[0007] According to a first aspect of the embodiments of this application, a floating-gate flash memory structure is provided, comprising:
[0008] Substrate;
[0009] an ion implant layer formed on the substrate, source and drain formed in the ion implant layer;
[0010] a select gate formed on the ion implant layer;
[0011] a trench formed through the select gate and stopping on the surface of the ion implant layer, a floating gate structure with gradient formed on the bottom and opposite sidewalls of the trench, the floating gate structure formed by multiple deposition and etching of floating gate material in the trench, the thickness of each deposition of floating gate material less than the thickness of previous deposition of floating gate material, a control gate formed in the area of the trench other than the floating gate structure;
[0012] an erase gate formed on the control gate and the select gate.
[0013] In some embodiments, two floating gate structures with gradient are formed in the trench, the control gate formed between the two floating gate structures with gradient;
[0014] Each of the floating gate structures has multiple gradients, the number of the multiple gradients same as the number of the multiple deposition.
[0015] In some embodiments, the gap between the bottoms of the two floating gate structures with gradient is 800-1000 angstrom, the position of the source in the ion implant layer is below the gap, and the length of the source is greater than the length of the gap.
[0016] In some embodiments, the multiple deposition and etching includes but is not limited to three deposition and etching, the thickness of the first deposition of floating gate material is 1100-1300 angstrom, the thickness of the second deposition of floating gate material is 500-700 angstrom, and the thickness of the third deposition of floating gate material is 100-200 angstrom.
[0017] In some embodiments, the height of the floating gate structure is 1200-1500 angstrom.
[0018] In some embodiments, the floating gate material is N-type or P-type doped polysilicon, or the floating gate material is N-type or P-type doped amorphous silicon.
[0019] In some embodiments, the floating gate flash memory structure further comprises:
[0020] a target oxide layer formed on the select gate, the trench formed through the target oxide layer and the select gate and stopping on the surface of the ion implant layer, and the erase gate formed on the control gate and the oxide layer.
[0021] In some embodiments, the floating gate type flash memory structure further comprises:
[0022] a side wall formed on the side of the erase gate, and on the side of the target oxide layer and the select gate.
[0023] In some embodiments, the floating gate type flash memory structure further comprises:
[0024] an isolation layer, the isolation layer comprising a first isolation layer and a second isolation layer;
[0025] the first isolation layer is formed on the surface of the ion implantation layer facing away from the substrate, the surface and side of the target oxide layer, the surface and side of the erase gate, between the control gate and the erase gate;
[0026] the second isolation layer is formed on the side wall of the trench, and between the floating gate structure and the control gate.
[0027] A second aspect of the embodiments of the present application provides a floating gate type flash memory structure forming method, the forming method comprising:
[0028] providing a substrate;
[0029] forming an ion implantation layer on the substrate;
[0030] forming a select gate on the ion implantation layer;
[0031] forming a trench through the select gate and stopping on the surface of the ion implantation layer;
[0032] performing multiple times of deposition and etching of floating gate material on the bottom and opposite side walls of the trench to obtain a floating gate structure with gradient; the thickness of each time of deposition of floating gate material is less than the thickness of the previous time of deposition of floating gate material;
[0033] forming a source in the substrate;
[0034] forming a control gate in the region of the trench other than the floating gate structure;
[0035] forming an erase gate on the control gate and the select gate;
[0036] forming a drain in the substrate.
[0037] In some embodiments, the multiple times of deposition and etching include but are not limited to three times of deposition and etching, the multiple times of deposition and etching of floating gate material on the bottom and opposite side walls of the trench to obtain a floating gate structure with gradient, comprising:
[0038] The first deposition and etching of the floating gate material is performed on the bottom and opposite sidewalls of the trench to obtain a first floating gate structure; the thickness of the first deposited floating gate material is 1100-1300 angstroms;
[0039] The second deposition and etching of the floating gate material is performed on the top and opposite sidewalls of the first floating gate structure to obtain a second floating gate structure; the thickness of the second deposited floating gate material is 500-700 angstroms;
[0040] The third deposition and etching of the floating gate material is performed on the top and opposite sidewalls of the second floating gate structure to obtain a third floating gate structure; the thickness of the third deposited floating gate material is 100-200 angstroms;
[0041] The first floating gate structure, the second floating gate structure, and the third floating gate structure form the floating gate structure with a gradient.
[0042] In some embodiments, the first floating gate structure is two, and the cross-sectional shape of each of the first floating gate structures is a sector, and the gap between the bottoms of the two first floating gate structures is 800-1000 angstroms;
[0043] The second floating gate structure is two, and the cross-sectional shape of the surface of each of the second floating gate structures is an arc, and the distance between the second floating gate structures and the corresponding sidewalls of the trench is less than the distance between the first floating gate structures and the corresponding sidewalls of the trench;
[0044] The third floating gate structure is two, and the cross-sectional shape of the surface of each of the third floating gate structures is an arc, and the distance between the third floating gate structures and the corresponding sidewalls of the trench is less than the distance between the second floating gate structures and the corresponding sidewalls of the trench.
[0045] In some embodiments, before the trench is formed through the select gate and stops at the surface of the ion implantation layer, the method further comprises:
[0046] A target oxide layer is formed on the select gate;
[0047] The trench is formed through the select gate and stops at the surface of the ion implantation layer, comprising:
[0048] The trench is formed through the target oxide layer and the select gate and stops at the surface of the ion implantation layer;
[0049] The erase gate is formed on the control gate and the select gate, comprising:
[0050] The erase gate is formed on the target oxide layer and the control gate.
[0051] In some embodiments, before forming a control gate in the region of the trench other than the floating gate structure, the method further includes:
[0052] An oxide layer with a thickness of 20 Å-30 Å is formed on the surface of the floating gate structure;
[0053] A nitride layer with a thickness of 60 Å-80 Å is formed on the surface of the oxide layer with a thickness of 20 Å-30 Å;
[0054] An oxide layer with a thickness of 30 Å-50 Å is formed on the surface of the nitride layer with a thickness of 60 Å-80 Å to obtain a second isolation layer;
[0055] The control gate is formed in the region of the trench other than the floating gate structure, including:
[0056] The control gate is formed on the second isolation layer.
[0057] In some embodiments, after forming a control gate in a region of the trench other than the floating gate structure, the method further includes:
[0058] A first isolation layer with a thickness of 80Å-100Å is formed on the surface of the control gate;
[0059] After forming an erase gate on the control gate and the select gate, the method further includes:
[0060] Sidewalls are formed on the side of the erase gate, and on the side of the target oxide layer and the select gate.
[0061] In some embodiments, the method further includes:
[0062] A first isolation layer is formed on the surface of the ion implantation layer opposite to the substrate, the surface and sides of the target oxide layer, the surface and sides of the erase gate, and the side of the select gate;
[0063] A second isolation layer is formed on the sidewall of the trench.
[0064] A third aspect of this application provides an electronic device including a floating-gate flash memory structure as described in any of the above embodiments.
[0065] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:
[0066] This application provides a floating-gate flash memory structure, a formation method, and an electronic device. The floating-gate flash memory structure includes a substrate; an ion implantation layer formed on the substrate, wherein an active electrode and a drain electrode are formed in the ion implantation layer; a select gate formed on the ion implantation layer; a trench extending through the select gate and ending at the surface of the ion implantation layer; a gradient floating gate structure formed on the bottom and opposite sidewalls of the trench, wherein the floating gate structure is obtained by multiple depositions and etchings of floating gate material in the trench, wherein the thickness of each deposition of floating gate material is less than the thickness of the previous deposition; a control gate is formed in the area of the trench other than the floating gate structure; and an erase gate formed on the control gate and the select gate. Because the floating gate structure is obtained by multiple depositions and etchings of floating gate material in the trench, and the thickness of each deposition of floating gate material is less than the thickness of the previous deposition, the final floating gate structure is a gradient floating gate structure. As can be seen, the floating gate structure in this embodiment does not adopt a gate design with fixed thickness and length, but rather a gradient floating gate structure formed by multiple depositions and etchings. The height and length of this gradient floating gate structure can be flexibly adjusted according to actual needs during multiple depositions and etchings, thereby providing greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance. This optimizes the electrical characteristics of the storage cell and improves the reliability, durability, and read / write speed of the flash memory.
[0067] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0068] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.
[0069] Figure 1 This is a flowchart illustrating a method for forming a floating gate type flash memory structure according to an embodiment of this application.
[0070] Figures 2-12 This is a schematic diagram of the structure presented in each step of the method for forming the floating gate type flash memory structure in the embodiments of this application.
[0071] In the figure, the corresponding reference numerals are: 1-substrate, 2-ion implantation layer, 3-oxide layer, 4-select gate, 5-target oxide layer, 6-trench, 7-nitride layer, 8-floating gate structure, 801-first floating gate structure, 802-second floating gate structure, 803-third floating gate structure, 9-source, 10-control gate, 11-erase gate, 12-sidewall, 13-drain. Detailed Implementation
[0072] The following provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below in a simplified manner. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of an initial feature above or on a second feature in the following description may include embodiments where the initial and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the initial and second features such that the initial and second features do not need to be in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances throughout this application. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0073] Additionally, spatial relative terms, such as “below,” “under,” “lower part,” “above,” “upper part,” “front,” “back,” “above,” and similar terms, may be used in this application for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures.
[0074] Figure 1 This is a flowchart illustrating a method for forming a floating-gate flash memory structure according to an embodiment of this application. Figures 2-12 This is a schematic diagram illustrating the structural steps of the method for forming the floating-gate flash memory structure in the embodiments of this application. For example... Figure 1 As shown, the forming method includes:
[0075] S11. Provide a substrate.
[0076] The embodiments of this application can select a suitable substrate material according to actual needs. For example, the material of substrate 1 may include silicon, glass or quartz, etc. The silicon substrate may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate, etc. The embodiments of this application do not limit the material of the substrate.
[0077] S12. An ion implantation layer is formed on the substrate.
[0078] like Figure 2As shown, in some embodiments, the ion implantation layer 2 can be a P-type ion implantation layer, and the dopant used in the P-type ion implantation layer can be boron (B), indium (In), gallium (Ga), etc. The ion implantation layer 2 can be formed by performing P-type ion implantation on the substrate 1 using an ion implantation process.
[0079] In other embodiments, the ion implantation layer 2 may also be an N-type ion implantation layer, depending on actual needs.
[0080] S13. A selection gate is formed on the ion implantation layer.
[0081] Continue as Figure 2 As shown, in some embodiments, an oxide layer 3 can be formed on the surface of the ion implantation layer 2 away from the substrate 1 to form a first isolation layer. The material of the oxide layer 3 can be SiO2, HfO2, etc., and there is no specific limitation on it.
[0082] Next, a gate material of a predetermined thickness is deposited on the surface of the ion implantation layer 2 facing away from the substrate 1 (specifically, the surface of the first isolation layer) using a deposition process. Then, the gate pattern is defined by photolithography, and finally, the select gate 4 is formed by etching.
[0083] It should be noted that the embodiments of this application do not limit the growth process of the oxide layer, the deposition process of the gate material, the photolithography process, the etching process, etc.
[0084] Optionally, the material of the select gate 4 can be N-type or P-type doped polysilicon, or the floating gate material can be N-type or P-type doped amorphous silicon. Preferably, the material of the select gate 4 can be N-type or P-type doped polysilicon.
[0085] In some embodiments, before forming a trench that extends through the select gate and stops at the surface of the ion implantation layer, the method further includes forming a target oxide layer on the select gate.
[0086] Optionally, the target oxide layer 5 can serve as an isolation layer, and its material can include, but is not limited to, SiO2. It can be formed on the select gate 4 by a deposition process. This application does not limit the specific process of the deposition process.
[0087] S14. Form a trench that extends through the select gate and stops at the surface of the ion implantation layer.
[0088] Continue as Figure 2 As shown, in some embodiments, the target oxide layer 5 and the select gate 4 can be etched sequentially by an etching process, and then the etching stops at the surface of the ion implantation layer 2 to obtain a trench 6 that penetrates the target oxide layer 5 and the select gate 4.
[0089] Alternatively, the trench 6 can be a shallow trench isolation trench (STI).
[0090] For example, the formation process of trench 6 can be as follows:
[0091] Depositing a protective layer on the selected gate 4: Materials such as silicon nitride and aluminum oxide can be used to deposit a protective layer on the selected gate 4 through a deposition process.
[0092] Photolithography defines the STI region: photoresist is retained in the non-trench region.
[0093] Etching: Etching can be performed using gases such as SF6 / C4F8 and C4F8. During the etching process, the etching depth needs to be controlled.
[0094] Remove the protective layer: Remove the photoresist and protective layer in a distributed manner.
[0095] Continue as Figure 2 As shown, in some embodiments, after obtaining the trench 6, a second isolation layer can be formed on the sidewall of the trench 6. The structure of the second isolation layer can be an ONO structure, that is, the second isolation layer includes two oxide layers 3 and a nitride layer 7 located between the two oxide layers 3, thereby suppressing lateral leakage and crosstalk. At the same time, an oxide layer is formed at the bottom of the trench 6 to form a first isolation layer, thereby serving as a longitudinal insulating barrier to prevent the substrate 1 from forming a leakage path.
[0096] As can be seen, this application solves the leakage current and thermomechanical stress of the longitudinal substrate 1 by forming a first isolation layer at the bottom of the trench 6, which is a basic isolation guarantee. By forming an ONO structure on the sidewall of the trench 6, nanoscale lateral electrical isolation is achieved. The combination of the two achieves full-dimensional electrical isolation, effectively ensuring that the storage performance of the floating gate memory structure is maintained or improved.
[0097] It should be noted that this application does not limit the formation process of the first isolation layer and the second isolation layer.
[0098] S15. Multiple depositions and etchings of the floating gate material are performed on the bottom and opposite sidewalls of the trench to obtain a floating gate structure with a gradient; the thickness of each deposition of the floating gate material is less than the thickness of the previous deposition of the floating gate material.
[0099] like Figures 3-5 As shown, in some embodiments, after the trench 6 is formed, the floating gate material can be deposited and etched multiple times at the bottom and opposite sidewalls of the trench 6 to obtain a gradient floating gate structure 8. More specifically, since a second isolation layer is formed on the side of the trench 6, the floating gate material can be deposited at the bottom of the trench 6 and on the opposite sidewalls of the trench 6 where the second isolation layer is formed.
[0100] Optionally, "opposite sidewalls" refers to the two opposite inner sidewalls, left and right, in the cross-section of trench 6.
[0101] Optionally, in order to form a gradient floating gate structure, the thickness of each floating gate material deposition is less than the thickness of the previous floating gate material deposition. Assuming that the number of depositions and etchings is 3, the thickness of the second floating gate material deposition is less than the thickness of the first floating gate material deposition, and the thickness of the third floating gate material deposition is less than the thickness of the second floating gate material deposition.
[0102] It should be noted that this application does not limit the deposition and etching processes for the floating gate material. These processes may include: floating gate material deposition, photolithography to define the floating gate pattern, and floating gate etching. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The etching process may employ a dry etching process, which, due to its anisotropy, high selectivity, and nanometer-level precision, can improve the accuracy of the floating gate etching.
[0103] In some embodiments, the floating gate material may be N-type or P-type doped polycrystalline silicon, or the floating gate material may be N-type or P-type doped amorphous silicon. Preferably, the floating gate material may be N-type or P-type doped polycrystalline silicon.
[0104] S16. A source electrode is formed in the substrate.
[0105] like Figure 6 As shown, in some embodiments, the floating gate structure formed above can be considered as a memory cell, and the position of the source 9 in the substrate 1 can be determined according to the position of the floating gate structure.
[0106] Optionally, the source electrode 9 can be formed in the substrate 1 by ion implantation. The ion type used for ion implantation can be phosphorus or arsenic. It should be noted that the embodiments described herein do not limit the specific process for forming the source electrode 9 by ion implantation.
[0107] S17. A control gate is formed in the area of the trench other than the floating gate structure.
[0108] In some embodiments, before forming a control gate in the region of the trench other than the floating gate structure, the method further includes:
[0109] An oxide layer with a thickness of 20 Å-30 Å is formed on the surface of the floating grating structure.
[0110] A nitride layer with a thickness of 60 Å-80 Å is formed on the surface of the oxide layer with a thickness of 20 Å-30 Å.
[0111] An oxide layer with a thickness of 30 Å-50 Å is formed on the surface of the nitride layer with a thickness of 60 Å-80 Å to obtain a second isolation layer.
[0112] like Figure 7 As shown, optionally, an oxide layer 3 with a thickness of 20 Å-30 Å can be grown on the surface of the final floating gate structure using a rapid thermal oxidation (RTO) process. Next, a nitride layer 7 with a thickness of 60 Å-80 Å is deposited on the 20 Å-30 Å oxide layer as an intermediate layer of the ONO structure. Finally, an oxide layer 3 with a thickness of 30 Å-50 Å is formed on the surface of the 60 Å-80 Å nitride layer using a high-temperature oxidation (HTO) process, resulting in the second isolation layer of the ONO structure. Here, HTO refers to a semiconductor process that grows a silicon dioxide thin film on a silicon substrate at a high temperature of 800-1000°C through a dry or wet oxygen reaction. It can generate a high-purity, low-defect-density thermal oxide layer.
[0113] For example, the material of the oxide layer can be SiO2, HfO2, etc., and the material of the nitride layer can be Si3N4.
[0114] In some embodiments, a control gate is formed in a region of the trench other than the floating gate structure, including:
[0115] The control gate is formed on the second isolation layer.
[0116] like Figure 8 As shown, optionally, after forming a second isolation layer of ONO structure on the surface of the floating gate structure 8, the control gate 10 can be formed on the second isolation layer in the trench 6 by processes such as deposition of control gate material and etching. The material of the control gate 10 can be N-type or P-type doped polysilicon, or the floating gate material can be N-type or P-type doped amorphous silicon. Preferably, the material of the control gate 10 is N-type or P-type doped polysilicon.
[0117] It should be noted that the embodiments of this application do not specifically limit the process of forming the control gate 10 by deposition of control gate material, etching and other processes.
[0118] In some embodiments, the top of the control gate 10 deposited in the trench 6 is lower than the top of the target oxide layer 5. The main purpose is to control the height of the storage gate to be higher than the height of the control gate 10, thereby improving the erasure performance.
[0119] Therefore, by isolating the floating gate structure 8 and the control gate 10 through the second isolation layer of the ONO structure, charge leakage can be prevented, direct short circuits or interference can be avoided, and data retention capability can be improved. At the same time, the second isolation layer of the ONO structure serves as a dielectric layer, enhancing the capacitive coupling between the gates.
[0120] In some embodiments, after forming a control gate in the region of the trench other than the floating gate structure, the method further includes forming a layer with a thickness of 80 Å-100 Å on the surface of the control gate.
[0121] like Figure 9 As shown, optionally, an oxide layer 3 with a thickness of 80Å-100Å can be grown on the surface of the control gate 10 by high-temperature oxidation (HTO) to form an isolation oxide layer, thereby preventing the blocking of leakage paths, reducing power consumption, and effectively ensuring or improving the storage performance of the floating gate memory structure.
[0122] S18. An erase gate is formed on the control gate and the selection gate.
[0123] like Figure 10 As shown, in some embodiments, an erase gate 11 can be formed on the control gate 10 and the select gate 4 by depositing an erase gate material and performing processes such as photolithography and etching. Furthermore, the erase gate 11 can be formed on the control gate 10 and the target oxide layer 5 by depositing an erase gate material and performing processes such as photolithography and etching. It should be noted that, to achieve good isolation between the erase gates 11 formed on the target oxide layer 5, an oxide layer 3 can be formed on the surface of the target oxide layer 5 opposite to the select gate, thus obtaining a first isolation layer.
[0124] Optionally, the specific process of forming the erase gate 11 on the control gate 10 and the target oxide layer 5 by depositing erase gate material and photolithography, etching and other processes may include: depositing erase gate material by ALD, CVD, low-pressure chemical vapor deposition (LPCVD) and other processes, defining the erase gate by photolithography, and etching the erase gate.
[0125] Optionally, the material of the erase gate 11 can be N-type or P-type doped polysilicon, or the floating gate material can be N-type or P-type doped amorphous silicon. Preferably, the material of the erase gate 11 is N-type or P-type doped polysilicon.
[0126] Optionally, the erase gate 11 may cover the entire control gate 10 and a portion of the selection gate 4. Furthermore, the erase gate 11 may cover the entire control gate 10 and a portion of the target oxide layer 5.
[0127] In some embodiments, after the erase gate 11 is formed, an oxide layer can also be formed on the side of the target oxide layer 5, the surface and side of the erase gate 11, and the side of the select gate 4 to form a first isolation layer, which plays a good isolation role and effectively maintains or improves the storage performance of the floating gate type memory structure.
[0128] like Figure 11As shown, in some embodiments, after forming an erase gate 11 on the control gate 10 and the select gate 4, the above method may further include forming a sidewall 12 on the side of the erase gate and on the side of the target oxide layer and the select gate.
[0129] Optionally, the specific process for forming the sidewall 12 may include:
[0130] Sidewall material deposition: Sidewall materials can be deposited using deposition processes such as LPCVD and PECVD. For example, the sidewall material may include SiN, SiO2, etc.
[0131] Anisotropic etching: Anisotropic etching can be performed using a high-density plasma etching machine.
[0132] Post-processing includes annealing and surface passivation.
[0133] Therefore, by forming sidewalls 12 on the side of the erase gate 11 and on the side of the target oxide layer 5 and the select gate 4, the electrical performance can be improved and physical protection can be provided. At the same time, the process integration can be optimized, thereby effectively maintaining or improving the storage performance of the floating gate memory structure.
[0134] It should be noted that this application does not specify the dimensions of the side wall 12, which can be adjusted according to actual business needs.
[0135] S19. A drain electrode is formed in the substrate.
[0136] like Figure 12 As shown, in some embodiments, a lightly doped drain (LDD) region and drain 13 can be formed using processes such as photolithography and ion implantation. The LDD can be considered a shallow, lightly doped region, while the drain 13 can be considered a deep, heavily doped region. Photolithography defines the location of the impurity region, and ion implantation (LDD implantation and drain ion implantation) provides impurities of specific concentrations and depths.
[0137] It should be noted that the embodiments of this application do not specifically limit the photolithography, ion implantation and other processes for forming the lightly doped drain (LDD) region and drain 13.
[0138] The method for forming a floating gate flash memory structure provided in this application involves multiple depositions and etchings of floating gate material on the bottom and opposite sidewalls of a trench to obtain a gradient floating gate structure. The thickness of each deposition of floating gate material is less than the thickness of the previous deposition, resulting in a gradient floating gate structure. It is evident that the floating gate structure in this application does not employ a gate design with fixed thickness and length, but rather a gradient floating gate structure formed through multiple depositions and etchings. The height and length of this gradient floating gate structure can be flexibly adjusted during the multiple deposition and etching processes according to actual needs. This provides greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance, thereby optimizing the electrical characteristics of the storage cell and improving the reliability, durability, and read / write speed of the flash memory.
[0139] The following describes the process of obtaining a gradient floating gate structure through multiple depositions and etchings of the floating gate material in step S15 above, using several examples.
[0140] In some embodiments, the multiple deposition and etching include, but are not limited to, three-stage deposition and etching, wherein the multiple deposition and etching of the floating gate material on the bottom and opposite sidewalls of the trench to obtain a floating gate structure with a gradient includes:
[0141] The first deposition and etching of the floating gate material is performed on the bottom and opposite sidewalls of the trench to obtain the first floating gate structure; the thickness of the first deposited floating gate material is 1100 Å-1300 Å.
[0142] A second deposition and etching of the floating gate material is performed on the top and opposite sidewalls of the first floating gate structure to obtain a second floating gate structure; the thickness of the second deposited floating gate material is 500 Å-700 Å.
[0143] A third deposition and etching of the floating gate material is performed on the top and opposite sidewalls of the second floating gate structure to obtain a third floating gate structure; the thickness of the third deposited floating gate material is 100 Å-200 Å.
[0144] The first floating gate structure, the second floating gate structure, and the third floating gate structure form the floating gate structure with a gradient.
[0145] Continue as Figure 3As shown, in this embodiment, a first deposition and etching of a floating gate material with a thickness of 1100Å-1300Å can be performed on the bottom of the trench 6 and on the two opposite sidewalls to obtain a first floating gate structure 801. Since the "two opposite sidewalls" can refer to the left and right sidewalls of the cross-section of the trench 6, a first deposition and etching of a floating gate material with a thickness of 1100Å-1300Å can be performed on the bottom and left sidewall of the trench 6 to obtain one first floating gate structure 801. Simultaneously, a first deposition and etching of a floating gate material with a thickness of 1100Å-1300Å can be performed on the bottom and right sidewall of the trench 6 to obtain another first floating gate structure 801. That is, two first floating gate structures 801 can be obtained, meaning that this application can form two memory cells.
[0146] Continue as Figure 4 As shown, a second deposition and etching of a floating gate material with a thickness of 1100 Å-1300 Å is then performed on the top and opposite sidewalls of the first floating gate structure 801 to obtain a second floating gate structure 802. Essentially, the second floating gate structure 802 is stacked on top of the first floating gate structure 801 and partially covers the top of the first floating gate structure 801. Since the "opposite two sidewalls" can refer to the left and right sidewalls of the cross-section of the trench 6, a second deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and left sidewall of the first floating gate structure 801 to obtain one second floating gate structure 802. Simultaneously, a second deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and right sidewall of the first floating gate structure 801 to obtain one second floating gate structure 802. In other words, two second floating gate structures 802 can be obtained.
[0147] Continue as Figure 5 As shown, a third deposition and etching of a floating gate material with a thickness of 100 Å-200 Å is then performed on the top and opposite sidewalls of the second floating gate structure 802 to obtain a third floating gate structure 803. Essentially, the third floating gate structure 803 is stacked on top of the second floating gate structure 802 and covers part of the top structure of the second floating gate structure 802. Since the "opposite two sidewalls" can refer to the left and right sidewalls of the cross-section of the trench 6, a third deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and left sidewall of the second floating gate structure 802 to obtain one third floating gate structure 803. Simultaneously, a third deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and right sidewall of the second floating gate structure 802 to obtain one third floating gate structure 803. In other words, two third floating gate structures 803 can be obtained.
[0148] Continue as Figure 5As shown, since the thickness of the floating gate material deposited each time is different and they are stacked sequentially, the first floating gate structure 801, the second floating gate structure 802, and the third floating gate structure 803 can form a floating gate structure 8 with a gradient.
[0149] Because the thickness of the floating gate material deposited in each deposition and etching process varies and has a certain range, the deposition thickness of the floating gate material can be flexibly adjusted according to actual needs during multiple deposition and etching processes. This allows for flexible adjustment of the height and length of the final floating gate structure, thereby providing greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance. This, in turn, optimizes the electrical characteristics of the storage cell and improves the reliability, durability, and read / write speed of flash memory. Furthermore, since the thickness of the floating gate material deposited decreases sequentially with each deposition, the thickness of the floating gate structure left on the sidewalls will be much thinner than the previous one. By adjusting the etching process, more floating gate material can be retained in terms of height, thus increasing the height of the resulting floating gate structure. This further enables flexible adjustment of the height and length of the final floating gate structure.
[0150] Continue as Figure 3 As shown, in some embodiments, the cross-sectional shape of each of the first floating gate structures 801 is fan-shaped, and the gap between the bottoms of two first floating gate structures 801 is 800Å-1000Å.
[0151] Optionally, each of the first floating gate structures 801 has a fan-shaped cross-section, with one side of the fan-shaped first floating gate structure 801 located on the sidewall (more specifically, on the ONO structure layer of the sidewall), and the other side located on the ion implantation layer 2 (more specifically, on the first isolation layer on the ion implantation layer 2).
[0152] The "gap between the bottoms of the two first floating gate structures 801" refers to the distance between the endpoints of the right-angled sides of the two first floating gate structures 801 near the ion implantation layer 2. The "endpoint of the right-angled side" refers to the endpoint of the right-angled side other than the origin of the sector.
[0153] In some embodiments, there are two second floating grid structures 802, and the cross-sectional shape of the surface of each second floating grid structure 802 is arc-shaped. The distance between the second floating grid structure 802 and the sidewall corresponding to the groove 6 is less than the distance between the first floating grid structure 801 and the sidewall corresponding to the groove 6.
[0154] Continue as Figure 4As shown, the cross-sectional shape of the surfaces of both the left and right second floating grid structures 802 is arc-shaped. This "cross-sectional shape" refers to the surface that does not contact the sidewall of the trench 6 cross-section. Because the thickness of the second-deposited floating grid material is reduced, the distance between the left second floating grid structure 802 and the left sidewall of the trench 6 cross-section is less than the distance between the left first floating grid structure 801 and the left sidewall of the trench 6 cross-section, and the distance between the right second floating grid structure 802 and the right sidewall of the trench 6 cross-section is less than the distance between the right first floating grid structure 801 and the right sidewall of the trench 6 cross-section.
[0155] Continue as Figure 5 As shown, in some embodiments, there are two third floating gate structures 803, and the cross-sectional shape of the surface of each third floating gate structure 803 is arc-shaped. The distance between the third floating gate structure 803 and the sidewall of the cross-section of the trench 6 is less than the distance between the second floating gate structure 802 and the sidewall of the cross-section of the trench 6.
[0156] Optionally, the cross-sectional shape of the surfaces of both the left and right third floating gate structures 803 is arc-shaped, where "cross-sectional shape of the surface" refers to the surface that does not contact the sidewall of the trench 6 cross-section. Because the thickness of the third-deposited floating gate material is reduced, the distance between the left third floating gate structure 803 and the left sidewall of the trench 6 cross-section is less than the distance between the left third floating gate structure 803 and the right third floating gate structure 803 and the right sidewall of the trench 6 cross-section, and the distance between the right third floating gate structure 803 and the right sidewall of the trench 6 cross-section is less than the distance between the right third floating gate structure 803 and the right sidewall of the trench 6 cross-section.
[0157] By setting the gap between the bottoms of the two first floating gate structures to 800Å-1000Å, isolation between the two memory cells can be effectively avoided, and short circuits between the two memory cells can be prevented. This further optimizes the electrical characteristics of the memory cells and improves the reliability, durability, and read / write speed of the flash memory. In addition, by making the distance between the second floating gate structure and the sidewall of the corresponding trench smaller than the distance between the first floating gate structure and the sidewall of the corresponding trench, and making the distance between the third floating gate structure and the sidewall of the corresponding trench smaller than the distance between the second floating gate structure and the sidewall of the corresponding trench, the thickness of the floating gate material deposited on the sidewall each time is much thinner than the previous deposition. By adjusting the etching process, more floating gate material can be retained in the height, thus increasing the height of the formed floating gate structure. This further enables flexible adjustment of the height and length of the final floating gate structure.
[0158] In some embodiments, the height of the floating gate structure is 1200 Å-1500 Å. Thus, the gradient floating gate structure formed through multiple depositions and etchings allows for flexible adjustment of its height and length during the deposition and etching process, based on actual needs. This provides greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance, thereby optimizing the electrical characteristics of the storage cells and improving the reliability, durability, and read / write speed of the flash memory.
[0159] In some embodiments, the cross-sectional shape of the surface of the gradient floating grid structure is wavy, wherein the "surface of the gradient floating grid structure" refers to the surface that does not contact the bottom or sides of the trench 6. By setting the cross-sectional shape of the surface of the floating grid structure 8 to wavy, more floating grid material can be retained in height, thus increasing the height of the formed floating grid structure 8, thereby further realizing the flexible adjustment of the height and length of the final formed floating grid structure.
[0160] like Figure 12 As shown in the embodiments of this application, a floating-gate flash memory structure is also provided, which includes:
[0161] Substrate 1;
[0162] In some embodiments, the material of substrate 1 may include silicon, glass or quartz, etc. The silicon substrate may be a single crystal silicon substrate or a silicon-on-insulator (SOI) substrate, etc. The embodiments of this application do not limit the material of substrate 1.
[0163] An ion implantation layer 2 is formed on the substrate 1, wherein an active electrode 9 and a drain electrode 13 are formed in the ion implantation layer 2.
[0164] In some embodiments, the ion implantation layer 2 can be a P-type ion implantation layer 2, and the dopant used in the P-type ion implantation layer 2 can be boron (B), indium (In), gallium (Ga), etc.
[0165] In some embodiments, a lightly doped drain (LDD) region may also be formed in the ion implantation layer 2.
[0166] Selection gate 4 is formed on the ion implantation layer 2.
[0167] In some embodiments, the floating gate flash memory structure may further include an oxide layer 3 formed on the ion implantation layer 2, thereby forming a first isolation layer. This first isolation layer effectively isolates the ion implantation layer 2 from other structures, improving electrical performance.
[0168] In some embodiments, a gate material of a predetermined thickness can be deposited on the surface of the ion implantation layer 2 away from the substrate 1 (specifically, the surface of the first isolation layer) using a deposition process. The gate pattern is then defined by photolithography, and finally the select gate 4 is formed by etching.
[0169] In some embodiments, the gate-type flash memory structure may further include a target oxide layer 5 formed on the select gate 4. The target oxide layer 5 can serve as an isolation layer, and its material may include, but is not limited to, SiO2. It can be formed on the select gate 4 by a deposition process. This application does not limit the specific process of the deposition process.
[0170] A trench 6 extends through the select gate 4 and stops at the surface of the ion implantation layer 2; a gradient floating gate structure 8 is formed on the bottom and opposite sidewalls of the trench 6, the floating gate structure 8 being obtained by multiple depositions and etchings of floating gate material in the trench 6, the thickness of each deposition of floating gate material being less than the thickness of the previous deposition of floating gate material; a control gate 10 is formed in the area of the trench 6 other than the floating gate structure.
[0171] In some embodiments, the target oxide layer 5 and the select gate 4 can be etched sequentially by an etching process, and then the etching stops at the surface of the ion implantation layer 2 to obtain a trench 6 that penetrates the target oxide layer 5 and the select gate 4.
[0172] In some embodiments, the gate-type flash memory structure may further include a second isolation layer formed on the sidewall of the trench 6. The structure of the second isolation layer can be an ONO structure, that is, the second isolation layer includes two oxide layers 3 and a nitride layer 7 located between the two oxide layers 3, thereby suppressing lateral leakage and crosstalk. At the same time, an oxide layer is formed at the bottom of the trench 6 to form a first isolation layer, thereby serving as a vertical insulating barrier to prevent the substrate 1 from forming a leakage path.
[0173] In some embodiments, multiple depositions and etchings of the floating gate material can be performed on the bottom and opposite sidewalls of the trench 6 to obtain a gradient floating gate structure 8. More specifically, since a second isolation layer is formed on the side of the trench 6, the floating gate material can be deposited on the bottom of the trench 6 and on the opposite sidewalls of the trench 6 where the second isolation layer is formed. Optionally, "opposite sidewalls" refers to the two opposite left and right inner sidewalls in the cross-section of the trench 6. Optionally, in order to form a gradient floating gate structure, the thickness of each deposition of the floating gate material is less than the thickness of the previous deposition. Assuming that the number of depositions and etchings is 3, the thickness of the second deposition of the floating gate material is less than the thickness of the first deposition of the floating gate material, and the thickness of the third deposition of the floating gate material is less than the thickness of the second deposition of the floating gate material.
[0174] In some embodiments, the floating gate material is N-type or P-type doped polycrystalline silicon, or the floating gate material is N-type or P-type doped amorphous silicon. Because polycrystalline silicon has advantages such as excellent charge storage capability, tunable conductivity, excellent process compatibility and stability, and ease of patterning and etching, it is preferred as the floating gate material to improve the performance and reliability of the memory structure.
[0175] In some embodiments, the gate-type flash memory structure may further include a second isolation layer formed on the floating gate structure 8. The second isolation layer is an ONO structure, which includes: an oxide layer with a thickness of 20 Å-30 Å formed on the surface of the floating gate structure, a nitride layer with a thickness of 60 Å-80 Å formed on the surface of the 20 Å-30 Å oxide layer, and an oxide layer with a thickness of 30 Å-50 Å formed on the surface of the 60 Å-80 Å nitride layer.
[0176] In some embodiments, the control gate 10 is formed on the second isolation layer in the trench 6 by processes such as deposition of control gate material and etching. Thus, the floating gate structure 8 and the control gate 10 are isolated by the second isolation layer of the ONO structure, preventing charge leakage, avoiding direct short circuits or interference, and improving data retention capability. At the same time, the second isolation layer of the ONO structure serves as a dielectric layer, enhancing the capacitive coupling between the gates.
[0177] In some embodiments, the top of the control gate 10 deposited in the trench 6 is lower than the top of the target oxide layer 5. The main purpose is to control the height of the storage gate to be higher than the height of the control gate 10, thereby improving the erasure performance.
[0178] In some embodiments, the gate-type flash memory structure may further include forming an oxide layer 3 with a thickness of 80 Å-100 Å on the surface of the control gate 10 to obtain a first isolation layer. Optionally, the 80 Å-100 Å oxide layer can be grown on the surface of the control gate 10 by high-temperature oxidation (HTO) to prevent blocking leakage paths, reduce power consumption, and effectively ensure that the storage performance of the floating gate type memory structure is maintained or improved.
[0179] Erasure gate 11 is formed on the control gate 10 and the selection gate 4.
[0180] In some embodiments, an erase gate 11 can be formed on the control gate 10 and the select gate 4 by depositing an erase gate material and performing processes such as photolithography and etching. Furthermore, the erase gate 11 can be formed on the control gate 10 and the target oxide layer 5 by depositing an erase gate material and performing processes such as photolithography and etching. It should be noted that before forming the erase gate 11 on the target oxide layer 5, in order to achieve good isolation, an oxide layer can be formed on the surface of the target oxide layer 5 opposite to the select gate, resulting in a first isolation layer.
[0181] Optionally, the erase gate 11 may cover the entire control gate 10 and a portion of the selection gate 4. Furthermore, the erase gate 11 may cover the entire control gate 10 and a portion of the target oxide layer 5.
[0182] In some embodiments, after the erase gate is formed, an oxide layer 3 can also be formed on the side of the target oxide layer 5, the surface and side of the erase gate 11, and the side of the select gate 4 to form a first isolation layer, which plays a good isolation role and effectively maintains or improves the storage performance of the floating gate type memory structure.
[0183] In some embodiments, the gate-type flash memory structure may further include sidewalls 12 formed on the side of the erase gate 11 and on the side of the target oxide layer 5 and the select gate 4. By forming sidewalls 12 on the side of the erase gate 11 and on the side of the target oxide layer 5 and the select gate 4, electrical performance can be improved, physical protection can be provided, and process integration can be optimized, thereby effectively maintaining or improving the storage performance of the floating gate memory structure.
[0184] In some implementations, the multiple depositions and etchings include, but are not limited to, three depositions and etchings, in which the thickness of the first deposited floating gate material is 1100 Å-1300 Å, the thickness of the second deposited floating gate material is 500 Å-700 Å, and the thickness of the third deposited floating gate material is 100 Å-200 Å.
[0185] Optionally, a first deposition and etching of a floating gate material with a thickness of 1100 Å-1300 Å can be performed at the bottom of the trench 6 and on the two opposite sidewalls to obtain a first floating gate structure 801. Since the "two opposite sidewalls" can refer to the left and right sidewalls of the trench 6 cross-section, a first deposition and etching of a floating gate material with a thickness of 1100 Å-1300 Å can be performed on the bottom of the trench 6, on the left sidewall, to obtain one first floating gate structure 801. Simultaneously, a first deposition and etching of a floating gate material with a thickness of 1100 Å-1300 Å can be performed on the bottom of the trench 6, on the right sidewall, to obtain another first floating gate structure 801. That is, two first floating gate structures 801 can be obtained, meaning that this application can form two memory cells.
[0186] Next, a second deposition and etching of a floating gate material with a thickness of 1100 Å-1300 Å is performed on the top and opposite sidewalls of the first floating gate structure 801 to obtain a second floating gate structure 802. Essentially, the second floating gate structure 802 is stacked on top of the first floating gate structure 801 and partially covers the top of the first floating gate structure 801. Since the "opposite two sidewalls" can refer to the left and right sidewalls of the trench 6 cross-section, a second deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and left sidewall of the first floating gate structure 801 to obtain one second floating gate structure 802. Simultaneously, a second deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and right sidewall of the first floating gate structure 801 to obtain one second floating gate structure 802. In other words, two second floating gate structures 802 can be obtained.
[0187] Next, a third deposition and etching of a floating gate material with a thickness of 100 Å-200 Å is performed on the top and opposite sidewalls of the second floating gate structure 802 to obtain a third floating gate structure 803. Essentially, the third floating gate structure 803 is stacked on top of the second floating gate structure 802 and covers part of the top structure of the second floating gate structure 802. Since the "opposite two sidewalls" can refer to the left and right sidewalls of the cross-section of the trench 6, a third deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and left sidewall of the second floating gate structure 802 to obtain one third floating gate structure 803. Simultaneously, a third deposition and etching of a floating gate material with a thickness of 500 Å-700 Å can be performed on the top and right sidewall of the second floating gate structure 802 to obtain one third floating gate structure 803. In other words, two third floating gate structures 803 can be obtained.
[0188] Since the thickness of the floating gate material deposited each time is different and they are stacked sequentially, the first floating gate structure 801, the second floating gate structure 802, and the third floating gate structure 803 can form a floating gate structure 8 with a gradient.
[0189] Because the thickness of the floating gate material deposited in each deposition and etching process varies and has a certain range, the deposition thickness of the floating gate material can be flexibly adjusted according to actual needs during multiple deposition and etching processes. This allows for flexible adjustment of the height and length of the final floating gate structure, thereby providing greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance. This, in turn, optimizes the electrical characteristics of the storage cell and improves the reliability, durability, and read / write speed of flash memory. Furthermore, since the thickness of the floating gate material deposited decreases sequentially with each deposition, the thickness of the floating gate structure left on the sidewalls will be much thinner than the previous one. By adjusting the etching process, more floating gate material can be retained in terms of height, thus increasing the height of the resulting floating gate structure. This further enables flexible adjustment of the height and length of the final floating gate structure.
[0190] In some embodiments, two gradient floating gate structures 8 are formed within the trench 6, and the control gate 10 is formed between the two gradient floating gate structures 8.
[0191] Each of the floating gate structures 8 has multiple gradients, the number of which is the same as the number of depositions in the multiple depositions.
[0192] Optionally, the two gradient-equipped floating gate structures 8 are formed at the bottom of the trench 6 and on two opposing sidewalls. The "two opposing sidewalls" can refer to the left and right sidewalls of the cross-section of the trench 6. The control gate 10 is formed between the two gradient-equipped floating gate structures 8.
[0193] Optionally, each of the floating gate structures 8 has multiple gradients, the number of which is the same as the number of depositions. For example, if the number of depositions is 3, then each floating gate structure 8 has 3 gradients. The cross-sectional shape of the surface of the gradient floating gate structure 8 is wavy, wherein the "surface of the gradient floating gate structure" refers to the surface that does not contact the bottom or sides of the trench 6.
[0194] By configuring each of the floating gate structures to have multiple gradients, the number of which is the same as the number of depositions, the height and length of the floating gate structure can be flexibly adjusted according to the number of depositions. This provides greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance, thereby optimizing the electrical characteristics of the storage cell and improving the reliability, durability, and read / write speed of the flash memory.
[0195] In some embodiments, the height of the floating gate structure 8 is 1200 Å-1500 Å. Thus, the height and length of the gradient floating gate structure, formed through multiple depositions and etchings, can be flexibly adjusted during the multiple deposition and etching processes according to actual needs. This provides greater design flexibility in the height and length of the floating gate structure while maintaining or improving storage performance, thereby optimizing the electrical characteristics of the storage cells and improving the reliability, durability, and read / write speed of the flash memory.
[0196] In some implementations, the gap between the bottoms of the two gradient floating gate structures 8 is 800 Å-1000 Å. The source electrode 9 is located below the gap in the ion implantation layer 2, and the length of the source electrode 9 is greater than the length of the gap. This can effectively avoid the isolation of the two memory cells and prevent short circuits between the two memory cells, thereby further optimizing the electrical characteristics of the memory cells and improving the reliability, durability, and read / write speed of the flash memory.
[0197] This application also provides an electronic device that includes the floating gate flash memory structure described in any of the above embodiments.
[0198] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0199] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A floating gate type flash memory structure, characterized by, include: Substrate; An ion implantation layer is formed on the substrate, wherein an active electrode and a drain electrode are formed in the ion implantation layer; A selection gate is formed on the ion implantation layer; A trench that extends through the select gate and stops at the surface of the ion implantation layer; A gradient floating gate structure is formed on the bottom and opposite sidewalls of the trench. The floating gate structure is obtained by multiple depositions and etchings of floating gate material in the trench, with the thickness of each deposition of floating gate material being less than the thickness of the previous deposition. A control gate is formed in the area of the trench other than the floating gate structure. The thickness represents the deposition extension dimension along the sidewall of the trench. An erase gate is formed on the control gate and the select gate; The method for forming the floating gate type flash memory structure includes: Provide substrate; An ion implantation layer is formed on the substrate; A selection gate is formed on the ion implantation layer; A trench is formed that extends through the select gate and stops at the surface of the ion implantation layer; Multiple depositions and etchings of the floating gate material are performed on the bottom and opposite sidewalls of the trench to obtain a floating gate structure with a gradient; the thickness of each deposition of the floating gate material is less than the thickness of the previous deposition. A source electrode is formed in the substrate; A control gate is formed in the area of the trench other than the floating gate structure; An erase gate is formed on the control gate and the selection gate; A drain electrode is formed in the substrate.
2. The floating gate type flash memory structure according to claim 1, wherein, Two gradient floating gate structures are formed within the trench, and the control gate is formed between the two gradient floating gate structures; Each of the floating gate structures has multiple gradients, the number of which is the same as the number of depositions in the multiple depositions.
3. The floating gate type flash memory structure according to claim 2, wherein, The gap between the bottoms of the two gradient floating gate structures is 800 Å-1000 Å, the source electrode is located below the gap in the ion implantation layer, and the length of the source electrode is greater than the length of the gap.
4. The floating gate type flash memory structure according to claim 1, wherein, The multiple depositions and etchings include, but are not limited to, three depositions and etchings, in which the thickness of the first deposited floating gate material is 1100 Å-1300 Å, the thickness of the second deposited floating gate material is 500 Å-700 Å, and the thickness of the third deposited floating gate material is 100 Å-200 Å.
5. The floating gate type flash memory structure according to claim 1, wherein, The height of the floating grating structure is 1200Å-1500Å.
6. The floating gate type flash memory structure according to claim 1, wherein, The floating gate material is N-type or P-type doped polycrystalline silicon, or the floating gate material is N-type or P-type doped amorphous silicon.
7. The floating gate type flash memory structure according to any one of claims 1 to 6, wherein, The floating-gate flash memory structure also includes: A target oxide layer is formed on the select gate, the trench extends through the target oxide layer and the select gate and stops at the surface of the ion implantation layer, and the erase gate is formed on the control gate and the oxide layer.
8. The floating gate type flash memory structure according to claim 7, wherein, The floating-gate flash memory structure also includes: Sidewalls are formed on the side of the erase gate and on the side of the target oxide layer and the select gate.
9. The floating gate type flash memory structure according to claim 8, wherein, The floating-gate flash memory structure also includes: An isolation layer, comprising a first isolation layer and a second isolation layer; The first isolation layer is formed on the surface of the ion implantation layer away from the substrate, the surface and side of the target oxide layer, the surface and side of the erase gate, between the control gate and the erase gate; The second isolation layer is formed on the sidewall of the trench, and between the floating gate structure and the control gate.
10. The floating gate type flash memory structure according to claim 1, wherein, The multiple deposition and etching includes but is not limited to three times of deposition and etching, the multiple deposition and etching of the floating gate material on the bottom and opposite sidewall of the trench, to obtain the floating gate structure with gradient, including: The first deposition and etching of the floating gate material on the bottom and opposite sidewall of the trench, to obtain the first floating gate structure; the thickness of the first deposited floating gate material is 1100Å-1300Å; The second deposition and etching of the floating gate material on the top and opposite sidewall of the first floating gate structure, to obtain the second floating gate structure; the thickness of the second deposited floating gate material is 500Å-700Å; The third deposition and etching of the floating gate material on the top and opposite sidewall of the second floating gate structure, to obtain the third floating gate structure; the thickness of the third deposited floating gate material is 100Å-200Å; The first floating gate structure, the second floating gate structure, and the third floating gate structure form the floating gate structure with gradient.
11. The floating gate type flash memory structure according to claim 10, wherein, The first floating gate structure is two, the cross-sectional shape of each first floating gate structure is a sector, and the gap between the bottoms of the two first floating gate structures is 800Å-1000Å; The second floating gate structure is two, the cross-sectional shape of the surface of each second floating gate structure is arc-shaped, and the distance between the second floating gate structures away from the corresponding sidewall of the trench is less than the distance between the first floating gate structures away from the corresponding sidewall of the trench; The third floating gate structure is two, the cross-sectional shape of the surface of each third floating gate structure is arc-shaped, and the distance between the third floating gate structures away from the corresponding sidewall of the trench is less than the distance between the second floating gate structures away from the corresponding sidewall of the trench.
12. The floating gate type flash memory structure according to claim 1, wherein, Before the forming of the trench penetrating through the select gate and stopping at the surface of the ion implantation layer, the forming method further comprises: forming a target oxide layer on the select gate; The forming of the trench penetrating through the select gate and stopping at the surface of the ion implantation layer comprises: forming a trench penetrating through the target oxide layer and the select gate and stopping at the surface of the ion implantation layer; The forming of the erase gate on the control gate and the select gate comprises: forming the erase gate on the target oxide layer and the control gate.
13. The floating gate type flash memory structure of claim 1, wherein, Before the forming of the control gate in the area of the trench except the floating gate structure, the forming method further comprises: forming an oxide layer with a thickness of 20Å-30Å on the surface of the floating gate structure; forming a nitride layer with a thickness of 60Å-80Å on the surface of the oxide layer with a thickness of 20Å-30Å; forming an oxide layer with a thickness of 30Å-50Å on the surface of the nitride layer with a thickness of 60Å-80Å, to obtain the second isolation layer; The area in the trench other than the floating gate structure forms a control gate, comprising: forming the control gate on the second isolation layer.
14. The floating gate type flash memory structure of claim 12, wherein, After forming the control gate in the trench other than the floating gate structure, the forming method further comprises: forming a first isolation layer with a thickness of 80-100 A on the surface of the control gate; After forming the erase gate on the control gate and the select gate, the method further comprises: forming a side wall on the side of the erase gate, and on the side of the target oxide layer and the select gate.
15. The floating gate type flash memory structure according to claim 14, wherein, The forming method further comprises: forming a first isolation layer on the surface and the side of the ion implantation layer away from the surface of the substrate, the surface and the side of the target oxide layer, the surface and the side of the erase gate, and the side of the select gate; forming a second isolation layer on the sidewall of the trench.
16. An electronic device, comprising: The floating gate type flash memory structure as claimed in any one of claims 1 to 15.
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