MIM capacitor manufacturing method and MIM capacitor
By using the parallel structure of ONO MIM capacitors, the problem of low capacitance value of ONO MIM capacitors is solved, realizing a capacitor manufacturing method with high integration density and high reliability, which is suitable for RF, analog/mixed signal and high voltage integrated circuits.
Patent Information
- Application Number
- CN202511366859.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-24
- Publication Date
- 2026-01-06
AI Technical Summary
ONO MIM capacitors have low capacitance values, which limits their application in integrated circuits.
The parallel connection of ONO MIM capacitors is achieved by forming openings on each plate and dielectric layer and filling them with conductive material.
It improves the integration density of capacitors while retaining the advantages of high reliability, low leakage current and high breakdown voltage of ONO MIM capacitors.
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Figure CN121284979A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application belong to the field of capacitor technology, and in particular, the embodiments of this application provide a method for manufacturing a MIM capacitor and a MIM capacitor. Background Technology
[0002] The advantages of ONO MIM capacitors compared to Si3N4 MIM capacitors are: while achieving higher capacitance density (thanks to silicon nitride), they also possess excellent reliability, low leakage current, high breakdown voltage, and good voltage linearity (thanks to the optimization of the oxide layer); ONO (ONO structure includes SiO2+Si3N4+SiO2) MIM capacitors are widely used in radio frequency (RF), analog / mixed signal, high voltage and other integrated circuits;
[0003] The capacitance of ONO MIM capacitors with the same dielectric thickness is ~15% lower than that of pure Si3N4 MIM capacitors. Due to the disadvantage of the lower capacitance of ONO MIN capacitors, their application is severely limited. Summary of the Invention
[0004] To address or mitigate the problems in the existing technology and to compensate for the low capacitance of ONO MIM, an ONO MIM capacitor structure is adopted. By connecting the ONO MIM capacitors in parallel, the capacitance can be doubled. This application can achieve high integration density while retaining the advantages of ONO MIM, such as high reliability, low leakage current, and high breakdown voltage.
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a MIM capacitor, comprising:
[0006] A first dielectric layer is disposed on the upper surface of the first electrode plate;
[0007] A second electrode plate is deposited on the upper surface of the first dielectric layer;
[0008] Photolithography and etching are performed on the second electrode plate and the first dielectric layer so that part of the upper surface of the first electrode plate is not covered by the first dielectric layer and the second electrode plate;
[0009] A second dielectric layer is disposed on the upper surface of the first electrode plate and the second electrode plate;
[0010] A first opening is formed in the second dielectric layer at a position corresponding to the second electrode plate, and a second opening is provided in the second dielectric layer at a position corresponding to the second dielectric layer.
[0011] The first and second openings are filled with conductive material;
[0012] A third electrode plate and a first metal layer are disposed at intervals on the upper surface of the second dielectric layer;
[0013] A third dielectric layer is disposed on the upper surface of the third electrode plate;
[0014] A fourth electrode plate is deposited on the upper surface of the third dielectric layer;
[0015] A fourth dielectric layer is disposed on the upper surface of the third electrode plate, the fourth electrode plate, and the first metal layer;
[0016] A third opening is formed in the fourth dielectric layer at the position corresponding to the third electrode plate, a fourth opening is provided in the fourth dielectric layer at the position corresponding to the third dielectric layer, and a fifth opening is provided in the fourth dielectric layer at the position corresponding to the first metal layer.
[0017] The third, fourth, and fifth openings are filled with conductive material.
[0018] A second metal layer and a fifth electrode plate are disposed at intervals on the upper surface of the fourth dielectric layer. The fifth electrode plate is only connected to the third opening, and the second metal layer is only connected to the fourth and fifth openings.
[0019] In a preferred embodiment of this application, the provision of a first dielectric layer on the upper surface of the first electrode plate includes:
[0020] Only a first insulating layer is disposed on the upper surface of the first electrode plate; or,
[0021] A first protective layer and a first insulating layer are sequentially disposed from bottom to top on the upper surface of the first electrode plate; or,
[0022] A first protective layer, a first insulating layer, and a second protective layer are sequentially disposed on the upper surface of the first electrode plate from top to bottom.
[0023] In a preferred embodiment of this application, after filling the first and second openings with conductive material, the method includes:
[0024] The surface of the second dielectric layer is planarized.
[0025] In a preferred embodiment of this application, the provision of a third dielectric layer on the upper surface of the third electrode plate includes:
[0026] Only a second insulating layer is provided on the upper surface of the third electrode plate; or,
[0027] A third protective layer and a second insulating layer are sequentially disposed on the upper surface of the third electrode plate from bottom to top; or,
[0028] A third protective layer, a second insulating layer, and a fourth protective layer are sequentially disposed on the upper surface of the third electrode plate.
[0029] In a preferred embodiment of this application, after filling the third, fourth, and fifth openings with conductive material, the process includes:
[0030] The surface of the fourth dielectric layer is planarized.
[0031] Secondly, embodiments of this application also provide a MIM capacitor, characterized in that it is prepared by any of the methods described in the first aspect, comprising a first capacitor and a second capacitor connected in parallel;
[0032] The first capacitor includes a first electrode, a first dielectric layer, a second electrode, and a third electrode; the second capacitor includes a third electrode, a third dielectric layer, a fourth electrode, and a fifth electrode.
[0033] A first dielectric layer and a second electrode plate are sequentially disposed above the first electrode plate from bottom to top. A third electrode plate is disposed above the second electrode plate. A first opening is disposed between the second electrode plate and the third electrode plate. A second opening is disposed above the first electrode plate. A first metal layer is disposed above the second opening.
[0034] The third electrode plate and the first metal layer are spaced apart;
[0035] A third dielectric layer and a fourth electrode are arranged sequentially from bottom to top above the third electrode. A fourth opening is provided above the fourth electrode. A fifth opening is provided above the first metal layer. A third opening is provided above the third electrode.
[0036] A fifth electrode plate is disposed above the third opening, and a second metal layer is disposed above the fourth and fifth openings. The fifth electrode plate and the second metal layer are disposed alternately.
[0037] The first, second, third, fourth, and fifth openings are filled with conductive material.
[0038] In a preferred embodiment of this application, the first dielectric layer includes a first insulating layer disposed on the upper surface of the first electrode plate; or...
[0039] A first protective layer and a first insulating layer are sequentially disposed from bottom to top on the upper surface of the first electrode plate; or,
[0040] A first protective layer, a first insulating layer, and a second protective layer are sequentially disposed from bottom to top on the upper surface of the first electrode plate.
[0041] In a preferred embodiment of this application, the third dielectric layer includes:
[0042] A second insulating layer is disposed on the upper surface of the third electrode plate; or,
[0043] A second protective layer and a second insulating layer are sequentially disposed from bottom to top on the upper surface of the third electrode plate; or,
[0044] A second protective layer, a second insulating layer, and a third protective layer are sequentially disposed on the upper surface of the third electrode plate.
[0045] In a preferred embodiment of this application, the conductive material is tungsten metal.
[0046] In a preferred embodiment of this application, the second metal layer serves as the negative electrode of the entire capacitor, and the fifth electrode plate serves as the positive electrode of the entire capacitor; or, the second metal layer serves as the positive electrode of the entire capacitor, and the fifth electrode plate serves as the negative electrode of the entire capacitor.
[0047] Compared with the prior art, the embodiments of this application provide a method for manufacturing a MIM capacitor and a MIM capacitor. The method adopts an ONO MIM capacitor structure and the ONO MIM capacitors are connected in parallel to obtain twice the capacitance value. This application can achieve high integration density while retaining the advantages of ONO MIM such as high reliability, low leakage current and high breakdown voltage. Attached Figure Description
[0048] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0049] Figures 1 to 11 This is a structure diagram corresponding to each step;
[0050] Figure 12 This is a diagram showing the connection relationship between two capacitors;
[0051] Figure 13 yes Figure 12 The equivalent diagram. Detailed Implementation
[0052] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0053] MIN capacitors utilize different layers of metal and the dielectric material between them to form a capacitor. A MIM capacitor is essentially a parallel-plate capacitor; the two top metal layers have a relatively large gap, resulting in a very small capacitance. MIM capacitors are generally composed of two top metal layers and a special intermediate metal layer.
[0054] In a first aspect, embodiments of this application provide a method for manufacturing a MIM capacitor, comprising:
[0055] Step S101: A first dielectric layer 102 is formed on the upper surface of the first electrode plate 101;
[0056] like Figure 1 As shown, the first dielectric layer 102 is provided on the upper surface of the first electrode plate 101 mainly to form the first capacitor. The first electrode plate 101 is made of aluminum, or aluminum, copper or titanium nitride can be deposited on the upper surface of the first electrode plate 101 by sputtering. The first electrode plate 101 serves as the lower electrode plate of the two parallel first capacitors and the upper electrode plate of the second electrode.
[0057] The provision of a first dielectric layer 102 on the upper surface of the first electrode plate 101 includes:
[0058] Only a first insulating layer is provided on the upper surface of the first electrode plate 101; or,
[0059] A first protective layer and a first insulating layer are sequentially disposed from bottom to top on the upper surface of the first electrode plate 101; or,
[0060] A first protective layer, a first insulating layer, and a second protective layer are sequentially disposed on the upper surface of the first electrode plate 101 from top to bottom.
[0061] Specifically, both the first and second protective layers are silicon dioxide, and the first insulating layer is silicon nitride. The first and second protective layers can prevent the charge in the first capacitor from flying through.
[0062] The first dielectric layer 102 serves to insulate the upper and lower plates of the first capacitor.
[0063] The overall thickness of the first dielectric layer 102 needs to meet the preset requirements.
[0064] Step S102: Deposit a second electrode plate 103 on the upper surface of the first dielectric layer 102;
[0065] It should be noted that, as Figure 2 As shown, a second electrode 103 is deposited on the upper surface of the first dielectric layer 102. The second electrode 103 is mainly the upper electrode of the first capacitor. The second electrode 103 is mainly formed by sputtering and depositing metallic aluminum, metallic copper or titanium nitride on the upper surface of the first dielectric layer 102.
[0066] Step S103: Photolithography and etching are performed on the second electrode plate 103 and the first dielectric layer 102 so that part of the upper surface of the first electrode plate 101 is not covered by the first dielectric layer 102 and the second electrode plate 103.
[0067] It should be noted that, as Figure 3 As shown, the second electrode plate 103 and the first dielectric layer 102 are etched using photolithography and etching processes well known to those skilled in the art, leaving a portion of the second electrode plate 103 and the first dielectric layer 102 on the upper surface of the first electrode plate 101.
[0068] Step S104: A second dielectric layer 104 is formed on the upper surface of the first electrode plate 101 and the second electrode plate 103.
[0069] It should be noted that, as Figure 4 As shown, the second dielectric layer 104 is an insulating material, such as silicon dioxide. The main purpose of setting the second dielectric layer 104 is to set the subsequent first opening 105 and second opening 106.
[0070] Step S105: A first opening 105 is formed in the second dielectric layer 104 at the position corresponding to the second electrode plate 103, and a second opening 106 is provided in the second dielectric layer 104 at the position corresponding to the second dielectric layer 104.
[0071] It should be noted that, as Figure 5 As shown, a first opening 105 and a second opening 106 are formed in the second dielectric layer 104 by photolithography and etching processes. The first opening 105 is mainly for the second electrode plate 103 to communicate with the third electrode plate 107, and the second opening 106 is mainly for the first electrode plate 101 to communicate with the first metal layer 108.
[0072] Step S106: Fill the first opening 105 and the second opening 106 with conductive material;
[0073] It should be noted that, in Figure 5 The first opening 105 and the second opening 106 in the structure shown are filled with conductive material. In this embodiment, the conductive material is tungsten metal. The second electrode 103 and the third electrode 107 are connected by the tungsten metal, and the first electrode 101 and the first metal layer 108 are connected.
[0074] After filling the first opening 105 and the second opening 106 with conductive material, the process includes:
[0075] The surface of the second dielectric layer 104 is planarized.
[0076] It should be noted that the planarization process is mainly carried out through the CMP process, which is mainly used to planarize the wafer surface during chip manufacturing.
[0077] Step S107: A third electrode plate 107 and a first metal layer 108 with spacing are provided on the upper surface of the second dielectric layer 104.
[0078] It should be noted that, as Figure 6 As shown, a metal layer is first deposited on the surface of the second dielectric layer 104, and then the metal is photolithographically etched to obtain the third electrode 107 and the first metal layer 108. The third electrode 107 is the upper electrode of the first capacitor and the lower electrode of the second capacitor, and the third electrode 107 is the common electrode.
[0079] Step S108: A third dielectric layer 109 is disposed on the upper surface of the third electrode plate 107;
[0080] It should be noted that, as Figure 7 As shown, similar to step S101, the third dielectric layer 109 is provided on the upper surface of the third electrode plate 107 mainly to form the second capacitor.
[0081] The provision of a third dielectric layer 109 on the upper surface of the third electrode plate 107 includes:
[0082] Only a second insulating layer is provided on the upper surface of the third electrode plate 107; or,
[0083] A third protective layer and a second insulating layer are sequentially disposed from bottom to top on the upper surface of the third electrode plate 107; or,
[0084] A third protective layer, a second insulating layer, and a fourth protective layer are sequentially disposed on the upper surface of the third electrode plate 107.
[0085] Specifically, the third and fourth protective layers are both silicon dioxide, and the second insulating layer is silicon nitride. The third and fourth protective layers can prevent the charge in the first capacitor from flying through.
[0086] The third dielectric layer 109 serves to insulate the upper and lower plates of the second capacitor. The overall thickness of the third dielectric layer 109 needs to meet a preset requirement.
[0087] Step S109: Deposit a fourth electrode plate 110 on the upper surface of the third dielectric layer 109;
[0088] It should be noted that, as Figure 8As shown, a fourth electrode 110 is deposited on the upper surface of the third dielectric layer 109. The fourth electrode 110 is mainly the upper electrode of the second capacitor. The fourth electrode 110 is mainly formed by sputtering and depositing metallic aluminum, metallic copper or titanium nitride on the upper surface of the third dielectric layer 109.
[0089] Step S110: A fourth dielectric layer 111 is disposed on the upper surface of the third electrode plate 107, the fourth electrode plate 110 and the first metal layer 108;
[0090] It should be noted that, as Figure 9 As shown, the fourth dielectric layer 111 is an insulating material, such as silicon dioxide. The main purpose of setting the fourth dielectric layer 111 is to set the subsequent third opening 112, fourth opening 113 and fifth opening 114.
[0091] Step S111: A third opening 112 is formed in the fourth dielectric layer 111 at the position corresponding to the third electrode plate 107; a fourth opening 113 is provided in the fourth dielectric layer 111 at the position corresponding to the third dielectric layer 109; and a fifth opening 114 is provided in the fourth dielectric layer 111 at the position corresponding to the first metal layer 108.
[0092] It should be noted that, as Figure 10 As shown, a third opening 112, a fourth opening 113, and a fifth opening 114 are formed in the fourth dielectric layer 111 by photolithography and etching processes. The third opening 112 is mainly for connecting the third electrode plate 107 and the fifth electrode plate 115. The fourth opening 113 is mainly for connecting the fourth electrode plate 110 and the second metal layer 116. The fifth opening 114 is mainly for connecting the first metal layer 108 and the second metal layer 116.
[0093] Step S112: Fill the third opening 112, the fourth opening 113 and the fifth opening 114 with conductive material;
[0094] After filling the third opening 112, the fourth opening 113 and the fifth opening 114 with conductive material, the process includes: planarizing the surface of the fourth dielectric layer 111.
[0095] It should be noted that the planarization process is mainly carried out through the CMP process, which is mainly used to planarize the wafer surface during chip manufacturing.
[0096] It should be noted that, as Figure 10The third opening 112, the fourth opening 113 and the fifth opening 114 in the structure shown are filled with conductive material. In this embodiment, the conductive material is tungsten metal. The third electrode 107 and the fifth electrode 115 are connected through the tungsten metal, the fourth electrode 110 and the second metal layer 116 are connected, and the first metal layer 108 and the second metal layer 116 are connected.
[0097] In step S112, a second metal layer 116 and a fifth electrode plate 115 are disposed on the upper surface of the fourth dielectric layer 111 at intervals. The fifth electrode plate 115 is only connected to the third opening 112, and the second metal layer 116 is only connected to the fourth opening 113 and the fifth opening 114.
[0098] It should be noted that, as Figure 11 As shown, a metal layer is first deposited on the surface of the fourth dielectric layer 111, and then the metal is photolithographically etched to obtain the fifth electrode 115 and the second metal layer 116. The fifth electrode 115 is the lower electrode of the second capacitor, and the fourth electrode 110 and the second metal layer 116 are the upper electrode of the second capacitor.
[0099] Secondly, such as Figure 12 and Figure 13 As shown, this application embodiment also provides a MIM capacitor, which is prepared by the method of the first aspect, including a first capacitor and a second capacitor arranged in parallel;
[0100] The first capacitor includes a first electrode 101, a first dielectric layer 102, a second electrode 103, and a third electrode 107; the second capacitor includes a third electrode 107, a third dielectric layer 109, a fourth electrode 110, and a fifth electrode 115.
[0101] A first dielectric layer 102 and a second electrode 103 are sequentially disposed above the first electrode plate 101 from bottom to top. A third electrode plate 107 is disposed above the second electrode plate 103. A first opening 105 is disposed between the second electrode plate 103 and the third electrode plate 107. A second opening 106 is disposed above the first electrode plate 101. A first metal layer 108 is disposed above the second opening 106.
[0102] The third electrode plate 107 and the first metal layer 108 are spaced apart;
[0103] A third dielectric layer 109 and a fourth electrode 110 are sequentially disposed above the third electrode 107 from bottom to top. A fourth opening 113 is disposed above the fourth electrode 110. A fifth opening 114 is disposed above the first metal layer 108. A third opening 112 is disposed above the third electrode 107.
[0104] A fifth electrode plate 115 is disposed above the third opening 112, and a second metal layer 116 is disposed above the fourth opening 113 and the fifth opening 114. The fifth electrode plate 115 and the second metal layer 116 are disposed at intervals.
[0105] The first opening 105, the second opening 106, the third opening 112, the fourth opening 113 and the fifth opening 114 are filled with conductive material.
[0106] In a preferred embodiment of this application, the first dielectric layer 102 includes a first insulating layer disposed on the upper surface of the first electrode plate 101; or,
[0107] A first protective layer and a first insulating layer are sequentially disposed from bottom to top on the upper surface of the first electrode plate 101; or,
[0108] A first protective layer, a first insulating layer, and a second protective layer are sequentially disposed from bottom to top on the upper surface of the first electrode plate 101.
[0109] The third dielectric layer 109 includes:
[0110] A second insulating layer is disposed on the upper surface of the third electrode plate 107; or,
[0111] A second protective layer and a second insulating layer are sequentially disposed from bottom to top on the upper surface of the third electrode plate 107; or,
[0112] A second protective layer, a second insulating layer, and a third protective layer are sequentially disposed on the upper surface of the third electrode plate 107.
[0113] In this embodiment, the conductive material is tungsten metal.
[0114] Wherein, the second metal layer 116 serves as the negative electrode of the entire capacitor, and the fifth electrode plate 115 serves as the positive electrode of the entire capacitor; or, the second metal layer 116 serves as the positive electrode of the entire capacitor, and the fifth electrode plate 115 serves as the negative electrode of the entire capacitor.
[0115] exist Figure 12 The red dashed line represents the charge flow path of the first capacitor structure, and the black dashed line represents the charge flow path of the second capacitor. Figure 13 To be Figure 12 The structural equivalent diagram shows that the first capacitor and the second capacitor are connected in parallel. The positive terminal of the entire capacitor is connected to the upper plate of the first capacitor and the lower plate of the second capacitor, and the negative terminal of the entire capacitor is connected to the lower plate of the first capacitor and the upper plate of the second capacitor.
[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method of manufacturing a MIM capacitor, comprising: The method comprises the following steps: a first dielectric layer is arranged on the upper surface of a first electrode plate; a second electrode plate is deposited on the upper surface of the first dielectric layer; photolithography and etching are performed on the second electrode plate and the first dielectric layer, so that part of the upper surface of the first electrode plate is not covered by the first dielectric layer and the second electrode plate; a second dielectric layer is arranged on the upper surface of the first electrode plate and the second electrode plate; a first opening is formed in the second dielectric layer at a position corresponding to the second electrode plate, and a second opening is arranged in the second dielectric layer at a position corresponding to the second dielectric layer; a conductive material is filled in the first opening and the second opening; a third electrode plate and a first metal layer are arranged on the upper surface of the second dielectric layer in a spaced manner; a third dielectric layer is arranged on the upper surface of the third electrode plate; a fourth electrode plate is deposited on the upper surface of the third dielectric layer; a fourth dielectric layer is arranged on the upper surface of the third electrode plate, the fourth electrode plate and the first metal layer; a third opening is formed in the fourth dielectric layer at a position corresponding to the third electrode plate, a fourth opening is arranged in the fourth dielectric layer at a position corresponding to the third dielectric layer, and a fifth opening is arranged in the fourth dielectric layer at a position corresponding to the first metal layer; a conductive material is filled in the third opening, the fourth opening and the fifth opening; a second metal layer and a fifth electrode plate are arranged on the upper surface of the fourth dielectric layer in a spaced manner, the fifth electrode plate is only in communication with the third opening, and the second metal layer is only in communication with the fourth opening and the fifth opening.
2. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The step of arranging a first dielectric layer on the upper surface of a first electrode plate comprises the following steps: only a first insulating layer is arranged on the upper surface of the first electrode plate; or, a first protective layer and a first insulating layer are arranged on the upper surface of the first electrode plate in a sequential manner from bottom to top; or, a first protective layer, a first insulating layer and a second protective layer are arranged on the upper surface of the first electrode plate in a sequential manner from top to bottom.
3. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, After the step of filling a conductive material in the first opening and the second opening, the method further comprises the following step: a planarization treatment is performed on the surface of the second dielectric layer.
4. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The step of arranging a third dielectric layer on the upper surface of the third electrode plate comprises the following steps: only a second insulating layer is arranged on the upper surface of the third electrode plate; or, a third protective layer and a second insulating layer are arranged on the upper surface of the third electrode plate in a sequential manner from bottom to top; or, a third protective layer, a second insulating layer and a fourth protective layer are arranged on the upper surface of the third electrode plate in a sequential manner.
5. A method for manufacturing a MIM capacitor as described in claim 1, characterized in that, After the step of filling a conductive material in the third opening, the fourth opening and the fifth opening, the method further comprises the following step: a planarization treatment is performed on the surface of the fourth dielectric layer.
6. A MIM capacitor, comprising: Prepared by the method according to any one of claims 1 to 5, comprising a first capacitor and a second capacitor arranged in parallel; the first capacitor comprises a first electrode plate, a first dielectric layer, a second electrode plate and a third electrode plate; and the second capacitor comprises a third electrode plate, a third dielectric layer, a fourth electrode plate and a fifth electrode plate; a first dielectric layer and a second electrode plate are sequentially arranged on the upper surface of the first electrode plate from bottom to top, a third electrode plate is arranged above the second electrode plate, and a first opening is arranged between the second electrode plate and the third electrode plate; a second opening is arranged above the first electrode plate, and a first metal layer is arranged above the second opening; the third electrode plate and the first metal layer are arranged in a spaced manner; A third dielectric layer and a fourth plate are sequentially arranged above the third plate from bottom to top, a fourth opening is arranged above the fourth plate, a fifth opening is arranged above the first metal layer, and a third opening is arranged above the third plate; A fifth plate is arranged above the third opening, a second metal layer is arranged above the fourth opening and the fifth opening, and the fifth plate and the second metal layer are arranged in a spaced manner; The first opening, the second opening, the third opening, the fourth opening and the fifth opening are filled with conductive material.
7. The capacitor as described in claim 6, characterized in that, The first dielectric layer comprises a first insulating layer arranged on the upper surface of the first plate; or, A first protective layer and a first insulating layer are sequentially arranged on the upper surface of the first plate from bottom to top; or, A first protective layer, a first insulating layer and a second protective layer are sequentially arranged on the upper surface of the first plate from bottom to top.
8. The capacitor of claim 6, wherein, The third dielectric layer comprises: A second insulating layer arranged on the upper surface of the third plate; or, A second protective layer and a second insulating layer are sequentially arranged on the upper surface of the third plate from bottom to top; or, A second protective layer, a second insulating layer and a third protective layer are sequentially arranged on the upper surface of the third plate.
9. The capacitor of claim 6, wherein, The conductive material is tungsten.
10. The capacitor of claim 6, wherein The second metal layer serves as the negative electrode of the entire capacitor, and the fifth plate serves as the positive electrode of the entire capacitor; or the second metal layer serves as the positive electrode of the entire capacitor, and the fifth plate serves as the negative electrode of the entire capacitor.