Fin field effect transistors and methods for forming the same

Abstract

The application provides a fin field effect transistor and a forming method thereof. A first opening is formed in an epitaxial layer to form a stepped epitaxial layer; the epitaxial layer is continuously etched, the first opening extends into a substrate, and a second opening is formed in the epitaxial layer; a first shallow trench isolation structure is formed in the first opening, and a top surface of the first shallow trench isolation structure is flush with a bottom wall of the second opening; the epitaxial layer at the bottom of the second opening is etched to make the second opening extend into the substrate, and the remaining epitaxial layer constitutes a fin. The unexpected effect of the application is that a stepped epitaxial layer with different heights is formed through an etching process, the epitaxial layer is continuously etched to form first openings and second openings with different depths, the first shallow trench isolation structure flush with the bottom wall of the second opening is formed in the first opening, and the second opening is continuously etched into the substrate to form the fin. Due to the support of the first shallow trench isolation structure, the problem of collapse in the process of forming the fin is avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a fin field-effect transistor and a method for forming the same. Background Technology

[0002] With the development of the integrated circuit industry, to meet usage demands, the structure of MOS transistors has evolved from 2D to 3D. The mainstream 3D MOS structure now is FinFET (Fin Field-Effect Transistor). FinFET is a new type of complementary metal-oxide-semiconductor transistor. In chip development, to increase channel width and drive current, the design height of the fins has become increasingly tall; conversely, to increase the integration density per unit area, the design width of the fins has become increasingly narrow. However, this design inevitably leads to the problem of fin collapse during the fabrication of the fins and shallow trench isolation structure. Summary of the Invention

[0003] The purpose of this invention is to provide a fin field-effect transistor and a method for forming the same, so as to solve the problem of fin collapse during the fabrication of fins and shallow trench isolation structures.

[0004] To solve the above-mentioned technical problems, the present invention provides a method for forming a fin field-effect transistor, comprising:

[0005] A substrate is provided on which an epitaxial layer is formed;

[0006] Perform a first etching process to etch a portion of the epitaxial layer and form a first opening within the epitaxial layer to form a stepped epitaxial layer;

[0007] A hard mask layer is formed, which covers the sidewall of the first opening;

[0008] A second etching process is performed, using the hard mask layer as a mask to etch the epitaxial layer and the substrate, wherein the first opening extends into the substrate and a second opening is formed in the epitaxial layer;

[0009] A first shallow trench isolation structure is formed, the first shallow trench isolation structure is located inside the first opening, and the top surface of the first shallow trench isolation structure is flush with the bottom wall of the second opening;

[0010] A third etching process is performed to etch the epitaxial layer at the bottom of the second opening using the hard mask layer as a mask, so that the second opening extends into the substrate, and the remaining epitaxial layer between the first opening and the second opening constitutes the fin of the fin field-effect transistor.

[0011] Optionally, after forming the fins of the fin field-effect transistor, the method further includes:

[0012] A second shallow trench isolation structure is formed, which is located within the second opening and is flush with the first shallow trench isolation structure.

[0013] Optionally, the first shallow trench isolation structure and the second shallow trench isolation structure are silicon oxide with different dielectric constants.

[0014] Optionally, the step of forming the first shallow trench isolation structure includes:

[0015] A first isolation layer is formed, which fills the first opening and the second opening;

[0016] A portion of the first isolation layer within the first opening and all of the first isolation layer within the second opening are etched to expose the bottom wall of the second opening, and the top surface of the first isolation layer within the first opening is flush with the bottom wall of the second opening. The remaining first isolation layer within the first opening constitutes a first shallow trench isolation structure.

[0017] Optionally, the step of forming the second shallow trench isolation structure includes:

[0018] A second isolation layer is formed, which fills the first opening and the second opening;

[0019] All of the second isolation layer within the first opening and a portion of the second isolation layer within the second opening are etched so that the top surface of the first isolation layer within the first opening is flush with the top surface of the second isolation layer within the second opening, and the remaining second isolation layer within the second opening constitutes a second shallow trench isolation structure.

[0020] Optionally, the step of forming the hard mask layer includes:

[0021] A hard mask layer is formed, which covers the stepped epitaxial layer;

[0022] Perform a self-aligned etching process to remove the hard mask layer on the epitaxial layer, while retaining the hard mask layer on the first opening sidewall.

[0023] Optionally, the hard mask layer is a stacked structure of oxide and silicon nitride or a stacked structure of amorphous carbon and silicon nitride.

[0024] Optionally, the step of forming the first opening includes:

[0025] A patterned photoresist layer is formed, the patterned photoresist layer covering the epitaxial layer;

[0026] A first etching process is performed to etch a portion of the epitaxial layer, forming a first opening within the epitaxial layer to form a stepped epitaxial layer of varying heights.

[0027] Optionally, after forming the second shallow trench isolation structure, the method further includes:

[0028] An etch stop layer is formed, which covers the top and sidewalls of the fin;

[0029] A pseudo-gate material layer is formed, which covers the fin;

[0030] The pseudo-gate material layer is etched to form a pseudo-gate.

[0031] Based on the same inventive concept, the present invention also provides a fin field-effect transistor, which is fabricated using the fin field-effect transistor formation method described in any of the above claims.

[0032] In the method for forming a fin field-effect transistor provided by the present invention, a first etching process is first performed to form a first opening in the epitaxial layer, and a hard mask layer is formed to cover the sidewall of the first opening. Then, a second etching process is performed to form a second opening in the epitaxial layer, forming a first shallow trench isolation structure with its top surface flush with the bottom wall of the second opening. Next, a third etching process is performed to extend the second opening into the substrate. The remaining epitaxial layer between the first and second openings constitutes the fin. An unexpected effect of the present invention is that by forming stepped epitaxial layers of different heights through etching, and continuing to etch the epitaxial layer to form the first and second openings of different depths, a first shallow trench isolation structure flush with the bottom wall of the second opening is formed within the first opening. Then, the second opening is etched into the substrate to form the fin. Due to the support of the first shallow trench isolation structure, the problem of fin collapse during formation is avoided. Attached Figure Description

[0033] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0034] Figure 1 This is a flowchart of a method for forming a fin field-effect transistor according to an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the structure after the formation of the epitaxial layer and the shielding oxide layer in an embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of the structure after the formation of the first well region in an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the structure after the formation of the second well region in an embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram of the structure after the formation of the pad oxide layer according to an embodiment of the present invention.

[0039] Figure 6 This is a schematic diagram of the structure after the formation of the patterned third photoresist layer according to an embodiment of the present invention.

[0040] Figure 7 This is a schematic diagram of the structure after the first opening is formed according to an embodiment of the present invention.

[0041] Figure 8 This is a schematic diagram of the structure after removing the silicon nitride layer according to an embodiment of the present invention.

[0042] Figure 9 This is a schematic diagram of the structure after forming a hard mask layer according to an embodiment of the present invention.

[0043] Figure 10 This is a schematic diagram of the structure after removing part of the hard mask layer according to an embodiment of the present invention.

[0044] Figure 11 This is a schematic diagram of the structure after the second opening is formed according to an embodiment of the present invention.

[0045] Figure 12 This is a schematic diagram of the structure after the formation of the first isolation layer according to an embodiment of the present invention.

[0046] Figure 13 This is a schematic diagram of the structure after the formation of the first shallow trench isolation structure according to an embodiment of the present invention.

[0047] Figure 14 This is a schematic diagram of the structure after the fins are formed according to an embodiment of the present invention.

[0048] Figure 15 This is a schematic diagram of the structure after the formation of the second isolation layer in an embodiment of the present invention.

[0049] Figure 16 This is a schematic diagram of the structure after the formation of the second shallow trench isolation structure according to an embodiment of the present invention.

[0050] Figure 17 This is a schematic diagram of the structure after removing the hard mask layer according to an embodiment of the present invention.

[0051] Figure 18 This is a schematic diagram of the structure after the formation of the pseudo-gate in an embodiment of the present invention.

[0052] In the attached figures: 10-substrate; 10a-first well region definition area; 10b-second well region definition area; 11-epitaxy layer; 11a-first well region; 11b-second well region; 12-shielding oxide layer; 13a-patterned first photoresist layer; 13b-patterned second photoresist layer; 13c-patterned third photoresist layer; 14a-first top anti-reflective coating; 14b-second top anti-reflective coating; 15-pad oxide layer; 16-silicon nitride layer; 17-sacrificial layer; 18-bottom anti-reflective layer; 19-first opening; 20-hard mask layer; 21-second opening; 22-first isolation layer; 22a-first shallow trench isolation structure; 23-fin; 24-second isolation layer; 24a-second shallow trench isolation structure; 25-etch stop layer; 26-dummy gate. Detailed Implementation

[0053] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0054] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0055] The applicant's research revealed that in the structural design of a fin field-effect transistor, both the source and drain regions are vertically positioned. The gate refers to the portion sandwiched between the two sides in the middle. The channel length L refers to the length of the gate sandwiched in the middle (Lg), the vertical channel width W refers to the height of the fin (Hfin), and the width of the source and drain regions is the width of the fin (Wfin). The distance between every two fins is the fin pitch (Pfin). The ratio of the gate length Lg to the width Wfin of the source and drain regions directly affects the drain-induced barrier lowering (DIBL) effect. Research shows that a ratio of gate length Lg to the width Wfin of the source and drain regions greater than 1.5 is necessary to effectively suppress the DIBL effect, while a smaller gate length Lg is better because it directly determines the drain saturation current Idsat. Therefore, the width Wfin of the source and drain regions must be 2 / 3 of the gate length Lg. In FinFET structures, the minimum dimension is no longer the channel length of traditional MOSFETs, but rather the fin width (Wfin). Therefore, the fin width (Wfin) is the real challenge in photolithography. Furthermore, a smaller fin is better for hot-carrier properties. Additionally, FinFET structures are divided into Double-FinFET (DG-FinFET, dual-gate fin field-effect transistor) and Tri-FinFET (triple-gate fin field-effect transistor). The main difference lies in the fact that the portion of the fin surrounded by the gate has three surfaces: two gate regions on either side, a front gate (1st gate), and a back gate (2nd gate). If the top is a thick oxide layer, it is not considered a channel and is called a Double Gate. If the top and sides are thin gate oxide layers, it is called a Tri-Gate. Tri-Gates have relatively high drive currents due to increased channel widths (W = Wfin + 2 * Hfin). Therefore, in chip development, to increase channel width and drive current, the fin design height has become increasingly taller; conversely, to improve device integration per unit area, the fin design width has become increasingly narrower. However, this design inevitably leads to fin collapse issues during the fabrication of the fins and shallow trench isolation structures.

[0056] Based on this, this embodiment provides a method for forming a fin field-effect transistor. First, a first etching process is performed to form a first opening within the epitaxial layer. A hard mask layer is then formed to cover the sidewalls of the first opening. Next, a second etching process is performed to form a second opening within the epitaxial layer, forming a first shallow trench isolation structure with its top surface flush with the bottom wall of the second opening. Then, a third etching process is performed to extend the second opening into the substrate. The remaining epitaxial layer between the first and second openings constitutes the fin. An unexpected effect of this invention is that by forming stepped epitaxial layers of different heights through etching, and further etching the epitaxial layer to form the first and second openings of different depths, a first shallow trench isolation structure flush with the bottom wall of the second opening is formed within the first opening. Then, the second opening is further etched into the substrate to form the fin. Due to the support of the first shallow trench isolation structure, the problem of fin collapse during formation is avoided.

[0057] Figure 1 This is a flowchart illustrating a method for forming a finned field-effect transistor according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a fin field-effect transistor according to the present invention, including:

[0058] Step S10: Provide a substrate on which an epitaxial layer is formed;

[0059] Step S20: Perform a first etching process to etch a portion of the epitaxial layer and form a first opening within the epitaxial layer to form a stepped epitaxial layer;

[0060] Step S30: Form a hard mask layer that covers the sidewall of the first opening;

[0061] Step S40: Perform a second etching process, using the hard mask layer as a mask to etch the epitaxial layer and the substrate, wherein the first opening extends into the substrate and a second opening is formed in the epitaxial layer;

[0062] Step S50: A first shallow trench isolation structure is formed. The first shallow trench isolation structure is located inside the first opening, and the top surface of the first shallow trench isolation structure is flush with the bottom wall of the second opening.

[0063] Step S60: Perform a third etching process to etch the epitaxial layer at the bottom of the second opening using the hard mask layer as a mask, so that the second opening extends into the substrate, and the remaining epitaxial layer between the first opening and the second opening constitutes the fin of the fin field-effect transistor.

[0064] Figures 2 to 18 This is a structural schematic diagram of the corresponding steps in the method for forming a fin field-effect transistor according to an embodiment of the present invention; the following is in conjunction with... Figures 2 to 18This section details the formation process of a fin field-effect transistor.

[0065] like Figure 2 As shown, a substrate 10 is provided. The substrate 10 can be a single-crystal silicon or polycrystalline silicon substrate, or it can be made of semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, etc., or it can be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art can select a suitable type of semiconductor substrate according to the needs of the semiconductor device, and the type of semiconductor substrate should not limit the scope of protection of this invention. The doping type of the substrate 10 is a first doping type, such as p-type doping.

[0066] Please continue to refer to this. Figure 2 An epitaxial layer 11 is formed on the substrate 10. The epitaxial layer 11 is made of single-crystal silicon and is formed using an epitaxial growth process. The thickness of the epitaxial layer 11 is, for example, 1 μm. A shielding oxide layer 12 is formed on the epitaxial layer 11. The shielding oxide layer 12 can protect the epitaxial layer 11 from damage by the ion implantation process in subsequent ion implantation processes.

[0067] like Figure 3 As shown, a patterned first photoresist layer 13a and a first top anti-reflective coating 14a are sequentially formed. The first top anti-reflective coating 14a is located on the patterned first photoresist layer 13a. The patterned first photoresist layer 13a covers the second well region definition region 10b and exposes the first well region definition region 10a. A first ion implantation process is performed to form a first well region 11a within the epitaxial layer 11. The doping type of the first well region 11a is a first doping type, that is, the doping type of the first well region 11a is P-type, and the first well region 11a is a P-type well region (P Well). Examples of doping in the first ion implantation process include B and BF2.

[0068] like Figure 4 As shown, a patterned second photoresist layer 13b and a second top anti-reflective coating 14b are sequentially formed. The second top anti-reflective coating 14b is located on the patterned second photoresist layer 13b. The patterned second photoresist layer 13b covers the first well region 11a and exposes the second well region definition region 10b. A second ion implantation process is performed to form the second well region 11b within the epitaxial layer 11. The doping type of the second well region 11b is a second doping type, that is, the doping type of the second well region 11b is N-type, and the second well region 11b is an N-type well region (N Well). Examples of doping in the second ion implantation process include P and As.

[0069] After forming the first well region 11a and the second well region 11b, if the patterned second photoresist layer 13b is not completely consumed, a photoresist removal process is required. This is typically done by ashing or stripping to remove the remaining patterned second photoresist layer 13b. The shielding oxide layer 12 is also removed.

[0070] like Figure 5 As shown, a rapid thermal annealing process is performed to repair the lattice of the first well region 11a and the second well region 11b, activate the first well region 11a and the second well region 11b, and then regenerate a pad oxide layer 15. The pad oxide layer 15 is formed using a thermal oxidation process and is located on the first well region 11a and the second well region 11b.

[0071] like Figure 6 As shown, a silicon nitride layer 16 and a sacrificial layer 17 are formed sequentially. The silicon nitride layer 16 is located on the pad oxide layer 15, and the sacrificial layer 17 is located on the silicon nitride layer 16. The sacrificial layer 17 is made of amorphous carbon, and the silicon nitride layer 16 and the sacrificial layer 17 are formed using a chemical vapor deposition process. Next, a bottom anti-reflective layer 18 and a patterned third photoresist layer 13c are formed. The patterned third photoresist layer 13c is located on the first well region 11a and the second well region 11b. Specifically, the patterned third photoresist layer 13c is located on the bottom anti-reflective layer 18.

[0072] like Figure 6 and Figure 7 As shown, a first etching process is performed, using a patterned third photoresist layer 13c as a mask to etch a portion of the epitaxial layer 11, forming a first opening 19 within the epitaxial layer 11 to create epitaxial layers 11 of varying heights, i.e., epitaxial layers 11 with a stepped shape. The first etching process is a dry etching process.

[0073] like Figure 8 As shown, a wet etching process is performed to remove the silicon nitride layer 16 and the pad oxide layer 15. The silicon nitride layer 16 is removed using a phosphoric acid solution, and the pad oxide layer 15 is removed using a DHF solution.

[0074] like Figure 9 and Figure 10 As shown, a hard mask layer 20 is formed, which is located on the sidewall of the first opening 19. Specifically, the steps for forming the hard mask layer 20 include: as shown in the diagram. Figure 9 As shown, a hard mask layer 20 is formed, which covers the stepped epitaxial layer 11; the hard mask layer 20 is an oxide and silicon nitride stacked structure or an amorphous carbon (aC) and silicon nitride stacked structure, and can be formed using a chemical vapor deposition process. Figure 10 As shown, a self-aligned etching process is performed to remove the hard mask layer 20 on the epitaxial layer 11, while retaining the hard mask layer 20 on the sidewall of the first opening 19. The self-aligned etching process is a dry etching process.

[0075] like Figure 11 As shown, a second etching process is performed, using the hard mask layer 20 as a mask to etch the epitaxial layer 11 and the substrate 10. The first opening 19 extends into the substrate 10, and a second opening 21 is formed in the epitaxial layer 11. The depth d1 of the first opening 19 is greater than the depth d2 of the second opening 21.

[0076] like Figure 12 and Figure 13 As shown, a first shallow trench isolation structure 22a is formed. The first shallow trench isolation structure 22a is located within the first opening 19, and the top surface of the first shallow trench isolation structure 22a is flush with the bottom wall of the second opening 21. In this embodiment, "flush" means approximately flush, that is, the height difference between the top surface of the first shallow trench isolation structure 22a and the bottom wall of the second opening 21 falls within the allowable range of the process. Specifically, the steps for forming the first shallow trench isolation structure 22a include: as follows Figure 12 As shown, a first isolation layer 22 is formed, filling the first opening 19 and the second opening 21, and covering the hard mask layer 20. The first isolation layer 22 is made of an oxide layer and is formed using a chemical vapor deposition process. It is then polished using a chemical mechanical polishing process until it contacts the hard mask layer 20, at which point polishing stops. Finally, high-temperature annealing is used to make the formed first isolation layer 22 more dense. Figure 13 As shown, using a hard mask layer 20 as a mask, a dry etching process is employed to etch part of the first isolation layer 22 within the first opening 19 and all of the first isolation layer 22 within the second opening 21, exposing the bottom wall of the second opening 21. The top surface of the first isolation layer 22 within the first opening 19 is flush with the bottom wall of the second opening 21. The remaining first isolation layer 22 within the first opening 19 constitutes a first shallow trench isolation structure 22a. In this document, "flush" refers to approximately flush, meaning the height difference between the top surface of the first isolation layer 22 within the first opening 19 and the bottom wall of the second opening 21 falls within the allowable range of the process.

[0077] like Figure 14As shown, a third etching process is performed, using the hard mask layer 20 as a mask to etch the epitaxial layer 11 at the bottom of the second opening 21, so that the second opening 21 extends into the substrate 10. The remaining epitaxial layer 11 between the first opening 19 and the second opening 21 forms a fin 23. The third etching process is a dry etching process. In the third etching process, the etching selectivity of silicon is much greater than that of the oxide layer, meaning that the epitaxial layer 11 can be mainly etched. In the third etching process, each fin 23 is supported by a first shallow trench isolation structure 22a of a certain thickness to prevent the fin 23 from collapsing.

[0078] like Figure 15 and Figure 16 As shown, after forming the fin 23, a second shallow trench isolation structure 24a is formed. The second shallow trench isolation structure 24a is located within the second opening 21, and the top surface of the second shallow trench isolation structure 24a is flush with the top surface of the first shallow trench isolation structure 22a. Here, "flush" means approximately flush, that is, the height difference between the top surfaces of the second shallow trench isolation structure 24a and the first shallow trench isolation structure 22a falls within the allowable range of the process. Specifically, the steps for forming the second shallow trench isolation structure 24a include: forming a second isolation layer 24, which fills the first opening 19 and the second opening 21. The material of the second isolation layer 24 is an oxide layer, formed using a chemical vapor deposition process. Then, it is polished using a chemical mechanical polishing process until it contacts the hard mask layer 20, and then high-temperature annealing is used to make the formed second isolation layer 24 more dense. Figure 16As shown, all of the second isolation layer 24 within the first opening 19 and a portion of the second isolation layer 24 within the second opening 21 are etched to make the top surface of the first isolation layer 22 within the first opening 19 flush with the top surface of the second isolation layer 24 within the second opening 21. Here, "flush" means approximately flush, meaning the height difference between the top surface of the first isolation layer 22 within the first opening 19 and the top surface of the second isolation layer 24 within the second opening 21 falls within the process allowable range. The remaining second isolation layer 24 within the second opening 21 constitutes the second shallow trench isolation structure 24a. The first shallow trench isolation structure 22a and the second shallow trench isolation structure 24a can be made of the same material or different materials, depending on the different requirements of the device. In this embodiment, the first shallow trench isolation structure 22a and the second shallow trench isolation structure 24a are silicon oxide with different dielectric constants. This differentiated filling strategy holds significant potential in 3D ICs, heterogeneous integration, and the More-than-Moore technology, enabling precise optimization for different functional blocks (logic, memory, analog, or RF) and representing a crucial direction for future high-performance chip design. Filling shallow trench isolation (STI) structures with different insulating materials in different regions allows for multifaceted performance optimization through customized design. Specific advantages include: reduced parasitic capacitance: In high-speed or high-frequency circuit regions (such as logic cells), using low-k materials (such as carbon-doped oxides) reduces parasitic capacitance, thereby lowering signal latency and dynamic power consumption. Enhanced isolation: In high-voltage or high-density regions (such as memory cells), using high-k materials improves insulation strength, preventing leakage and breakdown. Matched thermal expansion coefficients: In power devices or heat-prone areas, selecting materials with high thermal stability and a thermal expansion coefficient matching that of the silicon substrate (such as silicon nitride) reduces interface defects caused by thermal stress. Optimized heat dissipation: Certain materials (such as fluorine-doped oxides) may possess better thermal conductivity, aiding in localized heat dissipation. In terms of mechanical stress control, stress effects are mitigated: In advanced structures such as FinFETs or nanosheet transistors, filling STI with low-stress materials (such as porous silica) can reduce stress interference in the channel region and maintain carrier mobility. Crack propagation is also prevented: using tougher polymer composites in brittle regions improves mechanical reliability. For enhanced process compatibility, integration processes are simplified: in areas requiring subsequent metallization, selecting materials compatible with metal deposition processes (such as specifically doped oxides) reduces interface defects and contact resistance. Furthermore, CMP processes are optimized: differences in removal rates of different materials during chemical mechanical polishing (CMP) can be utilized to achieve flatter surface morphologies.In terms of reliability enhancement, electromigration resistance is improved: in high current density areas (such as near power lines), the use of dense, high-quality insulating layers (such as atomically deposited Al2O3) can suppress electromigration. Radiation hardening: in aerospace or high-radiation environments, some areas can be filled with radiation-resistant materials (such as hydrogen-rich silicon nitride) to reduce soft error rates. For cost-performance balance, high performance in critical areas is achieved: high-performance materials (such as high-k silicon nitride) are used in critical paths or high-density storage areas, while low-cost oxides are used in non-critical areas to optimize cost-effectiveness. And material waste is reduced: overall manufacturing costs are lowered by using expensive materials (such as fluorosilicone glass) in specific areas.

[0079] like Figure 17 As shown, after forming the second shallow trench isolation structure 24a, the hard mask layer 20 is first removed by wet etching.

[0080] like Figure 18 As shown, an etch stop layer 25 is formed, covering the top and sidewalls of the fin 23. The etch stop layer (ESL) is made of oxide and formed using a thermal oxidation process. A dummy gate material layer is formed, covering the fin 23; the dummy gate material layer is made of polysilicon or amorphous silicon and can be formed using a chemical vapor deposition process. A portion of the dummy gate material layer is etched to form a dummy gate 26.

[0081] like Figure 18 As shown, this embodiment also provides a fin field-effect transistor, fabricated using the fin field-effect transistor formation method described in any of the above embodiments. It includes a substrate 10 and fins 23 located on the substrate 10. Isolation structures are formed between adjacent fins 23. A first shallow trench isolation structure 22a and a second shallow trench isolation structure 24a are formed on both sides of each fin 23. Etch stop layers 25 are formed on the top and sidewalls of the fins 23. A dummy gate 26 is also formed on the substrate 10, spanning multiple fins 23.

[0082] In summary, in the method for forming a fin field-effect transistor provided in this embodiment of the invention, a first etching process is first performed to form a first opening in the epitaxial layer, and a hard mask layer is formed to cover the sidewall of the first opening. Then, a second etching process is performed to form a second opening in the epitaxial layer, forming a first shallow trench isolation structure with its top surface flush with the bottom wall of the second opening. Next, a third etching process is performed to extend the second opening into the substrate. The remaining epitaxial layer between the first and second openings constitutes the fin. An unexpected effect of this invention is that by forming stepped epitaxial layers of different heights through etching, and then further etching the epitaxial layer to form the first and second openings of different depths, a first shallow trench isolation structure flush with the bottom wall of the second opening is formed within the first opening. Then, the second opening is further etched into the substrate to form the fin. Due to the support of the first shallow trench isolation structure, the problem of fin collapse during formation is avoided.

[0083] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0084] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method for forming a fin field-effect transistor, characterized in that, include: A substrate is provided on which an epitaxial layer is formed; Perform a first etching process to etch a portion of the epitaxial layer and form a first opening within the epitaxial layer to form a stepped epitaxial layer; A hard mask layer is formed, which covers the sidewall of the first opening; A second etching process is performed, using the hard mask layer as a mask to etch the epitaxial layer and the substrate, wherein the first opening extends into the substrate and a second opening is formed in the epitaxial layer; A first shallow trench isolation structure is formed, the first shallow trench isolation structure is located inside the first opening, and the top surface of the first shallow trench isolation structure is flush with the bottom wall of the second opening; A third etching process is performed to etch the epitaxial layer at the bottom of the second opening using the hard mask layer as a mask, so that the second opening extends into the substrate, and the remaining epitaxial layer between the first opening and the second opening constitutes the fin of the fin field-effect transistor. The steps for forming the first shallow trench isolation structure include: A first isolation layer is formed, which fills the first opening and the second opening; A portion of the first isolation layer within the first opening and all of the first isolation layer within the second opening are etched to expose the bottom wall of the second opening, and the top surface of the first isolation layer within the first opening is flush with the bottom wall of the second opening. The remaining first isolation layer within the first opening constitutes a first shallow trench isolation structure.

2. The method for forming a fin field-effect transistor according to claim 1, characterized in that, After forming the fins of the fin field-effect transistor, the method further includes: A second shallow trench isolation structure is formed, which is located within the second opening and is flush with the first shallow trench isolation structure.

3. The method for forming a fin field-effect transistor according to claim 2, characterized in that, The first shallow trench isolation structure and the second shallow trench isolation structure are silicon oxide with different dielectric constants.

4. The method for forming a finned field-effect transistor according to claim 2, characterized in that, The steps for forming the second shallow trench isolation structure include: A second isolation layer is formed, which fills the first opening and the second opening; All of the second isolation layer within the first opening and a portion of the second isolation layer within the second opening are etched so that the top surface of the first isolation layer within the first opening is flush with the top surface of the second isolation layer within the second opening, and the remaining second isolation layer within the second opening constitutes a second shallow trench isolation structure.

5. The method for forming a finned field-effect transistor according to claim 1, characterized in that, The steps for forming the hard mask layer include: A hard mask layer is formed, which covers the stepped epitaxial layer; Perform a self-aligned etching process to remove the hard mask layer on the epitaxial layer, while retaining the hard mask layer on the first opening sidewall.

6. The method for forming a fin field-effect transistor according to claim 1, characterized in that, The hard mask layer is a stacked structure of oxide and silicon nitride or a stacked structure of amorphous carbon and silicon nitride.

7. The method for forming a finned field-effect transistor according to claim 1, characterized in that, The steps for forming the first opening include: A patterned photoresist layer is formed, the patterned photoresist layer covering the epitaxial layer; A first etching process is performed to etch a portion of the epitaxial layer, forming a first opening within the epitaxial layer to form a stepped epitaxial layer with varying heights.

8. The method for forming a fin field-effect transistor according to claim 2, characterized in that, After forming the second shallow trench isolation structure, it also includes: An etch stop layer is formed, which covers the top and sidewalls of the fin; A pseudo-gate material layer is formed, which covers the fin; The pseudo-gate material layer is etched to form a pseudo-gate.

9. A fin field-effect transistor, characterized in that, It is fabricated using the method for forming a fin field-effect transistor as described in any one of claims 1 to 8.

Images