A normally-off gate-controlled junction field effect transistor

Abstract

The application provides a normally-off gate-controlled junction field effect transistor, comprising a JFET structure, the JFET structure comprising: a JFET base region of a wide-bandgap semiconductor of a second doping type; gate regions of a respective first doping type are formed on two opposite sides of the JFET base region, a part of the JFET base region between the two gate regions serving as a channel region, and the two gate regions and the channel region forming two back-to-back first PN junctions; wherein the doping concentration of the channel region is less than the doping concentration of the gate region, and the width 2L of the channel region, the doping concentration of the channel region and the doping concentration of the gate region satisfy a preset relationship, so that when no external voltage is connected, the depletion regions of the two first PN junctions completely cover the entire width range of the channel region, and the normally-off gate-controlled junction field effect transistor is kept off. The application solves the technical problems of safety risk and high cost of the driving circuit of the traditional normally-on gate-controlled junction field effect transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a normally-off gate-controlled junction field-effect transistor. Background Technology

[0002] Figure 1 This is a schematic diagram of patent CN202311790958. (As shown) Figure 1 As shown, patent CN202311790958 describes a vertical junction field-effect transistor (VJFET) with an integrated source-drain anti-parallel diode. The VJFET portion employs a top-source, vertical L-shaped trench gate, and bottom-drain structure. The vertical diode unit includes a vertical L-shaped P-type anode region, anti-parallel coupled to the VJFET unit. Similar to the principle of a conventional VJFET, this patent's VJFET is a normally-on device, meaning that a current path exists in the device channel region when the gate is at zero bias. To turn off this VJFET device, a negative value Vgs below the threshold voltage needs to be applied to the gate to deplete the channel region. This may cause penetration breakdown between the gate region 20 and the anode region 22, thus placing higher demands on the breakdown voltage.

[0003] Figure 2 This is a schematic diagram of patent CN200980148435. (As shown) Figure 2 As shown, patent CN200980148435 describes a vertical junction field-effect transistor (JFET) with tilted sidewalls, employing a top-side source, vertical L-shaped trench gates on both sides of the channel, and a bottom-side drain. The channel layer of the device is made of n-type doped semiconductor material, and the gate is made of p-type doped semiconductor material. This device is a normally-on JFET. When a negative voltage is applied to the gate, the depletion region between the gate and the channel widens. As the negative voltage on the gate continues to shift negatively until it falls below the threshold voltage, the channel of the device is pinched off.

[0004] The defects of normally open gate controlled junction field-effect transistors are as follows:

[0005] First: Normally open devices remain in a conducting state during the power-on initialization phase of the drive circuit or when the drive circuit malfunctions (such as short circuit or open circuit), which may lead to safety risks such as system short circuit, burnout of load or power transistor.

[0006] Second: Driving an N-channel normally open JFET requires applying a power supply to the gate. The additional negative power supply generation circuit will increase the complexity and area of ​​the circuit, and increase the cost of the driving circuit.

[0007] Therefore, the traditional normally open gate-controlled junction field-effect transistor (MOSFET) poses safety risks and has high driving circuit costs, which are technical problems that urgently need to be solved by those skilled in the art.

[0008] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0009] This application provides a normally off gate-controlled junction field-effect transistor to solve the technical problems of safety risks and high cost of driving circuits in traditional normally open gate-controlled junction field-effect transistors.

[0010] This application provides a normally-off gate-controlled junction field-effect transistor, including a JFET structure, wherein the JFET structure includes:

[0011] JFET substrate region of a wide-bandgap semiconductor of the second doping type;

[0012] Each of the two JFET substrate regions is formed on opposite sides of the JFET substrate region, and the portion of the JFET substrate region between the two gate regions is used as a channel region. The two gate regions and the channel region form two back-to-back first PN junctions.

[0013] Wherein, the doping concentration of the channel region is less than the doping concentration of the gate region, and the width 2L of the channel region, the doping concentration of the channel region and the doping concentration of the gate region satisfy a preset relationship, so that when the first PN junction is not connected to an external voltage, the depletion regions of the two first PN junctions completely cover the entire width range of the channel region, thereby keeping the normally off gate-controlled junction field-effect transistor off.

[0014] This application, by adopting the above technical solution, has the following technical effects:

[0015] By precisely designing the channel width 2L and the relationship between the doping concentration of the channel region and the doping concentration of the gate region, the depletion regions of the two back-to-back first PN junctions of the gate-controlled junction field-effect transistor can completely cover the channel region when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage). This fundamentally changes the traditional gate-controlled junction field-effect transistor's conduction characteristic at zero gate voltage (i.e., no external voltage is applied to the gate), realizing the device's "normally off" state and providing possibilities for low-power applications. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of patent CN202311790958;

[0017] Figure 2 This is a schematic diagram of patent CN200980148435;

[0018] Figure 3This is a partial schematic diagram of a specific implementation of the normally-off gate-controlled junction field-effect transistor of this application;

[0019] Figure 4 for Figure 3 The diagram shows a partial schematic of a normally off gate-controlled junction field-effect transistor where the first PN junction remains off when a non-zero preset external voltage Va is applied.

[0020] Figure 5 for Figure 3 The diagram shows a partial schematic of a normally off gate-controlled junction field-effect transistor where the external voltage of the first PN junction reaches the threshold voltage Vth, causing the device to turn on.

[0021] Figure 6 This is a partial schematic diagram of another specific implementation of the normally-off gate-controlled junction field-effect transistor of this application;

[0022] Figure 7 This is a schematic diagram of the normally off gate-controlled junction field-effect transistor of this application;

[0023] Figure 8 for Figure 7 Simulation diagram of a normally off gate-controlled junction field-effect transistor in the off state when the gate bias voltage VGS=0V;

[0024] Figure 9 for Figure 7 Simulation diagram of the current path of a normally off gate-controlled junction field-effect transistor with zero gate bias.

[0025] Figure 10 for Figure 7 Simulation diagram of a normally off gate-controlled junction field-effect transistor when the gate VGS approaches Vth, and the device switches from off to on.

[0026] Figure 11 for Figure 7 Simulation diagram of the current path of a normally off gate-controlled junction field-effect transistor at the gate VGS close to Vth.

[0027] Figure 12 for Figure 7 A schematic diagram of the current density of a normally off gate-controlled junction field-effect transistor during breakdown;

[0028] Figure 13 for Figure 7 Simulation diagram of a normally off gate-controlled junction field-effect transistor in the off state when the gate bias voltage Vgs=0V.

[0029] Figure 14 for Figure 13 Energy band diagram showing the energy bands of the gate region on one side extending through the channel region to the gate region on the other side.

[0030] Figure label:

[0031] First epitaxial layer 1, second epitaxial layer 2, substrate 3, source region 4, JFET substrate region 5.

[0032] Gate region 6, channel shielding region 8, dielectric layer 9, source ohmic contact 10, gate ohmic contact 11

[0033] Drain ohmic contact 12. Detailed Implementation

[0034] To make the technical solutions and advantages of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0035] The traditional junction field-effect transistor (JFET) is essentially a normally-on device. The core principle of a normally-on JFET is as follows:

[0036] Normally On State: Under zero gate voltage (i.e., no external voltage applied to the gate region), the conductive channel of a junction field-effect transistor (JFET) is naturally present and fully open. Therefore, as long as a voltage is applied between the drain and source, current will flow, and the device will be in the on state. This is the meaning of "normally on".

[0037] Traditional normally open gate-controlled junction field-effect transistors (GMT transistors) pose safety risks and have high driving circuit costs, which are technical problems that urgently need to be solved by those skilled in the art.

[0038] Example 1

[0039] The normally-off gate-controlled junction field-effect transistor of this application includes a JFET structure, such as... Figure 3 , Figure 4 and Figure 5 As shown, the JFET structure includes:

[0040] JFET substrate region 5 of a wide bandgap semiconductor of the second doping type;

[0041] Gate regions 6 of a first doping type are formed on opposite sides of the JFET substrate region. The portion of the JFET substrate region 5 located between the two gate regions serves as a channel region. The two gate regions 6 and the channel region form two back-to-back first PN junctions.

[0042] Wherein, the doping concentration of the channel region is less than the doping concentration of the gate region, and the width 2L of the channel region, the doping concentration of the channel region and the doping concentration of the gate region satisfy a preset relationship, so that when the first PN junction is not connected to an external voltage, the depletion regions of the two first PN junctions completely cover the entire width range of the channel region, thereby keeping the normally off gate-controlled junction field-effect transistor off.

[0043] Specifically, the gate region serves as the gate electrode, and the two sides of the JFET substrate region where the gate region is not formed serve as the source and drain electrodes, respectively.

[0044] The normally-off gate-controlled junction field-effect transistor of this application features an innovative design for the JFET structure:

[0045] First, the JFET substrate region is limited to a wide bandgap semiconductor of the second doping type;

[0046] The reasons for using a wide-bandgap semiconductor in the JFET substrate region are as follows:

[0047] Wide bandgap semiconductors have significantly larger band gaps than silicon. The band gap of silicon is approximately 1.12 eV (at 300 K, i.e., room temperature), while the band gap of wide bandgap semiconductors is >3.0 eV.

[0048] Under the same doping conditions, the larger the bandgap of a semiconductor, the higher the built-in potential of its PN junction.

[0049] The higher the built-in potential Vbi, the higher the potential barrier of the PN junction, and the easier it is for the depletion region to expand, thus making it easier to achieve self-pinch-off and turn-off.

[0050] Secondly, the doping concentration of the channel region and the doping concentration of the gate region are limited, with the doping concentration of the channel region being much smaller than that of the gate region. This results in a larger depletion region of the first PN junction formed by the gate region and the channel region in the channel region, providing the condition that the depletion region of the first PN junction completely covers the entire width of the channel region.

[0051] Third, the width 2L of the channel region, the doping concentration of the channel region, and the doping concentration of the gate region satisfy a preset relationship, so that when the first PN junction is not connected to an external voltage, the depletion regions of the two first PN junctions completely cover the entire width range of the channel region, thereby keeping the normally off gate-controlled junction field-effect transistor off.

[0052] By controlling the width 2L of the channel region, the doping concentration of the channel region, and the doping concentration of the gate region, the width of the two depletion regions generated by the built-in potential of the two first PN junctions formed by the gate region and the channel region is sufficient to clamp the width of the entire channel region when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage). This means that the device is in a turned-off state when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage). This is also known as the self-depletion effect. Correspondingly, the normally-off gate-controlled junction field-effect transistor is a normally-off device.

[0053] The normally-off gate-controlled junction field-effect transistor of this application has the following technical advantages:

[0054] Achieving a normally-off operating mode: By precisely designing the channel width 2L and the relationship between the doping concentration of the channel region and the gate region, the depletion regions of the two back-to-back first PN junctions of the gate-controlled junction field-effect transistor can completely cover the channel region when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage). This fundamentally changes the traditional gate-controlled junction field-effect transistor's conduction characteristic at zero gate voltage (i.e., no external voltage is applied to the gate), realizing the device's "normally off" state and providing possibilities for low-power applications.

[0055] Improved turn-off reliability: By quantifying design parameters through "preset formulas," it is ensured that when the gate-controlled junction field-effect transistor has no external voltage applied to the gate (i.e., the first PN junction is not connected to an external voltage), the channel region is completely pinched off by the depletion region, and the drain current is suppressed to an extremely low level. This significantly improves the stability and reliability of the device in the turn-off state.

[0056] Simple structure and good process compatibility: This solution innovates upon the classic JFET structure, achieving functional transformation through optimization of doping concentration and geometry without adding complex process steps. This allows the normally-off gate-controlled junction field-effect transistor of this application to be well compatible with existing semiconductor manufacturing processes, reducing R&D and mass production costs.

[0057] In practice, the doping concentration in the channel region ranges from greater than or equal to 1 × 10⁻⁶. 15 cm -3 And less than or equal to 1×10 19 cm -3 ;

[0058] The doping concentration of the gate region is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 20 cm -3 ;

[0059] The width 2L of the channel region is greater than or equal to 0.08 μm and less than or equal to 0.5 μm.

[0060] That is, the doping concentration of the gate region, the doping concentration of the channel region, and the width must not only meet the above-mentioned value range, but also meet the preset relationship.

[0061] Specifically, the wide bandgap semiconductor material of the JFET substrate region can be silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), or gallium oxide (Ga2O3).

[0062] The normally-off gate-controlled junction field-effect transistor of this application has two ways to achieve the depletion region of the two back-to-back first PN junctions completely covering the channel region when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage), which are described in Embodiment 2 and Embodiment 3 respectively.

[0063] Example 2

[0064] In the normally-off gate-controlled junction field-effect transistor of this application embodiment, the depletion region of the two back-to-back first PN junctions can completely cover the channel region when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage). The implementation method is the first:

[0065] like Figure 3 As shown, when no external voltage is applied, the depletion regions of the two first PN junctions completely cover the entire width of the channel region in a manner that at least partially overlaps.

[0066] Furthermore, the preset applied voltage Va is aligned with the threshold voltage Vth of the gate-controlled junction field-effect transistor (i.e., the first PN junction is externally positive biased), and the absolute value of Vth is greater than the absolute value of Va.

[0067] like Figure 4 As shown, when a non-zero preset external voltage Va is applied to the first PN junction, the depletion regions of the two first PN junctions each narrow, the overlapping portion of the depletion regions of the two first PN junctions narrows, and the depletion regions of the two first PN junctions still completely cover the entire width range of the channel region.

[0068] like Figure 5As shown, when the external forward bias voltage of the first PN junction continues to increase, the effect of the built-in electric field is weakened because the direction of the electric field of the external voltage is opposite to the direction of the built-in electric field formed by the gate region and the channel region of the first PN junction. The depletion region width W of the first PN junction continues to narrow. With the continued increase of the external forward bias voltage of the first PN junction, the depletion region of the first PN junction continues to narrow until the external voltage of the first PN junction reaches the threshold voltage Vth. At this point, the depletion regions of the first PN junction separate to form an undepleted region in the channel region, creating a current path, and the device is thus turned on.

[0069] In this way, the normally off gate-controlled junction field-effect transistor of this application embodiment is in the off state when the first PN junction is not connected to an external voltage;

[0070] When the first PN junction is connected to a non-zero preset external voltage Va, the normally off gate-controlled junction field-effect transistor of this application embodiment remains in the off state.

[0071] When the external voltage of the first PN junction reaches the threshold voltage Vth, the normally off gate-controlled junction field-effect transistor of the application embodiment is turned on.

[0072] When a non-zero preset external voltage Va is applied to the first PN junction, the depletion regions of both first PN junctions narrow, and the overlap between the depletion regions of the two first PN junctions narrows, but still completely covers the entire width of the channel region, avoiding the formation of an effective conductive path. This keeps the normally-off gate-controlled junction field-effect transistor (GFET) off. This characteristic ensures that the first PN junction remains reliably off when a non-zero preset external voltage Va is applied, enhancing the tolerance of the first PN junction to external voltage fluctuations and improving the consistency and stability of device operation.

[0073] The preset relationship between the width 2L of the channel region, the doping concentration of the channel region, and the doping concentration of the gate region is as follows:

[0074]

[0075] Where, N D N represents the doping concentration of the gate region for the first doping type. A The doping concentration of the JFET substrate region is the second type of doping, and k is the Boltzmann constant. Let n be the dielectric constant of the semiconductor, q be the electron charge, and n be the... i Where is the intrinsic carrier concentration, and T is the absolute temperature.

[0076] As an optional approach, corresponding Figures 3 to 5 When the first doping type is P-type and the second doping type is N-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is positive and greater than 1V.

[0077] When Va is set to 0.5V, .

[0078] That is, when the external voltage is 0.5V, the first PN junction satisfies The depletion regions of the two first PN junctions still completely cover the entire width of the channel region, remaining off. This characteristic allows the first PN junctions of the device to remain reliably off when the external voltage is 0.5V, enhancing the tolerance of the first PN junctions to external voltage fluctuations and improving the consistency and stability of device operation.

[0079] The threshold voltage Vth of a normally-off gate-controlled junction field-effect transistor is positive and greater than 1V, meaning that the absolute value of the threshold voltage Vth is relatively large (e.g., greater than 1V), rather than very small (e.g., 0.1V). This mainly brings the following core advantages:

[0080] 1. Improve the reliability and stability of devices.

[0081] Enhanced noise immunity: When the absolute value of the threshold voltage Vth is large, the device is less sensitive to small fluctuations in the gate voltage. For example, a gate-controlled junction field-effect transistor (GFET) with a threshold voltage Vth of 1.5V will only conduct when the gate voltage is higher than 1.5V. This allows the GFET to effectively resist noise and voltage glitches that may exist in the circuit, thereby avoiding accidental conduction due to false triggering and greatly improving the stability of circuit operation.

[0082] More reliable turn-off state: Under zero gate voltage conditions, a larger absolute value of the threshold voltage Vth means that the channel is pinched off more completely, resulting in very small leakage current (turn-off current). This ensures the high impedance characteristics of the device in the "turn-off" state, which is crucial for applications requiring strict isolation, such as power switches and signal isolators.

[0083] 2. Reduce static power consumption

[0084] Reduced leakage current: As mentioned above, a large absolute value of the threshold voltage Vth ensures extremely low leakage current in the off state. This directly reduces the power consumption of the circuit in the static (non-operating) state, which is a very important advantage for battery-powered portable devices or power-sensitive applications.

[0085] 3. Provides a wider voltage control margin

[0086] Greater design tolerance: A larger threshold voltage Vth provides a greater safety margin for circuit design. For example, a device with a threshold voltage of 1.5V can be designed to ensure that the gate voltage fluctuates between 0V and 1.5V without unexpectedly turning on. This makes the circuit design more robust and more tolerant of power supply voltage fluctuations and manufacturing process variations.

[0087] 4. Better compatibility with existing circuit standards

[0088] Matching standard logic levels: In many digital and analog circuits, standard logic levels (such as TTL or CMOS circuits) typically use 0.8V to 2.0V as the boundary between high and low levels. A device with a threshold voltage Vth absolute value greater than 1V has a switching threshold that falls within the transition region of this standard logic level, making it easier to interface with these standard circuits and achieve seamless integration and driving.

[0089] As an alternative approach, when the first doping type is N-type and the second doping type is P-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is negative and less than -1V.

[0090] When Va is set to -0.5V, .

[0091] Example 3

[0092] In the normally-off gate-controlled junction field-effect transistor of this application embodiment, the second method is used to ensure that the depletion regions of the two back-to-back first PN junctions can completely cover the channel region when no external voltage is applied to the gate (i.e., the first PN junction is not connected to an external voltage):

[0093] like Figure 6 As shown, when no external voltage is applied to the first PN junction, the depletion regions of the two first PN junctions are connected in a manner that completely covers the entire width of the channel region; that is, the depletion regions of the two first PN junctions are connected in a manner that does not overlap.

[0094] In this way, when the first PN junction is subjected to an external voltage and the external voltage and the threshold voltage Vth of the gate-controlled junction field-effect transistor are of the same sign, the gate-controlled junction field-effect transistor of this application will be turned on, resulting in low power consumption.

[0095] Furthermore, the channel width 2L, the doping concentration of the channel region, and the doping concentration of the gate region satisfy the following preset relationship:

[0096]

[0097] Where, N D N represents the doping concentration of the gate region for the first doping type. AThe doping concentration of the JFET substrate region is the second type of doping, and k is the Boltzmann constant. ν is the semiconductor dielectric constant, q is the electron charge, ni is the intrinsic carrier concentration, and T is the absolute temperature.

[0098] As an optional approach, corresponding Figure 6 When the first doping type is P-type and the second doping type is N-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is positive and greater than 1V.

[0099] As an alternative approach, when the first doping type is N-type and the second doping type is P-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is negative and less than -1V.

[0100] To facilitate understanding of this application, the principle of the normally-off gate-controlled junction field-effect transistor of this application and the derivation process of the channel width 2L, the doping concentration of the channel region and the doping concentration of the gate region satisfying the preset relationship are explained below.

[0101] In the ideal PN junction model, theoretically, the width W of the depletion region of the PN junction satisfies the following formula:

[0102] Formula (1)

[0103] For the sake of brevity, the following derivation will be illustrated using an example of a heavily p-type gate region and a lightly p-type channel region:

[0104] The gate region is heavily doped with P-type (N) A The channel region is lightly doped with N-type (N...) D ), satisfying N A Much greater than N D This forms a single-sided abrupt junction. The depletion region width of the first PN junction formed by the gate and channel regions is mainly determined by the lightly doped channel region, so 1 / N A It can be omitted.

[0105] Therefore, formula (1) is simplified for engineering purposes to form formula (2):

[0106] Formula (2).

[0107] It is the built-in potential of the PN junction, determined by the doping concentration: Formula (3).

[0108] Substituting formula (3) into formula (2) yields: Formula (4).

[0109] Theoretically, gate-controlled junction field-effect transistors (GFETs) have the characteristics of being always off, meaning that when a zero gate voltage (V0) is applied... a When the gate and channel regions are both equal to 0, the depletion region of the first PN junction completely covers the entire width of the channel region, thus interrupting the current path. In other words, the condition that needs to be met is: the width of the channel region is represented by 2L, where L is less than the theoretical width of the depletion region of the first PN junction formed by a single-sided gate and channel region. Formula (5).

[0110] Substituting formula (4) into formula (5), we get:

[0111] Formula (6);

[0112] Finally, substituting Va=0V into formula (6), we get... Formula (7).

[0113] In practical applications, considering the critical turn-off condition, leakage current still exists. Therefore, a 0.5V margin is reserved in the channel width geometry design (taking a heavily P-type gate region and a lightly N-type channel region as an example) to ensure that the leakage current of the device is almost zero at zero gate voltage (corresponding to the first PN junction being unconnected to an external voltage). The physical meaning of reserving a 0.5V margin in the channel width geometry design is as follows:

[0114] When no external voltage is applied, the depletion regions of the two first PN junctions completely cover the entire width of the channel region in a manner that at least partially overlaps.

[0115] When the first PN junction is externally connected to 0.5V, the depletion regions of the two first PN junctions each narrow, the overlapping portion of the depletion regions of the two first PN junctions narrows, and the depletion regions of the two first PN junctions still completely cover the entire width of the channel region.

[0116] Therefore, the half-width of the channel region and the channel doping concentration should satisfy:

[0117] The preset relationship between the width 2L of the channel region, the doping concentration of the channel region, and the doping concentration of the gate region is as follows:

[0118] .

[0119] Taking a heavily P-type gate region and a lightly N-type channel region as an example, the threshold voltage of the normally off gate-controlled junction field-effect transistor of this application is positive and greater than 1V.

[0120] Similarly, the derivation process is the same for a heavily doped N-type gate region and a lightly doped P-type channel region, and will not be repeated here.

[0121] Example 4

[0122] like Figure 7 As shown, the normally-off gate-controlled junction field-effect transistor of this application embodiment includes:

[0123] Substrate 3 of the second doping type;

[0124] A second epitaxial layer 2 of the second doping type is formed on the substrate 3;

[0125] The first epitaxial layer 1 of the second doping type is formed on the second epitaxial layer 2.

[0126] Multiple stepped trenches are arranged laterally in the first epitaxial layer 1, each stepped trench including an upper trench and a lower trench, the upper trench having a larger aperture than the lower trench; wherein, a protrusion is formed between adjacent stepped trenches.

[0127] The second doped source region 4 is disposed in the top region of the protrusion, and the bottom surface of the source region 4 is higher than the top surface of the trench below.

[0128] A gate region 6 of the first doped type is formed within the trench wall of the lower trench.

[0129] The first doped type of channel shielding region 8 is located on the side of the lower trench facing the substrate;

[0130] A dielectric layer 9 is formed at the bottom of the lower trench and above the channel shielding area 8, and there is a gap between the dielectric layer 9 and the gate area 6 in the vertical direction, such that there is a gap between the channel shielding area 8 and the gate area 6 in the vertical direction.

[0131] Source ohmic contact 10 is formed on the source region 4.

[0132] A gate ohmic contact 11 is formed on the vertical surface of the gate region 6;

[0133] A drain ohmic contact 12 is formed on the back side of the substrate.

[0134] In this structure, the first epitaxial layer 1 serves as the JFET base region 5, and the gate region 6 is the gate region 6 in the JFET structure.

[0135] Example 4 is a specific instance of the normally-off gate-controlled junction field-effect transistor (JFET) structure of Examples 1 to 3 applied to a specific normally-off gate-controlled junction field-effect transistor, and is not intended to limit the normally-off gate-controlled junction field-effect transistors of Examples 1 to 3; the normally-off gate-controlled junction field-effect transistor (JFET) structure of Examples 1 to 3 can also be applied to gate-controlled junction field-effect transistors of various structures.

[0136] Figure 8 for Figure 7 Simulation diagram of a normally off gate-controlled junction field-effect transistor in the off state when the gate bias voltage Vgs=0V.

[0137] Figure 9 for Figure 7 Simulation diagram of the current path of a normally off gate-controlled junction field-effect transistor with zero gate bias.

[0138] like Figure 8 and Figure 9 As shown, when the gate zero bias voltage Vgs=0V, the device is in the off state, indicating that the device is a normally off gate-controlled junction field-effect transistor.

[0139] like Figure 8 As shown, the white line marks the boundary of the device's depletion region. The first PN junction formed by the gate region and the channel region depletes each other. When the gate is at zero bias, the depletion regions of the first PN junctions on both sides occupy the entire width of the channel region, and the device's current path is cut off.

[0140] like Figure 9 As shown, when the gate is at zero bias, there is no current path in the channel region of the device.

[0141] Figure 10 for Figure 7 Simulation diagram of a normally off gate-controlled junction field-effect transistor switching from off to on when the gate Vgs is close to Vth.

[0142] Figure 11 for Figure 7 Simulation diagram of the current path of a normally off gate-controlled junction field-effect transistor with the gate Vgs close to Vth.

[0143] like Figure 10 As shown, the white line marks the depletion region boundary of the device. The first N-junction formed by the gate region and the channel region depletes each other. When the gate Vgs approaches Vth, the depletion region width of the first PN junctions on both sides narrows, and an undepleted region appears in the channel region to form a current path.

[0144] like Figure 11As shown, when the gate Vgs is close to Vth, a current path appears in the channel region, but the path is very narrow. As Vgs increases further, the depletion region continues to shrink, and the current path gradually increases until it approaches the width of the entire channel region.

[0145] When the gate zero bias voltage Vgs=0V, the channel region is pinched off, and increasing the drain voltage of the device will cause the device to break down. Figure 12 for Figure 7 A schematic diagram of the current density of a normally off gate-controlled junction field-effect transistor during breakdown. (See diagram for example.) Figure 12 As shown, breakdown occurs at the edge of the shielding region in the channel region of the device, the device is damaged, and a large breakdown current occurs from the source to the drain.

[0146] Figure 13 for Figure 7 Simulation diagram of a normally off gate-controlled junction field-effect transistor in the off state when the gate bias voltage Vgs=0V. Figure 14 for Figure 13 Energy band diagram showing the energy bands of the gate region on one side extending through the channel region to the gate region on the other side.

[0147] The conduction band bottom and valence band top exhibit a "U" shape along the entire path, with higher energy levels in the gate region and lower energy levels in the channel region. The energy level drops to its lowest point at the center of the channel region, forming the valley of the energy band.

[0148] The energy band of the U-shaped structure is a direct manifestation of the built-in potential of the first PN junction formed by the gate-channel region. Due to the significant Fermi level difference between the P+ region and the N region, under thermal equilibrium (zero bias), the charge redistribution forms a built-in electric field, resulting in energy band bending.

[0149] A large electronic barrier forms between the gate and channel regions, preventing electrons from being transported from the source to the drain through the channel. In other words, the conduction band bottom at the center of the channel region is completely depleted, there is no free electron gas, and the conductive path is completely clamped off. This directly proves from band structure theory that the device is in a reliable off state at zero gate voltage.

[0150] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0151] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0152] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0153] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0154] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0155] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A normally-off gate-controlled junction field-effect transistor, characterized in that, Includes a JFET structure, the JFET structure comprising: JFET substrate region of a wide-bandgap semiconductor of the second doping type; Each of the two JFET substrate regions is formed on opposite sides of the JFET substrate region, and the portion of the JFET substrate region between the two gate regions is used as a channel region. The two gate regions and the channel region form two back-to-back first PN junctions. Wherein, the doping concentration of the channel region is less than the doping concentration of the gate region, and the width 2L of the channel region, the doping concentration of the channel region and the doping concentration of the gate region satisfy a preset relationship, so that when the first PN junction is not connected to an external voltage, the depletion regions of the two first PN junctions completely cover the entire width range of the channel region, thereby keeping the normally off gate-controlled junction field-effect transistor off. When no external voltage is applied, the depletion regions of the two first PN junctions completely cover the entire width of the channel region in a manner that at least partially overlaps. The preset relationship between the width 2L of the channel region, the doping concentration of the channel region, and the doping concentration of the gate region is as follows: ； Where, N D N represents the doping concentration of the gate region for the first doping type. A The doping concentration of the JFET substrate region is the second type of doping, and k is the Boltzmann constant. Let n be the dielectric constant of the semiconductor, q be the electron charge, and n be the... i Where is the intrinsic carrier concentration, and T is the absolute temperature.

2. The normally-off gate-controlled junction field-effect transistor according to claim 1, characterized in that, The preset applied voltage Va is consistent with the threshold voltage Vth of the gate-controlled junction field-effect transistor, and the absolute value of Va is less than the absolute value of Vth. When a non-zero preset external voltage Va is applied to the first PN junction, the depletion regions of the two first PN junctions still completely cover the entire width of the channel region.

3. The normally-off gate-controlled junction field-effect transistor according to claim 2, characterized in that, When the first doping type is P-type and the second doping type is N-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is positive and greater than 1V. When Va is set to 0.5V, .

4. The normally-off gate-controlled junction field-effect transistor according to claim 2, characterized in that, When the first doping type is N-type and the second doping type is P-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is negative and less than -1V. When Va is set to -0.5V, .

5. The normally-off gate-controlled junction field-effect transistor according to any one of claims 1 to 4, characterized in that, The doping concentration in the channel region is greater than or equal to 1×10¹⁵ cm⁻³ and less than or equal to 1×10¹⁹ cm⁻³. The doping concentration of the gate region is greater than or equal to 1×10¹⁷ cm⁻³ and less than or equal to 1×10²⁰ cm⁻³. The width 2L of the channel region is greater than or equal to 0.08 μm and less than or equal to 0.5 μm.

6. A normally-off gate-controlled junction field-effect transistor, characterized in that, Includes a JFET structure, the JFET structure comprising: JFET substrate region of a wide-bandgap semiconductor of the second doping type; Each of the two JFET substrate regions is formed on opposite sides of the JFET substrate region, and the portion of the JFET substrate region between the two gate regions is used as a channel region. The two gate regions and the channel region form two back-to-back first PN junctions. Wherein, the doping concentration of the channel region is less than the doping concentration of the gate region, and the width 2L of the channel region, the doping concentration of the channel region and the doping concentration of the gate region satisfy a preset relationship, so that when the first PN junction is not connected to an external voltage, the depletion regions of the two first PN junctions completely cover the entire width range of the channel region, thereby keeping the normally off gate-controlled junction field-effect transistor off. When no external voltage is applied, the depletion regions of the two first PN junctions completely cover the entire width of the channel region in a connected manner. The preset relationship between the width 2L of the channel region, the doping concentration of the channel region, and the doping concentration of the gate region is as follows: ； Where ND is the doping concentration of the gate region of the first doping type, NA is the doping concentration of the JFET substrate region of the second doping type, and k is the Boltzmann constant. ν is the semiconductor dielectric constant, q is the electron charge, ni is the intrinsic carrier concentration, and T is the absolute temperature.

7. The normally-off gate-controlled junction field-effect transistor according to claim 6, characterized in that, When the first doping type is P-type and the second doping type is N-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is positive and greater than 1V. Alternatively, if the first doping type is N-type and the second doping type is P-type, the threshold voltage Vth of the normally off gate-controlled junction field-effect transistor is negative and less than -1V.

8. The normally-off gate-controlled junction field-effect transistor according to any one of claims 6 to 7, characterized in that, The doping concentration in the channel region is greater than or equal to 1 × 10⁻⁶. 15 cm -3 And less than or equal to 1×10 19 cm -3 ; The doping concentration of the gate region is greater than or equal to 1 × 10⁻⁶. 17 cm -3 And less than or equal to 1×10 20 cm -3 ; The width 2L of the channel region is greater than or equal to 0.08 μm and less than or equal to 0.5 μm.

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