Display device, method for manufacturing the same, and electronic device including the same

Abstract

A display device, a method for manufacturing the same, and an electronic device including the same are provided. The display device includes: a substrate including a display area and a non-display area; a first transistor including a first semiconductor layer disposed on the display area of the substrate and a first gate electrode disposed on the first semiconductor layer; and a first gate insulator disposed between the first semiconductor layer and the first gate electrode, in which the first semiconductor layer includes a first layer and a second layer stacked on each other in a direction perpendicular to the substrate, and in which an indium content of the second layer is higher than an indium content of the first layer, and a height of the first layer is lower than a height of the second layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0088642, filed on July 5, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to a display device and a method of manufacturing the display device. Background Technology

[0003] With the development of multimedia technology, display devices have become increasingly important. Therefore, various display devices such as liquid crystal displays and light-emitting displays are currently being developed. Summary of the Invention

[0004] The disclosed aspect provides a display device comprising an oxide semiconductor having high mobility characteristics and a method for manufacturing the same.

[0005] These and other aspects, embodiments, and advantages disclosed will immediately become apparent to those skilled in the art upon review of the detailed embodiments and claims.

[0006] Details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the following description.

[0007] According to the disclosed aspects, a display device includes: a substrate including a display area and a non-display area; a first transistor including a first semiconductor layer disposed on the display area of ​​the substrate and a first gate electrode disposed on the first semiconductor layer; and a first gate insulator disposed between the first semiconductor layer and the first gate electrode, wherein the first semiconductor layer includes a first layer and a second layer stacked on top of each other in a direction perpendicular to the substrate, and wherein the indium content of the second layer is higher than the indium content of the first layer, and the height of the first layer is lower than the height of the second layer.

[0008] In an embodiment, the first layer may include an oxide semiconductor containing about 30 at% to about 40 at% indium, and the second layer may include an oxide semiconductor containing about 65 at% to about 70 at% indium.

[0009] In an embodiment, the first layer may include indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO), and the second layer may include indium tin gallium zinc oxide (ITGZO).

[0010] In an embodiment, the height of the first layer can be in the range of about 20 angstroms to about 70 angstroms, and the height of the second layer can be in the range of about 100 angstroms to about 200 angstroms.

[0011] In one embodiment, the second layer may be in contact with the first gate insulator.

[0012] In one embodiment, the first gate insulator may include silicon oxide.

[0013] In an embodiment, under heat treatment conditions performed in the first gate insulator at a temperature ranging from about 50°C to about 550°C, the amount of nitric oxide released can be about 2.5E+18 mol / cm³. 3 Or even less, releasing approximately 3E+19 mol / cm³ of hydrogen gas. 3 And the amount of oxygen released is approximately 2.76E+19 mol / cm³. 3 Or smaller.

[0014] In an embodiment, the first semiconductor layer may include a channel region superimposed on a first gate insulator and a source region and a drain region located at the ends of the channel region, wherein the first gate insulator may be an insulating pattern that exposes the drain region and the source region.

[0015] In an embodiment, the first layer and the second layer can be located in the channel region, the source region, and the drain region.

[0016] In this embodiment, the first layer and the second layer may be disposed in the channel region, and the first layer and the second layer may not be disposed in the source region or the drain region.

[0017] In an embodiment, the first semiconductor layer may further include a third layer, which is spaced apart from the first layer in a direction perpendicular to the substrate, and a second layer is disposed between the third layer and the first layer. The first layer and the third layer may include the same material, and the height of the third layer may be lower than the height of the second layer.

[0018] In an embodiment, the height of the third layer can be in the range of about 20 angstroms to about 70 angstroms.

[0019] In an embodiment, the display device may further include: a second transistor disposed on a non-display area of ​​a substrate, and including a second semiconductor layer and a second gate electrode disposed on the second semiconductor layer; and a second gate insulator disposed between the second semiconductor layer and the second gate electrode.

[0020] In an embodiment, the second semiconductor layer may be disposed in the same layer as the first semiconductor layer in a non-display area, and wherein the second semiconductor layer may include: a first sublayer having the same material and height as the first layer; and a second sublayer having the same material and height as the second layer.

[0021] In an embodiment, the second semiconductor layer may be disposed in a non-display area and may further include a third sub-layer, which is spaced apart from the first sub-layer in a direction perpendicular to the substrate, and the second sub-layer is disposed between the third sub-layer and the first sub-layer.

[0022] According to the disclosed aspects, a method for manufacturing a display device is provided, the method comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulator on the semiconductor layer; and forming a gate electrode on the gate insulator, wherein the semiconductor layer comprises a first layer, a second layer, and a third layer stacked one on top of the other in the order of a first layer, a second layer, and a third layer, and wherein the indium content of the first layer and the indium content of the third layer are lower than the indium content of the second layer.

[0023] In an embodiment, the first, second, and third layers may be stacked with the gate electrode and the gate insulator in a direction perpendicular to the substrate.

[0024] In this embodiment, the height of the first layer and the height of the third layer may be lower than the height of the second layer.

[0025] According to the disclosed aspects, an electronic device may include a panel circuit layer disposed on a substrate, the substrate including a display area and a non-display area, wherein the panel circuit layer includes: a first transistor including a first semiconductor layer disposed on the display area of ​​the substrate and a first gate electrode disposed on the first semiconductor layer; and a first gate insulator disposed between the first semiconductor layer and the first gate electrode, the first semiconductor layer including a first layer and a second layer stacked on top of each other in a direction perpendicular to the substrate, and the indium content of the second layer is higher than that of the first layer, and the height of the first layer is lower than the height of the second layer.

[0026] The electronic device may be at least one of the following: smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (PMP), navigation system, and ultra-mobile computer.

[0027] According to the disclosed embodiments, in a display device, the semiconductor layer stacked with the gate electrode is composed of multiple layers with different indium contents and different heights, thereby providing an oxide semiconductor with high mobility characteristics.

[0028] It should be noted that the effects of disclosure are not limited to those described above, and other effects of disclosure will be apparent to those skilled in the art based on the following description. Attached Figure Description

[0029] The above and other aspects and features disclosed will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic plan view illustrating a display device according to a disclosed embodiment.

[0031] Figure 2 It is shown Figure 1 A schematic floor plan of the display panel.

[0032] Figure 3 It is a schematic diagram of the equivalent circuit diagram of a pixel according to the disclosed embodiments.

[0033] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display panel taken by line D-D'.

[0034] Figure 5 yes Figure 4 An enlarged schematic diagram of region A in the image.

[0035] Figure 6 yes Figure 5 An enlarged schematic cross-sectional view of the semiconductor layer.

[0036] Figure 7 According to yet another embodiment Figure 4 An enlarged schematic cross-sectional view of region A.

[0037] Figure 8 It spans Figure 2 The display area and non-display area in the diagram show a schematic cross-sectional view of the display panel.

[0038] Figure 9 yes Figure 8 Enlarged schematic cross-sectional view of region C.

[0039] Figure 10 According to yet another embodiment Figure 8 Enlarged schematic cross-sectional view of region C.

[0040] Figures 11 to 19 It shows the manufacturing process. Figure 4 A schematic cross-sectional view of the processing steps of the pixel transistor shown.

[0041] Figure 20 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0042] Figure 21 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0043] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of the apparatus or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. These various embodiments are not necessarily exclusive, nor are they intended to limit the disclosure. For example, specific shapes, constructions, and characteristics of the embodiments may be used or implemented in the embodiments.

[0044] Unless otherwise stated, the illustrated embodiments should be understood as providing features of the invention. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0045] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, or any other characteristics, properties, etc. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. Where embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals and / or figure marks denote the same elements.

[0046] When an element (such as a layer) is referred to as being "on" another element or layer, "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element. Furthermore, the D1 axis, D2 axis, and D3 axis are not limited to the three axes of a Cartesian coordinate system (such as the x-axis, y-axis, and z-axis) and can be interpreted in a broader sense. For example, the D1 axis, D2 axis, and D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z (species / man)" and "at least one selected from the group consisting of X, Y, and Z (species / man)" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0047] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0048] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element to another(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. Furthermore, the use of the terms “comprising,” “including,” and / or variations thereof in this specification indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to interpret the inherent biases of measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0050] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of examples and / or intermediate structures. Therefore, variations in the illustrated shapes will be expected due to, for example, manufacturing techniques and / or tolerances. Thus, the embodiments disclosed herein should not be construed as limited to the specific shapes shown for a particular region, but rather include shape deviations caused, for example, by manufacturing processes. For instance, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are thus not intended to be limiting.

[0051] In accordance with convention in the art, some embodiments are described and illustrated in the accompanying drawings as functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0052] The disclosed embodiments will be described in detail below with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic plan view illustrating a display device according to a disclosed embodiment. Figure 2 It is shown Figure 1 A schematic floor plan of the display panel.

[0054] Reference Figures 1 to 2 The display device 100 is used to display moving or still images. The display device 100 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices (or systems), portable computers, and ultra-mobile PCs (UMPCs), as well as for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices. Those listed above are merely examples, and the display device 100 can also be used in other electronic devices such as virtual reality (VR) devices, mixed reality (MR) devices, or augmented reality (AR) devices.

[0055] Display device 100 may be a light-emitting display device, such as an organic light-emitting display device including organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, and an ultra-miniature light-emitting display device using ultra-miniature light-emitting diodes such as micro or nano light-emitting diodes (micro LEDs or nano LEDs). However, the disclosure is not limited thereto. For example, display device 100 may be other types of display devices besides light-emitting display devices. In the following description, an organic light-emitting display device is used as display device 100.

[0056] The display device 100 may include a display panel 110, a first driver 120, and a second driver 130.

[0057] exist Figure 1 and Figure 2 The diagram defines a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 can be perpendicular to each other, as can the first direction D1 and the third direction D3, and vice versa. For example, the first direction D1 can be the horizontal direction of the display panel 110 (e.g., row direction), the second direction D2 can be the vertical direction of the display panel 110 (e.g., column direction), and the third direction D3 can be the thickness direction of the display panel 110 (e.g., height direction).

[0058] According to the disclosed embodiments, the display panel 110 may have a rectangular shape when viewed from above (e.g., in a plan view). For example, the display panel 110 may include two first sides extending in a first direction D1 and two second sides extending in a second direction D2 intersecting the first direction D1. Although in Figure 1 and Figure 2 In the example shown, the first side of the display panel 110 in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel 110 is not limited to this. For example, the display panel 110 may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or it may have a shape in which the first side and the second side have substantially the same length.

[0059] The display panel 110 may include, but is not limited to, an angled corner where the first and second sides meet. For example, the display panel 110 may include a rounded corner (bevel) where the first and second sides meet.

[0060] When viewed from above (e.g., in a plan view), the shape of the display panel 110 is not limited to the rectangular shape described above, but may take other shapes. For example, when viewed from above (e.g., in a plan view), the display panel 110 may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes.

[0061] The display panel 110 may be substantially flat on a plane defined by a first direction D1 and a second direction D2, and may have a uniform thickness in a third direction D3. According to another embodiment, the display panel 110 may be implemented in a three-dimensional shape having curved surfaces, etc.

[0062] The display panel 110 can be a rigid display panel that is substantially non-deformable, or a flexible display panel that can deform (i.e., at least partially fold, bend, or roll). The display panel 110 can be disposed on the display device 100 without bending or with partial bending.

[0063] The display panel 110 may include a base SUB and a plurality of pixels PX disposed on the base SUB.

[0064] According to the disclosed embodiments, the substrate SUB can be a substrate component used to manufacture or provide the display panel 110, and can form the substrate surface of the display panel 110. The substrate SUB may include a display area DA, a non-display area NDA, and a pad (or "soldering pad") area PA.

[0065] According to embodiments, the display area DA can have various shapes. For example, the display area DA can have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other shapes. When viewed from above (e.g., in a plan view), the display area DA can have, but is not limited to, a shape that conforms to the shape of the display panel 110.

[0066] Pixels (PX) can be arranged within the display area (DA) of the substrate (SUB). Pixels (PX) can be in RGB stripe, RGB delta, or PenTile configurations. ® A matrix or any other geometric arrangement.

[0067] The non-display area NDA can surround the display area DA. The non-display area NDA can refer to the edge of the substrate SUB. In the non-display area NDA, multiple circuits for driving the first driver 120 and the display area DA can be set.

[0068] Multiple pads (PDs) may be disposed in pad areas (PAs). At least one circuit board (140) may be disposed on and / or bonded to the multiple pads (PDs). The pads (PDs) may include signal pads and power pads for transmitting drive signals and power voltages required to drive pixels (PXs) and / or the first driver (120) to the interior of the display panel (110).

[0069] According to the disclosed embodiments, the first driver 120 and the second driver 130 can generate drive signals for controlling the operating timing and brightness of the pixel PX, and can provide the drive signals to the pixel PX. For example, the first driver 120 can be a gate driver including a scan driver, and can be electrically connected to the pixel PX via gate lines. The first driver 120 can provide gate signals (e.g., drive signals controlling the operating timing of the pixel PX, such as...) to the pixel PX. Figure 3 The second driver 130 can be a data driver including source driver circuitry and can be electrically connected to the pixel PX via corresponding data lines. The second driver 130 can supply corresponding data signals to the pixel PX.

[0070] According to the disclosed embodiments, circuit board 140 can be electrically connected to display panel 110 via pad PD. Circuit board 140 can be, but is not limited to, a printed circuit board (PCB) such as a flexible printed circuit board (FPCB) or a rigid printed circuit board, or a flexible film such as chip on film (COF). Circuit board 140 can be electrically connected to timing controller and / or power supply unit via another circuit board or connector.

[0071] Figure 3 This is a schematic diagram of the equivalent circuit diagram of pixel PX according to a disclosed embodiment. Figure 3The pixel PX is merely an example, and the structure or type of the pixel PX may vary depending on the implementation.

[0072] Combination Figure 1 and Figure 2 Reference Figure 3 A pixel PX may include a light-emitting element (ED) and a pixel circuit PC connected to the ED. The ED is the light source of the pixel PX and may be, but is not limited to, an organic light-emitting diode (OLED). The pixel circuit PC may provide a drive current Id associated with a data signal DATA to the ED to control the emission of the ED.

[0073] A pixel circuit PC may include a pixel transistor Tpx and at least one capacitor Ct. For example, a pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Ct. The structure of the pixel circuit PC, or the type and number of circuit elements forming it, may vary depending on the embodiment. For example, the pixel circuit PC may also include at least one other pixel transistor and / or at least one other capacitor. Figure 3 In this embodiment, all pixel transistors Tpx are n-type transistors. It should be noted that the type of pixel transistor Tpx is not limited to this. For example, at least one pixel transistor Tpx can be implemented as a p-type transistor.

[0074] The pixel circuit PC can supply a drive current Id to the light-emitting element ED in response to a drive signal supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC can supply a drive current Id to the light-emitting element ED in response to at least one gate signal GW (e.g., a scan signal for selecting each horizontal row of pixels PX) supplied from the first driver 120 via at least one gate line GWL (e.g., a scan line connected to each horizontal row of pixels PX) and a data signal DATA supplied from the second driver 130 via a data line DL.

[0075] The first transistor T1 can be a switching transistor that is turned on or off according to the gate-source voltage. The second transistor T2 can be a driving transistor of the pixel PX, wherein the magnitude of the drain-source current (e.g., drive current Id) is determined according to the gate-source voltage. Depending on the type (e.g., p-type or n-type transistor) and / or operating conditions of each of the first transistor T1 and the second transistor T2, the first electrode of each of the first transistor T1 and the second transistor T2 can be a drain electrode (or drain region) or a source electrode (or source region), while the second electrode of each of the first transistor T1 and the second transistor T2 can be an electrode different from the first electrode. For example, if the first electrode of the first transistor T1 is a drain electrode, then the second electrode of the first transistor T1 can be a source electrode.

[0076] Pixel PX can be electrically connected to the gate line GWL (e.g., scan line) for transmitting gate signals GW (e.g., scan signals) and the data line DL for transmitting data signals DATA. Pixel PX can also be electrically connected to the first pixel voltage line VDL for transmitting the first pixel voltage ELVDD (also referred to as the "first pixel power supply voltage") and the second pixel voltage line VSL for transmitting the second pixel voltage ELVSS (also referred to as the "second pixel power supply voltage").

[0077] The first transistor T1 and the second transistor T2 can be positioned in corresponding pixel regions (e.g., pixel region PXA of pixel PX in display region DA, see [reference]). Figure 4 In the process of constructing a first transistor T1 and a second transistor T2, the semiconductor layer (also referred to as an active pattern or semiconductor pattern) may be formed of an oxide transistor, which may include an oxide semiconductor (e.g., an oxide semiconductor material). However, the disclosed embodiments are not limited thereto. For example, at least one pixel transistor Tpx may be formed of a semiconductor material other than oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0078] Oxide semiconductors possess high carrier mobility (e.g., high electron mobility in the case of n-type transistors) and low leakage current; therefore, even when driving oxide transistors for extended periods, no large voltage drop occurs. For example, because changes in image brightness and / or color due to voltage drop are negligible even when driven at low frequencies, pixels PX including oxide transistors can be driven at low frequencies. For a display device 100 in which pixel transistors Tpx include oxide semiconductors, leakage current of pixel PX can be reduced or prevented, and power consumption can be saved.

[0079] The bottom electrode (also known as the back gate electrode, counter gate electrode, or bottom electrode) can be disposed beneath the semiconductor layer forming at least one pixel transistor Tpx. For example, by disposing the bottom electrode beneath the semiconductor layer comprising an oxide semiconductor of the pixel transistor Tpx, external light can be blocked. The bottom electrode can be opposite the gate electrode, and the semiconductor layer of the pixel transistor Tpx is located between the bottom electrode and the gate electrode.

[0080] Each pixel transistor Tpx may include a bottom electrode. For example, the first transistor T1 may include a first bottom electrode BG1, and the second transistor T2 may include a second bottom electrode BG2. By providing a bottom electrode for the pixel transistor Tpx, current fluctuations in the pixel transistor Tpx caused by light can be prevented or reduced, and the operating characteristics of the pixel transistor Tpx can be stabilized.

[0081] The first transistor T1 may include a gate electrode electrically connected to a gate line GWL, a first electrode electrically connected to a data line DL, and a second electrode electrically connected to a first node N1. The first transistor T1 can be turned on by a gate signal GW (e.g., a scan signal of the gate on-state voltage) transmitted to the gate line GWL to electrically connect the data line DL to the first node N1. Therefore, the data signal DATA transmitted on the data line DL can be transmitted to the first node N1.

[0082] The first transistor T1 may further include a first bottom electrode BG1 (or a first back gate electrode). The first bottom electrode BG1 may be electrically connected to one electrode of the first transistor T1, such as the gate electrode. When the first bottom electrode BG1 is electrically connected to the gate electrode of the first transistor T1, the operating characteristics of the first transistor T1 can be improved and / or stabilized. For example, since the first transistor T1 may have a dual-gate structure, the cutoff characteristics and switching speed of the first transistor T1 can be improved, additional voltage tolerance can be obtained, leakage current can be reduced, and voltage stability can be improved.

[0083] The second transistor T2 may include a gate electrode electrically connected to the first node N1 (or gate node), a first electrode (e.g., drain electrode or drain region) electrically connected to the first pixel voltage line VDL, and a second electrode (e.g., source electrode or source region) electrically connected to the second node N2. The second node N2 may be electrically connected to the light-emitting element ED. The second transistor T2 may control the magnitude (e.g., current amount) of the drive current Id flowing to the light-emitting element ED in response to a data signal DATA transmitted according to the switching operation of the first transistor T1.

[0084] The second transistor T2 may also include a second bottom electrode BG2. For example, the second transistor T2 may also include a second bottom electrode BG2 (or a second back gate electrode) electrically connected to the second node N2. When the second bottom electrode BG2 is electrically connected to the second node N2 together with the second electrode of the second transistor T2, the operating characteristics of the second transistor T2 can be improved.

[0085] A capacitor Ct can be electrically connected between the first node N1 and the second node N2. For example, capacitor Ct can be electrically connected between the gate electrode and the second electrode of the second transistor T2. Capacitor Ct can be the storage capacitor of pixel PX and can store the voltage corresponding to the data signal DATA (e.g., data voltage).

[0086] The light-emitting element (ED) can be electrically connected between the pixel circuit PC and the second pixel voltage line VSL. The ED can include a first electrode (e.g., an anode electrode or pixel electrode), a second electrode facing the first electrode (e.g., a cathode electrode or counter electrode), and an emitting layer disposed between the first and second electrodes. The first electrode of the ED can be electrically connected to a second node N2. The second electrode of the ED can be electrically connected to the second pixel voltage line VSL. The second electrode of the ED can be a common electrode shared by multiple pixels PX. While supplying a driving current Id from the pixel circuit PC, the ED can emit light with a brightness proportional to the driving current Id.

[0087] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display panel taken by line D-D'.

[0088] Combination Figures 1 to 3 Reference Figure 4 The display panel 110 according to the disclosed embodiments may include a substrate SUB (also referred to as a "substrate member" or "substrate layer"), a panel circuit layer PCL, a light-emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light-emitting element layer LEL, and the encapsulation layer ENL may be disposed or provided on the substrate SUB such that they are stacked on top of each other. For example, in the display area DA, the panel circuit layer PCL, the light-emitting element layer LEL, and the encapsulation layer ENL may be sequentially disposed on or formed on the substrate SUB in a third direction D3. However, the embodiments are not limited thereto. The relative positions of the panel circuit layer PCL, the light-emitting element layer LEL, and / or the encapsulation layer ENL may be varied. For example, the panel circuit layer PCL and the light-emitting element layer LEL may be integral with each other, or the light-emitting element layer LEL may be disposed on the panel circuit layer PCL.

[0089] According to the disclosed embodiments, the substrate SUB can be a base component for forming the display panel 110, and can be a rigid or flexible substrate (or film). The substrate SUB can be an insulating material including glass and can be a rigid substrate that is inflexible. According to another embodiment, the substrate SUB can be a flexible substrate including polyimide or other insulating materials and allowing deformations such as bending, folding, or rolling, and can be bent or not bent. The type and / or material of the substrate SUB can be varied according to the embodiments.

[0090] The base SUB may include a display area DA. Within the display area DA, pixel regions PXA may be defined, with each pixel PX disposed therein.

[0091] According to the disclosed embodiments, a barrier layer (BRL) can be disposed on a substrate SUB. The barrier layer BRL can protect the pixel PX from moisture that penetrates through the moisture-sensitive substrate SUB. The material of the barrier layer BRL can vary depending on the embodiments.

[0092] The barrier layer (BRL) may include at least one inorganic layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials).

[0093] In some embodiments, the barrier layer BRL can be eliminated. If the barrier layer BRL is eliminated, the substrate SUB and the panel circuit layer PCL can contact each other.

[0094] According to the disclosed embodiments, the panel circuit layer PCL can be positioned on the barrier layer BRL. The panel circuit layer PCL may include a pixel transistor Tpx, a buffer layer BFL, an interlayer dielectric layer ILD, a first passivation layer PSV1, and a second passivation layer PSV2.

[0095] According to the disclosed embodiments, the pixel transistor Tpx may be included as referenced above. Figure 3 The pixel circuit PC is described for each pixel PX. The pixel transistor Tpx may include a first transistor T1 and a second transistor T2 in the display area DA.

[0096] According to the disclosed embodiments, the first transistor T1 may include a first conductive layer CDL1, a semiconductor layer SCL, a second conductive layer CDL2, a third conductive layer CDL3, and a fourth conductive layer CDL4. The first transistor T1 may include a first bottom electrode BG1 of the first conductive layer CDL1, a first semiconductor layer ACT1 of the semiconductor layer SCL, a first gate electrode GE1 of the second conductive layer CDL2, and a first drain electrode DE1 and a first source electrode SE1 of the third conductive layer CDL3.

[0097] According to the disclosed embodiments, the first bottom electrode BG1, included in the first conductive layer CDL1, can be disposed between the substrate SUB and the buffer layer BFL. For example, the first conductive layer CDL1 can be disposed on the barrier layer BRL and covered by the buffer layer BFL.

[0098] The first bottom electrode BG1 can be stacked on the third direction D3 with the first semiconductor layer ACT1. For example, the first bottom electrode BG1 can be disposed below the first semiconductor layer ACT1, such that it is stacked at least with the first channel region CH1. The first bottom electrode BG1 and the first semiconductor layer ACT1 can be spaced apart from each other by a distance equal to the thickness of the buffer layer BFL. For example, the first bottom electrode BG1 can face the first gate electrode GE1, and the first semiconductor layer ACT1 can be disposed between the first bottom electrode BG1 and the first gate electrode GE1.

[0099] According to the disclosed embodiments, the first semiconductor layer ACT1 included in the semiconductor layer SCL can be disposed between the buffer layer BFL and the interlayer dielectric layer ILD. For example, the first semiconductor layer ACT1 can be disposed on the buffer layer BFL and can be covered by the gate insulator GI and the interlayer dielectric layer ILD.

[0100] The first semiconductor layer ACT1 may include: a first channel region CH1, stacked with a first gate electrode GE1; and a first source region SR1 and a first drain region DR1, spaced apart from each other in a direction parallel to the substrate SUB, with the first channel region CH1 positioned between the first source region SR1 and the first drain region DR1. The first source region SR1 and the first drain region DR1 may be located at opposite ends of the first channel region CH1.

[0101] The first channel region CH1 may not be conductive and may retain semiconductor properties, while the first source region SR1 and the first drain region DR1 may be conductive regions.

[0102] The first semiconductor layer ACT1 can be stacked on the third direction D3 with the first bottom electrode BG1 and the first gate electrode GE1. The first channel region CH1 of the first semiconductor layer ACT1 can be disposed on the third direction D3 between the first bottom electrode BG1 and the first gate electrode GE1, and can be stacked on the first bottom electrode BG1 and the first gate electrode GE1.

[0103] According to an embodiment, a first gate electrode GE1 included in the second conductive layer CDL2 can be disposed between the gate insulator GI and the interlayer dielectric layer ILD. The first gate electrode GE1 can be positioned on the first gate insulator GI1 and can be covered by the interlayer dielectric layer ILD.

[0104] The first gate electrode GE1 may be stacked on the third direction D3 with the first channel region CH1 of the first semiconductor layer ACT1. The first gate electrode GE1 and the first semiconductor layer ACT1 may be spaced apart from each other, and the first gate insulator GI1 is placed between the first gate electrode GE1 and the first semiconductor layer ACT1.

[0105] According to the disclosed embodiments, the first drain electrode DE1 and the first source electrode SE1, included in the third conductive layer CDL3, can be positioned between the interlayer dielectric layer ILD and the first passivation layer PSV1. For example, the first drain electrode DE1 and the first source electrode SE1 can be positioned on the interlayer dielectric layer ILD and covered by the first passivation layer PSV1.

[0106] The first drain electrode DE1 can be electrically connected to the first drain region DR1 through at least one contact hole penetrating the interlayer dielectric layer ILD, and the first source electrode SE1 can be electrically connected to the first source region SR1 through at least one contact hole penetrating the interlayer dielectric layer ILD.

[0107] According to the disclosed embodiments, the second transistor T2 may include a second bottom electrode BG2 of the first conductive layer CDL1, a second semiconductor layer ACT2 of the semiconductor layer SCL, a second gate electrode GE2 of the second conductive layer CDL2, and a second drain electrode DE2 and a second source electrode SE2 of the third conductive layer CDL3.

[0108] According to the disclosed embodiments, the second bottom electrode BG2, included in the first conductive layer CDL1, can be disposed between the substrate SUB and the buffer layer BFL. For example, the first conductive layer CDL1 can be disposed on the barrier layer BRL and covered by the buffer layer BFL. The first bottom electrode BG1 and the second bottom electrode BG2 can be provided on the substrate SUB and / or disposed in the same layer, such that they are spaced apart from each other and can comprise the same material.

[0109] The second bottom electrode BG2 can be stacked on the second semiconductor layer ACT2 on the third-direction D3. For example, the second bottom electrode BG2 can be disposed below the second semiconductor layer ACT2, such that the second bottom electrode BG2 is at least stacked with the second channel region CH2. A buffer layer BFL can be disposed between the second bottom electrode BG2 and the second semiconductor layer ACT2. The second bottom electrode BG2 and the second semiconductor layer ACT2 can be spaced apart from each other by a distance equal to the thickness of the buffer layer BFL. The second bottom electrode BG2 can face the second gate electrode GE2, and the second semiconductor layer ACT2 is disposed between the second bottom electrode BG2 and the second gate electrode GE2.

[0110] According to the disclosed embodiments, a second semiconductor layer ACT2 included in the semiconductor layer SCL can be disposed between the buffer layer BFL and the interlayer dielectric layer ILD. For example, the second semiconductor layer ACT2 can be disposed on the buffer layer BFL and can be covered by the second gate insulator GI2 and the interlayer dielectric layer ILD. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 can be provided on the substrate SUB and / or disposed in the same layer, such that the first semiconductor layer ACT1 and the second semiconductor layer ACT2 are spaced apart from each other and can include the same oxide semiconductor.

[0111] The second semiconductor layer ACT2 may include: a second channel region CH2, stacked on a third direction D3 with a second gate electrode GE2; and a second source region SR2 and a second drain region DR2, spaced apart from each other in a direction parallel to the substrate SUB, with the second channel region CH2 between the second source region SR2 and the second drain region DR2. The second source region SR2 and the second drain region DR2 may be located at opposite ends of the second channel region CH2.

[0112] The second channel region CH2 may not be conductive and may retain semiconductor properties, while the second source region SR2 and the second drain region DR2 may be conductive regions.

[0113] The second semiconductor layer ACT2 can be stacked on the third-direction D3 with the second bottom electrode BG2 and the second gate electrode GE2. For example, the second channel region CH2 of the second semiconductor layer ACT2 can be stacked on the third-direction D3 with the second bottom electrode BG2 and the second gate electrode GE2.

[0114] According to the disclosed embodiments, the semiconductor layer SCL can be an oxide semiconductor including indium (In). For example, each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can be an oxide semiconductor including indium (In) in a content of about 30 at% (atomic percentage) to about 75 at%.

[0115] In the display panel 110 according to the embodiment, the atomic ratio of indium (In) included in the semiconductor layer is controlled within the above range, such that the carrier concentration and / or conductivity of the semiconductor layer SCL can be controlled, and the device characteristics of the transistors (e.g., mobility and threshold voltage) can be controlled and / or ensured. For example, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can control the characteristics of the first transistor T1 and the second transistor T2, such that each of the first transistor T1 and the second transistor T2 has an appropriate mobility for driving the pixel PX (e.g., at approximately 60 cm). 2 The electron mobility (in the range of / Vs or higher) and threshold voltage (e.g., about -2.0V or higher). The mobility and threshold voltage of the first transistor T1 and the second transistor T2 are not limited to the ranges mentioned above, but can vary depending on the design conditions or driving conditions of the display panel 110.

[0116] According to the disclosed embodiments, the second gate electrode GE2, included in the second conductive layer CDL2, can be disposed between the gate insulator GI and the interlayer dielectric layer ILD. For example, the second gate electrode GE2 can be positioned on the second gate insulator GI2 and can be covered by the interlayer dielectric layer ILD. The first gate electrode GE1 and the second gate electrode GE2 can be provided and / or disposed in the same layer, such that they are spaced apart from each other.

[0117] The second gate electrode GE2 can be stacked on the third-direction D3 with the second channel region CH2 of the second semiconductor layer ACT2. The second gate electrode GE2 and the second semiconductor layer ACT2 can be spaced apart from each other, and the second gate insulator GI2 is between the second gate electrode GE2 and the second semiconductor layer ACT2.

[0118] According to the disclosed embodiments, the second drain electrode DE2 and the second source electrode SE2, included in the third conductive layer CDL3, can be positioned between the interlayer dielectric layer ILD and the first passivation layer PSV1. For example, the second drain electrode DE2 and the second source electrode SE2 can be positioned on the interlayer dielectric layer ILD and covered by the first passivation layer PSV1. The second drain electrode DE2 and the second source electrode SE2 can be disposed in the same layer as the first drain electrode DE1 and the first source electrode SE1 disposed on the substrate SUB.

[0119] The second drain electrode DE2 can be electrically connected to the second drain region DR2 through at least one contact hole penetrating the interlayer dielectric layer (ILD), and the second source electrode SE2 can be electrically connected to the second source region SR2 through at least one contact hole penetrating the interlayer dielectric layer (ILD). According to an embodiment, the second source electrode SE2 can be electrically connected to the second bottom electrode BG2 in addition to being electrically connected to the second source region SR2.

[0120] According to an embodiment, a first passivation layer PSV1 can be positioned on a third conductive layer CDL3. The first passivation layer PSV1 can cover (e.g., completely cover) the third conductive layer CDL3.

[0121] The first passivation layer PSV1 can protect the circuit elements and lines disposed in the panel circuit layer PCL from the effects of moisture penetration, etc. The first passivation layer PSV1 can have a multilayer structure including at least one inorganic film (e.g., an inorganic insulating layer) and an organic film (e.g., an organic insulating layer).

[0122] The first passivation layer PSV1 may include a first inorganic film IOL1 and a first organic film ORL1 sequentially disposed on the interlayer dielectric layer ILD in the third direction D3. The first inorganic film IOL1 may be disposed on the third conductive layer CDL3 and the interlayer dielectric layer ILD, and may contact and cover the third conductive layer CDL3. The first inorganic film IOL1 may include silicon nitride. The first organic film ORL1 may be disposed on the first inorganic film IOL1, and may provide a flat surface over the first inorganic film IOL1 having a horizontal difference. The first organic film ORL1 may include an organic material.

[0123] According to an embodiment, the fourth conductive layer CDL4 can be positioned between the first passivation layer PSV1 and the second passivation layer PSV2. For example, the fourth conductive layer CDL4 can be disposed on the first passivation layer PSV1 and covered by the second passivation layer PSV2.

[0124] The fourth conductive layer CDL4 may include a connection electrode CNE. The connection electrode CNE may be disposed on the first organic film ORL1 and covered by the second inorganic film IOL2. The connection electrode CNE can electrically connect the light-emitting element ED to the second transistor T2.

[0125] According to the embodiment, the second passivation layer PSV2 can be positioned on the fourth conductive layer CDL4. The second passivation layer PSV2 can protect the circuit elements and lines disposed in the panel circuit layer PCL from the effects of moisture penetration, etc.

[0126] The second passivation layer PSV2 may have a multilayer structure comprising at least one inorganic film (e.g., an inorganic insulating layer) and an organic film (e.g., an organic insulating layer). The second passivation layer PSV2 may comprise a second inorganic film IOL2 and a second organic film ORL2 sequentially disposed on the first passivation layer PSV1 in a third direction D3. The second inorganic film IOL2 and the first inorganic film IOL1 may comprise the same material, and the second organic film ORL2 and the first organic film ORL1 may comprise the same material. Redundant descriptions will be omitted.

[0127] The electrodes, conductive patterns, and / or lines disposed in each of the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, and the fourth conductive layer CDL4 of the panel circuit layer PCL may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, and other conductive materials. Each of the electrodes, conductive patterns, and / or lines may have a single-layer or multi-layer structure. Electrodes, conductive patterns, and / or lines disposed in the same conductive layer may be formed simultaneously using the same conductive material.

[0128] According to an embodiment, the light-emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) in the display area (DA). The light-emitting element layer (LEL) may include light-emitting elements (ED), pixel defining layers (PDL), and spacers (SPC).

[0129] According to the disclosed embodiments, the light-emitting element ED may include a first electrode ET1, an emitting layer EML, and a second electrode ET2 electrically connected to at least one pixel transistor Tpx.

[0130] According to the disclosed embodiments, the first electrode ET1 can be disposed on the panel circuit layer PCL. The first electrode ET1 can be disposed on the second passivation layer PSV2, and can be electrically connected to the connection electrode CNE through at least one contact hole or via penetrating the second passivation layer PSV2.

[0131] The first electrode ET1 may include a conductive metallic material with high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or it may have a multilayer structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF2, ITO / Ag, ITO / Ag / ITO, etc.).

[0132] According to the disclosed embodiments, the emitting layer EML may comprise a polymeric or low-molecular-weight material. Light emitted from the emitting layer EML can contribute to image display. The emitting layer EML may be set in a pixel PX (see...). Figure 3 In each of the pixels PX, the emission layer EML of each pixel PX can emit visible light of the color associated with the corresponding pixel PX.

[0133] According to the disclosed embodiments, the second electrode ET2 may include a conductive material. The second electrode ET2 may be a common electrode formed on the entire display area DA to cover the emitter layer EML and the pixel definition layer PDL.

[0134] The second electrode ET2 can be formed from a transparent conductive material (TCO) such as ITO, IZO, ZnO and ITZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag) and alloys of magnesium (Mg) and silver (Ag).

[0135] According to the disclosed embodiments, the pixel defining layer PDL can define an opening OP and can expose a portion of the pixel electrode ET1 through the opening OP. For example, the pixel defining layer PDL can be formed to cover the edge of the first electrode ET1 of the light-emitting element ED, and can define an opening OP that exposes the remaining portion of the first electrode ET1. The region where the exposed first electrode ET1 overlaps with the emission layer EML (or the region including the exposed first electrode ET1 and the emission layer EML) can be defined as the emission region (i.e., pixel region PXA) of each pixel PX.

[0136] The pixel defining layer (PDL) may include at least one organic insulating layer comprising an organic insulating material. For example, the pixel defining layer (PDL) may include acryloyl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or other organic insulating materials.

[0137] According to the disclosed embodiments, the spacer SPC can be disposed on a portion of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer comprising an organic insulating material. The spacer SPC may comprise the same material as the pixel defining layer PDL or may comprise a different material from the pixel defining layer PDL. The pixel defining layer PDL and the spacer SPC can be formed sequentially via a corresponding masking process. According to another embodiment, the pixel defining layer PDL and the spacer SPC can be formed simultaneously using a halftone mask. For example, the pixel defining layer PDL and the spacer SPC can be considered as a single insulating film.

[0138] According to the disclosed embodiments, the encapsulation layer ENL can be disposed on the light-emitting element layer LEL. The encapsulation layer ENL can cover the light-emitting element layer LEL in the display area DA and can extend to the non-display area NDA to contact the panel circuit layer PCL. The encapsulation layer ENL can prevent oxygen or moisture from penetrating into the light-emitting element layer LEL and can mitigate electrical and / or physical shocks to the panel circuit layer PCL and the light-emitting element layer LEL.

[0139] The encapsulation layer ENL may have a multilayer structure comprising a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially disposed on a third-party direction D3. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer containing inorganic materials, and the second encapsulation layer ENL2 may be an organic encapsulation layer containing organic materials. The structure and / or materials of the encapsulation layer ENL may be varied according to embodiments.

[0140] Figure 5 yes Figure 4 An enlarged schematic diagram of region A in the image.

[0141] Combination Figures 1 to 4 Reference Figure 5According to an embodiment, the first semiconductor layer ACT1 included in the semiconductor layer SCL may include a first layer A1, a second layer A2, and a third layer A3 stacked on top of each other on a third-direction D3. The first layer A1, the second layer A2, and the third layer A3 may be positioned such that the first layer A1, the second layer A2, and the third layer A3 are disposed in the first source region SR1, the first drain region DR1, and the first channel region CH1. The first layer A1 may be in contact with the buffer layer BFL, the third layer A3 may be in contact with the first gate insulator GI1, and the second layer A2 may be positioned between the first layer A1 and the third layer A3.

[0142] According to the disclosed embodiments, the first layer A1 may include at least one of gallium (Ga), zinc (Zn), and tin (Sn). For example, the first layer A1 may be an oxide semiconductor containing indium (In) at a content of about 30 at% to about 75 at% and containing at least one of gallium (Ga), zinc (Zn), and tin (Sn). For example, the first layer A1 may contain indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO).

[0143] According to an embodiment, the second layer A2 may comprise all of gallium (Ga), zinc (Zn), and tin (Sn). For example, the second layer A2 may be an oxide semiconductor comprising indium (In) at a content of about 30 at% to about 75 at% and comprising all of gallium (Ga), zinc (Zn), and tin (Sn). For example, the second layer A2 may comprise indium tin gallium zinc oxide (ITGZO).

[0144] According to the disclosed embodiments, the third layer A3 may comprise the same material as the first layer A1. The third layer A3 may comprise at least one of gallium (Ga), zinc (Zn), and tin (Sn). For example, the third layer A3 may be an oxide semiconductor comprising indium (In) in a content of about 30 at% to about 75 at% and containing at least one of gallium (Ga), zinc (Zn), and tin (Sn). For example, the third layer A3 may comprise indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO).

[0145] According to the disclosed embodiments, the indium (In) content in the second layer A2 can be greater than the indium (In) content in the first layer A1 and the third layer A3. For example, the indium (In) content in the first layer A1 and the third layer A3 can be in the range of about 30 at% to about 40 at%, and the indium (In) content in the second layer A2 can be in the range of about 65 at% to about 70 at%.

[0146] According to the disclosed embodiments, the first gate insulator GI1 may be disposed on the third layer A3 of the first semiconductor layer ACT1.

[0147] In the display panel 110A according to an embodiment, the electrical characteristics of the first transistor T1 can be optimized and / or stabilized by controlling the amounts of nitric oxide (NO), hydrogen (H2), and / or oxygen (O2) released from the first gate insulator GI1 during the manufacturing process. For example, based on the analysis of the first gate insulator GI1 using thermal desorption spectroscopy (TDS) of a heat treatment (e.g., a heat treatment performed at a surface temperature in the range of about 50°C to about 550°C) (or using thermal desorption gas spectroscopy of a heat treatment (e.g., a heat treatment performed at a surface temperature in the range of about 50°C to about 550°C), the amount of nitric oxide (NO) released can be about 2.5E+18 mol / cm³. 3 Or even less, the amount of hydrogen (H2) released could be approximately 3E+19 mol / cm³. 3 Or even less, and the amount of oxygen (O2) released could be approximately 2.76E+19 mol / cm³. 3 Or smaller.

[0148] For example, in the display panel 110A according to the embodiment, even if a separate oxygen supply layer is not formed inside and / or around the transistor during the manufacturing process, the device characteristics of each transistor can be controlled by controlling the concentrations of nitric oxide (NO), hydrogen (H2), and / or oxygen (O2) released from the first gate insulator GI1. Therefore, the manufacturing process of the display panel 110A can be simplified and / or reduced, thereby improving manufacturing efficiency. This manufacturing process will be described later.

[0149] According to an embodiment, the second semiconductor layer ACT2 included in the semiconductor layer SCL may include a first layer B1, a second layer B2, and a third layer B3 stacked on top of each other on a third-direction D3. The first layer B1, the second layer B2, and the third layer B3 may be positioned such that the first layer B1, the second layer B2, and the third layer B3 are disposed in the second source region SR2, the second drain region DR2, and the second channel region CH2.

[0150] The first layer B1, the second layer B2, and the third layer B3 included in the second semiconductor layer ACT2 can have the same structure and characteristics as the first layer A1, the second layer A2, and the third layer A3 included in the first semiconductor layer ACT1, respectively. The first layer B1 can be in contact with the buffer layer BFL, the third layer B3 can be in contact with the second gate insulator GI2, and the second layer B2 can be positioned between the first layer B1 and the third layer B3.

[0151] According to the disclosed embodiments, the first layer B1 may include indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO) containing about 30 at% to about 75 at% indium (In), the second layer B2 may include indium tin gallium zinc oxide (ITGZO) containing about 30 at% to about 75 at% indium (In), and the third layer B3 may include the same material as the first layer B1. That is, the third layer B3 may include indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO) containing about 30 at% to about 75 at% indium (In).

[0152] According to the disclosed embodiments, the indium (In) content in the second layer B2 can be greater than the indium (In) content in the first layer B1 and the third layer B3. For example, the indium (In) content in the first layer B1 and the third layer B3 can be in the range of about 30 at% to about 40 at%, and the indium (In) content in the second layer B2 can be in the range of about 65 at% to about 70 at%.

[0153] According to the disclosed embodiments, the second gate insulator GI2 can be disposed on the third layer B3 of the second semiconductor layer ACT2. The second gate insulator GI2 can have the same structure and material as the first gate insulator GI1. In the second gate insulator GI2, the amount of nitric oxide (NO) released can be approximately 2.5E+18 mol / cm³. 3 Or even less, the amount of hydrogen (H2) released could be approximately 3E+19 mol / cm³. 3 Or even less, and the amount of oxygen (O2) released could be approximately 2.76E+19 mol / cm³. 3 Or smaller.

[0154] In the display panel 110A according to an embodiment, the electrical characteristics of the second transistor T2 can be stabilized by controlling the concentrations of nitric oxide (NO), hydrogen (H2), and / or oxygen (O2) released from the second gate insulator GI2 during the manufacturing process. Further redundant descriptions will be omitted.

[0155] Figure 6 yes Figure 5 An enlarged schematic cross-sectional view of the semiconductor layer. Figure 6 It shows that it includes Figure 5 Enlarged cross-sectional view of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 in the semiconductor layer SCL.

[0156] Combination Figures 1 to 5 Reference Figure 6 The height Ha2 of the second layer A2, which is included in the first semiconductor layer ACT1, can be greater than the height Ha1 of the first layer A1 and the height Ha3 of the third layer A3. The aforementioned height and thickness can have the same meaning.

[0157] In some embodiments, the height Ha1 of the first layer A1 and the height Ha3 of the third layer A3 can be in the range of about 20 angstroms to about 70 angstroms, and the height Ha2 of the second layer A2 can be in the range of about 100 angstroms to about 200 angstroms.

[0158] The height Hb2 of the second layer B2 included in the second semiconductor layer ACT2 can be greater than the height Hb1 of the first layer B1 and the height Hb3 of the third layer B3.

[0159] In some embodiments, the heights Hb1 of the first layer B1 and Hb3 of the third layer B3 can be in the range of about 20 angstroms to about 70 angstroms, and the height Hb2 of the second layer B2 can be in the range of about 100 angstroms to about 200 angstroms.

[0160] In the display panel 110A according to an embodiment, the first semiconductor layer ACT1 includes a first layer A1, a second layer A2, and a third layer A3 with different ranges of indium (In) content, and the second semiconductor layer ACT2 includes a first layer B1, a second layer B2, and a third layer B3 with different ranges of indium (In) content, thereby providing a high mobility (e.g., at approximately 60 cm⁻¹). 2 Oxide semiconductors with electron mobility in the range of / Vs or higher and an appropriate threshold voltage (e.g., about -2.0V or higher).

[0161] In the display panel 110A according to the embodiment, since the semiconductor layer SCL is formed using a high-mobility oxide semiconductor, the pixel transistor Tpx can be formed at microscale (e.g., including the dimensions of a semiconductor layer having a width and / or length in the range of about a few micrometers to about tens of micrometers) while obtaining the mobility characteristics of the pixel transistor Tpx. Therefore, even in a high-resolution display device with a relatively narrow pixel area, the display panel 110A allows for easy arrangement and / or formation of the pixel transistor Tpx while obtaining the device characteristics and / or operational characteristics of the pixel transistor Tpx.

[0162] Figure 7 According to yet another embodiment Figure 4 An enlarged schematic cross-sectional view of region A.

[0163] Combination Figures 1 to 6 Reference Figure 7 The semiconductor layer SCL of the display panel 110B according to the disclosed embodiments may have a different shape than the semiconductor layer SCL of the display panel 110A. The following description will focus on the differences and redundant descriptions will be omitted.

[0164] The first semiconductor layer ACT1 included in the semiconductor layer SCL of the display panel 110B may include a first layer A1, a second layer A2, and a third layer A3 stacked on a third-direction D3, aligned with the first channel region CH1. For example, the first semiconductor layer ACT1 included in the semiconductor layer SCL of the display panel 110B may not include the first layer A1, the second layer A2, or the third layer A3 in the first drain region DR1 or the first source region SR1. In embodiments, the first layer A1 and the third layer A3 may not be disposed in the first source region SR1 or the first drain region DR1.

[0165] The first layer A1, the second layer A2, and the third layer A3 included in the first semiconductor layer ACT1 of the display panel 110B may have the same structure and material properties as the first layer A1, the second layer A2, and the third layer A3 included in the first semiconductor layer ACT1 of the display panel 110A. Redundant descriptions will be omitted.

[0166] The first semiconductor layer ACT1 disposed in the first drain region DR1 and the first source region SR1 of the display panel 110B may contain the same material as the first layer A1 and / or the third layer A3 disposed in the first channel region CH1. For example, the first semiconductor layer ACT1 disposed in the first drain region DR1 and the first source region SR1 of the display panel 110B may be an oxide semiconductor containing at least one of gallium (Ga), zinc (Zn), and tin (Sn) in a content of about 30 at% to about 75 at% of indium (In). For example, the first semiconductor layer ACT1 disposed in the first drain region DR1 and the first source region SR1 may include indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO).

[0167] The first semiconductor layer ACT1 disposed in the first drain region DR1 and the first source region SR1 of the display panel 110B can be formed by the same process as the first layer A1 disposed in the first channel region CH1, or it can be formed by the same process as the third layer A3 disposed in the first channel region CH1.

[0168] The second semiconductor layer ACT2 included in the semiconductor layer SCL of the display panel 110B may include a first layer B1, a second layer B2, and a third layer B3 stacked on each other in the third direction D3 in the second channel region CH2. However, the second semiconductor layer ACT2 included in the semiconductor layer SCL of the display panel 110B may not include the first layer B1, the second layer B2, or the third layer B3 in the second drain region DR2 or the second source region SR2.

[0169] The first layer B1, the second layer B2, and the third layer B3 included in the second semiconductor layer ACT2 of the display panel 110B can have the same structure and material properties as the first layer A1, the second layer A2, and the third layer A3 included in the first semiconductor layer ACT1 of the display panel 110B, respectively. Redundant descriptions will be omitted.

[0170] The second semiconductor layer ACT2 disposed in the second drain region DR2 and the second source region SR2 of the display panel 110B may comprise the same material as the first layer B1 and / or the third layer B3 disposed in the second channel region CH2. For example, the second semiconductor layer ACT2 disposed in the second drain region DR2 and the second source region SR2 of the display panel 110B may be an oxide semiconductor comprising at least one of gallium (Ga), zinc (Zn), and tin (Sn) in a content of about 30 at% to about 75 at% of indium (In). For example, the second semiconductor layer ACT2 disposed in the second drain region DR2 and the second source region SR2 may comprise indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO).

[0171] The second semiconductor layer ACT2 disposed in the second drain region DR2 and the second source region SR2 of the display panel 110B can be formed by the same process as the first layer B1 disposed in the second channel region CH2, or it can be formed by the same process as the third layer B3 disposed in the second channel region CH2.

[0172] The gate insulator GI included in display panel 110B may have the same structure and material properties as the gate insulator GI included in display panel 110A. Redundant descriptions will be omitted.

[0173] In the display panel 110B according to this embodiment, the first semiconductor layer ACT1 includes a first layer A1, a second layer A2, and a third layer A3 with different ranges of indium (In) content disposed in the first channel region CH1, and the second semiconductor layer ACT2 includes a first layer B1, a second layer B2, and a third layer B3 with different ranges of indium (In) content disposed in the second channel region CH2, thereby providing a high mobility (e.g., at approximately 60 cm⁻¹). 2 Oxide semiconductors with electron mobility in the range of / Vs or higher and an appropriate threshold voltage (e.g., about -2.0V or higher).

[0174] Figure 8 It spans Figure 2 The display area and non-display area in the diagram show a schematic cross-sectional view of the display panel.

[0175] Combination Figures 1 to 7 Reference Figure 8The structure of the display panel 110 in the display area DA can be the same as described above. In the following text, the structure of the display panel 110 in the non-display area NDA will be described instead of the structure of the display panel 110 in the display area DA.

[0176] According to the disclosed embodiments, the display panel 110 may include a driving circuit region DRA in the non-display area NDA. The display panel 110 according to the embodiments may include a driver transistor Tdr provided or disposed in the driving circuit region DRA.

[0177] According to an embodiment, the driver transistor Tdr can be disposed in a stage region located in the drive circuit region DRA (e.g., a stage region where a stage circuit of a shift register forming the first driver 120 is disposed). In the following description, the driver transistor Tdr is used as an example. Figure 8 The diagram shows a driver transistor Tdr, which will be referred to as the third transistor T3.

[0178] According to an embodiment, the third transistor T3 may include a semiconductor layer SCL, a second conductive layer CDL2, and a third conductive layer CDL3. For example, the third transistor T3 may include a third semiconductor layer ACT3 of the semiconductor layer SCL, a third gate electrode GE3 of the second conductive layer CDL2, and a third drain electrode DE3 and a third source electrode SE3 of the third conductive layer CDL3. Although the third transistor T3 does not include the first conductive layer CDL1 in the figures, the disclosure is not limited thereto. In some embodiments, the third transistor T3 may include the first conductive layer CDL1.

[0179] According to an embodiment, the third semiconductor layer ACT3 can be disposed between the buffer layer BFL and the interlayer dielectric layer ILD. For example, the third semiconductor layer ACT3 can be disposed on the buffer layer BFL and can be covered by the third gate insulator GI3 and the interlayer dielectric layer ILD. The third semiconductor layer ACT3 located in the non-display area NDA can be disposed in the same layer as the first semiconductor layer ACT1 and the second semiconductor layer ACT2 located in the display area DA.

[0180] The third semiconductor layer ACT3 may include: a third channel region CH3, stacked on the third direction D3 with a third gate electrode GE3; and a third source region SR3 and a third drain region DR3, spaced apart from each other in a direction parallel to the substrate SUB, with the third channel region CH3 located between the third source region SR3 and the third drain region DR3. For example, the third source region SR3 and the third drain region DR3 may be located at opposite ends of the third channel region CH3. The third channel region CH3 may be non-conductive and may maintain semiconductor properties, while the third source region SR3 and the third drain region DR3 may be conductive regions.

[0181] The third semiconductor layer ACT3 can be stacked on the third-direction D3 with the third gate electrode GE3. The third semiconductor layer ACT3 may comprise the same oxide semiconductor as the first semiconductor layer ACT1 and / or the second semiconductor layer ACT2, and may be formed together with the first semiconductor layer ACT1 and / or the second semiconductor layer ACT2. The first semiconductor layer ACT1, the second semiconductor layer ACT2, and the third semiconductor layer ACT3 may have the same structure and characteristics. A more detailed description is given below.

[0182] According to an embodiment, the third gate electrode GE3, included in the second conductive layer CDL2, can be disposed between the third gate insulator GI3 and the interlayer dielectric layer ILD. For example, the third gate electrode GE3 can be positioned on the third gate insulator GI3 and can be covered by the interlayer dielectric layer ILD. The third gate electrode GE3 positioned in the non-display area NDA can be disposed in the same layer as the first gate electrode GE1 and the second gate electrode GE2 positioned in the display area DA.

[0183] The third gate electrode GE3 can be disposed on the third semiconductor layer ACT3, such that the third gate electrode GE3 is stacked with the third channel region CH3. The third gate electrode GE3 and the third semiconductor layer ACT3 can be spaced apart from each other, and the third gate insulator GI3 is located between the third gate electrode GE3 and the third semiconductor layer ACT3.

[0184] According to an embodiment, the third drain electrode DE3 and the third source electrode SE3, included in the third conductive layer CDL3, can be positioned between the interlayer dielectric layer ILD and the first passivation layer PSV1. For example, the third drain electrode DE3 and the third source electrode SE3 can be positioned on the interlayer dielectric layer ILD and covered by the first passivation layer PSV1. The third drain electrode DE3 and the third source electrode SE3 positioned in the non-display area NDA can be disposed in the same layer as the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2 positioned in the display area DA.

[0185] The third drain electrode DE3 can be electrically connected to the third drain region DR3 through at least one contact hole penetrating the interlayer dielectric layer ILD, and the third source electrode SE3 can be electrically connected to the third source region SR3 through at least one contact hole penetrating the interlayer dielectric layer ILD. According to another embodiment, the third transistor T3 may not include separate drain and / or source electrodes, and the third drain region DR3 and / or the third source region SR3 of the third semiconductor layer ACT3 can be electrically connected to other circuit elements, lines, and / or conductive patterns to function as the drain and / or source electrodes of the third transistor T3.

[0186] According to an embodiment, the third gate insulator GI3 may comprise the same material as the first gate insulator GI1 and / or the second gate insulator GI2, and may be formed together with the first gate insulator GI1 and / or the second gate insulator GI2. For example, the first gate insulator GI1, the second gate insulator GI2, and the third gate insulator GI3 may comprise the same insulating material (e.g., silicon oxide) and may be formed to have substantially equivalent or similar film quality. A more detailed description is given below.

[0187] According to the embodiment, the third transistor T3 can be covered by the first passivation layer PSV1, the second passivation layer PSV2, and the encapsulation layer ENL, and thus can protect the circuit elements and lines disposed in the panel circuit layer PCL from the effects of moisture penetration, etc. Other redundant descriptions will be omitted.

[0188] Figure 9 yes Figure 8 Enlarged schematic cross-sectional view of region C.

[0189] Reference Figure 9 The third semiconductor layer ACT3 in the non-display area NDA may include a first layer C1, a second layer C2, and a third layer C3 stacked on top of each other on the third direction D3. The first layer C1, the second layer C2, and the third layer C3 may be positioned such that the first layer C1, the second layer C2, and the third layer C3 are disposed in the third source region SR3, the third drain region DR3, and the third channel region CH3.

[0190] The first layer C1, the second layer C2, and the third layer C3 included in the third semiconductor layer ACT3 can have the same structure and characteristics as the first layer A1, the second layer A2, and the third layer A3 included in the first semiconductor layer ACT1, respectively. The first layer C1 can be in contact with the buffer layer BFL, the third layer C3 can be in contact with the third gate insulator GI3, and the second layer C2 can be positioned on the third direction D3 between the first layer C1 and the third layer C3.

[0191] According to an embodiment, the first layer C1 may comprise indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO) containing about 30 at% to about 75 at% indium (In), the second layer C2 may comprise indium tin gallium zinc oxide (ITGZO) containing about 30 at% to about 75 at% indium (In), and the third layer C3 may comprise the same material as the first layer C1. That is, the third layer C3 may comprise indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO) containing about 30 at% to about 75 at% indium (In).

[0192] According to the disclosed embodiments, the indium (In) content in the second layer C2 can be greater than the indium (In) content in the first layer C1 and the third layer C3. For example, the indium (In) content in the first layer C1 and the third layer C3 can be in the range of about 30 at% to about 40 at%, and the indium (In) content in the second layer C2 can be in the range of about 65 at% to about 70 at%.

[0193] According to the disclosed embodiments, a third gate insulator GI3 can be disposed on the third layer C3 of the third semiconductor layer ACT3. The third gate insulator GI3 can have the same structure and material as the first gate insulator GI1 described above. In the third gate insulator GI3, the amount of nitric oxide (NO) released can be approximately 2.5E+18 mol / cm³. 3 Or even less, the amount of hydrogen (H2) released could be approximately 3E+19 mol / cm³. 3 Or even less, and the amount of oxygen (O2) released could be approximately 2.76E+19 mol / cm³. 3 Or smaller.

[0194] In the display panel 110A according to the embodiment, the electrical characteristics of the third transistor T3 can be stabilized by controlling the concentrations of nitric oxide (NO), hydrogen (H2), and / or oxygen (O2) released from the third gate insulator GI3. Further redundant descriptions will be omitted.

[0195] In some embodiments, the height Hc1 of the first layer C1 and the height Hc3 of the third layer C3 can be in the range of about 20 angstroms to about 70 angstroms, and the height Hc2 of the second layer C2 can be in the range of about 100 angstroms to about 200 angstroms.

[0196] Figure 10 According to yet another embodiment Figure 8 Enlarged schematic cross-sectional view of region C.

[0197] Reference Figure 10 The third semiconductor layer ACT3 of the display panel 110B in the non-display area NDA may include a first layer C1, a second layer C2, and a third layer C3 stacked on top of each other on the third direction D3. It should be noted that the third semiconductor layer ACT3 included in the display panel 110B may not include the first layer C1, the second layer C2, or the third layer C3 in the third drain area DR3 or the third source area SR3.

[0198] The first layer C1, the second layer C2, and the third layer C3 included in the display panel 110B and aligned with the third channel region CH3 can be respectively connected to the first layer C1, the second layer C2, and the third layer C3 included in the display panel 110B. Figure 9The first layer C1, the second layer C2, and the third layer C3 in the third semiconductor layer ACT3 of the display panel 110A have the same structure and material properties. Redundant descriptions will be omitted.

[0199] The third semiconductor layer ACT3 disposed in the third drain region DR3 and the third source region SR3 of the display panel 110B may contain the same material as the first layer C1 and / or the third layer C3 disposed in the third channel region CH3. For example, the third semiconductor layer ACT3 disposed in the third drain region DR3 and the third source region SR3 of the display panel 110B may include indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO) containing indium (In) in a content of about 30 at% to about 75 at% and containing at least one of gallium (Ga), zinc (Zn) and tin (Sn).

[0200] The third semiconductor layer ACT3 disposed in the third drain region DR3 and the third source region SR3 of the display panel 110B can be formed by the same process as the first layer C1 disposed in the third channel region CH3, or it can be formed by the same process as the third layer C3 disposed in the third channel region CH3.

[0201] In the non-display area NDA, the third gate insulator GI3 included in the display panel 110B can be combined with the third gate insulator GI3 included in the display panel 110B. Figure 9 The third gate insulator GI3 in the display panel 110A has the same structure and material properties. Redundant descriptions will be omitted.

[0202] In the display panel 110B according to an embodiment, the third semiconductor layer ACT3 includes a first layer C1, a second layer C2, and a third layer C3 disposed in the first channel region CH1 with different ranges of indium (In) content, thereby providing a high mobility (e.g., at approximately 60 cm⁻¹). 2 Oxide semiconductors with electron mobility in the range of / Vs or higher and an appropriate threshold voltage (e.g., about -2.0V or higher).

[0203] Figures 11 to 19 This shows the diagram used for manufacturing. 4 A schematic cross-sectional view of the processing steps of the pixel transistor shown. Figures 11 to 19 The sequence shows the manufacturing process. Figure 4 In the step of forming pixel transistors Tpx on the substrate SUB in the display panel 110 process, wherein, Figure 14 An example is shown. Figure 13 An enlarged schematic cross-sectional view of region M.

[0204] Reference Figure 11 and Figure 12A substrate SUB including a display area DA can be formed, and a barrier layer BRL can then be formed on the substrate SUB. In this process, the display area DA of the substrate SUB may include a pixel area PXA, and the barrier layer BRL can be formed via a film formation process (e.g., a deposition process) using an insulating film employing at least one of the insulating materials listed above (e.g., an inorganic insulating material). The materials and / or methods used to form the barrier layer BRL may vary depending on the embodiments.

[0205] Subsequently, a first conductive layer CDL1 can be formed on the barrier layer BRL. The first conductive layer CDL1 may include a first bottom electrode BG1 and a second bottom electrode BG2. The first bottom electrode BG1 and the second bottom electrode BG2 can be formed in the pixel region PXA and can be spaced apart from each other.

[0206] The first bottom electrode BG1 and the second bottom electrode BG2 can be formed via a conductive film formation process (e.g., deposition process) and a conductive film patterning process (e.g., etching process using a mask). The materials and / or methods used to form the first bottom electrode BG1 and the second bottom electrode BG2 may vary depending on the embodiment.

[0207] Subsequently, a buffer layer BFL covering the first conductive layer CDL1 can be formed. The buffer layer BFL can be formed via a deposition process that forms a film of at least one of the insulating materials listed above (e.g., an inorganic insulating material). The materials and / or methods used to form the buffer layer BFL can vary depending on the embodiments.

[0208] Subsequently, referring to Figures 13 to 15 A semiconductor layer SCL is formed on the buffer layer BFL. The semiconductor layer SCL can be formed via a sputtering deposition process. The semiconductor layer SCL may include a first semiconductor layer ACT1 and a second semiconductor layer ACT2.

[0209] The semiconductor layer SCL can be positioned to be stacked on the third-direction D3 with the first conductive layer CDL1. The first semiconductor layer ACT1 can be stacked on the third-direction D3 with the first bottom electrode BG1, and the second semiconductor layer ACT2 can be stacked on the third-direction D3 with the second bottom electrode BG2.

[0210] In this process, the first semiconductor layer ACT1 may include the first layer A1, the second layer A2, and the third layer A3 stacked on top of each other in the order of first layer A1, second layer A2, and third layer A3. As described above, the first layer A1 and the third layer A3 may include indium gallium zinc oxide (IGZO) or indium tin gallium oxide (ITGO), and the second layer A2 may include indium tin gallium zinc oxide (ITGZO).

[0211] Different indium (In) contents in the first layer A1, the second layer A2, and the third layer A3 can be obtained by controlling the indium (In) ratio of the sputtering target from about 30 at% to about 75 at% in the manufacturing process, thereby forming the first layer A1, the second layer A2, and the third layer A3 with different indium (In) contents.

[0212] The second semiconductor layer ACT2 may include a first layer B1, a second layer B2, and a third layer B3 stacked on top of each other in the order of a first layer B1, a second layer B2, and a third layer B3. The first layer B1 of the second semiconductor layer ACT2 may be formed together with the first layer A1 of the first semiconductor layer ACT1, the second layer B2 of the second semiconductor layer ACT2 may be formed together with the second layer A2 of the first semiconductor layer ACT1, and the third layer B3 of the second semiconductor layer ACT2 may be formed together with the third layer A3 of the first semiconductor layer ACT1.

[0213] Accordingly, the first layer B1, the second layer B2, and the third layer B3 included in the second semiconductor layer ACT2 may have the same structure and material properties as the first layer A1, the second layer A2, and the third layer A3 included in the first semiconductor layer ACT1. Redundant descriptions will be omitted.

[0214] In this process, the semiconductor layer SCL of the display panel 110 can include various structures depending on the process conditions. For example, the display panel 110 can have the shape of a display panel 110A in which the first semiconductor layer ACT1 is formed across the first region AA1, the second region AA2, and the third region AA3, consisting of the first layer A1, the second layer A2, and the third layer A3, or the shape of a display panel 110B in which the first layer A1, the second layer A2, and the third layer A3 are formed only in the first region AA1.

[0215] In this process, the first region AA1 can refer to... Figure 18 The first channel region CH1 is the same part, and the second region AA2 can refer to the same part. Figure 18 The first leak zone DR1 is the same part, and the third zone AA3 can refer to the same part. Figure 18 The second semiconductor layer ACT2 is the same portion as the first semiconductor layer ACT1, although not shown in the figures.

[0216] In the following text, the structure of display panel 110A will be used as an example to describe the subsequent processes of display panel 110.

[0217] Reference Figure 15A gate insulator GI can be formed on the semiconductor layer SCL. The gate insulator GI can contact the first semiconductor layer ACT1 and the second semiconductor layer ACT2, and can cover (e.g., completely cover) the first semiconductor layer ACT1 and the second semiconductor layer ACT2. The gate insulator GI can include silicon oxide.

[0218] This process can be performed by controlling at least one of deposition pressure, deposition power, distance between the deposition apparatus and the target substrate, and flow rate ratio of the deposition gas in order to control the film quality of the gate insulator GI.

[0219] Therefore, the amount of nitric oxide (NO) released in the gate insulator GI during this process can be approximately 2.5E+18 mol / cm³. 3 Or even less, the amount of hydrogen (H2) released could be approximately 3E+19 mol / cm³. 3 Or even less, and the amount of oxygen (O2) released could be approximately 2.76E+19 mol / cm³. 3 Or smaller.

[0220] Subsequently, referring to Figures 16 to 18 A second conductive layer CDL2, including a first gate electrode GE1 and a second gate electrode GE2, can be formed on the gate insulator GI. In this process, the first gate electrode GE1 can be stacked on the third-direction D3 with the first semiconductor layer ACT1, and the second gate electrode GE2 can be stacked on the third-direction D3 with the second semiconductor layer ACT2.

[0221] In this process, the same conductive material can be used to form the first gate electrode GE1 and the second gate electrode GE2 together. For example, the first gate electrode GE1 and the second gate electrode GE2 can be formed together via a process of forming a conductive film using at least one of the conductive materials listed above and a process of patterning the conductive film. The materials and / or methods used to form the first gate electrode GE1 and the second gate electrode GE2 may vary depending on the embodiment.

[0222] Subsequently, the gate insulator GI can be etched to have a shape conformal to each of the first gate electrode GE1 and the second gate electrode GE2. This process can be performed using separate masks, or the first gate electrode GE1 and the second gate electrode GE2 can be used as masks to etch the gate insulator GI.

[0223] This process allows for the separate formation of a first gate insulator GI1 aligned with the first gate electrode GE1 and a second gate insulator GI2 aligned with the second gate electrode GE2. For example, the first gate insulator GI1 can be formed on a portion of the first semiconductor layer ACT1 aligned with the first gate electrode GE1, and can have a shape and / or size corresponding to the shape and / or size of the first gate electrode GE1. The second gate insulator GI2 can be formed on a portion of the second semiconductor layer ACT2 aligned with the second gate electrode GE2, and can have a shape and / or size corresponding to the shape and / or size of the second gate electrode GE2.

[0224] In this process, each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can be divided into multiple regions with different characteristics. For example, a portion of the first semiconductor layer ACT1 that is superimposed on the first gate electrode GE1 in the third direction D3 can serve as the first channel region CH1, the side of the first semiconductor layer ACT1 that is not superimposed on the first gate electrode GE1 in the third direction D3 can serve as the first source region SR1, and the opposite side of the first semiconductor layer ACT1 that is not superimposed on the first gate electrode GE1 in the third direction D3 can serve as the first drain region DR1.

[0225] For example, in this process, oxygen vacancies may appear in the first drain region DR1 and the first source region SR1 of the first semiconductor layer ACT1. Therefore, the first semiconductor layer ACT1 can be divided into a first drain region DR1, a first source region SR1, and a first channel region CH1 with different characteristics. In some embodiments, oxygen vacancies may even diffuse into a portion of the first channel region CH1 that is superimposed with the first gate electrode GE1.

[0226] Similarly, the portion of the second semiconductor layer ACT2 that overlaps with the second gate electrode GE2 can be defined as the second channel region CH2, and the two ends of the second channel region CH2 can be divided into the second source region SR2 and the second drain region DR2.

[0227] In this process, oxygen vacancies may occur in the second drain region DR2 and the second source region SR2 of the second semiconductor layer ACT2, and accordingly, the second semiconductor layer ACT2 can be divided into a second drain region DR2, a second source region SR2 and a second channel region CH2 with different properties.

[0228] Subsequently, an interlayer dielectric layer (ILD) covering the semiconductor layer SCL, the second conductive layer CDL2, and the gate insulator GI can be formed. The interlayer dielectric layer (ILD) can be formed via a process that uses at least one of the insulating materials listed above (e.g., an inorganic insulating material) to form an insulating film. The materials and / or methods used to form the interlayer dielectric layer (ILD) can vary depending on the embodiment.

[0229] In this process, hydrogen gas can be introduced into the first semiconductor layer ACT1 and the second semiconductor layer ACT2. Therefore, through this process, the oxygen vacancy portions of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can become conductive (e.g., become n-type). The first drain region DR1 and the first source region SR1 of the first semiconductor layer ACT1, and the second drain region DR2 and the second source region SR2 of the second semiconductor layer ACT2 can become conductive.

[0230] Subsequently, referring to Figure 19 Before forming the first drain electrode DE1, the first source electrode SE1, the second drain electrode DE2, and the second source electrode SE2, multiple contact holes can be formed in the interlayer dielectric layer ILD.

[0231] Subsequently, a first drain electrode DE1, a first source electrode SE1, a second drain electrode DE2, and a second source electrode SE2 can be formed on the interlayer dielectric layer ILD.

[0232] The first drain electrode DE1 and the first source electrode SE1 can be formed to be electrically connected to different portions of the first semiconductor layer ACT1. For example, the first drain electrode DE1 can be electrically connected to the first drain region DR1, and the first source electrode SE1 can be electrically connected to the first source region SR1. The second drain electrode DE2 and the second source electrode SE2 can be formed to be electrically connected to different portions of the second semiconductor layer ACT2. For example, the second drain electrode DE2 can be electrically connected to the second drain region DR2, and the second source electrode SE2 can be electrically connected to the second source region SR2. The second source electrode SE2 can be further electrically connected to the second bottom electrode BG2. Redundant descriptions will be omitted.

[0233] For example, a pixel transistor Tpx, including a first transistor T1 and a second transistor T2, can be formed in the display area DA.

[0234] The display device according to one embodiment of the present disclosure can be applied to various electronic devices. An electronic device according to one embodiment of the present disclosure includes the aforementioned display device, and may further include modules or devices with additional functions besides the display device.

[0235] Figure 20 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0236] Reference Figure 20 An electronic device 1 according to an embodiment of the present disclosure may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0237] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0238] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, which can process the received signals and output image information through the display screen.

[0239] The power module 14 may include a power module (such as a power adapter or battery) and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1.

[0240] At least one of the components of an electronic device 1 according to an embodiment of the present disclosure may be included in a display device 10 according to an embodiment of the present disclosure. Additionally, some modules that are functionally included in a single module may be included in the display device 10, while other modules may be disposed separately from the display device 10. For example, the display device 10 may include a display module 11, and a processor 12, a memory 13, and a power module 14 may be disposed within the electronic device 1 as other devices besides the display device 10.

[0241] Figure 21 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0242] Reference Figure 21 Various electronic devices employing the display device 10 according to embodiments of the present disclosure may include not only image display electronic devices such as smartphones 10_1a, tablet PCs (personal computers) 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) that include display modules, and vehicle electronic devices 10_3 that include display modules (such as central information displays (CIDs) and interior mirror displays arranged on the dashboard, center instrument panel, and instrument cluster of a car).

[0243] Embodiments have been disclosed herein, and although terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure set forth in the appended claims.

Claims

1. A display device comprising: a substrate including a display region and a non-display region; a first transistor including a first semiconductor layer provided over the display region of the substrate and a first gate electrode provided over the first semiconductor layer; and a first gate insulator provided between the first semiconductor layer and the first gate electrode, wherein the first semiconductor layer includes a first layer and a second layer stacked over one another in a direction perpendicular to the substrate, an indium content of the second layer is higher than an indium content of the first layer, and a height of the first layer is lower than a height of the second layer. the first layer includes an oxide semiconductor including indium at a content of 30 at% to 40 at%, and the second layer includes an oxide semiconductor including indium at a content of 65 at% to 70 at%.

2. The display device according to claim 1, wherein the first layer includes indium gallium zinc oxide or indium tin gallium oxide, and the second layer includes indium tin gallium zinc oxide.

3. The display device according to claim 2, wherein the height of the first layer is in a range of 20 angstroms to 70 angstroms, and the height of the second layer is in a range of 100 angstroms to 200 angstroms.

4. The display device according to claim 3, wherein the second layer is in contact with the first gate insulator, 5. The display device according to claim 1, wherein wherein the first gate insulator includes silicon oxide. the first semiconductor layer includes a channel region superposed with the first gate insulator, and a source region and a drain region positioned at end portions of the channel region, and 6. The display device of claim 5, wherein, The amount of released nitrogen monoxide is 2.5E+18 moles / cm 3 or less, the amount of released hydrogen is 3E+19 moles / cm 3 and the amount of released oxygen is 2.76E+19 moles / cm 3 or less under a heat treatment condition at a temperature in the range of 50°C to 550°C in the first gate insulator.

7. The display device according to claim 1, wherein the first gate insulator is an insulating pattern exposing the drain region and the source region. the first layer and the second layer are positioned in the channel region, the source region, and the drain region.

8. The display device of claim 7, wherein, the first layer and the second layer are provided in the channel region, and the first layer and the second layer are not provided in the source region or the drain region.

9. The display device according to claim 7, wherein the first semiconductor layer further includes a third layer spaced apart from the first layer in the direction perpendicular to the substrate with the second layer interposed between the third layer and the first layer, 10. The display device according to claim 1, wherein the first layer and the third layer include the same material, and a height of the third layer is lower than the height of the second layer, wherein the height of the third layer is in a range of 20 angstroms to 70 angstroms.

11. The display device according to claim 1, further comprising: a second transistor provided over the non-display region of the substrate and including a second semiconductor layer and a second gate electrode provided over the second semiconductor layer; and a second gate insulator provided between the second semiconductor layer and the second gate electrode. the second semiconductor layer is provided in the same layer as the first semiconductor layer in the non-display region, and the second semiconductor layer includes a first sub-layer having the same material and height as the first layer, and a second sub-layer having the same material and height as the second layer, 12. The display device of claim 11, wherein, wherein the second semiconductor layer is provided in the non-display region, and further includes a third sub-layer spaced apart from the first sub-layer in the direction perpendicular to the substrate with the second sub-layer interposed between the third sub-layer and the first sub-layer.

13. A method for manufacturing a display device, the method comprising the steps of: ​ ​ forming a semiconductor layer over a substrate; forming a gate insulator over the semiconductor layer; and forming a gate electrode over the gate insulator, wherein the semiconductor layer includes a first layer, a second layer, and a third layer stacked one over another in the order of the first layer, the second layer, and the third layer, and an indium content of the first layer and an indium content of the third layer are lower than an indium content of the second layer.

14. The method of claim 13, wherein, the first layer, the second layer, and the third layer are stacked with the gate electrode and the gate insulator in a direction perpendicular to the substrate.

15. The method of claim 14, wherein, a height of the first layer and a height of the third layer are lower than a height of the second layer.

16. An electronic device, the electronic device comprising: a display device including a panel circuit layer provided over a substrate, the substrate including a display region and a non-display region, wherein the panel circuit layer includes: a first transistor including a first semiconductor layer provided over the display region of the substrate and a first gate electrode provided over the first semiconductor layer; and a first gate insulator provided between the first semiconductor layer and the first gate electrode, the first semiconductor layer includes a first layer and a second layer stacked one over another in a direction perpendicular to the substrate, and an indium content of the second layer is higher than an indium content of the first layer, and a height of the first layer is lower than a height of the second layer. 17.The electronic device of claim 16, wherein, the first layer includes an oxide semiconductor including indium at a content of 30 at% to 40 at%, and the second layer includes an oxide semiconductor including indium at a content of 65 at% to 70 at%. 18.The electronic device of claim 17, wherein, the first layer includes indium gallium zinc oxide or indium tin gallium oxide, and the second layer includes indium tin gallium zinc oxide. 19.The electronic device of claim 18, wherein, the height of the first layer is in a range of 20 angstroms to 70 angstroms, and the height of the second layer is in a range of 100 angstroms to 200 angstroms, wherein the first gate insulator includes silicon oxide. 20.The electronic device of claim 16, wherein, the electronic device is at least one of a smart watch, a mobile phone, a smartphone, a portable computer, a tablet personal computer, a watch phone, a car display, smart glasses, a portable multimedia player, a navigation system, an ultra-mobile computer, a head-mounted display device, a virtual reality device, a mixed reality device, and an augmented reality device.

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