Display device, adhesive member forming apparatus for display device, and electronic device including display device

Abstract

Disclosed are a display device, an adhesive member forming apparatus for the display device, and an electronic device including the display device. The display device includes: a substrate; a pixel electrode on the substrate; a light emitting layer on the pixel electrode; a common electrode on the light emitting layer; an encapsulation layer on the common electrode; a polarization layer on the encapsulation layer; an adhesive member on the polarizing layer; a cover window on the adhesive member; and a light blocking layer disposed between the polarizing layer and the cover window so as to be adjacent to the adhesive member, in which an angle defined between a side surface of the adhesive member facing the light blocking layer and a top surface of the adhesive member facing the cover window is 90 degrees to 135 degrees.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0086294 filed on July 1, 2024, and all benefits arising therefrom, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates to a display device capable of improving image quality, an adhesive member forming apparatus for the display device, and a method of manufacturing the display device. BACKGROUND

[0003] Since an organic light emitting diode ("OLED") display is self-emissive and does not require a separate light source as a liquid crystal display does, it can reduce its thickness and weight. In addition, the organic light emitting diode ("OLED") display has attracted attention as a next-generation display for televisions ("TVs"), monitors, and portable electronic devices due to its excellent characteristics such as relatively low power consumption, relatively high brightness, and relatively high response speed. SUMMARY

[0004] The disclosed features provide a display device capable of improving image quality, an adhesive member forming apparatus for the display device, and a method of manufacturing the display device.

[0005] In the disclosed embodiments, a display device is provided, the display device including: a substrate; a pixel electrode on the substrate; an emission layer on the pixel electrode; a common electrode on the emission layer; an encapsulation layer on the common electrode; a polarizing layer on the encapsulation layer; an adhesive member on the polarizing layer; a cover window on the adhesive member; and a light blocking layer disposed between the polarizing layer and the cover window adjacent to the adhesive member, wherein an angle defined between a side surface of the adhesive member facing the light blocking layer and a top surface of the adhesive member facing the cover window is 90 degrees to 135 degrees.

[0006] In the disclosed embodiments, an adhesive member forming apparatus for a display device is provided, the adhesive member forming apparatus including: a guide rail; a stage moving on the guide rail along the guide rail; an alignment device aligning a substrate on the stage; a curing device curing an adhesive member of the substrate; an inkjet printing device provided between the alignment device and the curing device and providing a raw material of the adhesive member onto the substrate; and a printed pattern providing device providing a first printed pattern corresponding to a middle adhesive layer of the adhesive member and a second printed pattern corresponding to a first peripheral adhesive layer of the adhesive member and a second peripheral adhesive layer of the adhesive member.

[0007] In the disclosed embodiment, a method of manufacturing a display device is provided, the method including the steps of: forming an intermediate adhesive layer surrounding a display region of a substrate on the substrate; curing the intermediate adhesive layer; forming a first peripheral adhesive layer and a second peripheral adhesive layer on a first side surface and a second side surface of the intermediate adhesive layer, respectively; and curing the intermediate adhesive layer, the first peripheral adhesive layer, and the second peripheral adhesive layer.

[0008] According to the disclosed display device, the adhesive member forming apparatus for the display device, and the method of manufacturing the display device, a top surface of an edge of the adhesive member can be planarized. Therefore, adhesion between the adhesive member and a cover window at the edge of the adhesive member can be improved. Therefore, a gap (e.g., an air gap) can be prevented from being defined between the adhesive member and the cover window at the edge of the adhesive member. As a result, a point defect can be prevented from being visually recognized around the edge of the adhesive member, so that image quality of the display device can be improved.

[0009] The disclosed effects are not limited to the above-described effects, and other effects not described herein will become apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The disclosed above and other advantages and features will become more apparent from the following detailed description of the disclosed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 is a perspective view illustrating an embodiment of a display device; Figure 2 is a layout view illustrating an embodiment of a display panel; Figure 3 is a block diagram illustrating an embodiment of a display device; Figure 4 is an equivalent circuit diagram illustrating an embodiment of a pixel; Figure 5 is a layout view illustrating an embodiment of a display region of Figure 2 in detail; Figure 6 is a cross-sectional view of a display panel taken along line II-II' of Figure 5 ; Figure 7 is a cross-sectional view of a display panel taken along line I-I' of Figure 2 ; Figure 8 is a schematic plan view of an embodiment of a display panel including an adhesive layer; Figure 9 is a cross-sectional view taken along line III-III' of Figure 8 ; Figure 10 is a schematic plan view of an embodiment of a display panel including an adhesive layer; Figure 11 is a cross-sectional view taken along the line IV-IV' of Figure 10 Figure 12 is a schematic view of an embodiment of an adhesive member forming apparatus for a display device; Figure 13 is a cross-sectional view taken along the line V-V' of Figure 12 Figures 14 to 31 is a diagram for describing an embodiment of a method of manufacturing a display device; Figure 32 is a plan view of a base disposed on a stage in Figures 16 to 21 Figure 33 is a cross-sectional view taken along the line VI-VI' of Figure 32 Figure 34 is a cross-sectional view of a base disposed on a stage in Figures 26 to 31 Figure 35 is a schematic plan view of an embodiment of a display panel including an adhesive member; Figure 36 is a cross-sectional view taken along the line VII-VII' of Figure 35 Figure 37 is a schematic plan view of an embodiment of a display panel including an adhesive member; Figure 38 is a cross-sectional view taken along the line VIII-VIII' of Figure 37 Figure 39 is a schematic plan view of an embodiment of a display panel including an adhesive member; Figure 40 is a schematic plan view of an embodiment of a display panel including an adhesive member; Figure 41 is a block diagram illustrating an electronic device according to an embodiment; and Figure 42 is a view illustrating an embodiment of the electronic device of Figure 41 implemented as a smart phone. DETAILED DESCRIPTION

[0011] The disclosed embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the application are shown. The application may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0012] ​​​​​​​It will also be understood that, when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. In the entire description throughout this specification, the same reference numerals indicate the same components. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0013] Although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the embodiments. An element described as "first" need not necessarily be "second", and vice versa. The terms "first", "second", etc. can also be used herein to distinguish different categories or sets of elements. For the sake of clarity, the terms "first", "second", etc. can be used herein to simply denote "first category (or set)" and "second category (or set)", respectively, as opposed to "first" and "second" element.

[0014] Features of various embodiments disclosed can be combined partially or entirely. As will be clear to those skilled in the art, various interactions and operations are technically possible. Various embodiments can be practiced individually or in combination.

[0015] Hereinafter, predetermined embodiments will be described with reference to the accompanying drawings.

[0016] Figure 1 is a perspective view showing an embodiment of a display device 10.

[0017] Referring to Figure 1 The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things ("IoT") devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players ("PMPs"), navigation devices, and ultra-mobile PCs ("UMPCs").

[0018] The display device 10 can be a light-emitting display device such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micro or nano light-emitting diode ("LED"). In the following description, it is assumed that the display device 10 is an organic light-emitting display device, but the disclosure is not limited thereto.

[0019] The display device 10 includes a display panel 100, multiple source drive circuits 200, multiple flexible circuit boards 300, a timing control circuit 400, a power supply circuit 500, and a circuit board 600.

[0020] In a planar view, the display panel 100 can be formed in a quadrilateral shape, for example, a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect can be rounded to have a predetermined curvature, or it can be a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral shape (e.g., a rectangular shape), and can be formed in other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 can be flat, but is not limited to this. In embodiments, the display panel 100 may include, for example, curved portions formed at the left and right ends and having a constant or varying curvature. In addition, the display panel 100 can be flexibly formed such that it can be bent, folded, rolled up.

[0021] The display panel 100 may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA. The substrate of the display panel 100 (e.g., Figure 6 and Figure 7 The SUB in the text can include the display area DA and the non-display area NDA.

[0022] The display area DA can occupy most of the display panel 100. The display area DA can be positioned at the center of the display panel 100. Multiple pixels PX (refer to...) Figure 3 (This can be set in the display area DA to display the image.)

[0023] The non-display area NDA can be an area where no image is displayed. The non-display area NDA can be an edge area of ​​the display panel 100. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be set to surround the display area DA.

[0024] Display pad (or "soldering pad") PD (reference) Figure 2 The display pad (PD) can be located in the non-display area NDA to connect to multiple flexible circuit boards 300. Figure 2 It can be set on one side edge of the display panel 100.

[0025] Each of the source drive circuits 200 may be formed as an integrated circuit (“IC”) and attached to a corresponding flexible circuit board 300, but the disclosure is not limited thereto. Each of the source drive circuits 200 may be attached to the display panel 100 by a chip-on-glass (“COG”) method, a chip-on-plastic (“COP”) method, or an ultrasonic bonding method.

[0026] Each of the multiple flexible circuit boards 300 can be placed on the display pad PD (see reference). Figure 2 The display pad PD is disposed on one side edge of the display panel 100. Each of the plurality of flexible circuit boards 300 can be attached to the display pad PD (see reference) using a conductive adhesive member such as an anisotropic conductive film. Figure 2 Therefore, multiple flexible circuit boards 300 can be electrically connected to the signal lines of the display panel 100. The multiple flexible circuit boards 300 can be flexible printed circuit boards or flexible films such as chips on a film.

[0027] The timing control circuit 400 can generate signals for controlling the scan drive circuits GDC1 and GDC2 (see reference). Figure 2 ), transmit driver circuits EDC1 and EDC2 (refer to Figure 2 The timing control signals for the timing of the source drive circuit 200 and the power supply circuit 500 are also included. The power supply circuit 500 can generate multiple power voltages for driving the display panel 100 based on the input power from an external source. Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (“IC”) and attached to the circuit board 600.

[0028] Circuit board 600 can be connected to one side of each of a plurality of flexible circuit boards 300. Circuit board 600 can be a rigid printed circuit board.

[0029] Figure 2 This is a layout diagram showing an embodiment of the display panel 100.

[0030] Reference Figure 2 The display panel 100 may include a display pad PD, a first scan drive circuit GDC1, a first transmit drive circuit EDC1, a second scan drive circuit GDC2, a second transmit drive circuit EDC2, and a dam area DAMA.

[0031] Display pads (PDs) can be disposed on one side edge of the display panel 100. Display pads (PDs) can be grouped into multiple groups. When the display device 10 includes, as shown in the example... Figure 1 When five flexible circuit boards 300 are shown, the display pads PD can be divided into five groups. Each display pad PD in each group can correspond one-to-one with a corresponding bump on the flexible circuit board 300. Therefore, each display pad PD in each group can be electrically connected to its corresponding flexible circuit board 300.

[0032] Some display pads (PDs) can be electrically connected to the data line DL located in the display area (DA) (see reference). Figure 3 Some other display pads (PDs) in the display pad PD can be electrically connected to the first scan drive circuit GDC1, the second scan drive circuit GDC2, the first transmit drive circuit EDC1, and the second transmit drive circuit EDC2. Some other display pads (PDs) in the display pad PD can be connected to the first power line VSL (see reference 1). Figure 4 A first electrical voltage is applied to the first power line VSL.

[0033] The first power line VSL can be configured to surround at least three sides of the display area DA. In one embodiment, the first power line VSL can be configured, for example, to surround the left, top, and right sides of the display area DA. In an alternative embodiment, the first power line VSL can be configured to surround the left, top, right, and bottom sides of the display area DA.

[0034] The first scan drive circuit GDC1 and the second scan drive circuit GDC2 can be electrically connected to the scan lines GIL, GCL, GWL, and GBL of the display area DA (see reference). Figure 3 The first scan drive circuit GDC1 can be disposed in the non-display area NDA on the first side (e.g., the left side) of the display panel 100. The second scan drive circuit GDC2 can be disposed in the non-display area NDA on the second side (e.g., the right side) of the display panel 100.

[0035] The first transmit driver circuit EDC1 and the second transmit driver circuit EDC2 can be electrically connected to the transmit control line EML of the display area DA (see reference). Figure 3 The first transmission drive circuit EDC1 can be disposed in the non-display area NDA on the first side (e.g., the left side) of the display panel 100. The second transmission drive circuit EDC2 can be disposed in the non-display area NDA on the second side (e.g., the right side) of the display panel 100.

[0036] The first scan drive circuit GDC1 can be disposed between the display area DA and the first transmit drive circuit EDC1. The first scan drive circuit GDC1 can be disposed closer to the display area DA than the first transmit drive circuit EDC1. In addition, the first transmit drive circuit EDC1 can be disposed closer to the first side edge of the display panel 100 than the first scan drive circuit GDC1.

[0037] The second scan drive circuit GDC2 can be disposed between the display area DA and the second transmit drive circuit EDC2. The second scan drive circuit GDC2 can be disposed closer to the display area DA than the second transmit drive circuit EDC2. In addition, the second transmit drive circuit EDC2 can be disposed closer to the second side edge of the display panel 100 than the second scan drive circuit GDC2.

[0038] The dam area DAMA may include at least one dam DAM1 and DAM2 (see reference). Figure 7 ), to prevent organic encapsulation layer TFE2 (refer to Figure 7 It overflows into the display pad PD. The dam area DAMA can be set to surround the display area DA.

[0039] The dam area DAMA can be located outside the first transmit drive circuit EDC1 and the second transmit drive circuit EDC2. The dam area DAMA can be located closer to the first side edge of the display panel 100 than the first transmit drive circuit EDC1. Alternatively, the dam area DAMA can be located closer to the second side edge of the display panel 100 than the second transmit drive circuit EDC2.

[0040] Figure 3 This is a block diagram illustrating an embodiment of the display device 10.

[0041] Reference Figure 3 The display area DA can include multiple pixels PX, multiple scan lines SL, multiple emission control lines EML, and multiple data lines DL.

[0042] Multiple pixels (PX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EML) can extend on the first direction DR1 and be arranged on the second direction DR2. Multiple data lines (DL) can extend on the second direction DR2 and be arranged on the first direction DR1. The multiple scan lines (SL) include multiple write scan lines (GWL), multiple control scan lines (GCL), multiple initialization scan lines (GIL), and multiple bias scan lines (GBL).

[0043] Each of the multiple pixels PX can be connected to any one of the following: write scan lines GWL, control scan lines GCL, initialization scan lines GIL, bias scan lines GBL, emission control lines EML, and data lines DL. Each of the multiple pixels PX can receive the data voltage from the data line DL according to the write scan signal of the write scan line GWL, and can emit light from its light-emitting element according to the data voltage.

[0044] The non-display area NDA includes a first scan drive circuit GDC1, a second scan drive circuit GDC2, a first transmit drive circuit EDC1, and a second transmit drive circuit EDC2.

[0045] Each of the first scan drive circuit GDC1 and the second scan drive circuit GDC2 may include a write scan drive circuit GWC, a control scan drive circuit GCC, an initialization scan drive circuit GIC, and a bias scan drive circuit GBC. Figure 3 The write scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, and the bias scan drive circuit GBC are shown arranged sequentially from the display area DA to the edge of the display panel 100, but the disclosure is not limited thereto.

[0046] The write scan driver circuit GWC can receive the write timing signal GWTS from the timing control circuit 400. The write scan driver circuit GWC can generate write scan signals according to the write timing signal GWTS and output them sequentially to the write scan line GWL.

[0047] The control scan drive circuit GCC can receive the control timing signal GCTS from the timing control circuit 400. The control scan drive circuit GCC can generate control scan signals according to the control timing signal GCTS and output them sequentially to the control scan line GCL.

[0048] The initialization scan drive circuit GIC can receive the initialization timing signal GITS from the timing control circuit 400. The initialization scan drive circuit GIC can generate initialization scan signals according to the initialization timing signal GITS and output them sequentially to the initialization scan line GIL.

[0049] The bias scan drive circuit GBC can receive the bias timing signal GBTS from the timing control circuit 400. The bias scan drive circuit GBC can generate bias scan signals according to the bias timing signal GBTS and output them sequentially to the bias scan line GBL.

[0050] Each of the first transmit drive circuit EDC1 and the second transmit drive circuit EDC2 can receive a transmit timing signal EMTS from the timing control circuit 400. Each of the first transmit drive circuit EDC1 and the second transmit drive circuit EDC2 can generate transmit control signals according to the transmit timing signal EMTS and output them sequentially to the transmit control line EML.

[0051] The data driving circuit 200G includes multiple source driving circuits 200. Each of the multiple source driving circuits 200 can receive digital video data DATA and a data timing signal DCS from the timing control circuit 400. Each of the multiple source driving circuits 200 converts the digital video data DATA into an analog data voltage according to the data timing signal DCS and outputs them to the data line DL. In this case, a pixel PX can be selected by writing a scan signal, and the analog data voltage can be supplied to the selected pixel PX.

[0052] The timing control circuit 400 can receive digital video data DATA and timing signals TS from an external source. Based on the timing signals TS, the timing control circuit 400 generates a write timing signal GWTS, a control timing signal GCTS, an initialization timing signal GITS, a bias timing signal GBTS, and a transmit timing signal EMTS. The timing control circuit 400 can output the write timing signal GWTS to the write scan driver circuit GWC, and can output the control timing signal GCTS to the control scan driver circuit GCC. Additionally, the timing control circuit 400 can output the initialization timing signal GITS to the initialization scan driver circuit GIC, and can output the bias timing signal GBTS to the bias scan driver circuit GBC. The timing control circuit 400 can output the transmit timing signal EMTS to the first transmit driver circuit EDC1 and the second transmit driver circuit EDC2. Furthermore, the timing control circuit 400 can output the digital video data DATA and the data timing signal DCS to the source driver circuit 200.

[0053] The power supply circuit 500 can generate multiple panel driving voltages based on an external power voltage. In an embodiment, for example, the power supply circuit 500 can generate a first power voltage VSS, a second power voltage VDD, a third power voltage VINT, a fourth power voltage VAINT, and a fifth power voltage VOB, and supply them to the display panel 100. The first power voltage VSS can be a relatively low potential voltage, and the second power voltage VDD can be a relatively high potential voltage. The third power voltage VINT can be a first initialization voltage, the fourth power voltage VAINT can be a second initialization voltage, and the fifth power voltage VOB can be a third initialization voltage. The third power voltage VINT, the fourth power voltage VAINT, and the fifth power voltage VOB can be voltages higher than the first power voltage VSS and lower than the second power voltage VDD.

[0054] Figure 4 This is an equivalent circuit diagram illustrating an embodiment of pixel PX.

[0055] Reference Figure 4 In this embodiment, the pixel PX can be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EML, and the data line DL.

[0056] The pixel PX in this embodiment includes a driving transistor DT, a switching element, a capacitor Cst, and a light-emitting element LE. The switching element may include the first to the seventh transistors T1, T2, T3, T4, T5, T6, and T7.

[0057] The driving transistor DT controls the source-drain current (hereinafter also referred to as the "drive current") based on the data voltage applied to the first gate electrode. The second gate electrode of the driving transistor DT can be connected to the second power line VDL and the second power voltage VDD (see reference). Figure 3 ) is applied to the second power line VDL.

[0058] The light-emitting element LE can be an organic light-emitting diode (OLED). The LE emits light through a driving current. The amount of light emitted by the LE is proportional to the driving current. The first electrode of the LE can be connected to the first electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6. The second electrode of the LE can be connected to the first power line VSL and the first power voltage VSS (see reference). Figure 3 An electric field is applied to the first electric field line VSL. The first electrode of the light-emitting element LE can be an anode electrode or a pixel electrode, and its second electrode can be a cathode electrode or a common electrode.

[0059] The first transistor T1 is turned on by a write scan signal that applies a gate on-state voltage to the write scan line GWL, and connects the data line DL to the first electrode of the driving transistor DT. Therefore, while the first transistor T1 is turned on, a data voltage can be applied to the first electrode of the driving transistor DT. The gate electrode of the first transistor T1 can be connected to the write scan line GWL, its first electrode can be connected to the data line DL, and its second electrode can be connected to the first electrode of the driving transistor DT.

[0060] The second transistor T2 is turned on by a control scan signal applied to the gate turn-on voltage of the control scan line GCL, and connects the second electrode and the first gate electrode of the driving transistor DT. While the second transistor T2 is turned on, the driving transistor DT can operate like a diode. The gate electrode of the second transistor T2 can be connected to the control scan line GCL, its first electrode can be connected to the second electrode of the driving transistor DT, and its second electrode can be connected to the first gate electrode of the driving transistor DT.

[0061] The third transistor T3 is turned on by an initialization scan signal applied to the gate turn-on voltage of the initialization scan line GIL, and connects the first gate electrode of the driving transistor DT to the third power line VIL. Simultaneously with the turn-on of the third transistor T3, the first gate electrode of the driving transistor DT can be initialized to the third power voltage VINT of the third power line VIL (see reference). Figure 3 The gate electrode of the third transistor T3 can be connected to the initialization scan line GIL, its first electrode can be connected to the first gate electrode of the driving transistor DT, and its second electrode can be connected to the third power line VIL.

[0062] The fourth transistor T4 is turned on by an emitter control signal applied to the emitter control line EML with a gate turn-on voltage, and connects the second power line VDL to the first electrode of the drive transistor DT. Simultaneously with the fourth transistor T4 being turned on, the second power voltage VDD (refer to...) of the second power line VDL... Figure 3 An electrode can be applied to the first electrode of the driving transistor DT. The gate electrode of the fourth transistor T4 can be connected to the emitter control line EML, its first electrode can be connected to the second power line VDL, and its second electrode can be connected to the first electrode of the driving transistor DT.

[0063] The fifth transistor T5 is turned on by an emission control signal applied to the emission control line EML with a gate turn-on voltage, and connects the second electrode of the driving transistor DT to the first electrode of the light-emitting element LE. Simultaneously with the fifth transistor T5 turned on, the drive current of the driving transistor DT can be supplied to the light-emitting element LE. The gate electrode of the fifth transistor T5 can be connected to the emission control line EML, its second electrode can be connected to the second electrode of the driving transistor DT, and its first electrode can be connected to the first electrode of the light-emitting element LE.

[0064] The sixth transistor T6 is turned on by a bias scan signal applied to the gate turn-on voltage of the bias scan line GBL, and connects the first electrode of the light-emitting element LE to the fourth power line VAIL. Simultaneously with the sixth transistor T6 being turned on, the first electrode of the light-emitting element LE can be initialized to the fourth power voltage VAINT of the fourth power line VAIL (see reference). Figure 3 The gate electrode of the sixth transistor T6 can be connected to the bias scan line GBL, its second electrode can be connected to the first electrode of the light-emitting element LE, and its first electrode can be connected to the fourth power line VAIL.

[0065] The seventh transistor T7 is turned on by a bias scan signal applied to the gate turn-on voltage of the bias scan line GBL, and connects the first electrode of the driving transistor DT to the fifth power line VOBL. Simultaneously with the seventh transistor T7 being turned on, the first electrode of the driving transistor DT can be initialized to the fifth power voltage VOB of the fifth power line VOBL (see reference). Figure 3 The gate electrode of the seventh transistor T7 can be connected to the bias scan line GBL, its first electrode can be connected to the first electrode of the driving transistor DT, and its second electrode can be connected to the fifth power line VOBL.

[0066] A capacitor Cst is formed between the first gate electrode of the driving transistor DT and the second power line VDL. One electrode of the capacitor Cst can be connected to the first gate electrode of the driving transistor DT, and its remaining (other) electrode can be connected to the second power line VDL.

[0067] The driving transistor DT, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layer of each of the driving transistors DT, T1, T4, T5, T6, and T7 can include or be composed of polysilicon. Furthermore, the driving transistors DT, T1, T4, T5, T6, and T7 can be turned on by a signal with a relatively low gate voltage.

[0068] Alternatively, the second transistor T2 and the third transistor T3 can be formed as n-type metal-oxide-semiconductor field-effect transistors. In this case, the active layer of each of the second transistor T2 and the third transistor T3 may include or be composed of oxide semiconductor. Furthermore, the second transistor T2 and the third transistor T3 can be turned on by a signal with a relatively high gate voltage.

[0069] Figure 5 It is shown in detail Figure 2 A layout diagram of an embodiment of the display area DA.

[0070] Reference Figure 5 Multiple unit pixels (UPXs) can be arranged in a matrix. A unit pixel (UPX) can include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) that are adjacent to each other.

[0071] The first pixel PX1 can provide first light through the first emission area ELU1, the second pixel PX2 can provide second light through the second emission area ELU2, and the third pixel PX3 can provide third light through the third emission area ELU3.

[0072] In an embodiment, the first light may be blue wavelength light, the second light may be green wavelength light, and the third light may be red wavelength light. In an embodiment, for example, the blue wavelength is a band of light whose main peak wavelength is in the range of about 370 nanometers (nm) to about 460 nm, the green wavelength is a band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength is a band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0073] Figure 5 The illustration shows a unit pixel UPX comprising three pixels, but the disclosure is not limited thereto. In embodiments, a unit pixel UPX may include, for example, four or more pixels. In embodiments, for example, when a unit pixel UPX comprises four pixels, a first emission region of a first pixel may provide a first light, a second emission region of a second pixel and a fourth emission region of a fourth pixel may each provide a second light, and a third emission region of a third pixel may provide a third light. In an alternative embodiment, a first emission region of a first pixel may provide a first light, a second emission region of a second pixel may provide a second light, a third emission region of a third pixel may provide a third light, and a fourth emission region of a fourth pixel may provide a fourth light. Here, the fourth light may be white light. Additionally, in each of the plurality of pixels PX, the first emission region of the first pixel, the second emission region of the second pixel, the third emission region of the third pixel, and the fourth emission region of the fourth pixel may be arranged in a stripe shape or a pentile pattern.® shape.

[0074] Figure 6 It is along Figure 5 The cross-sectional view of the display panel 100 taken by line II-II'. Figure 6 A cross-section of the display panel 100 is shown, which shows the first emission area ELU1, the second emission area ELU2, and the third emission area ELU3 of the display area DA.

[0075] Reference Figure 6 The substrate SUB may include, or be composed of, an insulating material such as glass or polymer resin.

[0076] The barrier film BR can be disposed on the substrate SUB. The barrier film BR is a film used to protect thin-film transistors TFT1 and TFT2 and the light-emitting layer EL from moisture that permeates through the moisture-permeable substrate SUB. The barrier film BR can be formed as multiple inorganic layers stacked alternately.

[0077] The first thin-film transistor TFT1 can be disposed on the barrier film BR. The first thin-film transistor TFT1 can be... Figure 4 Either the fifth transistor T5 or the sixth transistor T6 shown. The first thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0078] The first active layer ACT1 of the first thin-film transistor TFT1 can be disposed on the barrier film BR. The first active layer ACT1 of the first thin-film transistor TFT1 may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon.

[0079] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region superimposed on the first gate electrode G1 on a third direction DR3, which is the thickness direction of the substrate SUB. The third direction DR3 may be defined as the thickness direction of the substrate SUB or the thickness direction of the display panel 100. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the opposite side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third direction DR3 that are not superimposed on the first gate electrode G1. The first source region S1 and the first drain region D1 may be regions that are conductive by using ion-doped semiconductor materials.

[0080] The first gate insulating layer 131 can be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1.

[0081] A first gate metal layer may be disposed on a first gate insulating layer 131. The first gate metal layer may include a first gate electrode G1 and a first capacitor electrode CAE1 of a first thin-film transistor TFT1. The first gate electrode G1 may be stacked on a third-direction DR3 with a first active layer ACT1.

[0082] The second gate insulating layer 132 can be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1.

[0083] A second gate metal layer may be disposed on the second gate insulating layer 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may be stacked on the third-direction DR3 with the first capacitor electrode CAE1. Since the second gate insulating layer 132 has a predetermined dielectric constant, the capacitor Cst ( Figure 4 It can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2 and a second gate insulating layer 132 disposed therebetween.

[0084] The first intermediate insulating layer 141 can be disposed on the second capacitor electrode CAE2.

[0085] The second thin-film transistor TFT2 can be disposed on the first intermediate insulating layer 141. The second thin-film transistor TFT2 can be Figure 4 Either the second transistor T2 or the third transistor T3 shown. The second thin-film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0086] The second active layer ACT2 of the second thin-film transistor TFT2 may be disposed on the first intermediate insulating layer 141. The second active layer ACT2 may include an oxide semiconductor. In embodiments, the second active layer ACT2 may include, for example, indium (In)-gallium (Ga)-zinc (Zn)-oxygen (O) (“IGZO”), indium (In)-gallium (Ga)-zinc (Zn)-tin (Sn)-oxygen (O) (“IGZTO”) or indium (In)-gallium (Ga)-tin (Sn)-oxygen (O) (“IGTO”).

[0087] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region on the third-direction DR3 that is superimposed on the second gate electrode G2. The second source region S2 may be located on one side of the second channel region CHA2, and the second drain region D2 may be located on the opposite side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions on the third-direction DR3 that are not superimposed on the second gate electrode G2. The second source region S2 and the second drain region D2 may be regions that are conductive by using ion-doped oxide semiconductors.

[0088] The third gate insulating layer 133 can be disposed on the second active layer ACT2 of the second thin film transistor TFT2.

[0089] The third gate metal layer may be disposed on the third gate insulating layer 133. The third gate metal layer may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be stacked on the third-direction DR3 with the second active layer ACT2.

[0090] The second intermediate insulating layer 142 can be disposed on the second gate electrode G2 of the second thin film transistor TFT2.

[0091] A first data metal layer may be formed on a second intermediate insulating layer 142. The first data metal layer may include a first connection electrode BE1, a second connection electrode BE2, and a third connection electrode BE3. The first connection electrode BE1 can be connected to the first drain region D1 of the first active layer ACT1 through a first connection hole BCT1 penetrating the first gate insulating layer 131, the second gate insulating layer 132, the first intermediate insulating layer 141, the third gate insulating layer 133, and the second intermediate insulating layer 142. The second connection electrode BE2 can be connected to the second source region S2 of the second active layer ACT2 through a second connection hole BCT2 penetrating the third gate insulating layer 133 and the second intermediate insulating layer 142. The third connection electrode BE3 can be connected to the second drain region D2 of the second active layer ACT2 through a third connection hole BCT3 penetrating the third gate insulating layer 133 and the second intermediate insulating layer 142.

[0092] A first organic layer 160 may be provided on the first connecting electrode BE1, the second connecting electrode BE2, and the third connecting electrode BE3 to planarize the step portion caused by the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0093] A second data metal layer may be disposed on the first organic layer 160. The second data metal layer may include a fourth connection electrode BE4. The fourth connection electrode BE4 may be connected to the first connection electrode BE1 through a fourth connection hole BCT4 penetrating the first organic layer 160.

[0094] The second organic layer 180 can be disposed on the fourth connecting electrode BE4.

[0095] The barrier film BR, the first gate insulating layer 131, the second gate insulating layer 132, the third gate insulating layer 133, the first intermediate insulating layer 141, and the second intermediate insulating layer 142 may include inorganic layers (e.g., silicon nitride (SiN)). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO)x ) or aluminum oxide (AlO x Or it may be composed of an inorganic layer (e.g., silicon nitride (SiN)). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x ))composition.

[0096] The first gate metal layer, the second gate metal layer, the third gate metal layer, the first data metal layer, and the second data metal layer may comprise a single layer or multiple layers, or be composed of a single layer or multiple layers. The single layer or multiple layers comprise any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any alloy thereof, or be composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any alloy thereof.

[0097] The first organic layer 160 and the second organic layer 180 may include or be composed of organic layers (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin).

[0098] Multiple light-emitting elements (LEs) and a dam 190 may be disposed on the second organic layer 180. Each of the multiple light-emitting elements (LEs) may include a pixel electrode (PXE), a light-emitting layer (EL), and a common electrode (CE). Each of the multiple light-emitting elements (LEs) is an element that emits light by recombination of holes from the pixel electrode (PXE) with electrons from the common electrode (CE) in the light-emitting layer (EL). Each of the multiple light-emitting elements (LEs) may be an organic light-emitting diode (OLED) in which the light-emitting layer (EL) comprises an organic light-emitting layer or is composed of an organic light-emitting layer, but the disclosure is not limited thereto.

[0099] A pixel electrode layer may be disposed on the second organic layer 180. The pixel electrode layer may include pixel electrodes PXE. Each of the pixel electrodes PXE can be connected to a fourth connection electrode BE4 through a pixel connection hole PCT penetrating the second organic layer 180. Each of the pixel electrodes PXE can be connected to a first source region S1 or a first drain region D1 of a first thin-film transistor TFT1 through a first connection electrode BE1 and a fourth connection electrode BE4. Therefore, a voltage controlled by the first thin-film transistor TFT1 can be applied to each of the pixel electrodes PXE. The pixel electrode layer may be formed as a single layer or multiple layers, said single layer or multiple layers comprising any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof, or composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

[0100] The dam 190 is used to define the first emission region to the third emission regions ELU1, ELU2, and ELU3 of the unit pixel UPX. For this purpose, the dam 190 can be formed to expose a portion of the pixel electrode PXE on the second organic layer 180. The dam 190 can cover the edges of the pixel electrode PXE.

[0101] Spacers 191 used to stably support the mask during the process of depositing the luminescent layer EL can be provided on the embankment 190.

[0102] The dam 190 and spacer 191 may include or be composed of organic layers (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin).

[0103] Each of the light-emitting layers (ELs) can be exposed without being covered by the dam 190 and can be disposed on its corresponding pixel electrode (PXE). Each of the light-emitting layers (ELs) can include an organic material and can emit predetermined light. In an embodiment, for example, the light-emitting layer (EL) of the first emitting region (ELU1) can emit a first light, the light-emitting layer (EL) of the second emitting region (ELU2) can emit a second light, and the light-emitting layer (EL) of the third emitting region (ELU3) can emit a third light. Each of the light-emitting layers (ELs) can include a hole transport layer, an organic material layer, and an electron transport layer.

[0104] A common electrode CE can be disposed on the light-emitting layer EL and the dam 190. The common electrode CE can be formed to cover the top surface of each of the light-emitting layers EL and the top surface of the dam 190. The common electrode CE can be commonly disposed throughout the entire display area DA. The common electrode CE can also be disposed in a portion of the non-display area NDA.

[0105] The common electrode CE may comprise a transparent conductive material (“TCO”) (such as indium tin oxide (“ITO” or indium zinc oxide (“IZO”)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)) that can transmit light in the top emitting structure, or may be composed of a transparent conductive material (“TCO”) (such as indium tin oxide (“ITO” or indium zinc oxide (“IZO”)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)) that can transmit light in the top emitting structure. When the common electrode CE comprises or is composed of a semi-transmissive conductive material, the light emission efficiency of each of the light-emitting elements LE can be increased due to the microcavity effect.

[0106] The encapsulation layer TFE can be formed on the common electrode CE. The encapsulation layer TFE may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting layer EL. Alternatively, the encapsulation layer TFE may include at least one organic layer to prevent voids from forming in at least one inorganic layer due to foreign matter such as dust.

[0107] The encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, an intermediate inorganic encapsulation layer 155, and a second inorganic encapsulation layer TFE3, which are stacked sequentially. The first inorganic encapsulation layer TFE1 may be disposed on the common electrode CE, the organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, the intermediate inorganic encapsulation layer 155 may be disposed on the organic encapsulation layer TFE2, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2.

[0108] The first inorganic encapsulation layer TFE1, the intermediate inorganic encapsulation layer 155, and the second inorganic encapsulation layer TFE3 may include or be composed of multiple films, silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and aluminum oxide (AlO) x One or more inorganic layers are alternately stacked in multiple films. The organic encapsulation layer TFE2 may include or be composed of organic layers (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin).

[0109] A polarizing layer (POL) can be disposed on the encapsulation layer TFE to prevent visibility degradation due to external light. The POL may include a first substrate component, a linear polarizer, a phase retardation film such as a quarter-wave plate (λ / 4 plate), and a second substrate component. The POL can be replaced by another antireflective layer, such as a color filter layer comprising multiple color filters.

[0110] The sensor electrode layer, including the sensor electrodes for detecting touch, can be disposed between the encapsulation layer TFE and the polarization layer POL.

[0111] The cover window CSUB can be placed on the polarizing layer POL. The cover window CSUB can be attached to the polarizing layer POL by an adhesive member ADL such as optically transparent resin (“OCR”).

[0112] The adhesive layer (ADL) can be positioned between the polarizing layer (POL) and the cover window (CSUB). The adhesive layer (ADL) can be a transparent adhesive layer.

[0113] Figure 7 It is along Figure 2 The sectional view of the display panel 100 taken by line I-I'. Figure 7 A cross-section of the display panel 100 is shown, which shows the non-display area NDA on the first side of the display panel 100.

[0114] Reference Figure 7 The transistors TR of the scan drive circuits GDC1 and GDC2 and the emitter drive circuits EDC1 and EDC2 can be disposed on the barrier film BR. Each transistor TR may include an active layer ACTE and a gate electrode GE. The active layer ACTE may include a channel region CHE, a source region SE, and a drain region DE. The active layer ACTE can be disposed on the barrier film BR. The gate electrode GE can be stacked on the third-direction DR3 with the channel region CHE and can be disposed on the first gate insulating layer 131.

[0115] The active layer ACTE can include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon.

[0116] The groove Gval penetrating the first organic layer 160 and the second organic layer 180 can be defined within the inorganic region VAL. Due to the inorganic region VAL, the first organic layer 160 and the second organic layer 180 adjacent to the edge of the first side of the display panel 100 can be separated from the first organic layer 160 and the second organic layer 180 adjacent to the display area DA. The first organic layer 160 and the second organic layer 180 can be cut off within the inorganic region VAL. Therefore, although oxygen or moisture permeates through the first organic layer 160 and the second organic layer 180 at the edge of the first side of the display panel 100, it prevents oxygen or moisture from being transmitted to the first organic layer 160 and the second organic layer 180 adjacent to the display area DA and affecting the light-emitting layer EL. In a plan view, the groove Gval can have a closed curve shape surrounding the display area DA.

[0117] The first data metal layer may further include a first electrical connection electrode VSCE1 and a second electrical connection electrode VSCE2. The first electrical connection electrode VSCE1 and the second electrical connection electrode VSCE2 may be disposed on the second intermediate insulating layer 142.

[0118] The first electrical connection electrode VSCE1 can be disposed in a groove Gval that penetrates the first organic layer 160 and the second organic layer 180. The groove Gval can have a V-shaped profile.

[0119] The second electrical connection electrode VSCE2 can be disposed in the dam region DAMA on the second intermediate insulating layer 142 that is exposed and not covered by the first organic layer 160.

[0120] The first power line VSL may include a first sub-power line SVSL1 and a second sub-power line SVSL2.

[0121] The first sub-electric line SVSL1 can be disposed on the first organic layer 160. The first sub-electric line SVSL1 can be connected to the first electrical connection electrode VSCE1 exposed in the groove Gval of the inorganic region VAL. The first sub-electric line SVSL1 can be disposed on the second electrical connection electrode VSCE2 in the dam region DAMA.

[0122] The second sub-electric line SVSL2 can be disposed on the second organic layer 180. The second sub-electric line SVSL2 can be disposed on the first sub-electric line SVSL1 in the groove Gval of the inorganic region VAL. The second sub-electric line SVSL2 can be disposed on the first sub-electric line SVSL1 in the dam region DAMA.

[0123] In an embodiment, for example, the second power connection electrode VSCE2, the first sub-power line SVSL1, and the second sub-power line SVSL2 can be stacked sequentially in the dam region DAMA.

[0124] The common electrode CE can be disposed on the dam 190 and the second organic layer 180 which is exposed and not covered by the dam 190. The common electrode CE can be connected to the second sub-electric line SVSL2 in the groove Gval of the inorganic region VAL. The common electrode CE can be disposed on the sidewall of the groove Gval of the inorganic region VAL. Therefore, when external light is incident on the groove Gval of the inorganic region VAL, the external light can be unpredictably diffusely reflected by the common electrode CE disposed on the sidewall of the groove Gval of the inorganic region VAL.

[0125] The first dam DAM1 and the second dam DAM2 can be set on the first power line VSL.

[0126] The first dam DAM1 and the second dam DAM2 can be structures that prevent the organic encapsulation layer TFE2 from overflowing to the edge of the first side of the display panel 100. The first dam DAM1 and the second dam DAM2 can be structures used to confine the organic encapsulation layer TFE2.

[0127] The first dam DAM1 may include a first subdam SDAM1_1, a second subdam SDAM2_1, and a third subdam SDAM3_1, which are sequentially stacked on the first power line VSL. The first subdam SDAM1_1 may include or be made of the same material as the second organic layer 180. The second subdam SDAM2_1 may include or be made of the same material as the dike 190. The third subdam SDAM3_1 may include or be made of the same material as the spacer 191.

[0128] The second sub-power line SVSL2 can be installed on the first sub-dam SDAM1_1 of the first dam DAM1. The second sub-power line SVSL2 can be configured to cover the first sub-dam SDAM1_1 of the first dam DAM1. In an embodiment, for example, the second sub-power line SVSL2 can be installed on the top and side surfaces of the first sub-dam SDAM1_1 of the first dam DAM1. The second sub-dam SDAM2_1 of the first dam DAM1 can be installed on the second sub-power line SVSL2.

[0129] The second dam DAM2 may include a first sub-dam SDAM1_2, a second sub-dam SDAM2_2, a third sub-dam SDAM3_2, and a fourth sub-dam SDAM4_2, sequentially stacked on the second intermediate insulation layer 142. The first sub-dam SDAM1_2 may include or be made of the same material as the first organic layer 160. The second sub-dam SDAM2_2 may include or be made of the same material as the second organic layer 180. The third sub-dam SDAM3_2 may include or be made of the same material as the dike 190. The fourth sub-dam SDAM4_2 may include or be made of the same material as the spacer 191.

[0130] The first sub-dam SDAM1_2 of the second dam DAM2 can be located on the second power connection electrode VSCE2. Additionally, the first sub-power line SVSL1 can be located on the first sub-dam SDAM1_2 of the second dam DAM2, and the second sub-dam SDAM2_2 of the second dam DAM2 can be located on the first sub-power line SVSL1. Furthermore, the second sub-power line SVSL2 can be located on the second sub-dam SDAM2_2 of the second dam DAM2, and the third sub-dam SDAM3_2 of the second dam DAM2 can be located on the second sub-power line SVSL2.

[0131] The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 can be in contact with each other outside the second dam DAM2, allowing for the formation of an inorganic encapsulation region IEA consisting only of inorganic layers. The organic layer is not disposed within the inorganic encapsulation region IEA. The display area DA can be surrounded by the inorganic encapsulation region IEA, preventing external oxygen or moisture from penetrating into the light-emitting layer EL of the display area DA. The inorganic encapsulation region IEA can be positioned adjacent to the edge of the first side of the display panel 100. The inorganic encapsulation region IEA can be positioned closer to the dam area DAMA than the inorganic region VAL.

[0132] The light-blocking layer BM can be disposed on one surface of the cover window CSUB. The light-blocking layer BM can be superimposed on the groove Gval of the inorganic region VAL on the third-direction DR3.

[0133] In an embodiment, the adhesive member ADL may include a first adhesive layer 710 (hereinafter, intermediate adhesive layer 710), a second adhesive layer 711 (hereinafter, first peripheral adhesive layer 711), and a third adhesive layer 712 (hereinafter, second peripheral adhesive layer 712). The construction of the adhesive member ADL will be described in detail below.

[0134] Figure 8This is a schematic plan view of the display panel 100 including the adhesive layer in the embodiment, and Figure 9 It is along Figure 8 The sectional view taken from line III-III'.

[0135] like Figure 8 and Figure 9 As shown, the adhesive member ADL can be disposed on the substrate SUB. In an embodiment, as... Figure 9 As shown, for example, the adhesive member ADL can be disposed on the polarizing layer POL to be superimposed on the substrate SUB.

[0136] The adhesive component ADL may include or be composed of a resin-containing material. The resin may be a liquid resin with viscosity. The resin may be a resin with light-transmitting properties; in some embodiments, the resin may be a photocurable resin or a thermosetting resin.

[0137] In an embodiment, for example, Figure 6 and Figure 7 The component between the substrate SUB and the polarization layer POL can also be set in Figure 9 Between the substrate SUB and the polarization layer POL.

[0138] The interior angle θ1 defined between the side surface SS2 and the top surface SS1 of the adhesive member ADL can be a right angle. In an embodiment, when the surface of the adhesive member ADL facing the light-blocking layer BM is defined as the side surface SS2 of the adhesive member ADL, and the surface of the adhesive member ADL facing the cover window CSUB is defined as the top surface SS1 of the adhesive member ADL, the interior angle θ1 defined between the side surface SS2 and the top surface SS1 of the adhesive member ADL can be, for example, 90 degrees to 135 degrees. In an embodiment, the aforementioned interior angle θ1 can be 90 degrees.

[0139] The adhesive component ADL may include an intermediate adhesive layer 710, a first peripheral adhesive layer 711, and a second peripheral adhesive layer 712.

[0140] In such Figure 8 In the plan view shown, the intermediate adhesive layer 710 may have a closed curve shape surrounding the display area DA. The intermediate adhesive layer 710 may be disposed between the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712.

[0141] In such Figure 9In the cross-sectional view shown, the intermediate adhesive layer 710 may have a width that gradually decreases along the direction toward the cover window CSUB (e.g., third direction DR3). In an embodiment, the intermediate adhesive layer 710 may have, for example, a triangular cross-section. In an embodiment, the top surface S33 of the intermediate adhesive layer 710 may have a circular shape (or a parabolic shape). In an embodiment, the top surface S33 of the intermediate adhesive layer 710 may be a surface facing (or in contact with) the cover window CSUB, such that the top surface S33 of the intermediate adhesive layer 710 may have, for example, a circular shape (or a parabolic shape) convex toward the cover window CSUB.

[0142] In an embodiment, each of the first side surfaces S11 (e.g., the outer surface of the intermediate adhesive layer 710) and the second side surface S22 (e.g., the inner surface of the intermediate adhesive layer 710) facing each other in the intermediate adhesive layer 710 may form an inclined oblique line shape. The center of the intermediate adhesive layer 710 may pass through the center between the first side surface S11 and the second side surface S22 of the intermediate adhesive layer 710 (e.g., the center of the top surface S33 of the intermediate adhesive layer 710) and may overlap with an imaginary extension line L1 parallel to the side surface SS2 (or parallel to the third direction DR3) of the adhesive member ADL. The first side surface S11 and the second side surface S22 of the intermediate adhesive layer 710 may have a shape symmetrical with respect to the aforementioned extension line L1.

[0143] The first outer adhesive layer 711 can be disposed on one side of the intermediate adhesive layer 710. In an embodiment, such as Figure 9 As shown, for example, the first peripheral adhesive layer 711 may be disposed between the light blocking layer BM and the first side surface S11 of the intermediate adhesive layer 710.

[0144] The first peripheral adhesive layer 711 may include a plurality of first sub-adhesive layers 711a and 711b with different densities. In embodiments, for example, the plurality of first sub-adhesive layers 711a and 711b may have a higher density as they are positioned further away from the intermediate adhesive layer 710. As a predetermined example, the plurality of first sub-adhesive layers 711a and 711b may have a higher density as they are positioned further away from the center (or extension line L1) of the intermediate adhesive layer 710.

[0145] In an embodiment, the first peripheral adhesive layer 711 may include a first first sub-adhesive layer 711a and a first second sub-adhesive layer 711b with different densities. The first first sub-adhesive layer 711a may be disposed between the intermediate adhesive layer 710 and the first second sub-adhesive layer 711b. The first second sub-adhesive layer 711b may be disposed between the first first sub-adhesive layer 711a and the light-blocking layer BM. Among the plurality of first sub-adhesive layers 711a and 711b, the first first sub-adhesive layer 711a may be disposed closer to the center (or extension line L1) of the intermediate adhesive layer 710, and the first second sub-adhesive layer 711b among the plurality of first sub-adhesive layers 711a and 711b may be disposed further away from the center (or extension line L1) of the intermediate adhesive layer 710. In other words, the first second sub-adhesive layer 711b may be disposed further away from the center (or extension line L1) of the intermediate adhesive layer 710 than the first first sub-adhesive layer 711a.

[0146] In an embodiment, the density of the first and second sub-adhesive layers 711b can be higher than the density of the first first sub-adhesive layer 711a. In other words, the first first sub-adhesive layer 711a, which is positioned closer to the intermediate adhesive layer 710, can have a relatively lower density, and the first second sub-adhesive layer 711b, which is positioned further away from the intermediate adhesive layer 710, can have a relatively higher density.

[0147] In an embodiment, the interior angle θ1 defined between the side surface of the first and second sub-adhesive layers 711b (e.g., the side surface SS2 of the adhesive member ADL) and the top surface of the first and second sub-adhesive layers 711b (e.g., the top surface SS1 of the adhesive member ADL) can be from 90 degrees to 135 degrees. In an embodiment, the aforementioned interior angle θ1 can be 90 degrees.

[0148] The second outer adhesive layer 712 can be disposed on the opposite side of the intermediate adhesive layer 710. In an embodiment, such as Figure 9 As shown, for example, the second peripheral adhesive layer 712 may be disposed on the second side surface S22 of the intermediate adhesive layer 710.

[0149] The second peripheral adhesive layer 712 may include a plurality of second sub-adhesive layers 712a, 712b, and 712c with different densities. In embodiments, for example, the plurality of second sub-adhesive layers 712a, 712b, and 712c may have a higher density as they are positioned further away from the intermediate adhesive layer 710. As a predetermined example, the plurality of second sub-adhesive layers 712a, 712b, and 712c may have a higher density as they are positioned further away from the center (or extension line L1) of the intermediate adhesive layer 710.

[0150] In an embodiment, the second peripheral adhesive layer 712 may include a second first sub-adhesive layer 712a, a second second sub-adhesive layer 712b, and a second third sub-adhesive layer 712c with different densities. The second first sub-adhesive layer 712a may be disposed between the intermediate adhesive layer 710 and the second second sub-adhesive layer 712b. The second second sub-adhesive layer 712b may be disposed between the second first sub-adhesive layer 712a and the second third sub-adhesive layer 712c. The second third sub-adhesive layer 712c may be disposed close to the second second sub-adhesive layer 712b. Among the plurality of second sub-adhesive layers 712a, 712b, and 712c, the second first sub-adhesive layer 712a may be disposed closest to the center (or extension line L1) of the intermediate adhesive layer 710, and among the plurality of second sub-adhesive layers 712a, 712b, and 712c, the second third sub-adhesive layer 712c may be disposed furthest from the center (or extension line L1) of the intermediate adhesive layer 710. The second sub-adhesive layer 712b can be configured to be further away from the center (or extension line L1) of the intermediate adhesive layer 710 than the second first sub-adhesive layer 712a, and can be configured to be closer to the center (or extension line L1) of the intermediate adhesive layer 710 than the second third sub-adhesive layer 712c. In other words, the second sub-adhesive layer 712b can be configured to be further away from the center (or extension line L1) of the intermediate adhesive layer 710 than the second first sub-adhesive layer 712a, and the second third sub-adhesive layer 712c can be configured to be further away from the center (or extension line L1) of the intermediate adhesive layer 710 than the second sub-adhesive layer 712b.

[0151] In this embodiment, the density of the second sub-adhesive layer 712b can be higher than the density of the second first sub-adhesive layer 712a, and the density of the second third sub-adhesive layer 712c can be higher than the density of the second second sub-adhesive layer 712b. In other words, the second first sub-adhesive layer 712a, positioned closest to the intermediate adhesive layer 710, can have a relatively low density, and the second third sub-adhesive layer 712c, positioned furthest from the intermediate adhesive layer 710, can have a relatively high density. The density of the second second sub-adhesive layer 712b between the second first sub-adhesive layer 712a and the second third sub-adhesive layer 712c can be higher than the density of the second first sub-adhesive layer 712a, and lower than the density of the second third sub-adhesive layer 712c.

[0152] In an embodiment, the density of the intermediate adhesive layer 710 may differ from the density of at least one sub-adhesive layer included in the first peripheral adhesive layer 711. For example, in an embodiment, the density of the intermediate adhesive layer 710 may be higher than the density of the first sub-adhesive layer 711a. Additionally, the density of the intermediate adhesive layer 710 may be higher than the density of the first second sub-adhesive layer 711b.

[0153] In an embodiment, the density of the intermediate adhesive layer 710 may differ from the density of at least one sub-adhesive layer included in the second peripheral adhesive layer 712. For example, in an embodiment, the density of the intermediate adhesive layer 710 may be higher than the density of the second first sub-adhesive layer 712a. Additionally, the density of the intermediate adhesive layer 710 may be higher than the density of the second second sub-adhesive layer 712b.

[0154] In one embodiment, the density of the intermediate adhesive layer 710 may be the same as the density of at least one sub-adhesive layer included in the second peripheral adhesive layer 712. In another embodiment, for example, the density of the intermediate adhesive layer 710 may be the same as the density of the second and third sub-adhesive layers 712c.

[0155] In an embodiment, the density of the intermediate adhesive layer 710 and the density of the second and third sub-adhesive layers 712c may be higher than the density of the remaining (other) sub-adhesive layers.

[0156] In the embodiments, such as Figure 8 In the plan view shown, the second sub-adhesive layer 712b may surround the display area DA and the second and third sub-adhesive layers 712c. Additionally, in... Figure 8 In the plan view shown, the second first sub-adhesive layer 712a may surround the display area DA, the second third sub-adhesive layer 712c, and the second second sub-adhesive layer 712b. Additionally, in... Figure 8 In the plan view shown, the intermediate adhesive layer 710 may surround the display area DA, the second and third sub-adhesive layers 712c, the second sub-adhesive layers 712b, and the second sub-adhesive layer 712a. Additionally, in... Figure 8 In the plan view shown, the first sub-adhesive layer 711a may surround the display area DA, the second sub-adhesive layer 712c, the second sub-adhesive layer 712b, the second first sub-adhesive layer 712a, and the intermediate adhesive layer 710. Additionally, in... Figure 8 In the plan view shown, the first and second sub-adhesive layers 711b may surround the display area DA, the second and third sub-adhesive layers 712c, the second and second sub-adhesive layers 712b, the second and first sub-adhesive layers 712a, the intermediate adhesive layer 710, and the first sub-adhesive layer 711a.

[0157] In this embodiment, the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 may not be connected to each other. In other words, the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 may be separated from each other by an intermediate adhesive layer 710 located therebetween. Therefore, for example, the first sub-adhesive layer 711a and the second sub-adhesive layer 712a may not be connected to each other, but may be separated.

[0158] In one embodiment, the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 may not be disposed between the top surface S33 of the intermediate adhesive layer 710 and the cover window CSUB. In another embodiment, for example, the top surface S33 of the intermediate adhesive layer 710 (e.g., the center of the top surface S33) and the cover window CSUB may be in contact with each other (e.g., in direct contact).

[0159] Figure 10 This is a schematic plan view of the display panel 100 including the adhesive layer in the embodiment, and Figure 11 It is along Figure 10 A sectional view taken from line IV-IV'.

[0160] like Figure 10 and Figure 11 As shown, the adhesive member ADL can be disposed on the substrate SUB. In an embodiment, as... Figure 11 As shown, for example, the adhesive member ADL can be disposed on the polarizing layer POL to be superimposed on the substrate SUB.

[0161] In an embodiment, for example, Figure 6 and Figure 7 The component between the substrate SUB and the polarization layer POL can also be set in Figure 11 Between the substrate SUB and the polarization layer POL.

[0162] In such Figure 10 In the plan view shown, the edge of the adhesive member ADL (e.g., the side surface SS2 of the adhesive member ADL) may surround the display area DA.

[0163] The interior angle θ2 defined between the side surface SS2 and the top surface SS1 of the adhesive member ADL can be a right angle. In an embodiment, when the surface of the adhesive member ADL facing the light-blocking layer BM is defined as the side surface SS2 of the adhesive member ADL, and the surface of the adhesive member ADL facing the cover window CSUB is defined as the top surface SS1 of the adhesive member ADL, the interior angle θ2 defined between the side surface SS2 and the top surface SS1 of the adhesive member ADL can be, for example, 90 degrees to 135 degrees. In an embodiment, the aforementioned interior angle θ2 can be 90 degrees.

[0164] In an embodiment, the light-blocking layer BM and the adhesive member ADL can be separated from each other. In an embodiment, for example, a gap G can be defined between the light-blocking layer BM and the adhesive member ADL (or the side surface SS2 of the adhesive member). In a plan view, the gap G can surround the adhesive member ADL. The light-blocking layer BM and the adhesive member ADL can be kept from contacting each other due to the gap G. The interior angle θ2 defined between the side surface SS2 and the top surface SS1 of the adhesive member ADL can be formed into a right angle by a display device manufacturing method described later. Therefore, although the side surface SS2 of the adhesive member ADL is not supported by the light-blocking layer BM due to the aforementioned gap G, the side surface SS2 and the top surface SS1 of the adhesive member ADL at the edge of the adhesive member ADL can remain at a right angle.

[0165] In another embodiment, Figure 10 The light-blocking layer BM and the adhesive component ADL can be as described above. Figure 7 As shown, they are in contact with each other.

[0166] Figure 12 This is a schematic diagram of the adhesive member forming apparatus 800 for the display device 10 in the embodiment, and Figure 13 It is along Figure 12 A sectional view taken by line V-V'.

[0167] like Figure 12 and Figure 13 As shown, the adhesive component forming apparatus 800 may include a guide rail 860, a stage 810, an alignment device 820, an inkjet printing device 830, a curing device 840, and a printing pattern providing device 850.

[0168] The stage 810, alignment device 820, inkjet printing device 830 and curing device 840 can be arranged above the guide rail 860.

[0169] The guide rail 860 can extend along the first direction DR1.

[0170] Stage 810 can support base SUB. Base SUB can be placed on stage 810. Stage 810 can move along guide rail 860. In an embodiment, for example, stage 810 can move along guide rail 860 in a first direction DR1. Alternatively, stage 810 can move along guide rail 860 in the opposite direction to the first direction DR1 (hereinafter referred to as the first reverse direction).

[0171] Alignment device 820 may be disposed above guide rail 860 and stacked with guide rail 860. Alignment device 820 may include visual alignment device (or visual alignment system). Alignment device 820 may automatically identify reference marks (e.g., alignment marks) of substrate SUB, calculate the correct position error and rotation error of substrate SUB based on the identification results, and align substrate SUB to the correct position when the alignment status of substrate SUB is confirmed to be poor based on the calculation results.

[0172] The inkjet printing apparatus 830 may be disposed on and stacked with the guide rail 860. In an embodiment, for example, the inkjet printing apparatus 830 may be disposed above the guide rail 860 between the alignment device 820 and the curing device 840. The inkjet printing apparatus 830 may provide the raw material (e.g., resin) for the adhesive component ADL via inkjet printing. Inkjet printing can create patterns by forming droplets of tens of micrometers (μm) at desired locations using a non-contact patterning technique, and has the advantage of consuming less adhesive and significantly reducing the number of processes compared to other printing techniques. The inkjet printing apparatus 830 may spray the raw material (e.g., resin) for the adhesive component ADL onto the substrate SUB via inkjet printing. The inkjet printing apparatus 830 may include a support 831 and a plurality of heads 832 connected to the support 831. Each of the heads 832 may include a plurality of nozzles 833. The inkjet printing apparatus 830 may spray resin through the nozzles 833. In an embodiment, the inkjet printing apparatus 830 can individually control the degree of opening (e.g., the amount of opening) of each of the nozzles 833. When the nozzle orifice of the nozzle 833 is opened more, the amount of resin ejected from the nozzle 833 (e.g., the amount of resin ejected per unit time) can be increased.

[0173] The printing pattern providing device 850 can provide the inkjet printing device 830 with a pattern (or printing pattern) of a raw material (e.g., resin) to be applied (or formed) on the substrate SUB. In embodiments, the printing pattern providing device 850 can provide a plurality of different printing patterns. In embodiments, for example, the printing pattern providing device 850 can provide a first printing pattern PP1 and a second printing pattern PP2 that are different from each other.

[0174] For example, the first printed pattern PP1 may include a pattern corresponding to the shape of the intermediate adhesive layer 710 described above. In other words, the first printed pattern PP1 may include a pattern image of the raw material in the form of a closed curve surrounding the display area DA.

[0175] For example, the second printed pattern PP2 may include a pattern corresponding to the shape of the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 described above. In other words, the second printed pattern PP2 may include a pattern image for the raw material for being respectively disposed on the first side surface (or outer surface) and the second side surface (or inner surface) of the first printed pattern PP1 described above.

[0176] The first printed pattern PP1 and the second printed pattern PP2 can be transmitted to the inkjet printing apparatus 830. In an embodiment, for example, the printed pattern providing device 850 can select either the first printed pattern PP1 or the second printed pattern PP2 according to a control signal from an external source (e.g., a control signal from a control device), and can provide the selected printed pattern to the inkjet printing apparatus 830.

[0177] When the inkjet printing device 830 sprays raw material according to the first printing pattern PP1, the raw material can be sprayed onto the substrate SUB to form the shape of the intermediate adhesive layer 710.

[0178] When the inkjet printing device 830 sprays raw material according to the second printing pattern PP2, the raw material can be sprayed onto the substrate SUB to form the shape of the peripheral adhesive layer (e.g., the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712).

[0179] The curing device 840 may be disposed above and stacked with the guide rail 860. The curing device 840 can cure the raw material (e.g., resin) on the substrate SUB. For this purpose, in an embodiment, the curing device 840 can provide at least one of ultraviolet light, near-ultraviolet light, and heat.

[0180] Figures 14 to 31 This is a diagram illustrating an embodiment of a method for manufacturing a display device 10. In the embodiment, for example, Figures 14 to 31 It can be used to describe the above Figure 12 and Figure 13 A diagram illustrating a method for manufacturing a display device 10 using an adhesive component forming apparatus 800. Here, Figure 15 It is along Figure 14 The sectional view taken by line A1-A1' in the middle. Figure 17 It is along Figure 16 The sectional view taken by line A2-A2' in the middle. Figure 19 It is along Figure 18 The sectional view taken by line A3-A3' in the diagram. Figure 21 It is along Figure 20 The sectional view taken by line A4-A4'. Figure 23 It is along Figure 22 The sectional view taken by line A5-A5'. Figure 25 It is alongFigure 24 The sectional view taken by line A6-A6'. Figure 27 It is along Figure 26 The sectional view taken by line A7-A7' in the diagram. Figure 29 It is along Figure 28 The sectional view taken by line A8-A8' in the middle. Figure 31 It is along Figure 30 The sectional view is taken along line A9-A9'. Additionally, Figure 32 It is set in Figures 16 to 21 Plan view of the base SUB on platform 810 in the middle. Figure 33 It is along Figure 32 The sectional view taken by line VI-VI' in the middle. Figure 34 It is set in Figures 26 to 31 A cross-sectional view of the base SUB on platform 810.

[0181] Figures 14 to 31 The arrow AR in the diagram indicates the direction of movement of platform 810.

[0182] First, a substrate SUB on which a polarization layer POL is formed can be placed on stage 810. Here, for example, a space can also be placed between the substrate SUB and the polarization layer POL. Figure 6 and Figure 7 The component between the substrate SUB and the polarization layer POL.

[0183] After that, as Figure 14 and Figure 15 As shown, a stage 810 on which a substrate SUB is disposed can move along a guide rail 860 in a first direction DR1. When the stage 810 passes between the alignment device 820 and the guide rail 860, the substrate SUB can be correctly aligned by the alignment device 820. In an embodiment, for example, the alignment device 820 can capture an image of the substrate SUB on the stage 810, determine the alignment state of the substrate SUB based on the captured image, and correct any distortion of the substrate SUB according to the determination result.

[0184] Subsequently, as Figure 16 and Figure 17As shown, when the stage 810, which has already passed the alignment device 820, moves further in the first direction DR1 and passes between the inkjet printing device 830 and the guide rail 860, an intermediate adhesive layer 710 according to the first printed pattern PP1 can be formed on the substrate SUB. In an embodiment, for example, the printed pattern providing device 850 can provide the first printed pattern PP1 to the inkjet printing device 830 before the stage 810 reaches the inkjet printing device 830 (e.g., when the stage 810 reaches the alignment device 820), such that the inkjet printing device 830 can spray the raw material 70 onto the substrate SUB through the nozzle 833 corresponding to the first printed pattern PP1 from the printed pattern providing device 850. When the raw material 70 is sprayed onto the substrate SUB through the nozzle 833 corresponding to the first printed pattern PP1, an intermediate adhesive layer 710 can be formed on the polarization layer POL on the substrate SUB.

[0185] In an embodiment, the inkjet printing apparatus 830 can be controlled such that raw material with maximum density (e.g., 100% density) is ejected from the corresponding nozzle 833 (e.g., the nozzle 833 corresponding to the first printed pattern PP1). Therefore, as... Figure 32 and Figure 33 As shown, an intermediate adhesive layer 710 can be provided on the polarization layer POL on the substrate SUB, surrounding the display area DA.

[0186] In an embodiment, the inkjet printing apparatus 830 can open each of the jet orifices of the corresponding nozzle 833 (e.g., the nozzle 833 corresponding to the first printed pattern PP1) to its maximum (e.g., 100% open) and can jet the raw material 70 onto the substrate SUB. In an embodiment, for example, the opening amount of each of the nozzles 833 corresponding to the first printed pattern PP1 can be 100%. Therefore, as Figure 32 and Figure 33 As shown, an intermediate adhesive layer 710 surrounding the display area DA can be provided on the polarizing layer POL on the substrate SUB. The amount of raw material 70 ejected from the nozzle 833 can be controlled according to the opening amount of the nozzle 833. In an embodiment, for example, the amount of raw material 70 ejected per unit time can be increased when the opening amount of the nozzle 833 increases.

[0187] Next, as Figure 18 , Figure 19 , Figure 20 and Figure 21As shown, when the stage 810 of the inkjet printing apparatus 830 has moved further in the first direction DR1 and passed between the curing apparatus 840 and the guide rail 860, the intermediate adhesive layer 710 on the substrate SUB can be cured. In an embodiment, for example, the curing apparatus 840 can cure the intermediate adhesive layer 710 on the substrate SUB by irradiating it with ultraviolet light.

[0188] Subsequently, as Figure 22 and Figure 23 As shown, the stage 810, which has passed through the curing device 840, can move in the opposite direction and return to its initial loading position. In an embodiment, for example, the stage 810 can move along the guide rail 860 in a first reverse direction and move to the front end of the alignment device 820. While the stage 810 moves along the guide rail 860 in the first reverse direction, the alignment device 820, the inkjet printing device 830, and the curing device 840 can remain in a non-driven state.

[0189] After that, as Figure 24 and Figure 25 As shown, when stage 810 passes between alignment device 820 and guide rail 860, the substrate SUB can be correctly aligned by alignment device 820. In an embodiment, for example, alignment device 820 can capture an image of the substrate SUB on stage 810, determine the alignment state of the substrate SUB based on the captured image, and correct any distortion of the substrate SUB according to the determination result.

[0190] Next, as Figure 26 and Figure 27 As shown, when the stage 810, having already moved further along the first direction DR1 via the alignment device 820, and passing between the inkjet printing device 830 and the guide rail 860, peripheral adhesive layers (e.g., a first peripheral adhesive layer 711 and a second peripheral adhesive layer 712) according to the second printed pattern PP2 can be formed on the substrate SUB. In an embodiment, for example, the printed pattern providing device 850 can provide the second printed pattern PP2 to the inkjet printing device 830 before the stage 810 reaches the inkjet printing device 830 (e.g., when the stage 810 reaches the alignment device 820), such that the inkjet printing device 830 can spray raw material 73 onto the substrate SUB via nozzles 833 corresponding to the second printed pattern PP2 from the printed pattern providing device 850. When the raw material 73 is sprayed onto the substrate SUB via nozzles 833 corresponding to the second printed pattern PP2, the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 can be formed on the polarization layer POL on the substrate SUB.

[0191] In an embodiment, the inkjet printing apparatus 830 can spray the raw material 73 onto the substrate SUB by adjusting the density of the raw material 73 sprayed from the corresponding nozzle 833 (e.g., the nozzle 833 corresponding to the second printed pattern PP2) or the opening degree of the spray orifice of the corresponding nozzle 833 (e.g., the nozzle 833 corresponding to the second printed pattern PP2). Therefore, as Figure 34 As shown, a first peripheral adhesive layer 711 and a second peripheral adhesive layer 712 can be formed on the polarization layer POL on the substrate SUB. In an embodiment, for example, the first peripheral adhesive layer 711 can be formed on the first side surface S11 of the intermediate adhesive layer 710, and the second peripheral adhesive layer 712 can be formed on the second side surface S22 of the intermediate adhesive layer 710 and in the display area DA. In this case, the second peripheral adhesive layer 712 can completely fill the area surrounded by the intermediate adhesive layer 710.

[0192] In an embodiment, to form the peripheral adhesive layers 711 and 712, the density of the raw material 73 ejected from the nozzle 833 corresponding to the first sub-adhesive layer 711a can be 20% of the maximum density, the density of the raw material 73 ejected from the nozzle 833 corresponding to the first second sub-adhesive layer 711b can be 80% of the maximum density, the density of the raw material 73 ejected from the nozzle 833 corresponding to the second first sub-adhesive layer 712a can be 30% of the maximum density, the density of the raw material 73 ejected from the nozzle 833 corresponding to the second second sub-adhesive layer 712b can be 80% of the maximum density, and the raw material 73 ejected from the nozzle 833 corresponding to the second third sub-adhesive layer 712c can be ejected at the maximum density. In this way, for example, the density of the raw material 73 ejected from each nozzle 833 corresponding to each sub-adhesive layer can be controlled, such that a layer with... Figure 34 The first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 are shown in the figure.

[0193] In an embodiment, to form the peripheral adhesive layers 711 and 712, the opening amount of the nozzle 833 corresponding to the first sub-adhesive layer 711a can be 20% of the maximum opening amount, the opening amount of the nozzle 833 corresponding to the first second sub-adhesive layer 711b can be 80% of the maximum opening amount, the opening amount of the nozzle 833 corresponding to the second first sub-adhesive layer 712a can be 30% of the maximum opening amount, the opening amount of the nozzle 833 corresponding to the second second sub-adhesive layer 712b can be 80% of the maximum opening amount, and the nozzle 833 corresponding to the second third sub-adhesive layer 712c can be opened to the maximum extent (e.g., 100%). In this way, for example, the opening amount of each of the nozzles 833 corresponding to each sub-adhesive layer can be adjusted differently, so that a layer with... Figure 34The first outer adhesive layer 711 and the second outer adhesive layer 712 are shown in the shape shown.

[0194] Next, as Figure 28 , Figure 29 , Figure 30 , Figure 31 As shown, when the stage 810 of the inkjet printing apparatus 830 has moved further in the first direction DR1 and passed between the curing apparatus 840 and the guide rail 860, the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 on the substrate SUB can be cured. In an embodiment, for example, the curing apparatus 840 can cure the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712 on the substrate SUB by irradiating them with ultraviolet light.

[0195] In an embodiment, the cumulative amount of ultraviolet light irradiated during the curing of the intermediate adhesive layer 710 and the cumulative amount of ultraviolet light irradiated during the curing of the outer adhesive layers 711 and 712 may be different from each other. In an embodiment, for example, the cumulative amount of ultraviolet light irradiated from the curing apparatus 840 during the curing of the outer adhesive layers (e.g., the first outer adhesive layer 711 and the second outer adhesive layer 712) may be greater than the cumulative amount of ultraviolet light irradiated from the curing apparatus 840 during the curing of the intermediate adhesive layer 710. The intermediate adhesive layer 710 may also be further cured while the outer adhesive layers (e.g., the first outer adhesive layer 711 and the second outer adhesive layer 712) are being cured.

[0196] In an embodiment, when the densities of the raw materials 70 and 73 sprayed onto the substrate SUB are controlled as described above, a polarizing layer POL can be formed with... Figure 8 and Figure 9 The adhesive member ADL is shown in the figure. In other words, when the density of the raw materials 70 and 73 ejected from the nozzle 833 is controlled to form the adhesive member ADL, the adhesive member ADL may include an intermediate adhesive layer 710, a first sub-adhesive layer 711a, a first second sub-adhesive layer 711b, a second first sub-adhesive layer 712a, a second second sub-adhesive layer 712b, and a second third sub-adhesive layer 712c, which are separated from each other by interfaces.

[0197] In an embodiment, when the spray amounts of raw materials 70 and 73 disposed on the substrate SUB are controlled as described above, a polarizing layer POL can be formed with... Figure 10 and Figure 11The adhesive member ADL is shown in the figure. In other words, when the amount of raw materials 70 and 73 supplied from nozzle 833 is controlled to form the adhesive member ADL, the adhesive member ADL may include an intermediate adhesive layer 710, a first sub-adhesive layer 711a, a first second sub-adhesive layer 711b, a second first sub-adhesive layer 712a, a second second sub-adhesive layer 712b, and a second third sub-adhesive layer 712c that are integrally formed without distinguishing interfaces.

[0198] In an embodiment, as described above, when controlling the density of raw materials 70 and 73 or the spraying amount of raw materials 70 and 73 and forming the adhesive member ADL, the top surface SS1 of the adhesive member ADL can be flattened. In an embodiment, for example, the top surface SS1 of the edge of the adhesive member ADL can be flattened. In other words, the top surface SS1 of the adhesive member ADL can be flattened to form an angle of 90 to 135 degrees relative to the side surface SS2 of the adhesive member ADL. In an embodiment, the aforementioned interior angle θ1 can be 90 degrees. Therefore, when the adhesive member ADL and the cover window CSUB are joined together, the adhesion between the adhesive member ADL and the cover window CSUB can be improved at the edge of the adhesive member ADL. Therefore, gaps (e.g., air gaps) can be prevented from being defined between the adhesive member ADL and the cover window CSUB at the edge of the adhesive member ADL. As a result, visually identifiable point defects around the edge of the adhesive member ADL can be prevented, thereby improving the image quality of the display device 10.

[0199] Figure 35 This is a schematic plan view of an embodiment of a display panel 100 including the adhesive member ADL, and Figure 36 It is along Figure 35 A sectional view taken from line VII-VII'.

[0200] Figure 35 and Figure 36 The display device 10 in the above Figure 8 and Figure 9 The difference in the display device 10 is that it also includes a hole 900 penetrating the substrate SUB, an intermediate adhesive layer 910 (hereinafter referred to as the second intermediate adhesive layer 910) disposed around the hole 900, and an outer adhesive layer (hereinafter referred to as the third outer adhesive layer 911 and the fourth outer adhesive layer 912), such that the differences will be mainly described below.

[0201] like Figure 35 and Figure 36 As shown, the display device 10 in the embodiment may further include a hole 900 penetrating the substrate SUB, the polarizing layer POL, and the adhesive member ADL in the display area DA. In the embodiment, Figure 6 and Figure 7The component between the substrate SUB and the polarizing layer POL can also be disposed between the substrate SUB and the polarizing layer POL, such that in this case, the hole 900 can also penetrate the insulating film in the component between the substrate SUB and the polarizing layer POL.

[0202] An electronic component 999, superimposed on the aperture 900, may be disposed below the aperture 900. In an embodiment, for example, the electronic component 999 may include at least one of a camera and various sensors.

[0203] In such Figure 35 In the plan view shown, hole 900 can have a circular shape.

[0204] like Figure 35 As shown, the adhesive component ADL may include an intermediate adhesive layer 710 (e.g., a first intermediate adhesive layer 710), a first peripheral adhesive layer 711, a second peripheral adhesive layer 712, a second intermediate adhesive layer 910, a third peripheral adhesive layer 911, and a fourth peripheral adhesive layer 912.

[0205] Figure 35 The first intermediate adhesive layer 710, the first outer adhesive layer 711, and the second outer adhesive layer 712 are respectively bonded to the above-mentioned... Figure 8 and Figure 9 The intermediate adhesive layer 710, the first outer adhesive layer 711, and the second outer adhesive layer 712 are the same.

[0206] In such Figure 35 In the plan view shown, the second intermediate adhesive layer 910 may have a closed curve shape around the hole 900. The second intermediate adhesive layer 910 may be disposed between the third peripheral adhesive layer 911 and the fourth peripheral adhesive layer 912.

[0207] In such Figure 36 In the cross-sectional view shown, the second intermediate adhesive layer 910 may have a width that gradually decreases along the direction toward the cover window CSUB (e.g., third direction DR3). In an embodiment, for example, the second intermediate adhesive layer 910 may have a triangular cross-section. In an embodiment, the top surface S30 of the second intermediate adhesive layer 910 may have a circular shape (or a parabolic shape). In an embodiment, for example, the top surface S30 of the second intermediate adhesive layer 910 may be a surface facing (or in contact with) the cover window CSUB, such that the top surface S30 of the second intermediate adhesive layer 910 may have a circular shape (or a parabolic shape) convex toward the cover window CSUB.

[0208] In an embodiment, each of the first side surfaces S10 (e.g., the outer surface of the second intermediate adhesive layer 910) and the second side surface S20 (e.g., the inner surface of the second intermediate adhesive layer 910) facing each other can form an inclined oblique shape. The center of the second intermediate adhesive layer 910 can pass through the center between the first side surface S10 and the second side surface S20 of the second intermediate adhesive layer 910 (e.g., the center of the top surface S30 of the second intermediate adhesive layer 910) and can be superimposed on an imaginary extension line L10 parallel to the side surface of the adhesive member ADL (or parallel to the third direction DR3). The first side surface S10 and the second side surface S20 of the second intermediate adhesive layer 910 can have a symmetrical shape with respect to the aforementioned extension line L10.

[0209] The third outer adhesive layer 911 can be disposed on one side of the second intermediate adhesive layer 910. In an embodiment, such as Figure 36 As shown, for example, the third peripheral adhesive layer 911 may be disposed between the second third sub-adhesive layer 712c and the first side surface S10 of the second intermediate adhesive layer 910.

[0210] The third peripheral adhesive layer 911 may include a plurality of third sub-adhesive layers with different densities. In an embodiment, for example, the plurality of third sub-adhesive layers 911a and 911b may have a higher density as they are positioned further away from the second intermediate adhesive layer 910. As a predetermined example, the plurality of third sub-adhesive layers 911a and 911b may have a higher density as they are positioned further away from the center (or extension line L10) of the second intermediate adhesive layer 910.

[0211] In an embodiment, the third peripheral adhesive layer 911 may include a third first sub-adhesive layer 911a and a third second sub-adhesive layer 911b with different densities. The third first sub-adhesive layer 911a may be disposed between the second intermediate adhesive layer 910 and the third second sub-adhesive layer 911b. The third second sub-adhesive layer 911b may be disposed between the third first sub-adhesive layer 911a and the second third sub-adhesive layer 712c. Among the plurality of third sub-adhesive layers 911a and 911b, the third first sub-adhesive layer 911a may be disposed closer to the center (or extension line L10) of the second intermediate adhesive layer 910, and the third second sub-adhesive layer 911b may be disposed further away from the center (or extension line L10) of the second intermediate adhesive layer 910. In other words, the third second sub-adhesive layer 911b may be disposed further away from the center (or extension line L10) of the second intermediate adhesive layer 910 than the third first sub-adhesive layer 911a.

[0212] In an embodiment, the density of the third second sub-adhesive layer 911b can be higher than the density of the third first sub-adhesive layer 911a. In other words, the third first sub-adhesive layer 911a, which is positioned closer to the second intermediate adhesive layer 910, can have a relatively lower density, and the third second sub-adhesive layer 911b, which is positioned further away from the second intermediate adhesive layer 910, can have a relatively higher density.

[0213] The fourth peripheral adhesive layer 912 can be disposed on the opposite side of the second intermediate adhesive layer 910. In an embodiment, such as... Figure 36 As shown, for example, the fourth peripheral adhesive layer 912 may be disposed between the hole 900 (or the inner wall of the hole 900) and the second side surface S20 of the second intermediate adhesive layer 910.

[0214] The fourth peripheral adhesive layer 912 may include a plurality of fourth sub-adhesive layers 912a and 912b with different densities. In an embodiment, for example, the plurality of fourth sub-adhesive layers 912a and 912b may have a higher density as they are positioned further away from the center (or extension line L1) of the second intermediate adhesive layer 910. As a predetermined example, the plurality of fourth sub-adhesive layers 912a and 912b may have a higher density as they are positioned further away from the center (or extension line L1) of the second intermediate adhesive layer 910.

[0215] In an embodiment, the fourth peripheral adhesive layer 912 may include a fourth first sub-adhesive layer 912a and a fourth second sub-adhesive layer 912b with different densities. The fourth first sub-adhesive layer 912a may be disposed between the second intermediate adhesive layer 910 and the fourth second sub-adhesive layer 912b. The fourth second sub-adhesive layer 912b may be disposed between the fourth first sub-adhesive layer 912a and the hole 900 (or the inner wall of the hole 900). Among the plurality of fourth sub-adhesive layers 912a and 912b, the fourth first sub-adhesive layer 912a may be disposed relatively close to the center (or extension line L10) of the second intermediate adhesive layer 910, and the fourth second sub-adhesive layer 912b may be disposed relatively far from the center (or extension line L10) of the second intermediate adhesive layer 910. In other words, the fourth second sub-adhesive layer 912b may be disposed further away from the center (or extension line L10) of the second intermediate adhesive layer 910 than the fourth first sub-adhesive layer 912a.

[0216] In an embodiment, the density of the fourth second sub-adhesive layer 912b can be higher than the density of the fourth first sub-adhesive layer 912a. In other words, the fourth first sub-adhesive layer 912a, which is positioned closer to the second intermediate adhesive layer 910, can have a relatively lower density, and the fourth second sub-adhesive layer 912b, which is positioned further away from the second intermediate adhesive layer 910, can have a relatively higher density.

[0217] In an embodiment, the interior angle θ3 defined between the side surface SS3 (e.g., the inner wall of the hole 900) of the fourth second sub-adhesive layer 912b and the top surface SS1 (e.g., the top surface of the adhesive member ADL) of the fourth second sub-adhesive layer 912b can be from 90 degrees to 135 degrees. In an embodiment, the aforementioned interior angle θ3 can be 90 degrees.

[0218] In an embodiment, the density of the second intermediate adhesive layer 910 may differ from the density of at least one sub-adhesive layer included in the third peripheral adhesive layer 911. For example, in an embodiment, the density of the second intermediate adhesive layer 910 may be higher than the density of the third first sub-adhesive layer 911a. Additionally, the density of the second intermediate adhesive layer 910 may be higher than the density of the third second sub-adhesive layer 911b.

[0219] In an embodiment, the density of the second intermediate adhesive layer 910 may differ from the density of at least one sub-adhesive layer included in the fourth peripheral adhesive layer 912. For example, in an embodiment, the density of the second intermediate adhesive layer 910 may be higher than the density of the fourth first sub-adhesive layer 912a. Additionally, the density of the second intermediate adhesive layer 910 may be higher than the density of the fourth second sub-adhesive layer 912b.

[0220] In an embodiment, the density of the second intermediate adhesive layer 910 may be higher than the density of the sub-adhesive layers included in the third peripheral adhesive layer 911 or the fourth peripheral adhesive layer 912.

[0221] In an embodiment, such as Figure 35 As shown, the fourth second sub-adhesive layer 912b can surround the hole 900 in the plan view. Additionally, in... Figure 35 In the plan view shown, the fourth first sub-adhesive layer 912a may surround the hole 900 and the fourth second sub-adhesive layer 912b. Additionally, in... Figure 35 In the plan view shown, the second intermediate adhesive layer 910 may surround the hole 900, the fourth second sub-adhesive layer 912b, and the fourth first sub-adhesive layer 912a. Additionally, in... Figure 35 In the plan view shown, the third first sub-adhesive layer 911a may surround the hole 900, the fourth second sub-adhesive layer 912b, the fourth first sub-adhesive layer 912a, and the second intermediate adhesive layer 910. Additionally, in... Figure 35In the plan view shown, the third second sub-adhesive layer 911b may surround the hole 900, the fourth second sub-adhesive layer 912b, the fourth first sub-adhesive layer 912a, the second intermediate adhesive layer 910, and the third first sub-adhesive layer 911a.

[0222] In this embodiment, the third peripheral adhesive layer 911 and the fourth peripheral adhesive layer 912 may not be connected to each other. In other words, the third peripheral adhesive layer 911 and the fourth peripheral adhesive layer 912 may be separated from each other by a second intermediate adhesive layer 910 located therebetween. Therefore, for example, the third first sub-adhesive layer 911a and the fourth first sub-adhesive layer 912a may not be connected to each other, but may be separated.

[0223] In an embodiment, the third peripheral adhesive layer 911 and the fourth peripheral adhesive layer 912 may not be disposed between the top surface S30 of the second intermediate adhesive layer 910 and the cover window CSUB. In an embodiment, for example, the top surface S30 of the second intermediate adhesive layer 910 (e.g., the center of the top surface S30) and the cover window CSUB may be in contact with each other (e.g., in direct contact).

[0224] In an embodiment, the second intermediate adhesive layer 910 can be formed using the same process as the intermediate adhesive layer 710. In an embodiment, for example, the second intermediate adhesive layer 910 and the intermediate adhesive layer 710 can be formed using the aforementioned process. Figures 14 to 21 The processes shown are essentially formed simultaneously.

[0225] In this embodiment, the third peripheral adhesive layer 911 and the fourth peripheral adhesive layer 912 can be formed using the same process as the first peripheral adhesive layer 711 and the second peripheral adhesive layer 712. In this embodiment, for example, the third peripheral adhesive layer 911, the fourth peripheral adhesive layer 912, the first peripheral adhesive layer 711, and the second peripheral adhesive layer 712 can be formed using the aforementioned process. Figures 22 to 31 The processes shown are essentially formed simultaneously.

[0226] In an embodiment, as described above, when controlling the density of raw materials 70 and 73 or the spraying amount of raw materials 70 and 73 and forming the adhesive member ADL, the top surface SS1 of the adhesive member ADL can be flattened. In an embodiment, for example, the top surface SS1 of the edge of the adhesive member ADL can be flattened. In other words, the top surface SS1 of the adhesive member ADL can be flattened to form an angle of 90 to 135 degrees relative to the side surface SS3 of the adhesive member ADL. In an embodiment, the aforementioned interior angle θ1 can be 90 degrees. Therefore, when the adhesive member ADL and the cover window CSUB are joined together, the adhesion between the adhesive member ADL and the cover window CSUB can be improved at the edge of the hole 900. Therefore, gaps (e.g., air gaps) can be prevented from being defined between the adhesive member ADL and the cover window CSUB at the edge of the hole 900. As a result, point defects can be prevented from being visually identified around the edge of the hole 900, and the image quality of the display device 10 can be improved.

[0227] Figure 37 This is a schematic plan view of the display panel 100 including the adhesive member ADL in the embodiment. Figure 38 It is along Figure 37 A sectional view taken from line VIII-VIII'.

[0228] Figure 37 and Figure 38 The display device 10 in the above Figure 10 and Figure 11 The difference in the display device 10 is that it also includes a hole 900 penetrating the substrate SUB, so that the differences will be mainly described below.

[0229] like Figure 37 and Figure 38 As shown, the display device 10 in the embodiment may further include a hole 900 penetrating the substrate SUB, the polarizing layer POL, and the adhesive member ADL in the display area DA. In the embodiment, Figure 6 and Figure 7 The component between the substrate SUB and the polarizing layer POL can also be disposed between the substrate SUB and the polarizing layer POL, such that, for example, the hole 900 can also penetrate the insulating film in the component between the substrate SUB and the polarizing layer POL.

[0230] In such Figure 37 In the plan view shown, hole 900 can have a circular shape.

[0231] In an embodiment, such as Figure 38 As shown, the interior angle θ4 defined between the inner wall S3 of the hole 900 and the top surface SS1 of the adhesive member ADL can be from 90 degrees to 135 degrees. In an embodiment, the aforementioned interior angle θ4 can be 90 degrees.

[0232] Figure 39 This is a schematic plan view of the display panel 100 including the adhesive component ADL.

[0233] Figure 39 The display device 10 in the middle is similar to the one described above in terms of the shape of the hole 909. Figure 35 and Figure 36 The display device 10 in this paper is different from the one in the paper, and the differences will be mainly described below.

[0234] In such Figure 39 In the plan view shown, hole 909 can have a triangular shape.

[0235] Figure 40 This is a schematic plan view of the display panel 100 including the adhesive component ADL.

[0236] Figure 40 The display device 10 in the middle is similar to the one described above in terms of the shape of the hole 909. Figure 37 and Figure 38 The display device 10 in this paper is different from the one in the paper, and the differences will be mainly described below.

[0237] In such Figure 40 In the plan view shown, hole 909 can have a triangular shape.

[0238] Figure 41 This is a block diagram illustrating an electronic device 1000 according to an embodiment. Figure 42 This shows what is implemented as a smartphone. Figure 41 A view of an embodiment of the electronic device 1000.

[0239] Reference Figure 41 and Figure 42 In this embodiment, the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be connected to… Figure 1 The electronic device 1000 corresponds to the display device 10. The electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, etc. In one embodiment, the electronic device 1000 may be implemented as a television. In another embodiment, the electronic device 1000 may be implemented as a smartphone. However, the embodiments are not limited thereto; in another embodiment, the electronic device 1000 may be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC (“PC”), car navigation system, computer monitor, laptop computer, head-mounted display (e.g., mounted display) (“HMD”), etc.

[0240] Processor 1010 can perform various computing functions. In embodiments, processor 1010 may be a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), etc. Processor 1010 may be integrated with other components via address buses, control buses, data buses, etc. In embodiments, processor 1010 may be integrated with an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0241] The memory device 1020 can store data for the operation of the electronic device 1000. In embodiments, the memory device 1020 may include at least one non-volatile memory device (e.g., an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.).

[0242] In an embodiment, storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. In an embodiment, I / O device 1040 may include input devices such as a keyboard, keypad, mouse device, touchpad, touch screen, etc., and output devices such as a printer, speaker, etc.

[0243] Power supply 1050 can provide power for the operation of electronic device 1000. Power supply 1050 can also provide power to display device 1060. Display device 1060 can be connected to other components via a bus or other communication link. In an embodiment, display device 1060 may be included in I / O device 1040.

[0244] In this embodiment, the electronic device 1000 can be implemented as a smartphone. However, the embodiments of this disclosure are exemplary and not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, television, tablet PC, vehicle display, computer monitor, laptop computer, head-mounted display device, etc. Alternatively, the electronic device 1000 can be a monitor or tablet. Additionally, the electronic device 1000 can be a car.

[0245] It will be understood by those skilled in the art that the disclosure may be implemented in other predetermined forms without altering the technical spirit or essential characteristics of the disclosure. Therefore, it will be understood that the above embodiments are illustrative rather than restrictive in all aspects. It will be understood that the scope of the disclosure is defined by the claims rather than the foregoing detailed description, and that all modifications and alterations derived from the claims and their equivalents fall within the scope of the disclosure.

Claims

1. A display device comprising: a substrate; a pixel electrode over the substrate; a light-emitting layer over the pixel electrode; a common electrode over the light-emitting layer; an encapsulation layer over the common electrode; a polarizing layer over the encapsulation layer; a bonding member over the polarizing layer and including a side surface and a top surface; a cover window over the bonding member; and a light-blocking layer disposed between the polarizing layer and the cover window adjacent to the bonding member, wherein an angle defined between the side surface of the bonding member facing the light-blocking layer and the top surface of the bonding member facing the cover window is 90 degrees to 135 degrees. An angle defined between the top surface of the bonding member and the side surface of the bonding member at an edge of the bonding member is 90 degrees to 135 degrees.

2. The display device according to claim 1, wherein A gap is defined between the bonding member and the light-blocking layer.

3. The display device according to claim 1, wherein The gap surrounds the bonding member in a plan view.

4. The display device according to claim 3, wherein An edge of the bonding member surrounds a display region of the substrate in a plan view.

5. The display device according to claim 1, wherein The bonding member includes:

6. The display device according to claim 1, wherein a first intermediate bonding layer having a closed curve shape surrounding a display region of the substrate; a first peripheral bonding layer disposed on a first side surface of the first intermediate bonding layer; and a second peripheral bonding layer disposed on a second side surface of the first intermediate bonding layer. The first peripheral bonding layer includes a plurality of first sub-bonding layers having different densities.

7. The display device of claim 6, wherein, The plurality of first sub-bonding layers have higher densities as the plurality of first sub-bonding layers are disposed farther from a center of the first intermediate bonding layer.

8. The display device of claim 7, wherein, The second peripheral bonding layer includes a plurality of second sub-bonding layers having different densities.

9. The display device of claim 6, wherein, The plurality of second sub-bonding layers have higher densities as the plurality of second sub-bonding layers are disposed farther from a center of the first intermediate bonding layer.

10. The display device of claim 9, wherein, The first intermediate bonding layer has a width gradually decreasing in a direction toward the cover window.

11. The display device according to claim 6, wherein A top surface of the first intermediate bonding layer has a circular shape convex in the direction toward the cover window.

12. The display device of claim 11, wherein, The top surface of the first intermediate bonding layer contacts the cover window.

13. The display device of claim 12, wherein, The first peripheral bonding layer and the second peripheral bonding layer do not contact each other.

14. The display device of claim 6, wherein, 15. The display device according to claim 1, further comprising a hole penetrating the bonding member, the polarizing layer, and the substrate in a display region of the substrate. An angle defined between an inner wall of the hole and the top surface of the bonding member is 90 degrees to 135 degrees.

16. The display device of claim 15, wherein, The bonding member includes:

17. The display device of claim 15, wherein, a second intermediate bonding layer having a closed curve shape surrounding the hole; a third peripheral bonding layer disposed on a first side surface of the second intermediate bonding layer; and a fourth peripheral bonding layer disposed on a second side surface of the second intermediate bonding layer, wherein the third peripheral bonding layer includes a plurality of third sub-bonding layers having different densities, wherein the plurality of third sub-bonding layers have higher densities as the plurality of third sub-bonding layers are disposed farther from a center of the second intermediate bonding layer. The fourth peripheral bonding layer includes a plurality of fourth sub-bonding layers having different densities, 18. The display device of claim 17, wherein, ​ Among them, the fourth sub-adhesive layers have higher densities as the fourth sub-adhesive layers are disposed farther away from the center of the second intermediate adhesive layer.

19. The display device of claim 17, wherein, The second intermediate adhesive layer has a width gradually decreasing in a direction toward the cover window.

20. An adhesive member forming apparatus for a display device, the adhesive member forming apparatus comprising: a guide rail; a stage moving on the guide rail; an alignment device aligning a substrate on the stage; a curing device curing an adhesive member of the substrate; an inkjet printing device disposed between the alignment device and the curing device and providing a raw material of the adhesive member onto the substrate; and a printing pattern providing device providing a first printing pattern corresponding to an intermediate adhesive layer of the adhesive member and a second printing pattern corresponding to a first peripheral adhesive layer of the adhesive member and a second peripheral adhesive layer of the adhesive member.

21. An electronic device, the electronic device comprising: a display device comprising: a substrate; a pixel electrode on the substrate; an emission layer on the pixel electrode; a common electrode on the emission layer; an encapsulation layer on the common electrode; a polarizing layer on the encapsulation layer; an adhesive member on the polarizing layer; a cover window on the adhesive member; and a light blocking layer disposed adjacent to the adhesive member between the polarizing layer and the cover window, wherein an angle defined between a side surface of the adhesive member facing the light blocking layer and a top surface of the adhesive member facing the cover window is 90 degrees to 135 degrees. ​

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