Multi-time-source PTP time service circuit based on Loongson SOC

Abstract

The invention relates to a multi-time-source PTP time service circuit based on a Loongson SOC, and belongs to the technical field of timing systems. The time service circuit comprises a Loongson SOC, an FPGA, a high-stability crystal oscillator, an RS422 transceiver, a network card, a switch, computing blades 1-6 and an external clock source. According to the design scheme, the performance is stable and reliable, the mode is novel, the problem that interfaces between devices are incompatible in the equipment development process is solved, meanwhile, a design thought is provided for the time service scheme of the reinforced server, and a new solution is provided for transition of a new time service scheme and an old time service scheme. The scheme has been successfully applied to a certain reinforced server.

Description

Technical Field

[0001] This invention belongs to the field of time synchronization technology, specifically relating to a multi-time-source PTP timing circuit based on Loongson SOC. Background Technology

[0002] Time is a crucial parameter in navigation and positioning systems, computer network communication systems, and other fields. To ensure time consistency among devices within a system, a clock source is typically used as a time reference. Traditional time synchronization methods mainly include B-code, PPS+TOD, NTP, and PTP. Each method differs in its approach, applicable scenarios, and accuracy. Currently, network-based PTP time synchronization has gradually become mainstream in ruggedized server applications due to its advantages such as low cost and high accuracy. This invention describes a multi-time-source PTP time synchronization circuit design based on Loongson SOC to address the compatibility issues between new and old devices in time synchronization systems during the upgrading of military equipment. This allows different time source devices to synchronize time via PTP while maintaining high-precision timekeeping. Summary of the Invention

[0003] (a) Technical problems to be solved The technical problem to be solved by this invention is how to provide a multi-time source PTP timing circuit based on Loongson SOC to solve the compatibility problem of interfaces between old and new timing systems during the upgrading and replacement of military equipment.

[0004] (II) Technical Solution To solve the above-mentioned technical problems, this invention proposes a multi-time source PTP timing circuit based on Loongson SOC. The timing circuit includes: Loongson SOC, FPGA, high-stability crystal oscillator, RS422 transceiver, network card, switch, computing blades 1-6 and external clock source. The Loongson SOC chip is connected to the FPGA and network card via the PCIe bus. The FPGA is connected to an external RS422 transceiver and a high-stability crystal oscillator. The RS422 transceiver is connected to an external clock source. The network card is connected to the switch via an Ethernet interface. At the same time, the external PTP time synchronization source and computing blades 1-6 are also connected to the switch via Ethernet interfaces. The time synchronization network is centered on the switch, and all time synchronization / timekeeping message information is distributed through the switching network. This time synchronization circuit is based on the Loongson SOC and is compatible with three time synchronization methods: B code, PPS+TOD, and PTP.

[0005] (III) Beneficial Effects This invention proposes a multi-time-source PTP timing circuit based on Loongson SOC. The design scheme described herein is stable and reliable, novel in approach, and solves the problem of interface incompatibility between devices during equipment development. It also provides a design concept for timing solutions in ruggedized servers and offers a new solution for the transition between old and new timing schemes. This solution has been successfully applied to a ruggedized server. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the time synchronization solution for a ruggedized server in this invention. Figure 2 This is a diagram of the overall board architecture. Detailed Implementation

[0007] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0008] General-purpose ruggedized servers typically consist of compute blades, switching blades, power blades, rear-mounted functional blades, backplanes, and chassis. Multiple compute blades are usually configured. When time synchronization is required for multiple compute blades within the server, the traditional method involves configuring a time synchronization board in the rear-mounted slot of each compute blade. This time synchronization board receives external B-code signals or PPS+TOD time message information and synchronizes the time of each compute blade point-to-point via the PCIe bus. In scenarios with multiple compute blades, a time synchronization board needs to be configured in the rear slot of each compute blade, which is unsuitable both in terms of cost and the overall time synchronization solution.

[0009] This invention takes the application of hardened server timing as a scenario. Under the condition that there are multiple external time sources, it proposes a multi-time source PTP timing circuit design method based on Loongson SOC. It can selectively receive external timing information, use PTP timing to time multiple computing blades, and use a high-stability crystal oscillator for timekeeping. The timing accuracy can reach 3.6us / h.

[0010] Figure 1 The schematic diagram of the server's overall timing solution is shown. The diagram includes: Loongson SOC, FPGA, high-stability crystal oscillator, RS422 transceiver, network card, switch, computing blades 1-6, and external clock source.

[0011] The Loongson SOC chip is connected to the FPGA and network card via the PCIe bus. The FPGA is connected to an external RS422 transceiver and a high-stability crystal oscillator. The RS422 transceiver is connected to an external clock source. The network card is connected to the switch via an Ethernet interface. At the same time, the external PTP time synchronization source and computing blades 1-6 are also connected to the switch via Ethernet interfaces. The time synchronization network is centered on the switch, and all time synchronization / timekeeping message information is distributed through the switching network. This time synchronization circuit is based on the Loongson SOC and is compatible with three time synchronization methods: B code, PPS+TOD, and PTP.

[0012] When the external time source is B code, the FPGA receives the B code signal input from the external time source, decodes it, and sends it to the SOC via the PCIe bus. After obtaining the time information, the SOC sends the time information to the switching blades via the network card by enabling the PTP master service. Each computing blade enables the PTP slave service, and the slave switching blades can then receive the time information and correct the time.

[0013] When the external time source is PPS+TOD, its time synchronization logic is similar to that of B code, only the FPGA decoding logic is different. The FPGA receives the PPS+TOD signal input from the external time source, decodes it, and sends it to the SOC via the PCIe bus. After obtaining the time information, the SOC sends the time information to the switching blades via the network card by enabling the PTP master service. Each computing blade enables the PTP slave service, and the slave switching blades can then receive the time information and correct their time.

[0014] In both of the above time synchronization methods, the FPGA will detect the interruption of the external time synchronization source. When an abnormality in the external PPS signal or the B code parsing is detected, the timekeeping mode will be entered, and a high-stability crystal oscillator will be used for timekeeping.

[0015] When the external time source is PTP, the external PTP network time information is directly connected to a port of the switching blade. At this time, the Loongson SOC and other computing blades all enable PTP slave service, receiving time information from the switching blade and correcting their time. The SOC writes the acquired PTP time message information to the FPGA's timekeeping-related registers via the PCIe bus. Simultaneously, the network card provides the FPGA with a PPS second pulse interrupt signal. When the external PTP time source is interrupted, the FPGA relies on a high-stability crystal oscillator for timekeeping. At this time, the SOC enables PTP master service, and the other computing blades maintain PTP slave service, thus receiving the SOC's timekeeping information.

[0016] 2. Implementation method Rugged servers typically adhere to certain industry standards. These standards constrain the most common components of the entire machine, similar to standardized boards such as motherboards, switching boards, and power supply boards. However, these standard boards only perform the most basic server functions, while specialized or custom-defined functions often require additional boards. The multi-time-source PTP timing circuit based on the Loongson SOC is implemented as a timing board, with the overall board architecture as follows: Figure 2 As shown.

[0017] The timing board is located on the back of the front-mounted switching blades and communicates directly with them via a bus backplane. The entire board is implemented using domestically produced chips. Key component selections include: Loongson Technology 2K1000 SOC, Fudan Microelectronics JFMK50T4 FPGA, Netcom Technology WX1860AL4 network card, Shenzhen Guowei SM3491 RS422 transceiver, Shenzhen Guowei SM41K256M16 DDR3 memory chips, Times Microelectronics B88E1111NB PHY chip, and China Electronics Technology Group Corporation 58th Research Institute CS32F103CB MCU.

[0018] The Loongson 2K1000 is a 1GHz SOC chip integrating two GS264 processor cores, various system I / O interfaces, and is primarily designed for network applications, while also being suitable for tablet and industrial control applications. The main function of using this SOC is to enable the domestically developed Linux operating system, thereby activating the PTP time synchronization service.

[0019] The Fudan Microelectronics JFMK50T4 is a small, low-cost, domestically produced FPGA chip with a high-speed transceiver. Its main function is to decode PPS+TOD or B-code information and interact with the SOC via the PCIe bus. It also provides timekeeping functionality based on a high-stability crystal oscillator.

[0020] Netcom Technology's WX1860AL4 is a domestically produced 4-channel gigabit network card chip. Its biggest feature is that it supports PTP hard timestamps and can receive PTP packets and output PPS second pulse signals.

[0021] Shenzhen Guowei's SM3491 RS422 transceiver can provide excellent level conversion for PPS+TOD signals or B-code signals on the RS422 interface.

[0022] The Shenzhen Guowei SM41K256M16 DDR3 memory chip, as the minimum system component of the 2K1000, provides excellent data storage for the operation of the SOC.

[0023] The Timesmin B88E1111NB chip is a three-speed Ethernet PHY chip with multiple operating modes to choose from. In this solution, the mode based on the switching interface (SGMII) is used, employing the PHY SGMII to copper mode, where SGMII is connected to the switching port and copper is connected to the Ethernet port of the network card.

[0024] The CS32F103CB, a domestically produced microcontroller developed by the 58th Research Institute of China Electronics Technology Group Corporation, is mainly used in this solution for functions such as controlling the power-on sequence and temperature detection of the entire board.

[0025] The timing board is mainly divided into three functional areas: the SOC minimum system functional area, the network card functional area, and the FPGA functional area. Each part works independently and exchanges information through the PCIE bus. The input of the whole board is B code or PPS+TOD, and the output is PTP network message.

[0026] This invention describes a multi-time-source PTP timing circuit design based on Loongson SOC, which offers stable and reliable performance and a novel approach. It solves the problem of interface incompatibility between devices during equipment development and provides a design concept for timing solutions in ruggedized servers, offering a new solution for the transition between old and new timing schemes. This solution has been successfully applied to a ruggedized server.

[0027] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-time-source PTP timing circuit based on Loongson SOC, characterized in that, The timing circuit includes: Loongson SOC, FPGA, high-stability crystal oscillator, RS422 transceiver, network card, switch, computing blades 1-6, and external clock source; The Loongson SOC chip is connected to the FPGA and network card via the PCIe bus. The FPGA is connected to an external RS422 transceiver and a high-stability crystal oscillator. The RS422 transceiver is connected to an external clock source. The network card is connected to the switch via an Ethernet interface. At the same time, the external PTP time synchronization source and computing blades 1-6 are also connected to the switch via Ethernet interfaces. The time synchronization network is centered on the switch, and all time synchronization / timekeeping message information is distributed through the switching network. This time synchronization circuit is based on the Loongson SOC and is compatible with three time synchronization methods: B code, PPS+TOD, and PTP.

2. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 1, characterized in that, When the external time source is B code, the FPGA receives the B code signal input from the external time source, decodes it, and sends it to the SOC via the PCIe bus. After obtaining the time information, the SOC sends the time information to the switching blades via the network card by enabling the PTP master service. Each computing blade enables the PTP slave service, and the slave switching blades can then receive the time information and correct the time.

3. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 2, characterized in that, When the external time source is PPS+TOD, the FPGA receives the PPS+TOD signal input from the external time source, decodes it, and sends it to the SOC via the PCIe bus. After the SOC obtains the time information, it sends the time information to the switching blades via the network card by enabling the PTP master service. Each computing blade enables the PTP slave service, and the slave switching blades can then receive the time information and correct the time.

4. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 3, characterized in that, After the external time source is interrupted, the FPGA will detect the interruption. When an abnormality in the external PPS signal or B code parsing is detected, the system will enter timekeeping mode and use a high-stability crystal oscillator for timekeeping.

5. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 4, characterized in that, When the external time source is PTP, the external PTP network time information is directly connected to a port of the switching blade. At this time, the Loongson SOC and other computing blades enable PTP slave service, receive time information from the switching blade, and correct the time. The SOC writes the acquired PTP time message information to the FPGA timekeeping-related registers through the PCIe bus. At the same time, the network card provides the FPGA with a PPS second pulse interrupt signal. When the external PTP time source is interrupted, the FPGA relies on a high-stability crystal oscillator to maintain timekeeping. At this time, the SOC enables PTP master service, and the other computing blades keep enabling PTP slave service, so they can receive the SOC's timekeeping information.

6. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 5, characterized in that, The timing board is located on the back of the front-inserted switching blades and communicates directly with the switching blades through the bus backplane. The entire board uses domestically produced chips.

7. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 5, characterized in that, The SOC uses Loongson Technology 2K1000, the FPGA uses Fudan Microelectronics JFMK50T4, the network card uses Netcom Technology WX1860AL4, the RS422 transceiver uses Shenzhen Guowei SM3491, the DDR3 memory chip uses Shenzhen Guowei SM41K256M16, the PHY chip uses Times Minxin B88E1111NB, and the MCU uses China Electronics Technology Group Corporation 58th Research Institute CS32F103CB.

8. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 7, characterized in that, The 2K1000 uses the domestic LINUX operating system, which enables PTP time synchronization service; the JFMK50T4 decodes PPS+TOD or B code information and interacts with the SOC via the PCIe bus, providing timekeeping functionality based on a high-stability crystal oscillator; the WX1860AL4 supports PTP hard timestamps, receives PTP messages, and outputs PPS second pulse signals; the SM3491 RS422 transceiver provides excellent level conversion for PPS+TOD or B code signals on the RS422 interface.

9. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 7, characterized in that, The B88E1111NB chip is a three-speed Ethernet PHY chip based on the SGMII switching interface mode. It uses the SGMII to copper PHY mode, where the SGMII is connected to the switching port and the copper is connected to the Ethernet port of the network card.

10. The multi-time-source PTP timing circuit based on Loongson SOC as described in claim 7, characterized in that, The timing board is divided into three functional areas: the SOC minimum system functional area, the network card functional area, and the FPGA functional area. Each part works independently and exchanges information through the PCIE bus. The input of the whole board is B code or PPS+TOD, and the output is PTP network message.

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