Synchronous control method, system and device for dual-domain controller and medium
By using a phase-locked loop module for frequency tracking and deviation detection in the automotive architecture, the problem of synchronization control between multiple domain controllers is solved, achieving fast-response and highly robust synchronization control, reducing wiring harness costs and safety hazards.
Patent Information
- Application Number
- CN202511239965.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-01
- Publication Date
- 2026-01-09
AI Technical Summary
In automotive architecture, synchronous control between multiple domain controllers suffers from time loss and signal delay, resulting in asynchronous execution objects. Existing technologies design synchronous control signals on the same domain controller, which occupies space and has low robustness.
A phase-locked loop (PLL) module is used for frequency tracking and deviation detection to compensate for the delay between slave domain controllers in real time. When it is confirmed that the slave domain controller and the master domain controller are successfully synchronized, an offset signal is returned to the master domain controller. Based on the offset signal and the synchronization command, the drive cycle of each actuator is determined to achieve synchronous control.
It achieves fast response and highly robust synchronous control, reduces wiring harness costs, simplifies wiring harness layout, saves vehicle body space, and reduces safety hazards of long wiring harnesses in vibration environments.
Smart Images
Figure CN121300145A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of vehicle technology, and in particular to a method, system, device and medium for synchronous control of a dual-domain controller. Background Technology
[0002] In current automotive architectures, body control (doors, seats, lights), thermal management, power modes, suspension, and other control systems are highly integrated into several domain controllers. However, communication between multiple domain controllers inevitably incurs time loss, and when two domain controllers need to perform synchronous control, signal delays inevitably lead to asynchrony between the executing objects. Current technologies design synchronous control signals on the same domain controller to mitigate delays, but this occupies more interior space, complicates wiring harness layout, and increases the risk of short circuits. Software filtering for compensation has low robustness and cannot truly achieve synchronous control. Summary of the Invention
[0003] The main objective of this application is to propose a dual-domain controller synchronous control method, system, device, and medium to improve the efficiency of synchronous control and save vehicle body space.
[0004] To achieve the above objectives, one aspect of this application proposes a dual-domain controller synchronization control method, the method comprising: driving a master domain controller to output a synchronization command to a slave domain controller; wherein the slave domain controller is provided with a phase-locked loop module; When it is confirmed that the domain controller has received the synchronization command, synchronization adjustment is performed through the phase-locked loop module according to the synchronization command; When it is confirmed that the slave domain controller and the master domain controller are successfully synchronized, the offset signal output by the slave domain controller to the master domain controller is adjusted. Based on the offset signal, the synchronization command is adjusted. Based on the offset signal and the adjusted synchronization command, a drive cycle is determined, and the master domain controller and the slave domain controller are driven to perform control operations on the corresponding actuators during the drive cycle.
[0005] Furthermore, the synchronization command includes the master clock signal and enable signal of the master domain controller; the process of driving the master domain controller to output the synchronization command to the slave domain controller includes: The master domain controller outputs the master clock signal and the enable signal to the slave domain controller, and drives the phase-locked loop module in the slave domain controller to operate according to the enable signal.
[0006] Furthermore, the step of performing synchronization adjustment through the phase-locked loop module according to the synchronization command includes: Obtain the slave clock signal of the slave domain controller and determine the phase difference between the master clock signal and the slave clock signal; Based on the phase difference, in the next clock cycle of the slave domain controller, the offset signal is set to a pull-up state, and the oscillation phase and oscillation frequency are adjusted until the slave clock signal is synchronized with the master clock signal.
[0007] Furthermore, the confirmation that the slave domain controller and the master domain controller have successfully synchronized includes: Determine whether the phase of the slave clock signal is the same as the phase of the master clock signal; If so, then the slave domain controller is considered to have successfully synchronized with the master domain controller.
[0008] Furthermore, adjusting the offset signal output from the domain controller to the primary domain controller includes: When the slave clock signal is synchronized with the master clock signal, the offset signal is set to a pull-down state, and the offset signal in the pull-down state is sent to the master domain controller.
[0009] Furthermore, adjusting the synchronization command based on the offset signal includes: Identify the offset signal and determine whether the offset signal has changed from an up state to a down state; If so, the main domain controller is adjusted to enter the actuator control state, and the enable signal is adjusted accordingly; Based on the adjusted enable signal, the slave domain controller is adjusted to enter the actuator control state.
[0010] Furthermore, determining the drive cycle based on the offset signal and the adjusted synchronization command includes: Calculate the time difference between the offset signal and the adjusted enable signal, and determine the drive cycle in the master clock signal based on the time difference.
[0011] To achieve the above objectives, another aspect of this application proposes a dual-domain controller synchronous control system, the system comprising: The first synchronization module is used to drive the master domain controller to output synchronization commands to the slave domain controller; wherein, the slave domain controller is equipped with a phase-locked loop module. The second synchronization module is used to perform synchronization adjustment through the phase-locked loop module according to the synchronization instruction when it is confirmed that the slave domain controller has received the synchronization instruction; The third synchronization module is used to adjust the offset signal output from the slave domain controller to the master domain controller when it is confirmed that the slave domain controller and the master domain controller are successfully synchronized. The fourth synchronization module is used to adjust the synchronization command according to the offset signal, determine the drive cycle according to the offset signal and the adjusted synchronization command, and drive the master domain controller and the slave domain controller to perform control operations on the corresponding actuators during the drive cycle.
[0012] To achieve the above objectives, another aspect of the embodiments of this application proposes a vehicle control device, including a memory, a processor, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the above-described dual-domain controller synchronous control method.
[0013] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described dual-domain controller synchronization control method.
[0014] The embodiments of this application include at least the following beneficial effects: This application provides a dual-domain controller synchronization control method, system, device, and medium. This scheme, based on the synchronization command output by the master domain controller, performs frequency tracking and deviation detection through a phase-locked loop module, and compensates for the delay between slave domain controllers in real time. When it is confirmed that the slave domain controller and the master domain controller are successfully synchronized, an offset signal is returned to the master domain controller. Based on the offset signal and the synchronization command, the drive cycle of each actuator is determined, so that each actuator can be controlled simultaneously. It has a rapid response and strong robustness, fundamentally solves the problem of asynchronous control signals between dual controllers, reduces wiring harness costs, simplifies wiring harness layout, saves vehicle body space, and reduces safety hazards such as wear, breakage, and short circuits of long wiring harnesses in vibration environments. Attached Figure Description
[0015] Figure 1 This is a flowchart of the dual-domain controller synchronization control method provided in the embodiments of this application; Figure 2 This is a schematic diagram of the phase-locked loop module of the dual-domain controller synchronous control method provided in this application embodiment; Figure 3 This is a waveform diagram showing the signal conditioning of the phase-locked loop module in the dual-domain controller synchronous control method provided in this application embodiment; Figure 4 This is a schematic diagram of the hardware structure framework of the vehicle control device provided in the embodiments of this application. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.
[0017] It is understood that the terms "first," "second," etc., used in this application may be used to describe various concepts herein, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of embodiments of this application, Ethernet signaling information may also be referred to as interface signaling information, and similarly, interface signaling information may also be referred to as Ethernet signaling information. Depending on the context, the words "if" or "when" as used herein may be interpreted as "when," "in response to a determination," or "in the event of a determination."
[0018] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.
[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0020] In some embodiments of one aspect of the present invention Figure 1 This is an optional flowchart of the dual-domain controller synchronization control method provided in the embodiments of this application. Figure 1 The method may include, but is not limited to, steps S100 to S400.
[0021] Step S100: Drive the master domain controller to output a synchronization command to the slave domain controller; wherein the slave domain controller is equipped with a phase-locked loop module.
[0022] Step S200: When it is confirmed that a synchronization command has been received from the domain controller, synchronization adjustment is performed through the phase-locked loop module according to the synchronization command.
[0023] Step S300: When it is confirmed that the slave domain controller and the master domain controller are successfully synchronized, adjust the offset signal output from the slave domain controller to the master domain controller.
[0024] Step S400: Adjust the synchronization command according to the offset signal, determine the drive cycle according to the offset signal and the adjusted synchronization command, and drive the master domain controller and slave domain controller to perform control operations on the corresponding actuators during the drive cycle.
[0025] Steps S100 to S400 as shown in the embodiments of this application involve frequency tracking and deviation detection through a phase-locked loop module to compensate for the delay between slave domain controllers in real time. When it is confirmed that the slave domain controller and the master domain controller are successfully synchronized, an offset signal is returned to the master domain controller. Based on the offset signal and the synchronization command, the drive cycle of each actuator is determined so that the actuators can be controlled simultaneously. This results in rapid response, strong robustness, and fundamentally solves the problem of asynchronous control signals between dual controllers. It also reduces wiring harness costs, simplifies wiring harness layout, saves vehicle body space, and reduces safety hazards such as wear, breakage, and short circuits of long wiring harnesses in vibration environments.
[0026] In some embodiments of S100, the master domain controller provides synchronization instructions to the slave domain controllers to achieve synchronized execution control. The slave domain controllers return offset signals to the master domain controller so that the master domain controller can monitor the slave clock signals of the slave domain controllers.
[0027] Synchronization commands include: a master clock signal and an enable signal for the master domain controller. The master clock signal serves as a reference for the slave domain controllers to adjust their slave clock signals. The enable signal is a control signal that enables synchronization between the master and slave domain controllers.
[0028] The domain controller has a phase-locked loop (PLL) module. The master clock signal is input to the PLL module to adjust the clock signal inside the domain controller, i.e., to adjust the slave clock signal.
[0029] In some embodiments of S200, it is determined whether the domain controller has received a synchronization command, that is, whether the domain controller has received a master clock signal.
[0030] If so, it is assumed that the master clock signal has been input to the phase-locked loop module. The phase-locked loop module inside the domain controller controls the frequency and phase of the oscillation signal in the loop according to the synchronization command, so that the oscillation signal is synchronized to the master clock signal for synchronization adjustment.
[0031] If not, the primary domain controller will send a synchronization command to the secondary domain controller again.
[0032] Specifically, refer to Figure 2 and Figure 3The phase-locked loop (PLL) module includes a phase detector, a low-pass filter, and a via oscillator. The phase detector in the domain controller detects a phase shift between the input master clock signal Vclk and the output slave clock signal Vent. Based on this phase difference Δt, a detection signal is generated. The low-pass filter removes high-frequency components, retaining only low-frequency components. The offset signal Vcont is pulled up, causing it to rise and adjusting the oscillation frequency and phase of the voltage-controlled oscillator (VCO) to make the oscillation faster and reduce the phase difference. Through repeated phase detection and adjustment, the frequency and phase of the VCO output signal eventually match the input master clock signal Vclk, at which point the PLL module enters a locked state.
[0033] In some embodiments of S300, it is determined whether the phase of the slave clock signal is the same as the phase of the master clock signal. If so, it is confirmed that the slave domain controller and the master domain controller have successfully synchronized. If not, it is considered that the slave domain controller and the master domain controller have failed to synchronize, and the phase-locked loop module enters the running state, returning to S200 for resynchronization adjustment.
[0034] When the slave domain controller and the master domain controller are successfully synchronized, the slave domain controller returns an offset signal to the master domain controller so that the master domain controller can monitor the slave clock signal of the slave domain controller and adjust the offset signal output by the slave domain controller to the master domain controller. The master domain controller can also monitor the slave clock signal of the slave domain controller and confirm that the slave clock signal is synchronized with the master clock signal based on the offset signal.
[0035] In some embodiments of S400, by identifying changes in the S300 offset signal, the master domain controller confirms that the clock synchronization of the slave domain controller is successful, then adjusts the enable signal in the synchronization command, and simultaneously controls the master domain controller to enter the actuator control state.
[0036] The master domain controller sends the adjusted enable signal to the slave domain controller, controlling the slave domain controller to also enter the actuator control state, thereby enabling it to quickly perform control operations on the corresponding actuators. Based on the changing offset signal and the adjustment synchronization command, the time difference between the two signals is determined, and the drive cycle is determined by this time difference.
[0037] During this drive cycle, the master domain controller performs control operations on the connected actuators, while the slave domain controllers also perform control operations on the connected actuators, thereby achieving synchronous control.
[0038] In other words, after identifying the changes in the S300 offset signal, the enable signal is pulled high and set to 1. The master domain controller and the slave domain controller simultaneously perform control operations on the actuator during the Nth cycle of the master clock signal (slave clock signal). N depends on the time difference between the offset signal and the enable signal.
[0039] In some embodiments of this invention, the output process of the synchronization instruction in S100 specifically includes: S110 drives the master domain controller to output the master clock signal and enable signal to the slave domain controller. Based on the enable signal, it drives the phase-locked loop module in the slave domain controller to run.
[0040] In this embodiment, the synchronization instructions include: a master clock signal and an enable signal for the master domain controller. The master clock signal is used as a reference for the slave domain controllers to adjust their slave clock signals. The enable signal is a control signal that enables the master and slave domain controllers to synchronize.
[0041] The master domain controller provides the master clock signal and enable signal to the slave domain controllers. The slave domain controllers return offset signals to the master domain controller so that the master domain controller can monitor the slave clock signal of the slave domain controllers.
[0042] The domain controller has a phase-locked loop (PLL) module. The master clock signal is input to the PLL module to adjust the clock signal inside the domain controller, i.e., to adjust the slave clock signal.
[0043] Once the enable signal is received, the phase-locked loop (PLL) module enters the running state and begins operation.
[0044] Reference Figure 2 and Figure 3 In some embodiments of this invention, the output process of the synchronization instruction in S200 specifically includes: S210, acquire the slave clock signal from the domain controller and determine the phase difference between the master clock signal and the slave clock signal; S220, based on the phase difference, sets the offset signal to a pull-up state in the next clock cycle of the slave domain controller, and adjusts the oscillation phase and oscillation frequency until the slave clock signal and the master clock signal are synchronized.
[0045] In this embodiment, when the slave domain controller receives the master clock signal, it acquires the slave clock signal of the slave domain controller.
[0046] In the phase-locked loop module inside the domain controller, the slave clock signal of the domain controller is obtained. With the master clock signal as a reference, the phase offset between the master clock signal and the slave clock signal is detected, and the phase difference between the master clock signal and the slave clock signal is determined.
[0047] Reference Figure 3Using this phase difference, at the rising edge of the next clock cycle of the slave domain controller, the offset signal is set to a pull-up state, i.e., the offset signal is set to 1. Based on the pull-up offset signal, the frequency and phase of the oscillation signal in the control loop are adjusted to increase the oscillation phase and frequency, making the oscillation faster and reducing the phase difference between the two, until the slave clock signal and the master clock signal are synchronized.
[0048] Specifically, refer to Figure 2 and Figure 3 The phase-locked loop (PLL) module includes a phase detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase detector in the domain controller detects a phase shift between the input master clock signal Vclk and the output slave clock signal Vent. Based on this phase difference Δt, a detection signal is generated. The low-pass filter removes high-frequency components, retaining only low-frequency components. The offset signal Vcont is pulled up, causing it to rise and adjusting the oscillation frequency and phase of the VCO to make the oscillation faster and reduce the phase difference. Through repeated phase detection and adjustment, the frequency and phase of the output slave clock signal and the input master clock signal become synchronized, at which point the PLL module enters a locked state.
[0049] In some embodiments of this invention, in step S300, the adjustment process of the offset signal specifically includes: S310, determine whether the phase of the slave clock signal is the same as the phase of the master clock signal; If S320 is correct, then the synchronization between the slave domain controller and the master domain controller is considered successful.
[0050] S330 sets the offset signal to a pull-down state when the slave clock signal and the master clock signal are synchronized, and sends the offset signal in the pull-down state to the master domain controller.
[0051] In this embodiment, it is determined whether the slave clock signal is in phase with the master clock signal. If so, the slave domain controller and the master domain controller are confirmed to be successfully synchronized. If not, the slave domain controller and the master domain controller are considered to have failed to synchronize, and the phase-locked loop module enters the running state and returns to S200 for resynchronization adjustment.
[0052] When the synchronization between the slave domain controller and the master domain controller is confirmed to be successful, the slave domain controller returns an offset signal to the master domain controller. This allows the master domain controller to monitor the slave clock signal of the slave domain controller, adjust the offset signal output from the slave domain controller to the master domain controller, and set the offset signal to a pull-down state (i.e., switch from a pull-up state to a pull-down state). The master domain controller then sends the offset signal in the pull-down state to the master domain controller. The master domain controller monitors the slave clock signal of the slave domain controller and can also confirm the synchronization between the slave clock signal and the master clock signal based on this offset signal.
[0053] The offset signal can be pulled down to 0, or pulled up to 1.
[0054] In some embodiments of this invention, in S400, the process of determining the driving cycle specifically includes: S410, identify the offset signal and determine whether the offset signal has switched from the pull-up state to the pull-down state; S420, if so, then adjust the main domain controller to enter the actuator control state and adjust the enable signal; S430, based on the adjusted enable signal, adjusts the domain controller to enter the actuator control state.
[0055] S440 calculates the time difference between the offset signal and the adjusted enable signal, and determines the drive cycle in the master clock signal based on the time difference.
[0056] In this embodiment, when the primary domain controller receives an offset signal in a pull-down state, it identifies changes in the offset signal.
[0057] When it is determined whether the offset signal has changed from the pull-up state to the pull-down state, that is, when it is determined that the offset signal has changed from set to 1 to set to 0, the master domain controller receives the change in the offset signal and enters the actuator control state, so that it can quickly perform control operations on the corresponding actuator. The master domain controller adjusts the enable signal, pulls the enable signal high to set to 1, and sends the adjusted enable signal to the slave domain controller. Through the adjusted enable signal, that is, the enable signal set to 1, the slave domain controller is controlled to also enter the actuator control state.
[0058] Based on the changing offset signal and the adjusted enable signal, the time difference between the two signals is determined. This time difference is then used to determine the drive cycle within the master clock signal. Since the master clock signal and slave clock signal are synchronized at this time, this time difference can also be used to determine the drive cycle within the slave clock signal.
[0059] During this drive cycle, the master domain controller performs control operations on the connected actuators, while the slave domain controllers also perform control operations on the connected actuators, thereby achieving synchronous control.
[0060] In other words, after identifying the changes in the S300 offset signal, the enable signal is pulled high and set to 1. The master domain controller and the slave domain controller simultaneously perform control operations on the actuator during the Nth cycle of the master clock signal (slave clock signal). N depends on the time difference between the offset signal and the enable signal.
[0061] Another embodiment of this application provides a dual-domain controller synchronous control system, including: a first synchronization module, a second synchronization module, a third synchronization module and a fourth synchronization module.
[0062] The first synchronization module is used to drive the master domain controller to output synchronization commands to the slave domain controller; wherein, the slave domain controller is equipped with a phase-locked loop module; The second synchronization module is used to perform synchronization adjustment through the phase-locked loop module according to the synchronization command when it is confirmed that a synchronization command has been received from the domain controller. The third synchronization module is used to adjust the offset signal output from the slave domain controller to the master domain controller when it is confirmed that the slave domain controller and the master domain controller are successfully synchronized. The fourth synchronization module is used to adjust the synchronization command according to the offset signal, determine the drive cycle according to the offset signal and the adjusted synchronization command, and drive the master domain controller and slave domain controller to perform control operations on the corresponding actuators during the drive cycle.
[0063] The system proposed in this application can reduce wiring harness costs, simplify wiring harness layout, save vehicle body space, and reduce safety hazards such as wear, breakage, and short circuits in long wiring harnesses under vibration environments. The system has strong real-time performance, robustness, and adaptability. It provides real-time compensation for delays between controllers without requiring additional external circuitry, resulting in low cost and a simple method.
[0064] Another embodiment of this application provides a vehicle control device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned dual-domain controller synchronous control method. This vehicle control device can be any smart terminal, including tablet computers, in-vehicle computers, etc.
[0065] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.
[0066] Please see Figure 4 , Figure 4 The hardware structure of a vehicle control device according to another embodiment is illustrated. The vehicle control device includes: The processor can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to achieve the technical solutions provided in the embodiments of this application. The memory can be implemented in the form of read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory and called and executed by the processor using the dual-domain controller synchronization control method of the embodiments of this application. Input / output interfaces are used to implement information input and output; The communication interface is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). A bus is used to transfer information between various components of a device, such as processors, memory, input / output interfaces, and communication interfaces. The processor, memory, input / output interfaces, and communication interfaces communicate with each other within the device via a bus.
[0067] This invention also provides a vehicle, including the dual-domain controller synchronous control method described in the above embodiments.
[0068] The vehicle can be a private car, such as a sedan, SUV, MPV, or pickup truck. It can also be a commercial vehicle, such as a van, bus, small truck, or large semi-trailer. The vehicle must have an electric motor capable of outputting power or acting as a generator to store mechanical energy. When the vehicle is a new energy vehicle, it can be a hybrid or a pure electric vehicle.
[0069] Since the vehicle applies all the technical solutions of the above-described vehicle control device, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.
[0070] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described dual-domain controller synchronization control method.
[0071] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.
[0072] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0073] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0074] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.
[0075] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0076] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.
[0077] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0078] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0079] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0080] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0081] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A dual-domain controller synchronous control method, characterized in that, The method includes: The master domain controller outputs synchronization commands to the slave domain controller; wherein the slave domain controller is equipped with a phase-locked loop module. When it is confirmed that the domain controller has received the synchronization command, synchronization adjustment is performed through the phase-locked loop module according to the synchronization command; When it is confirmed that the slave domain controller and the master domain controller are successfully synchronized, the offset signal output by the slave domain controller to the master domain controller is adjusted. Based on the offset signal, the synchronization command is adjusted. Based on the offset signal and the adjusted synchronization command, a drive cycle is determined, and the master domain controller and the slave domain controller are driven to perform control operations on the corresponding actuators during the drive cycle.
2. The dual-domain controller synchronous control method according to claim 1, characterized in that, The synchronization command includes the master clock signal and enable signal of the master domain controller; The process of driving the master domain controller to output synchronization commands to the slave domain controller includes: The master domain controller outputs the master clock signal and the enable signal to the slave domain controller, and drives the phase-locked loop module in the slave domain controller to operate according to the enable signal.
3. The dual-domain controller synchronous control method according to claim 2, characterized in that, The step of performing synchronization adjustment through the phase-locked loop module according to the synchronization command includes: Obtain the slave clock signal of the slave domain controller and determine the phase difference between the master clock signal and the slave clock signal; Based on the phase difference, in the next clock cycle of the slave domain controller, the offset signal is set to a pull-up state, and the oscillation phase and oscillation frequency are adjusted until the slave clock signal is synchronized with the period of the master clock signal.
4. The dual-domain controller synchronous control method according to claim 3, characterized in that, The confirmation that the slave domain controller and the master domain controller have successfully synchronized includes: Determine whether the phase of the slave clock signal is the same as the phase of the master clock signal; If so, then the slave domain controller is considered to have successfully synchronized with the master domain controller.
5. The dual-domain controller synchronous control method according to claim 3, characterized in that, The adjustment of the offset signal output from the slave domain controller to the master domain controller includes: When the slave clock signal is synchronized with the master clock signal, the offset signal is set to a pull-down state, and the offset signal in the pull-down state is sent to the master domain controller.
6. The dual-domain controller synchronous control method according to claim 2, characterized in that, The step of adjusting the synchronization command according to the offset signal includes: Identify the offset signal and determine whether the offset signal has changed from an up state to a down state; If so, the main domain controller is adjusted to enter the actuator control state, and the enable signal is adjusted accordingly; Based on the adjusted enable signal, the slave domain controller is adjusted to enter the actuator control state.
7. The dual-domain controller synchronous control method according to claim 6, characterized in that, Determining the drive cycle based on the offset signal and the adjusted synchronization command includes: Calculate the time difference between the offset signal and the adjusted enable signal, and determine the drive cycle in the master clock signal based on the time difference.
8. A dual-domain controller synchronous control system, characterized in that, The system includes: The first synchronization module is used to drive the master domain controller to output synchronization commands to the slave domain controller; wherein, the slave domain controller is equipped with a phase-locked loop module. The second synchronization module is used to perform synchronization adjustment through the phase-locked loop module according to the synchronization instruction when it is confirmed that the slave domain controller has received the synchronization instruction; The third synchronization module is used to adjust the offset signal output from the slave domain controller to the master domain controller when it is confirmed that the slave domain controller and the master domain controller are successfully synchronized. The fourth synchronization module is used to adjust the synchronization command according to the offset signal, determine the drive cycle according to the offset signal and the adjusted synchronization command, and drive the master domain controller and the slave domain controller to perform control operations on the corresponding actuators during the drive cycle.
9. A vehicle control device, characterized in that, It includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the dual-domain controller synchronous control method according to any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the dual-domain controller synchronous control method as described in any one of claims 1 to 7.