A multi-channel parallel gang mode digital ring implementation method

Abstract

The application relates to the technical field of power supply systems, and discloses a multi-channel parallel Gang mode digital ring implementation method, which comprises the following steps: configuring uniform voltage and current clamping values for a plurality of VI source channel modules; starting all the modules to independently execute control tasks; each module independently executes high-speed digital closed-loop control according to real-time feedback data of the module to update power output; through the independent control, self-regulated current sharing of total load current is realized without direct coordination among the modules; during operation, the states of the modules are continuously monitored, and when a fault is detected, the faulty module is isolated, and the remaining modules continue to supply power. The application provides a multi-channel parallel scheme, wherein each VI source channel module independently executes high-speed digital closed-loop control, and the technical effect that total load current is self-regulated and dynamically shared among the modules is achieved.

Description

Technical Field

[0001] This invention relates to the field of power supply system technology, specifically to a method for implementing a digital ring in a multi-channel parallel Gang mode. Background Technology

[0002] In modern high-tech fields, many applications place extremely high demands on supply current. For example, automated test equipment (ATE) requires a high-precision VI source capable of outputting extremely high current when performing wafer-level testing on large-scale integrated circuits or in semiconductor aging screening experiments. The output capability of a single VI source module is often limited and cannot meet this requirement.

[0003] To enable multiple parallel modules to work collaboratively, existing technologies employ several specific current sharing schemes. One approach uses an analog current sharing bus. This method connects all modules via a dedicated physical bus that provides a common analog reference signal. Each module adjusts its output based on this signal to achieve load distribution. Another approach is a digital master-slave control architecture. This architecture features a master controller that issues precise and coordinated control commands to all subordinate VI source modules via a high-speed communication bus, thereby orchestrating the output behavior of the entire parallel system.

[0004] However, these existing technologies have revealed several insurmountable defects in practical applications. First, both analog current-sharing buses and digital master-slave communication introduce tight coupling. This design limits the reliability of the entire system to the common bus or the master controller. Once this critical node fails, the entire parallel system will be completely paralyzed, and scalability is also limited. Second, in the digital control of high-precision VI sources, switching between constant voltage (CV) and constant current (CC) modes is a challenge. The two control loops usually operate independently. When the operating point switches, the internal control state of the newly activated loop is disconnected from the actual output of the system. This mismatch causes the controller to perform drastic compensation at the moment of switching, resulting in severe voltage or current spikes at the output, which can easily damage the measured load. Finally, these tightly coupled systems generally lack fault mitigation capabilities. When a single module fails, it cannot be effectively isolated and tends to propagate the fault to the entire parallel bus. The remaining healthy modules also cannot automatically take over and redistribute the load, ultimately leading to overall system failure instead of smooth degraded operation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for implementing a digital ring in a multi-channel parallel Gang mode, thereby solving the technical problems of low reliability and poor scalability caused by tight coupling in existing parallel systems, output disturbances during CV / CC mode switching, and the lack of fault mitigation mechanisms.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for implementing a multi-channel parallel Gang mode digital ring, comprising the following steps:

[0007] Parameter configuration and initialization are performed on multiple VI source channel modules. The parameter configuration and initialization includes configuring a unified voltage setting value and a unified current clamping value to obtain multiple configured VI source channel modules.

[0008] Based on the configured parameters of the multiple configured VI source channel modules, the multiple configured VI source channel modules are started. After starting, the multiple configured VI source channel modules simultaneously enable output and independently begin to execute control tasks.

[0009] During the process of multiple configured VI source channel modules independently executing the control task, each VI source channel module independently executes high-speed digital closed-loop control. The high-speed digital closed-loop control is used to calculate and update the control commands for the power output modules of each VI source channel module based on the real-time feedback data of each VI source channel module.

[0010] The high-speed digital closed-loop control is executed independently by multiple VI source channel modules. While maintaining the parallel point voltage together, the total load current is autonomously shared among the multiple VI source channel modules. The autonomous current sharing does not require direct coordination between the multiple VI source channel modules.

[0011] During the autonomous current sharing process of the multiple VI source channel modules, the operating status of the multiple VI source channel modules is monitored, and when any VI source channel module is detected to have failed, the failed VI source channel module is isolated from the parallel system, and the remaining VI source channel modules continue to supply power to the load under test.

[0012] Preferably, the parameter configuration and initialization of multiple VI source channel modules includes:

[0013] Configure the core operating parameters of multiple VI source channel modules, including the voltage setting value, forward current clamping value, and reverse current clamping value;

[0014] Configure the loop control parameters of the digital control core modules inside the multiple VI source channel modules;

[0015] Configure the core operating parameters of all the multiple VI source channel modules participating in parallel to have exactly the same value.

[0016] Preferably, activating the multiple configured VI source channel modules includes:

[0017] Multiple configured VI source channel modules receive output enable commands;

[0018] Each of the multiple configured VI source channel modules independently executes a controlled output ramp start-up process using its own digital control core module. During the output ramp start-up process, the digital control core module generates an internal ramp setpoint that increases linearly with time as the real-time target of the voltage loop PID controller.

[0019] When the internal ramp setting value reaches or exceeds the final voltage setting value, the digital control core module fixes the control target of the voltage loop to the voltage setting value, so that the VI source channel module enters the steady-state control stage.

[0020] Preferably, each of the VI source channel modules independently performs high-speed digital closed-loop control, including:

[0021] At the beginning of each control cycle, the feedback sampling module of the VI source channel module acquires the current voltage feedback value and current feedback value and transmits them to the digital control core module.

[0022] The parallel PID controllers inside the digital control core module, namely the PID controller for constant voltage control and the PID controller for current clamping, perform calculations simultaneously to generate their respective candidate control output values.

[0023] The mode arbitration logic inside the digital control core module selects from the candidate control output values ​​of the parallel PID controller based on the current feedback value to determine the preliminary effective control output for the current cycle.

[0024] The initial effective control output is determined as the final control word for the current cycle and sent to the power output module.

[0025] Preferably, the autonomous current sharing of the total load current among the multiple VI source channel modules includes:

[0026] A unified voltage control benchmark is established, and all VI source channel modules aim at constant voltage mode, independently executing the high-speed digital closed-loop control to maintain their respective output voltage at the voltage set value.

[0027] By utilizing the physical constraints of the parallel connection point for dynamic adjustment, all the VI source channel modules jointly participate in the dynamic adjustment process to stably maintain the voltage of the parallel connection point near the voltage set value.

[0028] During the dynamic adjustment process, the total load current is distributed to each of the VI source channel modules to achieve balanced current distribution in constant voltage mode.

[0029] Preferably, the step of monitoring the operating status of the multiple VI source channel modules and isolating the faulty VI source channel module from the parallel system when a fault is detected, allowing the remaining VI source channel modules to continue supplying power to the load under test, includes:

[0030] Each of the VI source channel modules independently reports status data, which is then reported to the host computer or system controller.

[0031] The host computer or system controller performs fault diagnosis on the received status data, and after determining that a certain VI source channel module has failed, sends an independent output disable command to the failed VI source channel module.

[0032] Upon receiving the output disable command, the malfunctioning VI source channel module performs a safety isolation operation, causing its output terminal to be in a high impedance state with the parallel bus.

[0033] The remaining healthy VI source channel modules detect the deviation of the parallel point voltage and independently increase their output to compensate, so that the total load current is automatically redistributed among the remaining healthy VI source channel modules.

[0034] Preferably, the parallel PID controller within the digital control core module includes:

[0035] A Force Servitude PID controller for constant voltage control, the Force Servitude PID controller performing calculations based on the voltage error between the voltage setpoint and the voltage feedback value;

[0036] A Positive Clamp PID controller for positive current clamping, the Positive Clamp PID controller calculating based on the current error between the positive current clamping value and the current feedback value;

[0037] A Negative Clamp PID controller for reverse current clamping, the Negative Clamp PID controller calculating based on the current error between the reverse current clamping value and the current feedback value.

[0038] Preferably, the independent execution of high-speed digital closed-loop control by each VI source channel module further includes the execution of a bumpless switching mechanism, the bumpless switching mechanism including:

[0039] After the mode arbitration logic determines the preliminary effective control output based on the current feedback value;

[0040] The value of the initial effective control output is forcibly updated to the historical output state of the PID controller that was not selected.

[0041] This ensures that the reference value used for incremental calculation by the unselected PID controller in the next control cycle is consistent with the value of the initial effective control output.

[0042] Preferably, the autonomous current sharing of the total load current among the multiple VI source channel modules further includes achieving a smooth transition to constant current mode, the smooth transition including:

[0043] When the total load current increases, and the output current of a certain VI source channel module reaches its set current clamping value first, the mode arbitration logic of the certain VI source channel module automatically switches from constant voltage mode to constant current mode.

[0044] The remaining VI source channel modules, which are still in constant voltage mode, attempt to compensate for the drop in the parallel point voltage by increasing their own output;

[0045] Until all the VI source channel modules are switched to the constant current mode in sequence, so that each of the VI source channel modules outputs the current clamping value, the current sharing in the constant current mode is realized.

[0046] Preferably, the feedback sampling module acquires the current voltage feedback value by:

[0047] The voltage across the load under test is acquired by setting up a pair of high-impedance voltage sampling terminals independent of the power output terminal.

[0048] The voltage difference between the high-impedance voltage sampling terminals is accurately measured using a differential amplifier.

[0049] The output of the differential amplifier is converted into the voltage feedback value via an analog-to-digital converter.

[0050] This invention provides a method for implementing a multi-channel parallel Gang mode digital ring. It has the following advantages:

[0051] 1. This invention provides a multi-channel parallel connection scheme, in which each VI source channel module independently executes its high-speed digital closed-loop control, achieving the technical effect of autonomous and dynamic current sharing of the total load current among the modules. Unlike the parallel connection method in the prior art that relies on analog current sharing bus or complex master-slave communication, this invention solves the defects of high system complexity, low reliability and difficulty in expansion in the traditional scheme.

[0052] 2. This invention sets up mode arbitration logic and a disturbance-free switching mechanism in the digital control core module. When the system switches between constant voltage and constant current modes, the historical state of the inactive PID controller is forcibly synchronized, realizing a smooth and disturbance-free mode transition. This avoids the problem of output step and disturbance caused by inconsistent historical states of the PID controller in the prior art, which significantly improves the safety of the tested load.

[0053] 3. Through monitoring and fault isolation steps, this invention safely isolates any module when a fault is detected. The remaining healthy VI source channel modules will immediately and independently compensate and automatically redistribute the total load current, realizing the fault-mitigated operation of the system. This overcomes the serious defect in traditional parallel systems where a single module failure may lead to the failure of the entire parallel bus and the complete collapse of the system, greatly improving the overall reliability of the system. Attached Figure Description

[0054] Figure 1 This is a single-channel functional block diagram according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of the system architecture according to an embodiment of the present invention;

[0056] Figure 3 This is a flowchart of a method according to an embodiment of the present invention.

[0057] Explanation of icon numbers:

[0058] 10. VI source channel module; 20. Load under test; 30. Digital control core module; 40. Power output module; 50. Feedback sampling module; 301. Force Servitude PID controller; 302. Positive Clamp PID controller; 303. Negative Clamp PID controller. Detailed Implementation

[0059] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] Reference Figure 2 , Figure 2 This is a schematic diagram of a multi-channel parallel Gang mode system architecture according to an embodiment of the present invention. The system may include multiple VI source channel modules 10 with identical structure and function, and a load under test 20. In this embodiment, a first VI source channel module 10a, a second VI source channel module 10b, and up to the Nth VI source channel module 10n are shown, where N is an integer greater than or equal to 2. To clearly illustrate its internal structure, the first VI source channel module 10a is shown as an example. The first VI source channel module 10a internally includes: a digital control core module 30, a power output module 40, and a feedback sampling module 50. The other VI source channel modules in the system, such as the second VI source channel module 10b to the Nth VI source channel module 10n, have the exact same internal structure as the first VI source channel module 10a, and are shown as lumped modules in the figure for clarity.

[0061] Each VI source channel module 10 is independent at the control level, and there is no direct communication bus or analog current sharing bus between the VI source channel modules 10 for current sharing control. The output terminals 11 of each VI source channel module 10 are electrically connected in parallel externally and are collectively connected to the load under test 20.

[0062] Reference Figure 1 , Figure 1 This is a functional block diagram of a single-channel digital VI source according to an embodiment of the present invention. The diagram shows in detail the specific composition of each module inside the VI source channel module 10.

[0063] Specifically, the digital control core module 30 in Figure 1 The system comprises multiple functional parts, including: a Force Servitude PID controller 301 for constant voltage control, a Positive Clamp PID controller 302 for positive current clamping, and a Negative Clamp PID controller 303 for reverse current clamping. These three PID controllers operate in parallel. The digital control core module 30 also includes mode arbitration logic for selecting one output from the three PID controllers based on the system's operating state. Figure 1(This is illustrated in the diagram as Clamp Selection and ForceSelection).

[0064] Power output module 40 in Figure 1 The power output module 40 consists of components such as a digital-to-analog converter (DAC), resistors (R1, R2), and amplifiers (AMP). The power output module 40 receives the final control word output from the digital control core module 30 and converts it into the analog voltage or current signal required to drive the load under test 20, which is then output through the output terminal (e.g., FH, FL).

[0065] Feedback sampling module 50 in Figure 1 The system consists of a voltage feedback path and a current feedback path. Each of these paths contains its own analog-to-digital converter (ADC), which is responsible for converting the actual output voltage and output current of the power output module 40 into digital signals, and providing them as voltage feedback signals and current feedback signals to the digital control core module 30, respectively.

[0066] In a preferred embodiment, to eliminate the impact of the voltage drop across the output path caused by the large current on measurement accuracy, the voltage feedback path can employ a four-wire (Kelvin) sampling structure. Specifically, as... Figure 1 As shown, a pair of high-impedance voltage sampling terminals (SH, SL) can be set independently of the power output terminals (FH, FL) and directly connected to the two ends of the load under test 20. This path may also include a high common-mode rejection ratio differential amplifier (Diff AMP) for accurately measuring the voltage difference between SH and SL, and its output is then sent to the digital control core module 30 via an analog-to-digital converter (ADC). This method can greatly improve the setting accuracy and stability of the system output voltage.

[0067] In summary, the digital control core module 30, the power output module 40, and the feedback sampling module 50 together constitute a complete, high-speed digital closed-loop control system for precisely controlling the output of the VI source channel module 10.

[0068] Reference Figure 3 , Figure 3 This is an overall flowchart of a digital ring implementation method according to an embodiment of the present invention. The present invention provides a method for implementing a multi-channel parallel Gang mode digital ring, comprising the following steps:

[0069] S100 configures and initializes the parameters of all VI source channel modules 10 participating in parallel connection. The configured parameters include unified voltage setting value, current clamping value and digital loop control parameters.

[0070] S200, start the multi-channel parallel system, all VI source channel modules 10 simultaneously enable output and independently start executing control tasks;

[0071] S300, each VI source channel module 10 independently performs high-speed digital closed-loop control, wherein the digital control core module 30 of the VI source channel module 10 performs calculations and updates the control commands to the power output module 40 based on real-time data from its feedback sampling module 50.

[0072] S400, the system realizes autonomous load current sharing, wherein, during the process of all VI source channel modules 10 jointly maintaining the parallel point voltage, the total load current is dynamically distributed to each VI source channel module 10, and this current sharing process does not require direct coordination between VI source channel modules 10.

[0073] S500 monitors the operating status of each VI source channel module 10, and when a fault is detected in any VI source channel module 10, it isolates the faulty VI source channel module 10 from the parallel system, and the remaining VI source channel modules 10 continue to supply power to the load under test 20.

[0074] The steps described above in the embodiments of the present invention will be explained in detail below.

[0075] In step S100, parameters are configured and initialized for all VI source channel modules 10 that will participate in parallel connection. This step may further include the following sub-steps:

[0076] S101, configure the core operating parameters of each VI source channel module 10. These parameters define the target range of output voltage and current for each individual VI source channel module 10. Specifically, the core operating parameters may include: voltage setpoint. Forward current clamping value This is used to limit the maximum value of the external output current of the VI source channel module 10, which is usually a positive number; and the reverse current clamping value. This is used to limit the maximum value of the current absorbed by the VI source channel module 10, and is usually a negative number or zero.

[0077] S102, configure the loop control parameters of the digital control core module 30 inside each VI source channel module 10. In a preferred embodiment, to optimize dynamic response and avoid output shock caused by step changes in setpoints, the PID controller inside the digital control core module 30 employs an incremental PID algorithm with differential feedforward. The output of this algorithm is the increment of the control quantity. The calculation method is as follows:

[0078] ;

[0079] Subsequently, the final control output value for the current cycle is:

[0080] ;

[0081] in, This is the current index of the discrete time series; and They were respectively in the second The and the first The controller output value for each control cycle; and They were respectively in the second The and the first Error signal for each control cycle; and They were respectively in the second The and the first Feedback measurements for each control cycle, when used in a voltage loop. Corresponding voltage feedback value When used in a current loop, Corresponding current feedback value ; This is the proportionality coefficient; The integral coefficient; These are the differential coefficients; This refers to the system's control cycle.

[0082] Since the digital control core module 30 includes a Force Servitude PID controller 301 for constant voltage control and a Clamp PID controller for constant current control, it is necessary to configure independent proportional coefficients (e.g., ...) for each of these controllers. , ), integral coefficient (e.g. , ) and differential coefficients (e.g. , (The subscripts in the above incremental PID algorithm formula are...) (For example in) and (The middle) represents retrieving the discrete value of the previous control cycle. This function is located in the appendix. Figure 1 In the schematic diagram of the digital control core module 30, the graphic symbol Z of the "Single-Cycle Delay" element, which is common in the art, is used. -1 To express.

[0083] S103, when multiple VI source channel modules 10 operate in parallel mode, the core operating parameters of all VI source channel modules 10 participating in the parallel connection, especially the voltage setting value, are recorded. Forward current clamping value and reverse current clamping value The parameters are configured to have exactly the same value. This consistency is a prerequisite for achieving autonomous and dynamic current sharing of the load current in the subsequent step S400.

[0084] The configuration process of these parameters, for example, is to send them from the host computer software to the digital control core module 30 of each VI source channel module 10 via a communication bus (such as Ethernet, USB, etc.) and store them in its internal registers or memory. The specific implementation method is well known in the art and will not be described in detail here.

[0085] In step S200, the system starts according to an external command. All VI source channel modules 10 participating in parallel simultaneously enable their power output modules 40 and independently begin executing control tasks. To avoid overvoltage or overcurrent to the load under test 20 at startup, this step may further include the following sub-steps:

[0086] S201, all VI source channel modules 10 participating in the parallel connection receive the output enable command from the host computer or system controller.

[0087] S202, upon receiving the instruction, each VI source channel module 10's digital control core module 30 independently executes a controlled output ramp initiation process. During this process, the digital control core module 30 generates an internal ramp setpoint that increases linearly with time. This is used as the real-time target for the voltage loop PID controller. Simultaneously, the PID controllers for forward and reverse current clamping also begin operating synchronously, monitoring the current feedback signal in real time. .

[0088] In one specific implementation, the slope setting value The generation method is as follows:

[0089] ;

[0090] in, This is the current index of the discrete time series; and They were respectively in the second The and the first The internal ramp setpoint for each control cycle, its initial value It can be set to 0 or the system's starting voltage; The voltage increment step size for each control cycle.

[0091] The voltage increment step The final voltage setting value can be determined. and a preset slope duration Joint decision:

[0092] ;

[0093] in, This is the system's control cycle. In this way, the output voltage of the power output module 40 rises smoothly from its initial value. During the voltage rise, if the current feedback signal... The forward current clamping value was triggered. or reverse current clamping value Then, the mode arbitration logic inside the digital control core module 30 will immediately switch the control from the voltage loop to the corresponding current clamping loop, enter the constant current working mode, and thus accurately limit the current during the startup process.

[0094] S203, when the internal ramp setting value Reaching or exceeding the final voltage setpoint And when the system is not in current clamping mode, the ramp-up process ends. Afterwards, the digital control core module 30 fixes the control target of the voltage loop to... The VI source channel module 10 enters the normal steady-state control stage and continues to execute subsequent steps S300.

[0095] The ramp start-up process is implemented by the logic inside the digital control core module 30. Its specific circuit design is a well-known technology in this field and will not be described in detail here.

[0096] Reference Figure 1 In step S300, after each VI source channel module 10 completes startup, its digital control core module 30 begins to independently and periodically execute high-speed digital closed-loop control. This process occurs in each control cycle. A complete iteration is performed within a given timeframe, continuously adjusting the output state. A complete control cycle may include the following sub-steps:

[0097] S301, in each control cycle At the initial moment, the analog-to-digital converter (ADC) in the feedback sampling module 50 synchronously samples the output of the power output module 40 to obtain the current voltage feedback value. and current feedback value These two digital values ​​are transmitted to the digital control core module 30.

[0098] S302, the digital control core module 30 received... and Then, its three internal parallel PID controllers, namely Force Servitude PID controller 301, Positive Clamp PID controller 302 and Negative Clamp PID controller 303, perform calculations simultaneously.

[0099] Specifically, the Force Servitude PID controller 301 for constant voltage control adjusts according to the voltage error. Calculate its control output increment And combine it with the output value of the previous cycle. To obtain the candidate control output value for the current period. .

[0100] Similarly, the Positive Clamp PID controller 302 and the Negative Clamp PID controller 303 also calculate and generate their candidate control output values ​​respectively. and .

[0101] S303, the mode arbitration logic inside the digital control core module 30, is based on the current feedback value of the current cycle. The effective control loop for the current cycle is determined by selecting from three parallel candidate control output values. The selection logic is as follows:

[0102] like The system then operates in constant voltage (CV) mode, selecting the output of the ForceServitude PID controller 301. This serves as the initial effective control output for the current cycle.

[0103] like The system then operates in positive constant current (CC) mode, selecting the output of the Positive Clamp PID controller 302. This serves as the initial effective control output for the current cycle.

[0104] like The system then operates in reverse constant current (CC) mode, selecting the output of the Negative Clamp PID controller 303. This serves as the initial effective control output for the current cycle.

[0105] S304, to ensure smooth and overshoot-free output of the VI source channel module 10 when switching between different control modes, the digital control core module 30 executes a bumpless switching mechanism. This mechanism forces synchronization of the historical state of the unselected PID controller. Specifically, in S303, the preliminary effective control output of the current cycle (e.g., ...) is determined. After that, this value is used to force an update of the historical output state of the other two unselected PID controllers (such as the Positive Clamp PID and the Negative Clamp PID). Algorithmically, this means that for the next cycle ( When preparing for the calculation, the historical output values ​​of the inactive loops are updated to the output values ​​of the currently active loops, that is:

[0106] ;

[0107] ;

[0108] In this way, the inactive loops use their reference values ​​for the next incremental calculation. It is leveled in real time to the actual output level of the current system. When the system operating state changes, such as when the current suddenly increases and needs to switch to the current loop, the calculation starting point of the new effective loop (e.g., Positive Clamp PID) is adjusted. The voltage loop output has been switched back to its previous state. Complete consistency eliminates output steps and disturbances caused by inconsistent controller historical states, ensuring smooth mode switching.

[0109] S305, the preliminary effective control output selected in S303, is ultimately determined as the final control word for the current cycle. The data is then sent to the power output module 40. The digital-to-analog converter (DAC) within the power output module 40 converts the digital control word... The signal is converted into an analog control signal, which drives the subsequent amplifier (AMP) circuit, ultimately regulating the voltage and current applied to the load under test 20.

[0110] The steps S301 to S305 described above constitute a complete closed-loop control cycle, which is executed repeatedly at the system's control frequency (e.g., hundreds of kHz to several MHz), enabling each VI source channel module 10 to independently achieve high-performance output control.

[0111] Reference Figure 2 In step S400, when the output terminals 11 of multiple VI source channel modules 10 are electrically connected in parallel externally to jointly drive a measured load 20, the system can achieve autonomous and dynamic current sharing of the total load current among the VI source channel modules 10. This process does not require setting up any dedicated current sharing bus or data communication between the VI source channel modules 10. This autonomous current sharing principle can be achieved based on the following steps:

[0112] S401, Establish a unified voltage control reference. Based on the configuration in step S103, all VI source channel modules 10 participating in parallel are set to the exact same voltage setpoint. When the total output current of the system is lower than the total current clamping capability of the parallel system, each VI source channel module 10 independently executes the high-speed closed-loop control of step S300 in constant voltage (CV) mode. Its core task is to maintain its respective output voltage at a constant voltage. .

[0113] S402 utilizes the physical constraints of the parallel connection point for dynamic adjustment. Since the output terminals 11 of all VI source channel modules 10 are physically connected to the same point, the voltage at this parallel connection point, i.e., the voltage across the measured load 20, is... This is unique for all channels. However, due to manufacturing tolerances, there are slight differences in component parameters and connection impedances for each VI source channel module 10. These differences result in slight variations in the equivalent output characteristics of each channel under closed-loop control. A channel with a slightly higher equivalent output voltage tends to output a larger current, but its increased output current causes its output voltage to decrease due to the internal impedance voltage drop, a change that is compensated for in real time by its own high-speed digital closed-loop control. All channels participate in this dynamic adjustment process, ultimately resulting in a lower parallel point voltage. Stably maintained at Nearby, total load current They are assigned to each VI source channel module 10.

[0114] S403 enables current balancing in constant voltage mode. This process can be described by modeling. For the first... Individual VI source channel modules ( Its output current for:

[0115] ;

[0116] in, It is the first The closed-loop control system of each channel strives to maintain an internal equivalent voltage that is approximately equal to... However, it includes the small static error unique to this channel; This is the equivalent output impedance of the channel; due to the high consistency in the design and manufacture of all VI source channel modules 10, its and The differences between them are very small; therefore, in the above dynamic balancing process, the current ultimately allocated to each channel is... They also tend to be consistent, thus achieving a uniform distribution of the total load current among the channels.

[0117] S404 enables a smooth transition to constant current mode and current sharing within constant current mode. When the total load current... As the number of channels continues to increase, due to the aforementioned minor differences, there will inevitably be a VI source channel module (e.g., the first one). Output current of each channel It will reach its set current clamping value first. At this time, the first The mode arbitration logic inside the digital control core module 30 of each channel will automatically switch from CV mode to CC mode, so that its output current is precisely limited to... .along with Further increase, due to the first Each channel no longer increases current output, and the voltage at the parallel point is no longer affected. The voltage will begin to drop. The remaining channels still in CV mode will attempt to compensate for this voltage drop by increasing their own output until the next channel also reaches its current clamping value. Then switch to CC mode. This process is repeated sequentially until all N VI source channel modules 10 have entered CC mode. At this point, each channel outputs... The current, the total output current is The system as a whole behaves as a large constant current source, and the current is still evenly distributed among the channels. This process ensures that the system can achieve autonomous current sharing throughout its entire operating range.

[0118] In step S500, the system continuously monitors the operating status of all VI source channel modules 10 participating in the parallel connection and performs safety isolation when a fault is detected to ensure the reliability of the entire parallel system and the safety of the load under test 20. This process may include the following sub-steps:

[0119] S501, each VI source channel module 10 independently reports its status data. During operation, the digital control core module 30 of each VI source channel module 10 periodically sends its key operating parameters to the host computer or system controller via the communication bus. These parameters may include: real-time voltage feedback values. Real-time current feedback value Internal operating temperature, current operating mode, and fault status indicators generated by internal self-test.

[0120] S502, the host computer or system controller performs fault diagnosis on the received data. Fault determination criteria may include, but are not limited to, one or more of the following:

[0121] A fault status flag was received from a certain VI source channel module 10.

[0122] The feedback value of a certain VI source channel module 10 is detected to deviate significantly from the set value over a period of time. For example, when the system should be in constant voltage mode, its voltage feedback value is continuously lower than a preset threshold value and its current does not reach the clamping value.

[0123] The status data of a certain VI source channel module 10 was not received within the preset time.

[0124] S503: When the host computer or system controller determines that a certain VI source channel module 10 has failed according to the diagnostic logic of S502, it immediately sends an independent output disable command to the failed VI source channel module 10.

[0125] S504, after receiving the disable command, the faulty VI source channel module 10 performs a safety isolation operation, making its output terminal 11 in a high impedance state with the parallel bus.

[0126] In one specific implementation, the high impedance state is achieved by the digital control core module 30 shutting down the drive signal of the final stage power device of the power amplifier (AMP) in the power output module 40.

[0127] In another embodiment, a physical relay can be provided at the output terminal 11 of the power output module 40, and physical isolation can be achieved by disconnecting the relay.

[0128] This operation effectively removes the faulty channel from the parallel bus, preventing its faulty state from affecting other normally operating VI source channel modules 10 or the load under test 20.

[0129] S505: After the faulty channel is isolated, the remaining N-1 healthy VI source channel modules 10 continue to supply power to the load under test 20. When the faulty channel is isolated, the total load current... The load will be temporarily handled entirely by the remaining N-1 channels, which may cause voltage fluctuations at the parallel connection points. A slight, momentary drop occurs. Each still-operating channel, with its independent digital closed-loop control system (as in step S300), detects this voltage deviation (i.e....). ), and independently and rapidly increase its output to compensate, in order to Re-stabilized During this process, the total load current is automatically redistributed among the remaining N-1 healthy channels according to the autonomous current sharing principle of step S400, thereby maintaining a stable power supply to the tested load 20 while reducing the total output capacity of the system, and realizing the fault-mitigated operation of the system.

[0130] The communication protocol and specific implementation of this status monitoring and fault isolation mechanism can be implemented by those skilled in the art using CAN bus, Ethernet, or other methods depending on the application scenario. These are well-known technologies in the field and will not be elaborated here.

[0131] To further illustrate the collaborative working process of the technical solution of this invention, a specific working scenario example will be used below.

[0132] In an exemplary scenario, assume that three (N=3) VI source channel modules 10 are connected in parallel to drive a programmable electronic load 20.

[0133] First, according to step S100, the parameters of the three VI source channel modules 10 are configured via the host computer. The voltage setting values ​​for all channels are set. Both are 5.0V, forward current clamping value Both are 10.0A, reverse current clamping value All are -1.0A. This configuration makes the entire parallel system appear as a 5.0V power supply system with a total output capacity of 30.0A.

[0134] Subsequently, the system receives an output enable command and executes step S200. The three VI source channel modules 10 simultaneously begin voltage ramp-up startup. The electronic load 20 is initially configured to draw 6.0A of current from the parallel system. During startup, the output voltage of each of the three channels smoothly rises from 0V to 5.0V, while their respective internal current clamping loops remain active to handle potential transient low impedance situations in the load.

[0135] After startup, the system enters steady-state operation. At this time, since the total load current of 6.0A is much smaller than the system's total clamping capacity of 30.0A, all three VI source channel modules 10 operate in constant voltage (CV) mode. Each channel independently executes the high-speed closed-loop control of step S300, controlling the voltage at the parallel connection point. The voltage is precisely maintained around 5.0V. Simultaneously, based on the autonomous current sharing principle of step S400, the total 6.0A load current is automatically and evenly distributed across the three channels, i.e., the actual output current of each channel (labeled as Channel 1, Channel 2, and Channel 3). , , Each is approximately equal to 2.0A.

[0136] Next, the setting of the electronic load 20 is changed to adjust the total current it needs to absorb. The A-to-A voltage increased linearly from 6.0A to 33.0A. During the increase, the output current of the three channels , , It also rises synchronously and maintains a uniform flow. When When the current exceeds 30.0A, the voltage at the parallel connection point Initially, the voltage could not be maintained at 5.0V and began to drop. Due to slight parameter differences, the output current of one of the channels (e.g., channel 1) would reach its 10.0A clamping value first. The mode arbitration logic within the digital control core module 30 of that channel would immediately respond, seamlessly switching control to the constant current (CC) loop, thus... It is precisely limited to 10.0A. With As demand increased further, channels 2 and 3 also reached 10.0A and smoothly switched to CC mode. Ultimately, the system as a whole entered a constant current state, with the total output current clamped at 30.0A. ), parallel point voltage Then, based on the load impedance decreasing to a stable value ( ).

[0137] Subsequently, the electronic load 20 was adjusted again, reducing the total current demand to 15.0A. Since the load demand was now below the system's clamping capability, the parallel point voltage... It began to recover. When... When the voltage approaches 5.0V, the mode arbitration logic within the three VI source channel modules 10 will sequentially determine whether to exit CC mode and seamlessly switch control back to CV mode. The system eventually stabilizes in CV mode, and the output voltage... Upon restoration to 5.0V, the total current is 15.0A, and this current is once again evenly distributed across the three channels. .

[0138] When the system is running stably at a current of 15.0A, a fault scenario is simulated. Assume that the temperature sensor in channel 2 detects an anomaly and reports an over-temperature fault. According to step S500, upon receiving the fault flag, the host computer immediately sends an output disable command to channel 2. Upon receiving the command, channel 2 places its power output module 40 in a high-impedance state, safely isolating it from the parallel bus. At the moment channel 2 exits, the 5.0A current previously handled by channel 2 needs to be borne by the remaining channels 1 and 3, which causes the parallel point voltage to... A brief, microsecond-level drop occurred. The digital closed-loop control systems of both Channel 1 and Channel 3 detected this voltage deviation and immediately increased their output to quickly reduce it. The voltage stabilized again at 5.0V. Ultimately, the system reached a new steady state: the parallel point voltage remained at 5.0V, and the total output current remained at 15.0A, but this current had re-established autonomous current sharing between the remaining two healthy channels (Channel 1 and Channel 3). , The system continues to reliably power the load even when one channel is lost.

[0139] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for implementing a digital ring in a multi-channel parallel Gang mode, characterized in that, Includes the following steps: Parameter configuration and initialization are performed on multiple VI source channel modules. The parameter configuration and initialization includes configuring a unified voltage setting value and a unified current clamping value to obtain multiple configured VI source channel modules. Based on the configured parameters of the multiple configured VI source channel modules, the multiple configured VI source channel modules are started. After starting, the multiple configured VI source channel modules simultaneously enable output and independently begin to execute control tasks. During the process of multiple configured VI source channel modules independently executing the control task, each VI source channel module independently executes high-speed digital closed-loop control. The high-speed digital closed-loop control is used to calculate and update the control commands for the power output modules of each VI source channel module based on the real-time feedback data of each VI source channel module. Each of the aforementioned VI source channel modules independently performs high-speed digital closed-loop control, including: At the beginning of each control cycle, the feedback sampling module of the VI source channel module acquires the current voltage feedback value and current feedback value, and transmits them to the digital control core module inside the VI source channel module. The parallel PID controllers inside the digital control core module, namely the PID controller for constant voltage control and the PID controller for current clamping, perform calculations simultaneously to generate their respective candidate control output values. The mode arbitration logic inside the digital control core module selects from the candidate control output values ​​of the parallel PID controller based on the current feedback value to determine the preliminary effective control output for the current cycle. The initial effective control output is determined as the final control word for the current cycle and sent to the power output module; Each VI source channel module independently performs high-speed digital closed-loop control, which also includes a bumpless switching mechanism, comprising: After the mode arbitration logic determines the preliminary effective control output based on the current feedback value; The value of the initial effective control output is forcibly updated to the historical output state of the PID controller that was not selected. This ensures that the reference value used for incremental calculation by the unselected PID controller in the next control cycle is consistent with the value of the initial effective control output; The high-speed digital closed-loop control is executed independently by multiple VI source channel modules. While maintaining the parallel point voltage together, the total load current is autonomously shared among the multiple VI source channel modules. The autonomous current sharing does not require direct coordination between the multiple VI source channel modules. During the autonomous current sharing process of the multiple VI source channel modules, the operating status of the multiple VI source channel modules is monitored, and when any VI source channel module is detected to have failed, the failed VI source channel module is isolated from the parallel system, and the remaining VI source channel modules continue to supply power to the load under test.

2. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 1, characterized in that, The parameter configuration and initialization of multiple VI source channel modules includes: Configure the core operating parameters of multiple VI source channel modules, including the voltage setting value, forward current clamping value, and reverse current clamping value; Configure the loop control parameters of the digital control core modules inside the multiple VI source channel modules; Configure the core operating parameters of all the multiple VI source channel modules participating in parallel to have exactly the same value.

3. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 1, characterized in that, The activation of multiple configured VI source channel modules includes: Multiple configured VI source channel modules receive output enable commands; Each of the multiple configured VI source channel modules independently executes a controlled output ramp start-up process using its own digital control core module. During the output ramp start-up process, the digital control core module generates an internal ramp setpoint that increases linearly with time as the real-time target of the voltage loop PID controller. When the internal ramp setting value reaches or exceeds the final voltage setting value, the digital control core module fixes the control target of the voltage loop to the voltage setting value, so that the VI source channel module enters the steady-state control stage.

4. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 1, characterized in that, The autonomous current sharing of total load current among the multiple VI source channel modules includes: A unified voltage control benchmark is established, and all the VI source channel modules aim at constant voltage mode, independently executing the high-speed digital closed-loop control to maintain their respective output voltage at the voltage set value. By utilizing the physical constraints of the parallel connection point for dynamic adjustment, all the VI source channel modules jointly participate in the dynamic adjustment process to stably maintain the voltage of the parallel connection point near the voltage set value. During the dynamic adjustment process, the total load current is distributed to each of the VI source channel modules to achieve balanced current distribution in constant voltage mode.

5. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 1, characterized in that, The monitoring of the operating status of multiple VI source channel modules, and the isolation of the faulty VI source channel module from the parallel system when a fault is detected, with the remaining VI source channel modules continuing to supply power to the load under test, includes: Each of the VI source channel modules independently reports status data, which is then reported to the host computer or system controller. The host computer or system controller performs fault diagnosis on the received status data, and after determining that a certain VI source channel module has failed, sends an independent output disable command to the failed VI source channel module. Upon receiving the output disable command, the malfunctioning VI source channel module performs a safety isolation operation, causing the output terminal of the malfunctioning VI source channel module to be in a high impedance state with the parallel bus. The remaining healthy VI source channel modules detect the deviation of the parallel point voltage and independently increase their output to compensate, so that the total load current is automatically redistributed among the remaining healthy VI source channel modules.

6. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 1, characterized in that, The parallel PID controllers within the core digital control module include: A PID controller for constant voltage control, the PID controller for constant voltage control performing calculations based on the voltage error between the voltage setpoint and the voltage feedback value; A PID controller for positive current clamping, the PID controller for positive current clamping performing calculations based on the current error between the positive current clamping value and the current feedback value; A PID controller for reverse current clamping, the PID controller for reverse current clamping calculating based on the current error between the reverse current clamping value and the current feedback value.

7. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 4, characterized in that, The autonomous current sharing of the total load current among the multiple VI source channel modules also includes a smooth transition to constant current mode, wherein the smooth transition includes: When the total load current increases, and the output current of a certain VI source channel module reaches the set current clamping value first, the mode arbitration logic of the certain VI source channel module automatically switches from constant voltage mode to constant current mode. The remaining VI source channel modules, which are still in constant voltage mode, attempt to compensate for the drop in the parallel point voltage by increasing their own output; Until all the VI source channel modules are switched to the constant current mode in sequence, so that each of the VI source channel modules outputs the current clamping value, the current sharing in the constant current mode is realized.

8. The method for implementing a multi-channel parallel Gang mode digital ring according to claim 1, characterized in that, The feedback sampling module obtains the current voltage feedback value by including: The voltage across the load under test is acquired by setting up a pair of high-impedance voltage sampling terminals independent of the power output terminal. The voltage difference between the high-impedance voltage sampling terminals is accurately measured using a differential amplifier. The output of the differential amplifier is converted into the voltage feedback value via an analog-to-digital converter.

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