A method for manufacturing LED packaged chips based on intelligent control

Abstract

This invention discloses a method for manufacturing LED packaged chips based on intelligent control, belonging to the field of intelligent packaging control technology. The method includes: constructing and correcting a digital twin model of the chip packaging based on chip packaging process data and chip packaging quality results; using the digital twin model to perform rapid simulations of different combinations of process parameters and outputting optimized process parameter corrections; superimposing the optimized process parameter corrections with the initial chip packaging process formula to generate an optimized chip packaging process formula; acquiring chip packaging defect information and mapping it to chip packaging process deviations according to a preset defect root cause map; finely correcting and constraining the optimized chip packaging process formula by fusing it with the optimized process parameter corrections; and generating a chip packaging process control instruction set. This invention improves the optimization efficiency, stability, and intelligence level of the packaging process.

Description

Technical Field

[0001] This invention relates to the field of intelligent packaging control technology, and in particular to a method for producing LED packaged chips based on intelligent control. Background Technology

[0002] As a crucial link in the semiconductor light source industry chain, LED chip packaging technology has evolved from a stage driven by manual experience in process parameter tuning to a stage of data-assisted decision-making and automated equipment collaborative control. With the widespread application of miniaturized, high-efficiency, and high-reliability LED chips, the packaging process chain, including wafer testing, dicing and sorting, die bonding, wire bonding, encapsulation, and finished product inspection, places higher demands on the precise control of parameters. In current production methods, chip classification information is typically generated based on preliminary wafer testing data, and packaging formulas are set using existing process knowledge bases. A fixed process is then executed by equipment to complete the packaging process. In recent years, technologies that utilize equipment process data for process tracking, analyze packaging results using statistical models, and adjust packaging parameters trend-wise have been gradually applied, providing a foundation for the automation and controllability of the packaging process.

[0003] While existing technologies can record packaging process data and perform some process optimizations based on it, they typically lack real-time simulation and verification methods for the interactive effects of different parameter combinations during the packaging process, resulting in long process optimization cycles. Furthermore, the root causes of packaging defects are complex, and existing technologies often rely on experienced engineers for manual judgment and corresponding parameter adjustments. This makes it difficult to establish a unified mapping mechanism between defect information and specific process deviations, thus limiting the adaptive control capabilities of the packaging process. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides an LED packaging chip production method based on intelligent control, which solves the problems of lack of rapid simulation verification of process parameter combinations and insufficient correlation between packaging defects and process deviations.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a method for producing LED packaged chips based on intelligent control, which includes acquiring LED chip wafer test data and removing severely defective chips, and forming a basic chip profile through wafer dicing and sorting;

[0008] Based on the chip's basic data, the initial chip packaging process formula is set and the chip packaging process chain is executed to obtain chip packaging process data and chip packaging quality results.

[0009] Based on chip packaging process data and chip packaging quality results, a chip packaging digital twin model is constructed and calibrated. The chip packaging digital twin model is then used to perform rapid simulations of different combinations of process parameters and output the optimized process parameter correction amount.

[0010] The optimized process parameter correction is superimposed on the initial chip packaging process formula to generate the optimized chip packaging process formula.

[0011] The chip packaging defect information is acquired and mapped to chip packaging process deviations based on a preset defect root cause map. By integrating the defect information with the optimized process parameter correction amount, the chip packaging optimized process formula is finely modified and constrained, and a chip packaging process control instruction set is generated.

[0012] As a preferred embodiment of the LED packaging chip production method based on intelligent control described in this invention, the LED chip wafer test data includes electrical parameters, optical parameters, and brightness luminous characteristics.

[0013] In a preferred embodiment of the intelligent control-based LED packaging chip manufacturing method of the present invention, the steps for forming the chip basic file are as follows:

[0014] According to the preset defect judgment conditions, severely defective chips are identified from the LED chip wafer test data and marked as rejection objects for rejection, thereby obtaining standard LED chip wafer test data;

[0015] The wafer is separated into multiple usable chips corresponding to test locations, and the usable chips are associated with the corresponding standard LED chip wafer test data to form a basic chip profile.

[0016] As a preferred embodiment of the intelligent control-based LED packaged chip production method of the present invention, the steps of setting the initial chip packaging process formula and executing the chip packaging process chain according to the chip basic file, and obtaining chip packaging process data and chip packaging quality results are as follows:

[0017] Read the chip's comprehensive characteristics information from the chip's basic file, and match the corresponding packaging equipment, packaging materials, and process conditions based on the chip's comprehensive characteristics information to determine the initial chip packaging process formula;

[0018] Based on the initial chip packaging process formula, the die bonding process, wire bonding process, packaging process and curing process are executed sequentially on the corresponding packaging equipment according to the chip packaging process chain, and the equipment operation status and process execution information are collected in real time to form chip packaging process data;

[0019] The packaged chip is used as the testing object for electrical testing, optical testing, and appearance testing to obtain the chip packaging quality results.

[0020] As a preferred embodiment of the intelligent control-based LED packaging chip production method of the present invention, the specific steps for constructing and correcting a digital twin model of the chip packaging based on chip packaging process data and chip packaging quality results are as follows:

[0021] Based on chip packaging process data, we construct behavior models for die bonding, wire bonding, packaging, and curing processes, and use each process behavior model as the process domain of the chip packaging digital twin model.

[0022] The chip packaging quality results are mapped to the corresponding chip packaging process data through a unified coordinate index to form a cross-process correspondence as the quality domain of the chip packaging digital twin model;

[0023] Under a unified timeline, the quality domain is associated one-to-one with the corresponding time position of the process domain in the chip packaging process chain according to the time position of the corresponding process, forming an initial digital twin model of chip packaging.

[0024] The chip packaging process is simulated using an initial digital twin model of the chip packaging to obtain simulation quality results. The simulation quality results are then compared with the chip packaging quality results to obtain deviation information.

[0025] The deviation information is injected into the process domain in reverse order of the chip packaging process chain, and the process parameters of each process are iteratively adjusted until the prediction error converges, thus obtaining a digital twin model of chip packaging.

[0026] As a preferred embodiment of the intelligent control-based LED packaging chip manufacturing method of the present invention, the specific steps of using a digital twin model of chip packaging to perform rapid simulation of different combinations of process parameters and outputting optimized process parameter corrections are as follows.

[0027] Packaging process parameters are selected as perturbation variables from the chip packaging digital twin model, and different combinations of process parameters are generated one by one within the adjustable range of the perturbation variables.

[0028] By using a digital twin model of chip packaging, proxy simulations are run on different combinations of process parameters to obtain packaging quality prediction results;

[0029] Based on the packaging quality prediction results, the target process parameter combination that meets the preset packaging quality requirements is determined, and the target process parameter combination is compared with the corresponding process parameters in the initial chip packaging process recipe, and the optimized process parameter correction amount is output.

[0030] As a preferred embodiment of the LED packaging chip production method based on intelligent control described in this invention, the step of generating the chip packaging optimized process formula refers to establishing a one-to-one correspondence between the optimized process parameter correction amount and the corresponding process parameter in the initial chip packaging process formula according to the process classification, and updating and replacing the corresponding process parameter in the initial chip packaging process formula according to the optimized process parameter correction amount.

[0031] As a preferred embodiment of the LED packaging chip production method based on intelligent control described in this invention, the defect root cause map is obtained by statistically analyzing the correlation between defect types, defect occurrence processes and corresponding process parameters in historical packaging batches, and determining key process parameters based on the process rules of each process, and organizing and setting them according to defect type-process-process parameter.

[0032] As a preferred embodiment of the intelligent control-based LED packaging chip production method of the present invention, the specific steps of acquiring chip packaging defect information and mapping the chip packaging defect information to chip packaging process deviations according to a preset defect root cause map are as follows.

[0033] Defect statistics and classification records are performed on the packaged chips to obtain chip packaging defect information;

[0034] Based on the defect root cause map, each chip packaging defect information is searched and matched according to the defect type and the process to which it belongs, and the affected process parameters and offset direction corresponding to the chip packaging defect information are read.

[0035] Using the affected process parameters as an index, all offset directions pointing to the same affected process parameter are merged to determine the process offset trend, forming the chip packaging process deviation.

[0036] As a preferred embodiment of the intelligent control-based LED packaging chip production method of the present invention, the step of finely modifying and constraining the chip packaging optimization process formula by integrating it with the optimized process parameter correction amount to generate a chip packaging process control instruction set includes the following specific steps.

[0037] By correlating and integrating chip packaging process deviations with optimized process parameter corrections under the same process steps and the same process parameter dimensions, an optimized process parameter combination is generated.

[0038] Based on the optimized process parameter combination, the different process parameter combinations in the chip packaging optimized process formula are finely modified and constrained to determine the optimal process parameter combination.

[0039] The optimal combination of process parameters is mapped item by item into the equipment executable instruction fields corresponding to the die bonding, wire bonding, packaging and curing processes according to the chip packaging process chain, and then arranged in the order of the processes to form a chip packaging process control instruction set.

[0040] The beneficial effects of this invention are as follows: by constructing a digital twin model of chip packaging that can realistically reflect the behavior of multiple processes, and using it to carry out rapid process simulation to output optimization parameters, as well as establishing a defect root cause map and quantifying and mapping defect information into process deviations and integrating them with optimization parameters, it is possible to efficiently obtain the optimal process settings in a virtual environment, reduce the actual trial production requirements, and perform structured diagnosis of defect causes and automatically generate process control instructions that can be executed by the equipment, thereby improving the optimization efficiency, stability and intelligence level of the packaging process. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a method for manufacturing LED packaged chips based on intelligent control.

[0043] Figure 2 A flowchart for generating the chip's basic profile.

[0044] Figure 3 A flowchart for the construction and calibration of a digital twin model for chip packaging.

[0045] Figure 4 A flowchart for generating a chip packaging process control instruction set. Detailed Implementation

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0048] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0049] Reference Figures 1-4 This is one embodiment of the present invention, which provides a method for producing LED packaged chips based on intelligent control, including the following steps:

[0050] S1. Obtain LED chip wafer test data and remove severely defective chips. Form a basic chip profile through wafer dicing and sorting.

[0051] It should be noted that the chip is contacted point by point by the wafer probe station, and the electrical parameters are collected by applying a set current / voltage in the tester. Then, the integrating sphere and spectrometer are used to perform optical measurements such as luminous flux, wavelength and color coordinates on the lit chip. The brightness changes are recorded under multiple current levels to obtain LED chip wafer test data.

[0052] S1.1 Identify severely defective chips from the LED chip wafer test data according to the preset defect judgment conditions, mark them as rejection objects and remove them, and obtain standard LED chip wafer test data.

[0053] Furthermore, the system calls upon LED chip wafer test data and loads preset defect judgment conditions. For each piece of LED chip wafer test data, it compares each parameter, such as forward voltage, reverse leakage current, luminous flux, wavelength, brightness, and luminous characteristics, to see if they exceed the defect judgment threshold. For all chips judged to be severely defective, a severely defective chip mark table is generated using the chip's unique identifier. The corresponding records in the LED chip wafer test data are then marked as severely defective chips. Using the severely defective chip mark table as a filtering basis, all data records corresponding to severely defective chips are removed from the LED chip wafer test data, and standard LED chip wafer test data is output.

[0054] It should be noted that the defect judgment criteria are obtained by automatically extracting features based on the parameter distribution of multiple batches of LED chip wafer test data, and identifying the common features of various abnormal parameter combinations through abnormal pattern clustering, parameter correlation analysis and multi-dimensional feature segmentation modeling.

[0055] The defect judgment threshold is obtained by performing statistical interval analysis, abnormal data density estimation, and automatic feature boundary segmentation on LED chip wafer test parameters. It is calculated by setting the boundary between the normal distribution area and the abnormal clustering area for each test parameter. The defect judgment threshold is usually set according to the normal distribution range of LED chip wafer test parameters in multiple batches of data. For example, the threshold for forward voltage can generally be set in the range of 2.60–2.90V. The specific value can be dynamically adjusted according to the actual product specifications, material characteristics, and batch statistical results to ensure that the identification of abnormal chips is sufficient without over-screening.

[0056] S1.2 Separate the wafer into multiple usable chips corresponding to test locations, and associate the usable chips with the corresponding standard LED chip wafer test data to form a chip basic profile.

[0057] Furthermore, a one-to-one mapping table is established using wafer coordinates and carrier coordinates after dicing. Based on the mapping, the wafer is cut into multiple usable chips, and the carrier coordinates of each usable chip are recorded. According to the one-to-one mapping table, the carrier coordinates of each usable chip are associated with the corresponding wafer coordinates, and matching test data records are extracted from standard LED chip wafer test data. Using the unique identifier of the usable chip as the primary key, the carrier coordinates, wafer coordinates, and corresponding test data of the usable chip are combined and stored to form the basic chip file.

[0058] S2. Based on the chip's basic data, set the initial chip packaging process formula and execute the chip packaging process chain to obtain chip packaging process data and chip packaging quality results.

[0059] S2.1 Read the chip's comprehensive characteristic information from the chip's basic file, and match the corresponding packaging equipment, packaging materials, and process conditions according to the chip's comprehensive characteristic information to determine the initial chip packaging process formula.

[0060] Furthermore, the system reads fields such as electrical parameters, optical parameters, and brightness and luminescence characteristics of the target chip from the chip's basic file, and generates comprehensive chip characteristic information through feature calculation. The comprehensive chip characteristic information is then input into the packaging resource matching rule base to automatically retrieve a list of compatible packaging equipment, a list of packaging materials, and a set of candidate process conditions. Packaging equipment, packaging materials, and candidate process conditions are paired one by one according to ternary combinations. For each ternary combination, hard constraints such as process window, material compatibility, and equipment capability are first verified, and those that do not meet the requirements are directly eliminated. For each packaging equipment-packaging material-process condition ternary combination that passes the hard constraint screening, historical quality performance indicators such as yield and key performance stability, as well as capacity and cost indicators such as production cycle time and cost per chip, are read from historical production data. At the same time, the characteristic matching degree between the chip's overall characteristics and the process window that the combination can provide is calculated. The three types of indicators are weighted and summed according to preset weights (e.g., quality performance 50%, production cycle time 30%, and characteristic matching degree 20%) to obtain a comprehensive score. The ternary combination with the best comprehensive score is selected as the target packaging equipment, material, and process conditions. The initial chip packaging process formula is generated with the target packaging equipment, target packaging material, and target process conditions as the components.

[0061] It should be noted that the packaging resource matching rule base automatically identifies the correspondence between available packaging resources and chip characteristics by extracting the quality performance patterns of different chip comprehensive characteristic information under various packaging equipment, packaging materials and process conditions, and then structures and organizes this correspondence.

[0062] S2.2. Based on the initial chip packaging process formula, the die bonding process, wire bonding process, packaging process and curing process are executed sequentially on the corresponding packaging equipment according to the chip packaging process chain, and the equipment operating status and process execution information are collected in real time to form chip packaging process data.

[0063] Furthermore, based on the initial chip packaging process formula, the target packaging equipment and process parameters corresponding to the die bonding, wire bonding, packaging, and curing processes are analyzed, and process execution instructions are issued to each target packaging equipment in the chip packaging process chain sequence. When each target packaging equipment executes the die bonding, wire bonding, packaging, and curing processes, it continuously outputs the actual operating status parameters and real-time process execution parameters through the equipment data interface. The operating status data and process execution data output by each target packaging equipment are timestamped, labeled with process tags, and associated with chip identifiers. The operating status data and process execution data arranged in the process chain sequence are combined and stored to form the chip packaging process data of the corresponding chip.

[0064] S2.3. Perform electrical, optical and appearance inspections on the packaged chip as the inspection object to obtain the chip packaging quality results.

[0065] Furthermore, a set current or voltage is applied to the packaged chip using electrical testing equipment, and electrical testing parameters such as forward voltage and reverse leakage current are collected and written into the electrical testing result record. The packaged chip is lit up using optical testing equipment, and optical testing parameters such as luminous flux, wavelength, color coordinates, and brightness are collected and written into the optical testing result record. The surface image of the packaged chip is acquired using appearance testing equipment, and feature recognition is performed on solder joint morphology, package structure, and appearance defects to generate appearance testing result records. Using the chip's unique identifier as an index, the electrical testing result records, optical testing result records, and appearance testing result records are integrated and output as the chip packaging quality result.

[0066] S3. Based on chip packaging process data and chip packaging quality results, construct and calibrate a chip packaging digital twin model, and use the chip packaging digital twin model to quickly simulate different combinations of process parameters, and output the optimized process parameter correction amount.

[0067] S3.1 Construct a die bonding process behavior model, a wire bonding process behavior model, a packaging process behavior model, and a curing process behavior model based on the chip packaging process data, and use the process behavior models of each process as the process domain of the chip packaging digital twin model.

[0068] Furthermore, the chip packaging process data is classified and extracted according to the process labels. For each type of chip packaging process data, the following process parameters are extracted: die bonding process parameters such as die bonding temperature, die bonding pressure, and die bonding time; wire bonding process parameters such as wire bonding pressure, wire bonding current, and wire bonding ultrasonic power; packaging process parameters such as encapsulation adhesive amount, packaging displacement, and packaging speed; and curing process parameters such as curing temperature, curing time, and curing temperature rise curve. At the same time, the process execution result feature parameters corresponding to each process are extracted.

[0069] Constructing a die bonding process behavior model: Extracting process parameters such as die bonding temperature, die bonding pressure, die bonding time, and die bonding displacement from die bonding process data as input feature vectors, and execution results such as die bonding pad wetting area, die bonding void ratio, and die bonding offset as output feature vectors to form a complete sample set; then performing cluster analysis based on the input feature vectors, dividing the samples into several sub-clusters according to different operating conditions (such as low temperature / high temperature, low pressure / high pressure combination); fitting a set of multivariate nonlinear regression models within each sub-cluster, and solving for the corresponding local regression coefficients by minimizing the error between the output features of the samples in that cluster and the regression prediction values; and encapsulating the combination of "operating condition clusterer + local nonlinear regression function of each operating condition" into a die bonding process behavior model to achieve a fine mapping of process execution results under different die bonding conditions;

[0070] Constructing a wire bonding process behavior model: Extracting time-varying process parameters such as wire bonding pressure, wire bonding current, wire bonding ultrasonic power, and wire bonding speed from wire bonding process data in chronological order. Representing each welding process as a time sequence input, and constructing an output vector with corresponding weld quality features such as weld ball diameter, necking degree, and tensile force value, forming a training sample set of "sequence input - result output"; Constructing a neural network structure with several layers of LSTM units as the main body and fully connected output layers at the ends, defining mean square error as the loss function, and using backpropagation and backpropagation time (BPTT) algorithms to iteratively train the network parameters so that the network output approximates the measured weld quality as closely as possible; After training convergence, solidifying the weights of the LSTM network, thus obtaining a wire bonding process behavior model that can predict weld quality features based on the time sequence parameters of the wire bonding process;

[0071] Constructing a packaging process behavior model: Process parameters such as encapsulation glue amount, encapsulation speed, encapsulation path length, and encapsulation preheating temperature are extracted from packaging process data as input features, while output features include encapsulation glue height, encapsulation glue width, and encapsulation bubble ratio. Multiple training subsets are generated through sample bootstrap sampling. A regression decision tree is trained on each subset, with each tree randomly selecting some process parameters as candidate splitting features at each node. The optimal split is selected by minimizing the variance of samples within each node. After integrating multiple regression trees, the average (or weighted average) of the prediction results from all trees is used as the final output. During the training phase, hyperparameters such as the number of trees, maximum depth, and minimum number of leaf node samples can be adjusted using grid search. The generalization error is evaluated using a validation set. Finally, the trained random forest model is saved as a packaging process behavior model, used to nonlinearly map packaging process parameters to key indicators such as colloid morphology and bubbles.

[0072] Constructing a curing process behavior model: Based on resin curing kinetics and heat conduction mechanisms, a simplified differential equation or state-space model is established with curing temperature curves, curing holding time, heating rate, and cooling rate as inputs. State variables describe the degree of curing, volume shrinkage, and internal stress evolution, while output variables correspond to process execution result indicators such as curing shrinkage rate, glass transition temperature Tg, and residual stress. Then, using actual curing process data, each curing temperature-time curve and its corresponding test results are used to form a training sample. By minimizing the time series error between the model output and the measured curing shrinkage rate / Tg / residual stress, unknown parameters in the kinetic equation (such as reaction rate constant, viscoelastic coefficient, etc.) are numerically identified. When the error converges, the kinetic model with calibrated parameters is solidified into a curing process behavior model, enabling it to predict the changes in curing quality indicators over time and the final result given any curing temperature curve and time setting.

[0073] Based on the chip packaging process chain sequence, the behavior models of die bonding, wire bonding, packaging, and curing processes are summarized in a process domain division method, which serves as the process domain of the chip packaging digital twin model.

[0074] S3.2 Map the chip packaging quality results to the corresponding chip packaging process data using a unified coordinate index to form a cross-process correspondence as the quality domain of the chip packaging digital twin model.

[0075] Furthermore, a unified coordinate index is generated based on the chip's unique identifier, the timestamps of each process in the chip packaging process chain, and the process identifier. This unified coordinate index serves as the common index key for chip packaging quality results and chip packaging process data. According to the unified coordinate index, chip packaging quality result records are mapped one-to-one with chip packaging process data records for the die bonding process, wire bonding process, packaging process, and curing process, which are divided by process. During the mapping process, a process number and time sequence mark are added to each pair of matching records to clarify the correspondence between processes. The one-to-one mapping relationship established through the unified coordinate index is stored as a set of cross-process correspondences organized according to the chip's unique identifier and the chip packaging process chain order. This set of cross-process correspondences serves as the quality domain of the chip packaging digital twin model.

[0076] S3.3 Under a unified time axis, the quality domain is associated one-to-one with the corresponding time position of the process domain in the chip packaging process chain according to the time position of the corresponding process, forming the initial model of the chip packaging digital twin.

[0077] Furthermore, based on the timestamps of the die bonding, wire bonding, packaging, and curing processes recorded in the chip packaging process data, a unified timeline is established for each chip, starting from the beginning time of the chip packaging process chain. The chip packaging process data records for the die bonding, wire bonding, packaging, and curing processes are mapped to their corresponding time positions on the unified timeline. Using the unified coordinate index and timeline, the chip packaging quality results are located at the corresponding time positions of the die bonding, wire bonding, packaging, and curing processes. Chip packaging quality result records with the same unique chip identifier and time position are associated one-to-one with chip packaging process data records with the same unique chip identifier and time position, generating a chip-level time series association structure that simultaneously contains process domain information and quality domain information. The collection of chip-level time series association structures across all chips is used as the initial model for the chip packaging digital twin.

[0078] S3.4. Simulate the chip packaging process using the initial digital twin model of chip packaging, obtain simulation quality results, and compare the simulation quality results with the chip packaging quality results to obtain deviation information.

[0079] Furthermore, using the process parameters of the die bonding, wire bonding, packaging, and curing processes from the chip packaging process data as input, the simulation calculations of the die bonding, wire bonding, packaging, and curing processes are performed sequentially along a unified timeline to obtain the corresponding chip simulation process state sequence. At the end time position of the unified timeline, the final state information obtained from the simulation of each process—die bonding, wire bonding, packaging, and curing—is extracted sequentially. This includes parameters such as pad wetting area, solder ball diameter, colloid height and width, curing shrinkage, and residual stress. Based on the established feature conversion relationships in the process, these state quantities are converted into quality parameters such as forward voltage, luminous flux, dominant wavelength, color coordinates, and appearance defect judgment. This completes the conversion from the state sequence to the simulation quality results. Finally, the corresponding chip packaging quality result record is retrieved from the chip packaging quality results using the chip's unique identifier. The difference, ratio, or error rate of the electrical, optical, and appearance inspection parameters in the simulation quality results and chip packaging quality results are calculated respectively. Deviation information is generated by performing the difference calculation operation on each quality indicator.

[0080] S3.5. Inject the deviation information into the process domain in reverse order of the chip packaging process chain, and iteratively adjust the process parameters of each process until the prediction error converges to obtain the chip packaging digital twin model.

[0081] Furthermore, the deviation information is injected into the process domain of the initial digital twin model of chip packaging step by step in reverse order of the chip packaging process chain (from the curing process to the die bonding process). In the process behavior model corresponding to each process, the process parameters of the process are iteratively adjusted using methods such as gradient descent or parameter search, with the deviation information as the optimization target. After each adjustment, the forward simulation is re-executed, and the new simulated chip packaging quality results are compared with the actual chip packaging quality results to calculate the updated prediction error. The closed-loop iterative process of the above reverse injection and forward simulation is repeated until the prediction error of all processes meets the preset convergence condition (e.g., the maximum number of iterations is 50 to 200), and the digital twin model of chip packaging is output.

[0082] It should be noted that, for the first The simulation results after the second iteration can be used to define the prediction error as follows:

[0083] Calculate the standardized error of the package quality results for each chip:

[0084] ;

[0085] In the formula, It is the first In the nth iteration, the 1st Standardized error (dimensionless) of chip packaging quality indicators. It is in the The first iteration obtained from the chip packaging digital twin model Individual chip package quality indicators, such as forward voltage, reverse leakage current, luminous flux, dominant wavelength, color coordinates, or appearance characteristic parameters; The first is obtained through actual chip packaging quality testing. Measured chip quality indicators for individual chip packaging quality metrics They are completely identical in physical meaning and dimensions; It is the first The scaling factor of each chip packaging quality indicator is obtained by statistically analyzing the historical test data of chip packaging quality indicators and taking characteristic values ​​with consistent dimensions such as specification range width or standard deviation. It is used to normalize the difference of quality indicators with different dimensions. It is the serial number of the chip packaging quality indicator; It represents the number of iterations.

[0086] The updated prediction error is calculated based on the standardized error:

[0087] ;

[0088] In the formula, It is the first The prediction error (dimensionless) obtained in the nth iteration is the root mean square value of the standardized error of all chip packaging quality indicators, used to evaluate the digital twin model in the nth iteration. The overall prediction bias at the next iteration; It is the total number of chip packaging quality indicators involved in error calculation, such as forward voltage, reverse leakage current, luminous flux, wavelength, color coordinates, and appearance defect characteristics.

[0089] S3.6 Select packaging process parameters as perturbation variables from the chip packaging digital twin model, and generate different combinations of process parameters one by one within the adjustable range of the perturbation variables.

[0090] Furthermore, packaging process parameters that affect packaging quality are identified from the chip packaging digital twin model and determined as perturbation variables. For each perturbation variable, its adjustable range is limited according to equipment capability, material characteristics, and process window (e.g., die bonding pressure is 0.1–0.5MPa, wire bonding ultrasonic power is 200–400mW, encapsulation adhesive volume is 0.8–1.2μL, and curing temperature is 130–160℃). Each perturbation variable is divided into several discrete levels within its adjustable range according to a preset step size (e.g., die bonding pressure is set to three levels: 0.2MPa, 0.3MPa, and 0.4MPa). Cartesian product operations are performed on all levels of all perturbation variables to generate all possible parameter combinations (e.g., if the three variables have 3, 4, and 2 levels respectively, then 3×4×2=24 combinations are generated), resulting in different combinations of process parameters.

[0091] S3.7. Use the chip packaging digital twin model to run proxy simulations for different combinations of process parameters to obtain packaging quality prediction results.

[0092] Furthermore, each set of packaging process parameters is sequentially input into the chip packaging digital twin model. The die bonding process behavior model, wire bonding process behavior model, packaging process behavior model, and curing process behavior model are called sequentially according to the chip packaging process chain for proxy simulation. Each process behavior model is deduced step by step according to the input process parameters, outputting the corresponding process execution result characteristic parameters, and passing them to the next process as the initial state. At the time of packaging completion, the simulation outputs of all processes are integrated to generate a packaging quality prediction result that includes electrical performance, optical performance, and appearance characteristics.

[0093] S3.8. Based on the packaging quality prediction results, determine the target process parameter combination that meets the preset packaging quality requirements, compare the target process parameter combination with the corresponding process parameters in the initial chip packaging process recipe, and output the optimized process parameter correction amount.

[0094] Furthermore, based on the packaging quality prediction results, each set of packaging process parameter combinations is compared to ensure that all electrical, optical, and appearance inspection parameters fall within the acceptable range of the preset packaging quality requirements. Packaging process parameter combinations that meet all quality indicators are selected as target process parameter combinations. For example, only process parameter combinations that simultaneously meet the following requirements are retained: forward voltage within the acceptable range, luminous flux reaching the specified lower limit, dominant wavelength and color coordinates falling within the target color region, and no bubbles or solder joint defects in the appearance. The die bonding, wire bonding, packaging, and curing process parameters in the target process parameter combinations are compared field-by-field with the original process parameters of the corresponding processes in the initial chip packaging process formula. The differences between each corresponding process parameter are calculated to form the optimized process parameter correction amount.

[0095] It should be noted that the packaging quality requirements are set through statistical analysis of the packaging quality results of historically qualified packaged chips.

[0096] S4. The optimized process parameter correction amount is superimposed with the initial chip packaging process formula to generate the optimized chip packaging process formula.

[0097] S4.1 Establish a one-to-one correspondence between the optimized process parameter correction amount and the corresponding process parameter in the initial chip packaging process formula according to the process classification, and update and replace the corresponding process parameter in the initial chip packaging process formula according to the optimized process parameter correction amount to generate the chip packaging optimized process formula.

[0098] Furthermore, the optimized process parameter corrections are matched with the process parameters in the initial chip packaging process recipe by process category (die bonding, wire bonding, packaging, curing) and full parameter name (such as die bonding pressure, wire bonding ultrasonic power, etc.). This ensures that each correction is paired only with its original process parameter of the same process and name, establishing a strict one-to-one mapping relationship. Based on the mapping relationship, for each process parameter in the initial chip packaging process recipe that has a one-to-one correspondence with the optimized process parameter correction, its original value is replaced with the algebraic sum of the original value and the corresponding optimized process parameter correction. For example, the original die bonding pressure value of 2.3MPa in the initial chip packaging process recipe is updated to 2.4MPa by adding the die bonding pressure correction +0.1MPa, thus generating the optimized chip packaging process recipe.

[0099] S5. Obtain chip packaging defect information, and map the chip packaging defect information to chip packaging process deviations according to the preset defect root cause map. By integrating with the optimized process parameter correction amount, finely modify and constrain the chip packaging optimized process formula, and generate a chip packaging process control instruction set.

[0100] S5.1 Perform defect statistics and classification records on the packaged chips to obtain chip packaging defect information.

[0101] Furthermore, the packaged chips undergo electrical, optical, and visual inspections in sequence to extract any abnormalities, including specific defect types such as excessive forward voltage, insufficient luminous flux, color coordinate offset, loose solder joints, bubbles in the package, and surface scratches. All defects are then structurally classified according to defect type, process (die bonding, wire bonding, packaging, or curing) and defect location to obtain chip packaging defect information.

[0102] S5.2. Based on the defect root cause map, search and match each chip packaging defect information according to the defect type and the process to which it belongs, and read the affected process parameters and offset direction corresponding to the chip packaging defect information.

[0103] Furthermore, the defect type and associated process of each chip packaging defect are used as the joint search key for precise matching in the defect root cause graph. The defect root cause graph stores historical correlation patterns in a four-tuple structure of "defect type - associated process - affected process parameter - offset direction". After a successful match, the affected process parameter field (such as die bonding pressure, wire bonding ultrasonic power, encapsulation glue amount or curing temperature) and offset direction field (such as "too high" or "too low") in the four-tuple are read, and the affected process parameters associated with each chip packaging defect and their offset direction are output to form a process deviation traceability record.

[0104] It should be noted that the defect root cause map is generated by statistically analyzing the correlation between defect types, defect occurrence processes, and corresponding process parameters in historical packaging batches, and determining key process parameters based on the process rules of each process, and organizing and setting them according to defect type-process-process parameter.

[0105] S5.3 Using the affected process parameters as an index, merge all offset directions pointing to the same affected process parameter to determine the process offset trend and form the chip packaging process deviation.

[0106] Furthermore, using the affected process parameters (such as die bonding pressure, wire bonding ultrasonic power, encapsulation adhesive amount, and curing temperature) as the merging index, all process deviation traceability records are grouped according to the parameter name; within each group, the frequency of occurrence of the two offset directions, "too high" and "too low", is counted; if the frequency of a certain offset direction exceeds a preset majority threshold (e.g., 70%), then that direction is determined as the process offset trend of the affected process parameter, and all affected process parameters and their corresponding process offset trends are combined to form the chip packaging process deviation.

[0107] It should be noted that most thresholds are determined based on the consistency of process parameter offset direction in historical packaging defect analysis. They are determined by calculating the minimum stable proportion of the same affected process parameter exhibiting the same offset direction in the same type of defect. Based on the statistical stability of process parameter offset direction in historical packaging defect data, the number of defect samples, and process sensitivity analysis, the value range of most thresholds is determined to be 60% to 85% of the example value.

[0108] S5.4. Correlate and integrate the chip packaging process deviation with the optimized process parameter correction amount under the same process and the same process parameter dimension to generate an optimized process parameter combination.

[0109] Furthermore, each affected process parameter in the chip packaging process deviation and its corresponding process offset trend are matched and aligned with the optimized process parameter correction amount for the same process step and the same process parameter name in the optimized process parameter correction amount. If a process parameter is marked as "too low" in the chip packaging process deviation, a positive enhancement amount is superimposed on its corresponding optimized process parameter correction amount; if it is marked as "too high", a negative suppression amount is superimposed. The magnitude of the enhancement or suppression amount is scaled proportionally according to the confidence strength of the process offset trend to generate an optimized process parameter combination.

[0110] S5.5. Based on the optimized process parameter combination, finely modify and constrain different process parameter combinations in the chip packaging optimization process formula to determine the optimal process parameter combination.

[0111] Furthermore, the process parameter corrections for each step in the optimized process parameter combination are progressively added to the corresponding process parameters of the chip packaging optimized process recipe, generating one or more updated candidate process parameter combinations. Next, equipment physical constraints, material thermal sensitivity constraints, and process window boundary constraints are applied to each candidate process parameter combination. Process parameters exceeding the boundaries are truncated or the entire candidate process parameter combination is removed, resulting in a set of feasible process parameter combinations that satisfy all constraints. Finally, based on the packaging quality prediction results, each process parameter combination in the set of feasible process parameter combinations is scored and ranked comprehensively. The process parameter combination that simultaneously meets the preset packaging quality requirements and has the highest comprehensive score is selected as the optimal process parameter group.

[0112] S5.6. Map the optimal combination of process parameters item by item into the equipment executable instruction fields corresponding to the die bonding process, wire bonding process, packaging process and curing process according to the chip packaging process chain, and arrange them in the order of the process to form a chip packaging process control instruction set.

[0113] Furthermore, the die-bonding pressure, die-bonding temperature, and die-bonding time in the optimal process parameter combination are read item by item. Based on the die-bonding equipment's instruction format, the die-bonding pressure is written into the "Pressure Setpoint" field according to the equipment's allowed units and ranges; the die-bonding temperature is matched to the die-bonding equipment's temperature control curve list and the corresponding "Temperature Control Curve Number" is filled in; the die-bonding time is converted to the second or millisecond time format required by the die-bonding equipment and written into the "Heating or Holding Time" field; these fields are then encapsulated into a die-bonding equipment instruction segment according to the equipment's specified order; the wire bonding ultrasonic power, wire bonding current, and wire bonding speed are numerically converted according to the wire bonding machine's setting rules. For example, the wire bonding ultrasonic power is converted into the wire bonding equipment's corresponding "Power Level Code," the wire bonding current is converted to the equipment's defined "Current Setpoint Register Format," and the wire bonding speed is converted into a motion axis "Speed ​​Command" according to the equipment's coordinate system; subsequently, these three fields are written into the wire bonding equipment's instruction template to form an executable wire bonding instruction segment; the encapsulated data is read from the optimal process parameters. The adhesive volume, encapsulation path coordinates, and encapsulation speed are calculated. The adhesive volume is converted into the "Valve Opening Duration" field according to the dispensing valve's flow calibration curve. The encapsulation path coordinates are converted into the "Motion Trajectory Coordinate Sequence" according to the dispensing platform coordinate system. The encapsulation speed is converted into the "Platform Movement Rate" field according to the platform controller's speed unit. Finally, these are combined into dispensing equipment instructions according to the dispensing equipment's program format. The curing temperature, curing time, and heating rate are read. The curing temperature is written into the curing oven's "Temperature Setpoint Field." The curing time is converted into the holding time format required by the curing oven program and written into the "Holding Time Field." The heating rate is written into the "Heating Slope Field" according to the equipment's heating curve definition. Subsequently, these three fields are combined into a complete curing oven executable instruction segment according to the curing oven's program segment format. The above four types of equipment executable instruction fields are arranged in sequence according to the chip packaging process chain—die bonding, wire bonding, encapsulation, and curing—to form a complete chip packaging process control instruction set.

[0114] In summary, this invention achieves the following by: constructing a digital twin model of chip packaging that can realistically reflect the behavior of multiple processes, using it to conduct rapid process simulation to output optimized parameters, and establishing a defect root cause map and quantifying and mapping defect information into process deviations and integrating them with the optimized parameters. This enables efficient acquisition of optimal process settings in a virtual environment, reduces the need for actual trial production, and allows for structured diagnosis of defect causes and automatic generation of process control instructions that can be executed by the equipment, thereby improving the optimization efficiency, stability, and intelligence level of the packaging process.

[0115] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for producing an LED package chip based on intelligent control, characterized by: The application relates to an LED chip packaging process parameter optimization method and device. According to the chip basic file, an initial packaging process formula of the chip is set, a chip packaging process chain is executed, chip packaging process data and chip packaging quality results are obtained, and the chip packaging process parameter optimization method comprises the following steps of, Selecting packaging process parameters from the chip packaging digital twin model as perturbation variables, and generating different process parameter combinations in the adjustable range of the perturbation variables; Running agent simulation on the chip packaging digital twin model for different process parameter combinations, obtaining packaging quality prediction results, and determining target process parameter combinations meeting preset packaging quality requirements according to the packaging quality prediction results; Comparing the target process parameter combinations with corresponding process parameters in the initial packaging process formula of the chip, and outputting the optimization process parameter correction amount; Superimposing the optimization process parameter correction amount and the initial packaging process formula of the chip to generate a chip packaging optimization process formula; Obtaining chip packaging defect information, mapping the chip packaging defect information to a chip packaging process deviation according to a preset defect root cause map, and performing fine correction and constraint on the chip packaging optimization process formula by fusing the optimization process parameter correction amount to generate a chip packaging process control instruction set. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device.

2. The LED package chip production method based on intelligent control according to claim 1, wherein: The application relates to an LED chip packaging process parameter optimization method and device.

3. The LED package chip production method based on intelligent control according to claim 1, wherein: The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device.

4. The LED package chip production method based on intelligent control according to claim 3, wherein: The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. The application relates to an LED chip packaging process parameter optimization method and device. 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The application relates Read the chip comprehensive characteristic information from the chip basic file, and match the corresponding packaging equipment, packaging materials and process conditions according to the chip comprehensive characteristic information, to determine the chip initial packaging process formula; According to the chip initial packaging process formula, the die bonding process, wire bonding process, packaging process and curing process are sequentially executed on the corresponding packaging equipment according to the chip packaging process chain, and the equipment running state and process execution information are collected in real time to form the chip packaging process data; The packaged chip is taken as a detection object for electrical detection, optical detection and appearance detection to obtain the chip packaging quality result.

5. The LED package chip production method based on intelligent control according to claim 4, wherein: Based on the chip packaging process data and the chip packaging quality result, the chip packaging digital twin model is constructed and corrected, and the specific steps are as follows, According to the chip packaging process data, the die bonding process behavior model, the wire bonding process behavior model, the packaging process behavior model and the curing process behavior model are constructed, and each process behavior model is taken as the process domain of the chip packaging digital twin model; The chip packaging quality result is mapped to the corresponding chip packaging process data through a unified coordinate index to form a cross-process correspondence relationship as the quality domain of the chip packaging digital twin model; Under the unified time axis, the quality domain is one-to-one associated with the same time position in the process domain according to the time position of the corresponding process in the chip packaging process chain to form the chip packaging digital twin initial model; The chip packaging process is simulated based on the chip packaging digital twin initial model to obtain the simulation quality result, and the simulation quality result is compared with the chip packaging quality result to obtain the deviation information; The deviation information is injected into the process domain in reverse order according to the chip packaging process chain, and each process parameter is iteratively adjusted until the prediction error converges to obtain the chip packaging digital twin model.

6. The smart control based LED package chip production method according to claim 1, wherein: The generation of the chip packaging optimization process formula refers to establishing a one-to-one correspondence between the optimization process parameter correction amount and the corresponding process parameter in the chip initial packaging process formula according to the process classification, and updating and replacing the corresponding process parameter in the chip initial packaging process formula according to the optimization process parameter correction amount.

7. The smart control based LED package chip production method according to claim 1, wherein: The defect root cause map is obtained by statistically analyzing the correlation rules of defect types, defect occurrence processes and corresponding process parameters in historical packaging batches, and determining the key process parameters according to the process rules of each process.

8. The smart control based LED package chip production method as claimed in claim 1, wherein: The fine correction and constraint of the chip packaging optimization process formula by fusing with the optimization process parameter correction amount are performed to generate the chip packaging process control instruction set, and the specific steps are as follows, The chip packaging process deviation and the optimization process parameter correction amount are associated and fused in the same process and the same process parameter dimension to generate an optimization process parameter combination; According to the optimization process parameter combination, the different process parameter combinations in the chip packaging optimization process formula are finely corrected and constrained to determine the optimal process parameter combination; According to the chip packaging process chain, the optimal process parameter combination is mapped to the device executable instruction field corresponding to the die bonding process, the wire bonding process, the packaging process and the curing process one by one, and is arranged and output in the order of the processes to form the chip packaging process control instruction set.

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