Voltage regulation circuit

Abstract

The invention discloses a voltage regulation circuit which comprises a first P tube source, a second P tube source, a fifth P tube source, a fifth N tube drain, an eighth N tube drain and a ninth N tube drain. The fifth to seventh N tube sources and the negative plate of the capacitor are grounded; the drain of the first P tube is connected with the source of the third P tube, and the gate is connected with the gate of the second P tube and the drain of the third P tube; the drain of the first P tube is connected with the source of the third P tube, and the gate is connected with the gate of the second P tube and the drain of the third P tube; the drain of the second P tube is connected with a fourth P tube source; the grid of the third P tube is connected with the grid of the fourth P tube; a drain of the fourth P tube is connected with a drain of the fourth N tube, an eighth N tube source and a ninth N tube grid; a drain of the fifth P tube is connected with a sixth P tube source, and a gate is connected with a second bias voltage; the drain of the sixth P tube is connected with the drain of the seventh N tube and the gate of the eighth N tube; the drain of the first N tube is connected with a third N tube source, the source is connected with a second N tube source and the drain of a sixth N tube, and the grid is connected with a reference voltage node; the drain of the second N tube is connected with a fourth N tube source, and the gate is connected with a ninth N tube source; the grid of the third N tube is connected with the grid of the fourth N tube; a fifth N tube grid is connected with a sixth N tube drain, a sixth N tube grid, a seventh N tube grid and an eighth N tube source; and the source forms an output end, and the grid is connected with the positive plate of the capacitor.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a voltage regulation circuit that can achieve rapid voltage regulation when the load current undergoes a step change. Background Technology

[0002] Voltage regulators / linear regulators are widely used in integrated circuits, mainly to convert fluctuating upstream power sources (batteries, AC-DC, DC-DC buses) into local power sources with extremely low ripple, controllable noise, precision, and fast transient response.

[0003] Voltage regulators / linear regulators are widely integrated into SoCs, PMICs, and subsystems such as RF, audio, and memory interfaces to provide low-ripple, low-noise local power for digital cores, analog front-ends, sensors, and interface IPs. With increasing system clock frequencies and expanding CPU / GPU Dynamic Voltage Frequency Scaling (DVFS) ranges, load currents can jump from microamps to milliamps or even amps in nanosecond increments. Traditional linear regulators, such as... Figure 1 As shown, the power PMOS transistor M0 is driven by an error amplifier, and the gate capacitor of the power transistor is charged and discharged through the node NGATE at the output terminal. When the load current at the output terminal OUT suddenly increases, the output voltage VOUT drops rapidly. Due to its own bias current IB (usually only a few microamps), the charging current of the capacitor is small, resulting in a slow rise in the potential of the NGATE node. The power transistor cannot increase its conduction current in time, and the time required for VOUT to recover to its rated value is long. The system may reset due to undervoltage or experience performance degradation. Summary of the Invention

[0004] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] The technical problem to be solved by the present invention is to provide a voltage regulation circuit that, based on the same bias current of the operational amplifier, can shorten the output voltage recovery time when the load current undergoes a step (especially a nanosecond-level step) and achieve fast voltage regulation.

[0006] To solve the above-mentioned technical problems, the voltage adjustment circuit provided by the present invention is characterized by comprising: first PMOS to sixth PMOS MP1, MP2, MP3, MP4, MP5, MP6, first NMOS to ninth NMOS MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9 and capacitor C1;

[0007] The power supply voltage VDD is connected to the drain of the fifth NMOS MN5 via the first current source IB, and to the drain of the eighth NMOS MN8 via the second current source IBA. It is also connected to the source of the first PMOS MP1, the source of the second PMOS MP2, the source of the fifth PMOS MP5, and the drain of the ninth NMOS MN9.

[0008] The ground node GND is connected to the source of the fifth NMOS MN5, the source of the sixth NMOS MN6, the source of the seventh NMOS MN7, and the negative plate of capacitor C1, respectively.

[0009] The first PMOS MP1 has its drain connected to the source of the third PMOS MP3, and its gate connected to the gate of the second PMOS MP2 and the drain of the third PMOS MP3.

[0010] The first PMOS MP1 has its drain connected to the source of the third PMOS MP3, and its gate connected to the gate of the second PMOS MP2 and the drain of the third PMOS MP3.

[0011] The drain of the second PMOS MP2 is connected to the source of the fourth PMOS MP4.

[0012] The drain of the third PMOS MP3 is connected to the drain of the third NMOS MN3, and its gate is connected to the gate of the fourth PMOS MP4.

[0013] The fourth PMOS MP4 has its drain connected to the drain of the fourth NMOS MN4 and the first electrical node NGATE;

[0014] The fifth PMOS MP5 has its drain connected to the source of the sixth PMOS MP6, and its gate connected to the second bias voltage VB4.

[0015] The sixth PMOS MP6 has its drain connected to the drain of the seventh NMOS MN7 and the gate of the eighth NMOS MN8, and its gate is connected to the first bias voltage VB3.

[0016] The first NMOS MN1 has its drain connected to the source of the third NMOS MN3, its source connected to the source of the second NMOS MN2 and the drain of the sixth NMOS MN6, and its gate connected to the reference voltage node VREF.

[0017] The drain of the second NMOS MN2 is connected to the source of the fourth NMOS MN4, and its gate is connected to the source of the ninth NMOS MN9;

[0018] The third NMOS MN3 has its gate connected to the gate of the fourth NMOS MN4;

[0019] The fifth NMOS MN5 has its gate connected to the drain of the sixth NMOS MN6, the gate of the sixth NMOS MN6, the gate of the seventh NMOS MN7, and the source of the eighth NMOS MN8;

[0020] The ninth NMOS MN9 has its gate connected to the first electrical node NGATE and its source forming the output terminal OUT.

[0021] Capacitor C1 has its positive plate connected to the first electrical node NGATE.

[0022] Preferably, in the voltage adjustment circuit described further, the width-to-length ratio of the fifth NMOS MN5, the seventh NMOS MN7 and the sixth NMOS MN6 is 1:N:M, and satisfies 1>N:M>1 / 2;

[0023] The width-to-length ratio of the fifth PMOS MP5, the first PMOS MP1, and the second PMOS MP2 is 1:1:1.

[0024] Preferably, the voltage adjustment circuit further includes: a first resistor R1 and a second resistor R2;

[0025] The first resistor R1 and the second resistor R2 are connected in series between the output terminal OUT and the ground node GND to form a voltage divider network. The gate of the second NMOS MN2 is connected between the first resistor R1 and the second resistor R2.

[0026] Preferably, the voltage adjustment circuit further describes different output voltages by adjusting the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0027] Preferably, in the voltage adjustment circuit described further, the current value provided by the second current source IBA is greater than the current value provided by the first current source IB.

[0028] Preferably, in the voltage adjustment circuit described further, the current value provided by the second current source IBA is 10 times that provided by the first current source IB.

[0029] Preferably, in the voltage adjustment circuit described further, the capacitance value of capacitor C1 is between 1pF and 100pF.

[0030] Preferably, in the further described voltage adjustment circuit, the reference voltage node VREF is connected to the output of the internal bandgap reference circuit to shorten the output voltage recovery time.

[0031] The main design concept of this invention is to inject an additional large current directly into the power transistor at the instant a sudden drop in output is detected, including the following operating conditions:

[0032] 1. Normal steady state: VREF = VFB, bias current IB is small, and power consumption is low.

[0033] 2. Load Step (High Current Draw): VOUT drops rapidly → VFB drops → MN2 turns off. The current mirror ratio setting makes the MP5 current momentarily greater than MN7, and node DET flips high. The high level of node DET turns on MN8, injecting an additional bias current IBA into the op-amp, increasing the total bias from IB to IB+IBA, and instantly increasing the op-amp bandwidth / slew rate. This accelerates the charging of the power transistor gate, and VOUT recovers quickly.

[0034] 3. Accelerated recovery: VFB≈VREF, node DET goes low, MN8 is turned off, and the bias recovers to low-power IB.

[0035] Under typical test conditions (load 1μA→1mA, 10ns step), the time for the output voltage of this invention to recover to 5% of its final value is shortened from 29μs in the traditional scheme to 19μs, improving the recovery speed by about 34%.

[0036] In steady state, it maintains the same low bias current as traditional circuits without increasing static power consumption; it only automatically provides "accelerating current" during transient large current jumps, thus balancing low power consumption and high-speed response. Attached Figure Description

[0037] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0038] Figure 1 This is a schematic diagram of the existing technology circuit structure.

[0039] Figure 2 This is a schematic diagram of the circuit structure of the first embodiment of the present invention.

[0040] Figure 3 This is a schematic diagram of the circuit structure of the second embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram comparing the simulation results of the present invention and the prior art. Detailed Implementation

[0042] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present invention is thorough and complete, and that the technical solutions of these exemplary embodiments are fully conveyed to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] First embodiment;

[0044] refer to Figure 2 As shown, the present invention provides a voltage regulation circuit, including: first PMOS to sixth PMOS MP1, MP2, MP3, MP4, MP5, MP6, first NMOS to ninth NMOS MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9 and capacitor C1;

[0045] The power supply voltage VDD is connected to the drain of the fifth NMOS MN5 via the first current source IB, and to the drain of the eighth NMOS MN8 via the second current source IBA. It is also connected to the source of the first PMOS MP1, the source of the second PMOS MP2, the source of the fifth PMOS MP5, and the drain of the ninth NMOS MN9.

[0046] The ground node GND is connected to the source of the fifth NMOS MN5, the source of the sixth NMOS MN6, the source of the seventh NMOS MN7, and the negative plate of capacitor C1, respectively.

[0047] The first PMOS MP1 has its drain connected to the source of the third PMOS MP3, and its gate connected to the gate of the second PMOS MP2 and the drain of the third PMOS MP3.

[0048] The first PMOS MP1 has its drain connected to the source of the third PMOS MP3, and its gate connected to the gate of the second PMOS MP2 and the drain of the third PMOS MP3.

[0049] The drain of the second PMOS MP2 is connected to the source of the fourth PMOS MP4.

[0050] The drain of the third PMOS MP3 is connected to the drain of the third NMOS MN3, and its gate is connected to the gate of the fourth PMOS MP4.

[0051] The fourth PMOS MP4 has its drain connected to the drain of the fourth NMOS MN4 and the first electrical node NGATE;

[0052] The fifth PMOS MP5 has its drain connected to the source of the sixth PMOS MP6, and its gate connected to the second bias voltage VB4.

[0053] The sixth PMOS MP6 has its drain connected to the drain of the seventh NMOS MN7 and the gate of the eighth NMOS MN8, and its gate is connected to the first bias voltage VB3.

[0054] The first NMOS MN1 has its drain connected to the source of the third NMOS MN3, its source connected to the source of the second NMOS MN2 and the drain of the sixth NMOS MN6, and its gate connected to the reference voltage node VREF; the reference voltage node VREF is connected to the output of the internal bandgap reference circuit.

[0055] The drain of the second NMOS MN2 is connected to the source of the fourth NMOS MN4, and its gate is connected to the source of the ninth NMOS MN9;

[0056] The third NMOS MN3 has its gate connected to the gate of the fourth NMOS MN4;

[0057] The fifth NMOS MN5 has its gate connected to the drain of the sixth NMOS MN6, the gate of the sixth NMOS MN6, the gate of the seventh NMOS MN7, and the source of the eighth NMOS MN8;

[0058] The ninth NMOS MN9 has its gate connected to the first electrical node NGATE and its source forming the output terminal OUT.

[0059] Capacitor C1 has its positive plate connected to the first electrical node NGATE.

[0060] Preferably, the width-to-length ratio of the fifth NMOS MN5, the seventh NMOS MN7 and the sixth NMOS MN6 is 1:N:M, and satisfies 1>N:M>1 / 2;

[0061] The width-to-length ratio of the fifth PMOS MP5, the first PMOS MP1, and the second PMOS MP2 is 1:1:1.

[0062] Preferably, the capacitance value of capacitor C1 is between 1pF and 100pF.

[0063] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0064] Second embodiment;

[0065] refer to Figure 3 As shown, the present invention provides a voltage regulation circuit, which is an improvement on the first embodiment described above. The same parts will not be repeated here, and it also includes:

[0066] First resistor R1 and second resistor R2;

[0067] The first resistor R1 and the second resistor R2 are connected in series between the output terminal OUT and the ground node GND, and the gate of the second NMOS MN2 is connected between the first resistor R1 and the second resistor R2.

[0068] Different output voltages can be generated by adjusting the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0069] Preferably, the current value provided by the second current source IBA in the first or second embodiment described above is greater than the current value provided by the first current source IB. For example, the current value provided by the second current source IBA is 10 times that provided by the first current source IB.

[0070] Preferably, the capacitance value of capacitor C1 is between 1pF and 100pF.

[0071] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0072] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A voltage regulation circuit, characterized in that, include: The first PMOS to the sixth PMOS (MP1, MP2, MP3, MP4, MP5, MP6), the first NMOS to the ninth NMOS (MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9) and the capacitor (C1); The supply voltage (VDD) is connected to the drain of the fifth NMOS (MN5) via the first current source (IB), and to the drain of the eighth NMOS (MN8) via the second current source (IBA). It is also connected to the source of the first PMOS (MP1), the source of the second PMOS (MP2), the source of the fifth PMOS (MP5), and the drain of the ninth NMOS (MN9). The ground node (GND) is connected to the source of the fifth NMOS (MN5), the source of the sixth NMOS (MN6), the source of the seventh NMOS (MN7), and the negative plate of the capacitor (C1), respectively. The first PMOS (MP1) has its drain connected to the source of the third PMOS (MP3), and its gate connected to the gate of the second PMOS (MP2) and the drain of the third PMOS (MP3). The first PMOS (MP1) has its drain connected to the source of the third PMOS (MP3), and its gate connected to the gate of the second PMOS (MP2) and the drain of the third PMOS (MP3). The drain of the second PMOS (MP2) is connected to the source of the fourth PMOS (MP4); The third PMOS (MP3) has its drain connected to the drain of the third NMOS (MN3) and its gate connected to the gate of the fourth PMOS (MP4). The fourth PMOS (MP4) has its drain connected to the drain of the fourth NMOS (MN4) and the first electrical node (NGATE); The fifth PMOS (MP5) has its drain connected to the source of the sixth PMOS (MP6), and its gate connected to the second bias voltage (VB4). The sixth PMOS (MP6) has its drain connected to the drain of the seventh NMOS (MN7) and the gate of the eighth NMOS (MN8), and its gate is connected to the first bias voltage (VB3). The first NMOS (MN1) has its drain connected to the source of the third NMOS (MN3), its source connected to the source of the second NMOS (MN2) and the drain of the sixth NMOS (MN6), and its gate connected to the reference voltage node (VREF). The second NMOS (MN2) has its drain connected to the source of the fourth NMOS (MN4) and its gate connected to the source of the ninth NMOS (MN9); The third NMOS (MN3) has its gate connected to the gate of the fourth NMOS (MN4); The fifth NMOS (MN5) has its gate connected to the drain of the sixth NMOS (MN6), the gate of the sixth NMOS (MN6), the gate of the seventh NMOS (MN7), and the source of the eighth NMOS (MN8); The ninth NMOS (MN9) has its gate connected to the first electrical node (NGATE) and its source forming the output terminal (OUT); The capacitor (C1) has its positive plate connected to the first electrical node (NGATE).

2. The voltage regulation circuit as described in claim 1, characterized in that: The width-to-length ratio of the fifth NMOS (MN5), the seventh NMOS (MN7), and the sixth NMOS (MN6) is 1:N:M, and satisfies 1>N:M>1 / 2; The width-to-length ratio of the fifth PMOS (MP5), the first PMOS (MP1), and the second PMOS (MP2) is 1:1:

1.

3. The voltage regulation circuit as described in claim 1 or 2, characterized in that, Also includes: First resistor (R1) and second resistor (R2); The first resistor (R1) and the second resistor (R2) are connected in series between the output terminal (OUT) and the ground node (GND), and the gate of the second NMOS (MN2) is connected between the first resistor (R1) and the second resistor (R2).

4. The voltage adjustment circuit as described in claim 3, characterized in that: Different output voltages are generated by adjusting the ratio of the resistance values ​​of the first resistor (R1) and the second resistor (R2).

5. The voltage regulation circuit as described in any one of claims 1-3, characterized in that: The current provided by the second current source (IBA) is greater than the current provided by the first current source (IB).

6. The voltage regulation circuit as described in claim 5, characterized in that: The second current source (IBA) provides 10 times the current provided by the first current source (IB).

7. The voltage regulation circuit as described in any one of claims 1-3, characterized in that, The capacitance value of capacitor (C1) is between 1pF and 100pF.

8. The voltage regulation circuit as described in any one of claims 1-3, characterized in that, The reference voltage node (VREF) is connected to the output of the internal bandgap reference circuit.

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