Intra-pulse modulation type real-time identification system and identification method based on multi-core DSP

Abstract

The invention discloses an intra-pulse modulation type real-time identification system and identification method based on a multi-core DSP (Digital Signal Processor), and the system comprises an FPGA (Field Programmable Gate Array) which is used for carrying out signal channelization sampling and outputting baseband IQ data; the DDR is in communication connection with the FPGA, and the DDR is used for receiving baseband IQ data of the FPGA; the DSP chip is respectively in communication connection with the DDR and the FPGA, the DSP chip is provided with eight processor cores capable of accessing the DDR at the same time, and each processor core can identify the modulation type of the baseband IQ data; one of the eight processor cores is a master core, and the other seven processor cores are slave cores; baseband IQ data in the DDR can be averagely divided into 8 parts, the 8 processor cores take the data according to the initial addresses of the data processed by the 8 processor cores and carry out identification processing, finally, the identification results of the 8 processor cores are statistically analyzed through the main core, and the optimal identification result is output. The system has the advantage that the system can realize real-time analysis of intra-pulse modulation type identification under high pulse density.

Description

Technical Field

[0001] This invention relates to the field of radar signal processing technology, and in particular to a real-time identification system and method for intra-pulse modulation type based on a multi-core DSP, as well as the use of the domestically produced multi-core DSP Phytium 6678 chip, which is suitable for scenarios such as electronic reconnaissance and signal analysis. Background Technology

[0002] With the rapid development of electronic technology, various new radar systems are emerging. The intra-pulse modulation types and parameters of radar signals are becoming increasingly complex. Common types include linear frequency modulated signals, conventional spot frequency signals, and phase-coded signals. Due to the increasing number and types of radiation source signals, coupled with various interference signals, the difficulty of signal sorting and target identification in electronic reconnaissance is growing. Therefore, there is an urgent need to increase the intra-pulse modulation type of radar signals as a sorting criterion to improve identification accuracy.

[0003] Currently, in engineering applications, pulse signal modulation type identification can be implemented using either FPGA chips or a single-core DSP chip. The advantage of FPGA chips is their fast processing speed and quick identification results. However, the limitation of FPGA chips makes them unsuitable for complex processing algorithms, resulting in low accuracy for intra-pulse modulation type identification. Another approach relies on single-core DSP chips. This method offers the advantage of identifying various modulation types through complex software algorithms, achieving high accuracy. However, its processing speed is slow. While existing single-core DSP chip-based identification methods are effective for low-repetition-rate pulse signals, their processing speed becomes insufficient for high pulse density, failing to meet real-time requirements. Therefore, improvements to existing identification technologies are necessary.

[0004] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0005] Based on the aforementioned technical problems, the purpose of this invention is to provide a real-time pulse modulation type identification system and method based on a multi-core DSP. This system combines an FPGA and a multi-core DSP chip processor. The DSP chip adopts a main core plus slave core parallel data processing architecture, which can realize real-time analysis of pulse modulation type identification under high pulse density, ensuring both identification speed and high identification accuracy.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] A real-time pulse modulation type identification system based on a multi-core DSP, comprising:

[0008] FPGA, which is used for channelized sampling of signals and outputting baseband IQ data;

[0009] DDR, which is connected to the FPGA for communication, is used to receive baseband IQ data from the FPGA;

[0010] The DSP chip communicates with both DDR and FPGA. The DSP chip has eight processor cores that can access DDR simultaneously. Each processor core can identify the modulation type of the baseband IQ data. One of the eight processor cores is the master core, and the other seven are slave cores. The baseband IQ data in DDR can be divided into eight equal parts. The eight processor cores retrieve the data according to the starting address of the data they are responsible for processing and perform identification processing. Finally, the master core performs statistical analysis on the identification results of the eight processor cores and outputs the optimal identification result.

[0011] Optionally, the FPGA can transmit baseband IQ data to the DDR via the SRIO high-speed interface.

[0012] Optionally, the DSP chip is a multi-core DSP Phytium 6678 chip.

[0013] Optionally, a recognition method for the aforementioned real-time pulse modulation type recognition system based on multi-core DSP includes:

[0014] The FPGA transmits baseband IQ data to the DDR and sends a doorbell signal to the DSP chip;

[0015] After receiving the doorbell, the eight processor cores of the DSP chip read the data that each processor core needs to process from the pre-specified DDR address into the DSP shared memory.

[0016] After receiving the data, the eight processor cores change their status from standby to working, and each processor core calculates the modulation type according to the recognition algorithm.

[0017] Each slave core sends its recognition result to the master core, and at the same time sets the corresponding calculation completion flag to 1, and its status changes from working state to standby state;

[0018] After the master core detects that the calculation completion flags of each slave core are all 1, it performs statistics on the 8-core recognition results, sorts the 8-core recognition results according to the number of occurrences, and outputs the recognition result with the most occurrences as the optimal recognition result.

[0019] Optionally, the FPGA transmits baseband IQ data to the DDR via the SRIO high-speed interface.

[0020] Optionally, the modulation type identification algorithm is the same for all processor cores.

[0021] Optionally, the modulation type identification algorithm of the main core includes:

[0022] Perform a phase difference operation on each baseband IQ data and calculate the corresponding instantaneous frequency f(t);

[0023] Calculate the standard deviation of the phase first difference for each baseband IQ data.

[0024] Calculate the phase quadratic difference for each baseband IQ data, and then calculate the standard deviation of the corresponding phase quadratic difference.

[0025] Using the minimum linear fitting method, linear fitting is performed on each instantaneous frequency f(t) to obtain the linear fitting error σ and the linear modulation slope k;

[0026] Calculate the mean and extreme values ​​of the first difference for each phase, then calculate the difference between each extreme value and the mean. This difference is the phase value of the transition. Record the phase value of the transition, and then identify the modulation type of each baseband IQ data based on the above data.

[0027] Optionally, the criteria for each processor core to identify the modulation type include:

[0028] Standard point frequency signal: Standard deviation of the first phase difference

[0029] Standard deviation of phase quadratic difference

[0030] Linear fitting error σ < threshold3;

[0031] Linear modulation slope k < threshold 4;

[0032] Linear frequency modulated signal: Standard deviation of the first phase difference

[0033] Standard deviation of phase quadratic difference

[0034] Linear fitting error σ < threshold3;

[0035] Linear modulation slope k > threshold4;

[0036] Biphasic coded signal: Standard deviation of the first phase difference

[0037] Linear modulation slope k < threshold 4;

[0038] The phase jump values ​​are around 0° and 180°;

[0039] Four-phase coded signal: Standard deviation of the first phase difference

[0040] Linear modulation slope k < threshold 4;

[0041] The phase jump values ​​are around 0°, 90°, 180°, and 270°;

[0042] Among them, threshold1, threshold2, threshold3 and threshold4 are the first threshold, the second threshold, the third threshold and the fourth threshold, respectively.

[0043] Compared with the prior art, the present invention has the following advantages:

[0044] The present invention discloses a real-time pulse modulation type identification system and method based on a multi-core DSP. The system combines an FPGA and a multi-core DSP chip processor. The DSP chip adopts a main core plus slave core parallel data processing architecture, which can realize real-time analysis of pulse modulation type identification under high pulse density, ensuring both identification speed and high identification accuracy. Attached Figure Description

[0045] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the drawings in the following description are one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0046] Figure 1 This is a schematic diagram of a real-time pulse modulation type identification system based on a multi-core DSP according to the present invention;

[0047] Figure 2 This is a schematic diagram of a recognition method for a real-time pulse modulation type recognition system based on a multi-core DSP according to the present invention. Detailed Implementation

[0048] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the real-time intra-pulse modulation type identification system and method based on a multi-core DSP proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0049] like Figure 1 The diagram illustrates a real-time intra-pulse modulation type identification system based on a multi-core DSP according to the present invention. The system comprises an FPGA, a DDR (memory system), and a DSP chip. The FPGA is used for signal channelization sampling and outputting baseband IQ data. The DDR is communicatively connected to the FPGA and receives the baseband IQ data from the FPGA. The DSP chip is communicatively connected to both the DDR and the FPGA. The DSP chip has eight processor cores that can simultaneously access the DDR, and each processor core can identify the modulation type of the baseband IQ data. One of the eight processor cores is the master core, and the other seven are slave cores. The baseband IQ data in the DDR can be divided into eight equal parts. The eight processor cores retrieve the data according to the starting address of their respective data processing units and perform identification processing. Finally, the master core performs statistical analysis on the identification results of the eight processor cores and outputs the optimal identification result.

[0050] As described above, the real-time intra-pulse modulation type identification system based on multi-core DSP of the present invention combines an FPGA and a multi-core DSP chip processor, enabling rapid intra-pulse modulation type identification of high repetition rate pulse signals. The DSP chip in this system adopts a master-slave core architecture for parallel data processing, achieving real-time analysis of intra-pulse modulation type identification under high pulse density, ensuring both identification speed and high identification accuracy.

[0051] like Figure 1As shown, in this embodiment, the FPGA transmits baseband IQ data to the DDR of the signal processor via the SRIO high-speed interface. The DSP chip has eight processor cores, Core 0 to Core 7, with Core 0 being the master core and the other seven being slave cores. The multi-core DSP chip can quickly identify the intra-pulse modulation type, including conventional pulse signals, linear frequency modulated signals, binary coded signals, and quadrature coded signals. It can also provide some characteristic parameters, such as the linear frequency modulation bandwidth and the linear modulation slope k, realizing the engineering application of radar signal intra-pulse modulation type identification. The linear modulation slope can be combined with the pulse parameter pw (which can be provided to the DSP chip by the FPGA after signal detection) to obtain the linear frequency modulation bandwidth (|k|·pw).

[0052] Furthermore, in this embodiment, the DSP chip hardware adopts the domestically produced multi-core DSP Phytium 6678 chip from the National University of Defense Technology, with each DSP chip containing 8 processor cores. Alternatively, the FPGA can also use domestically produced high-performance FPGA hardware (such as the SMQ7K410TFFG900 chip from Shenzhen Guowei Company). This approach satisfies both the demand for powerful signal processing capabilities and the requirement for domestic production. In practical applications, imported DSP chips and domestically produced DSP chips have different underlying drivers, and the code of the two platforms is incompatible. Imported DSP chips can bring many design difficulties.

[0053] Based on the same inventive concept, this invention also provides a recognition method for a real-time pulse modulation type recognition system based on a multi-core DSP. For example... Figure 2 As shown, the method includes: S1, the FPGA transmits baseband IQ data to DDR. After sending data to DDR, the FPGA sends a doorbell signal to the eight processor cores (Core 0 to Core 7) of the DSP chip; S2, after receiving the doorbell signal, the eight processor cores of the DSP chip read the data to be processed by each processor core from the pre-specified DDR address into the DSP shared memory; S3, after receiving the data, the eight processor cores change their state from standby to working state, and each processor core calculates the modulation type according to the recognition algorithm; S4, each slave core (Core 1 to Core 7) sends its recognition result to the master core (Core 0), and sets the corresponding calculation completion flag to 1, changing its state from working state to standby state; S5, after the master core detects that the calculation completion flags of each slave core are all 1, it performs statistics on the recognition results of the eight cores, sorts the recognition results of the eight cores according to the frequency of occurrence, and outputs the recognition result with the most occurrences as the optimal recognition result to the signal sorting module.

[0054] As can be seen from the above, the present invention makes full use of the advantages of multi-core DSP chips, adopts a master-slave model structure, processes data in parallel by multiple cores, and outputs the final recognition result by the master core. The division of labor is clear, the processing speed is efficient and the recognition accuracy is high.

[0055] Furthermore, in S1, the FPGA transmits baseband IQ data to the DDR of the signal processor via the SRIO high-speed interface. The effective transmission rate of a single channel of the SRIO high-speed interface is 2.5Gbps, and theoretically, all four channels can transmit 1.25GB of data per second. In actual design, the size of the baseband IQ data is related to the sampling rate of the FPGA and the data processing capability of the DSP.

[0056] In step S2, the baseband data in the DDR is divided into 8 equal parts so that the 8 cores can retrieve and process the data according to the starting address of the data they are responsible for processing.

[0057] On the other hand, as described above, in this invention, the eight processor cores of the DSP chip perform calculations in parallel. Optionally, each processor core executes the same modulation type recognition algorithm. In practical applications, the processor cores of the DSP chip can identify various modulation type signals through complex software algorithms, achieving fast recognition speed and high accuracy. The intra-pulse modulation types that the DSP chip can quickly identify include conventional pulse signals (conventional point-frequency signals), linear frequency modulated signals, binary coded signals, and quadrature coded signals. The processor cores of the DSP chip can provide some characteristic parameters, such as linear frequency modulation bandwidth and linear modulation slope k, realizing the engineering application of intra-pulse modulation type recognition for radar signals.

[0058] Taking the main core as an example, the modulation type identification algorithm of the main core includes the following steps: T1, performing a first-order phase difference on each baseband IQ data and calculating the corresponding instantaneous frequency f(t); T2, calculating the standard deviation of the first-order phase difference for each baseband IQ data. T3. Calculate the phase quadratic difference for each baseband IQ data, and calculate the standard deviation of the corresponding phase quadratic difference. T4. Using the minimum linear fitting method, perform linear fitting on each instantaneous frequency f(t) to obtain the linear fitting error σ and the linear modulation slope k. T5. Calculate the mean and extreme values ​​of the first-order difference for each phase, then calculate the difference between each extreme value and the mean. This difference is the phase value of the transition corresponding to the baseband IQ data, i.e., the phase transition value. Record the phase values ​​of the transitions corresponding to each baseband IQ data, and then identify the modulation type of each baseband IQ data based on the above data. It is understandable that each processor core can use the above process for identification.

[0059] In this invention, each processor core can identify the modulation type according to the following criteria:

[0060] Standard point frequency signal: Standard deviation of the first phase difference

[0061] Standard deviation of phase quadratic difference

[0062] Linear fitting error σ < threshold3;

[0063] Linear modulation slope k < threshold 4;

[0064] Linear frequency modulated signal: Standard deviation of the first phase difference

[0065] Standard deviation of phase quadratic difference

[0066] Linear fitting error σ < threshold3;

[0067] Linear modulation slope k > threshold4;

[0068] Biphasic coded signal: Standard deviation of the first phase difference

[0069] Linear modulation slope k < threshold 4;

[0070] The phase jump values ​​are around 0° and 180°;

[0071] Four-phase coded signal: Standard deviation of the first phase difference

[0072] Linear modulation slope k < threshold 4;

[0073] The phase jump values ​​are around 0°, 90°, 180°, and 270°;

[0074] Among them, threshold1, threshold2, threshold3, and threshold4 are the first threshold, second threshold, third threshold, and fourth threshold, respectively. Each threshold is a pre-set threshold, which is usually determined based on simulation results. Furthermore, 0° represents no transition, the occurrence of the above two transition values ​​is a two-phase coded signal, and the occurrence of the above four transition values ​​is a four-phase coded signal.

[0075] In summary, the present invention provides a real-time pulse modulation type identification system and method based on a multi-core DSP. This system combines an FPGA and a multi-core DSP chip processor. The DSP chip adopts a main core plus slave core parallel data processing architecture, which can realize real-time analysis of pulse modulation type identification under high pulse density, ensuring both identification speed and high identification accuracy.

[0076] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0077] In the description of this invention, it should be understood that the terms "center," "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0078] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0079] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0080] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A real-time pulse modulation type identification system based on a multi-core DSP, characterized in that, Includes: an FPGA, which is used for channelized sampling of signals and outputting baseband IQ data; DDR, which is connected to the FPGA for communication, is used to receive baseband IQ data from the FPGA; The DSP chip communicates with both DDR and FPGA. The DSP chip has eight processor cores that can access DDR simultaneously. Each processor core can identify the modulation type of the baseband IQ data. One of the eight processor cores is the master core, and the other seven are slave cores. The baseband IQ data in DDR can be divided into eight equal parts. The eight processor cores retrieve the data according to the starting address of the data they are responsible for processing and perform identification processing. Finally, the master core performs statistical analysis on the identification results of the eight processor cores and outputs the optimal identification result.

2. The real-time pulse modulation type identification system based on multi-core DSP as described in claim 1, characterized in that, The FPGA transmits baseband IQ data to the DDR via the SRIO high-speed interface.

3. The real-time pulse modulation type identification system based on multi-core DSP as described in claim 1, characterized in that, The DSP chip is a multi-core DSP Phytium 6678 chip.

4. A recognition method for a real-time pulse modulation type recognition system based on a multi-core DSP as described in any one of claims 1 to 3, characterized in that, Include: The FPGA transmits baseband IQ data to the DDR and sends a doorbell signal to the DSP chip; After receiving the doorbell, the eight processor cores of the DSP chip read the data that each processor core needs to process from the pre-specified DDR address into the DSP shared memory. After receiving the data, the eight processor cores change their status from standby to working, and each processor core calculates the modulation type according to the recognition algorithm. Each slave core sends its recognition result to the master core, and at the same time sets the corresponding calculation completion flag to 1, and its status changes from working state to standby state; After the master core detects that the calculation completion flags of each slave core are all 1, it performs statistics on the 8-core recognition results, sorts the 8-core recognition results according to the number of occurrences, and outputs the recognition result with the most occurrences as the optimal recognition result.

5. The identification method of the real-time pulse modulation type identification system based on multi-core DSP as described in claim 4, characterized in that, The FPGA transmits baseband IQ data to the DDR via the SRIO high-speed interface.

6. The identification method of the real-time identification system for intra-pulse modulation type based on multi-core DSP as described in claim 4, characterized in that, The modulation type identification algorithm is the same for all processor cores.

7. The identification method of the real-time pulse modulation type identification system based on multi-core DSP as described in claim 4, characterized in that, The modulation type identification algorithm of the main core includes: Perform a phase difference operation on each baseband IQ data and calculate the corresponding instantaneous frequency f(t); Calculate the standard deviation of the phase first difference for each baseband IQ data. Calculate the phase quadratic difference for each baseband IQ data, and then calculate the standard deviation of the corresponding phase quadratic difference. Using the minimum linear fitting method, linear fitting is performed on each instantaneous frequency f(t) to obtain the linear fitting error σ and the linear modulation slope k; Calculate the mean and extreme values ​​of the first difference for each phase, then calculate the difference between each extreme value and the mean. This difference is the phase value of the transition. Record the phase value of the transition, and then identify the modulation type of each baseband IQ data based on the above data.

8. The identification method of the real-time identification system for intra-pulse modulation type based on multi-core DSP as described in claim 4 or 7, characterized in that, The criteria for each processor core to identify the modulation type include: Standard point frequency signal: Standard deviation of the first phase difference Standard deviation of phase quadratic difference Linear fitting error σ < threshold3; Linear modulation slope k < threshold 4; Linear frequency modulated signal: Standard deviation of the first phase difference Standard deviation of phase quadratic difference Linear fitting error σ < threshold3; Linear modulation slope k > threshold4; Biphasic coded signal: Standard deviation of the first phase difference Linear modulation slope k < threshold 4; The phase jump values ​​are around 0° and 180°; Four-phase coded signal: Standard deviation of the first phase difference Linear modulation slope k < threshold 4; The phase jump values ​​are around 0°, 90°, 180°, and 270°; Among them, threshold1, threshold2, threshold3 and threshold4 are the first threshold, the second threshold, the third threshold and the fourth threshold, respectively.

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