Memory access request processing method, system on chip, storage medium and program product

Abstract

The application discloses a memory access request processing method, a system on chip, a storage medium and a program product. When receiving continuous at least two memory access requests, an enabling signal of a continuous transmission mode is acquired. If the enabling signal is in a triggering state, a bit field of a physical address corresponding to all memory access requests is acquired. A memory controller identifier in the bit field is remapped to a target position. The target position points to the same target memory controller. According to address information of the target position, all memory access requests are routed to the target memory controller. By aggregating continuous memory access requests to the same memory controller for processing, the application reduces switching of the memory controller, improves bandwidth utilization and reduces control overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to a memory access request processing method, a system on chip, a storage medium and a program product. BACKGROUND

[0002] In modern high-performance computing systems, the demand for data throughput grows exponentially. To break through the bandwidth limit of traditional DDR (Double Data Rate) memory, HBM (High Bandwidth Memory) has emerged. It integrates multiple groups of memory dies and controllers to form a high-density and high-parallel memory architecture. The HBMC (High Bandwidth Memory Controller) as the interaction core of HBM and the system directly determines the release degree of HBM bandwidth potential. Therefore, how to efficiently schedule and manage the access of these HBMCs directly affects the overall performance of the system.

[0003] In the prior art, when receiving a memory access request, a high-bandwidth memory system usually adopts a simple linear mapping strategy to remap the SMMU PA (System Memory Management Unit Physical Address) to a PA (Physical Address). In the remapping process, a fixed-grained address mapping is adopted, and the continuous memory access requests are dispersed to different HBMC controllers according to a fixed mode by using a simple polling or hashing algorithm. However, when continuous memory requests are dispersed to different HBMC controllers according to a fixed algorithm (such as polling), the system needs to frequently switch between different HBMCs. Due to the frequent switching of HBMCs, each HBMC cannot fully utilize its bandwidth capacity. When requests are dispersed to multiple HBMCs, each HBMC may be in an idle or low-load state, and cannot form a continuous data stream, resulting in a decrease in overall bandwidth utilization. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a memory access request processing method, a system on chip, a storage medium and a program product, which aggregate continuous memory access requests to the same memory controller for processing, thereby reducing the switching of memory controllers, improving bandwidth utilization and reducing control overhead.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application provide a memory access request processing method, comprising:

[0006] receiving the enable signal of the contiguous transmission mode when receiving the continuous at least two memory access requests;

[0007] if the enable signal is in the trigger state, obtaining a bit field of a physical address corresponding to all memory access requests;

[0008] remapping the memory controller identifier in the bit field to a target location; wherein the target location points to the same target memory controller;

[0009] routing all memory access requests to the target memory controller according to address information of the target location.

[0010] As an improvement of the above scheme, the bit field value of the target location is a fixed preset value.

[0011] As an improvement of the above scheme, the bit field includes a large range address offset field, a memory controller identifier, a partition identifier, a cache identifier, a partial offset field and a byte-level offset field; wherein the target location is a bit field where the partition identifier is located.

[0012] As an improvement of the above scheme, after obtaining the bit field of the physical address corresponding to all memory access requests, the method further comprises:

[0013] keeping the bit fields of the large range address offset field and the byte-level offset field unchanged;

[0014] superimposing the partial offset field on the large range address offset field;

[0015] remapping the partition identifier to the bit field of the cache identifier, and remapping the cache identifier to the bit field of the partial offset field.

[0016] As an improvement of the above scheme, the routing of all memory access requests to the target memory controller comprises:

[0017] finding a corresponding target cache according to the cache identifier, and using the target cache to route all memory access requests to the target memory controller; wherein each target cache is associated with at least one memory controller.

[0018] As an improvement of the above scheme, the finding of a corresponding target cache according to the cache identifier comprises:

[0019] when the number of continuous memory access requests does not exceed a preset request processing threshold, finding an initial target cache corresponding to the cache identifier;

[0020] When the number of continuous memory access requests exceeds the request processing threshold, the bit field value of the cache identifier is incremented, and another target cache corresponding to the incremented cache identifier is searched.

[0021] As an improvement of the above scheme, the method further comprises:

[0022] When it is detected that the bandwidth utilization of a memory channel is lower than a preset utilization threshold, an enable signal of the continuous transmission mode is triggered, wherein the memory channel is used to connect the memory controller and a memory chip.

[0023] To achieve the above object, the embodiment of the present application further provides a system on chip, comprising a physical address generation module and a routing port, the physical address generation module is connected with the routing port, wherein,

[0024] The physical address generation module is configured to:

[0025] When at least two continuous memory access requests are received, an enable signal of the continuous transmission mode is acquired;

[0026] If the enable signal is in a triggered state, a bit field of a physical address corresponding to all memory access requests is acquired, and a memory controller identifier in the bit field is remapped to a target position, wherein the target position points to a same target memory controller.

[0027] The routing port is configured to:

[0028] According to address information of the target position, all memory access requests are routed to the target memory controller.

[0029] To achieve the above object, the embodiment of the present application further provides a computer readable storage medium, the computer readable storage medium comprises a stored computer program, wherein when the computer program runs, the device where the computer readable storage medium is located executes the access request processing method as any one of the above embodiments.

[0030] To achieve the above object, the embodiment of the present application further provides a computer program product, comprising computer instructions, when the computer instructions are executed by a processor, the access request processing method as any one of the above embodiments is realized.

[0031] Compared with the prior art, the memory access request processing method, the system on chip, the storage medium and the program product disclosed by the application, by detecting continuous memory access requests and triggering a continuous transmission mode, combining the accurate remapping design of the physical address bit field, uniformly pointing the memory controller identifier to the same target memory controller, realizing the centralized routing of all continuous requests to the target memory controller, reducing the switching of the memory controller, effectively avoiding the access fragmentation problem caused by the dispersion of continuous requests to different memory controllers in the traditional mode, this centralized routing mode can reduce the scheduling delay between different controllers, reduce the frequency and delay loss of the Row switching of the memory controller, reduce the control overhead, at the same time, fully utilize the memory channel bandwidth resources corresponding to the target memory controller, avoid the idle of the channel bandwidth, improve the bandwidth utilization of the memory channel. In addition, the application does not need to increase the hardware complexity, but only through the logical optimization of the address bit field remapping can realize the performance improvement, and the implementation cost and adaptability are considered, which provides efficient and stable memory support for continuous large data block access. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a structural block diagram of the system on chip provided by the embodiment of the application;

[0033] Figure 2 is a flow chart of a memory access request processing method provided by the embodiment of the application;

[0034] Figure 3 is a schematic diagram of remapping the physical address corresponding to the memory access request provided by the embodiment of the application;

[0035] Figure 4 is a hierarchical relationship diagram of the memory controller and the memory chip provided by the embodiment of the application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0037] Reference Figure 1 , Figure 1is a structural block diagram of a system on chip provided by an embodiment of the present application, and the memory access request processing method described in the embodiment of the present application is implemented by the system on chip, for example, the system on chip can be a SoC (System on Chip, system-level chip), the SoC is a hardware system integrating a processor, a memory subsystem, a bus interconnection and other functional modules on a single chip, and can realize complete functions such as data processing, address management and device interconnection, and the SoC integrates two core hardware modules of a PAGEN (Physical Address Generation Module, physical address generation module) and an XBAR (Crossbar, crossbar) routing port, and the two modules cooperatively complete optimized scheduling of continuous memory access requests.

[0038] When the system on chip receives continuous at least two memory access requests, first, an enabling signal of a burst transmission mode (Burst4 mode) is detected by the PAGEN module, and it is judged whether an address remapping process is triggered. If the enabling signal is in a triggering state, the PAGEN module performs an address field remapping operation on an input SMMUPA, adjusts a bit field of the SMMUPA according to a preset rule, and generates an optimized NoCPA (On-Chip New Optimized Physical Address, on-chip new optimized physical address). Subsequently, the XBAR, as an in-chip bus switching module, based on a fixed memory controller identifier in the NoCPA, uniformly routes all continuous memory access requests to a same target HBMC through a preset fixed port routing rule, and finally the HBMC processes the concentrated continuous requests, and realizes efficient utilization of a memory channel bandwidth.

[0039] Referring to Figure 2 , Figure 2 is a flowchart of a memory access request processing method provided by an embodiment of the present application, and the memory access request processing method comprises steps S1-S4.

[0040] S1, when continuous at least two memory access requests are received, an enabling signal of a burst transmission mode is acquired.

[0041] Exemplarily, the memory access request refers to an instruction request initiated by a computing unit to a memory subsystem for reading or writing data, usually containing the virtual address of the target data, the access type (read / write), the data length, and the like, and is actively issued by various computing cores when performing data-intensive tasks. For example, the computing unit includes at least one of a CPU (Central Processing Unit), an AI (Artificial Intelligence) accelerator, a GPU (Graphics Processing Unit), and the like, and the data-intensive task can be a tensor operation, a graphics rendering, a large file read / write, and the like.

[0042] Exemplarily, the continuous memory access request refers to at least two requests in which the corresponding target data is continuously distributed in the physical address space, such as sequentially increasing addresses, cumulative data length not less than 256B (or other values such as 512B), and the like. The continuous transmission mode refers to the Burst4 mode, the core of which is to aggregate continuous small data block requests into a large data block request for centralized transmission, such as regarding four continuous 512B memory access requests as a whole. When the enable signal of the Burst4 mode is in the triggered state, it indicates that the address bit field remapping and centralized routing of the subsequent continuous requests to the same memory controller are performed; when the enable signal of the Burst4 mode is in the untriggered state, it indicates that the requests are dispersed to different memory controllers in the traditional way, and the independent small data block dispersion transmission mode is adopted.

[0043] Further, the method further comprises: when it is detected that the bandwidth utilization rate of the memory channel is lower than a preset utilization rate threshold, triggering the enable signal of the continuous transmission mode; wherein the memory channel is used to connect the memory controller and the memory chip.

[0044] Exemplarily, the memory channel Memory Channel refers to a physical transmission link and a logical communication channel connecting the memory controller HBMC and the memory chip HBM, which is composed of data lines, address lines, control lines, and supporting transmission protocols, and is used to realize high-speed data read-write interaction between the memory controller and the memory chip, and is the core carrier of the bandwidth of the memory subsystem. The performance advantage of the memory channel depends on the centralized transmission of continuous large data blocks. When the bandwidth utilization rate is lower than the threshold (such as 30%~50%), it indicates that the channel is in an idle state, which is usually caused by fragmented access of scattered requests and dispersion of different controllers, resulting in too large transmission gap of the channel. At this time, the continuous transmission mode is triggered, and the continuous requests can be aggregated and routed to the channel, so as to fully fill the transmission gap and avoid the waste of channel bandwidth.

[0045] In the embodiment of the present application, by detecting the bandwidth utilization of the memory channel and dynamically triggering the continuous transmission mode, the trigger mechanism realizes the on-demand optimization scheduling of the memory channel resources, initiatively initiates the continuous transmission for the channel with insufficient bandwidth utilization, aggregates the originally scattered requests into continuous large data block transmission, maximizes the potential of the rated bandwidth of the memory channel, greatly improves the actual utilization rate of the channel, and avoids the idle of hardware resources.

[0046] S2, if the enable signal is in a trigger state, acquiring a bit field of a physical address corresponding to all memory access requests.

[0047] For example, the bit field indicates the complete positioning information of the physical address corresponding to the memory access request in the memory subsystem, and the physical address is SMMUPA. The bit field includes a large range address offset field, a memory controller identifier, a partition identifier, a cache identifier, a partial offset field and a byte-level offset field; wherein the target position is the bit field where the partition identifier is located. The SMMUPA address field Format and field meaning are shown in Table 1.

[0048] Table 1 SMMUPA address field Format and field meaning

[0049]

[0050] S3, remapping the memory controller identifier in the bit field to a target position; wherein the target position points to the same target memory controller.

[0051] For example, the bit field value of the target position is a fixed preset value, such as binary 00, corresponding to the target memory controller HBMC0. The core target of the present application is to aggregate and centrally route the continuous memory access requests to the same memory controller, and by fixing the bit field value of the target position, all remapped continuous requests can carry a unified memory controller identifier, ensuring that the routing port can accurately identify and forward to the same target memory controller, avoiding the fragmentation access problem caused by the dispersion of requests to different controllers in the traditional mode;

[0052] Further, after step S2 is executed, the method further comprises: keeping the bit fields of the large range address offset field and the byte-level offset field unchanged; superimposing the partial offset field to the large range address offset field; remapping the partition identifier to the bit field of the cache identifier, and remapping the cache identifier to the bit field of the partial offset field.

[0053] Exemplarily, the step S2 and the above process are the process of remapping the SMMUPA, by remapping the SMMUPA address field to the NoCPA address field, and adjusting the bit field of part of the fields in the remapping process, so that the memory controller identifier is uniformly replaced by a fixed preset value and written into the original partition identifier bit field, ensuring that all continuous requests point to the same target memory controller, and realizing centralized routing.

[0054] Referring to Figure 3 , Figure 3 is a schematic diagram provided by the embodiment of the present application for remapping the physical address corresponding to the memory access request, the address field of the SMMUPA before remapping can refer to Table 1, and the address field Format of the NoCPA and the field meaning after remapping are shown in Table 2.

[0055] Table 2 Format and field meaning of NoCPA address field

[0056]

[0057] Exemplarily, by comparing Table 1 and Table 2, it can be seen that the remapping process of SMMUPA to NoCPA is realized by bit field range adjustment, field function reuse and identifier unification, and the remapping logic combined with Table 1 and Table 2 can be decomposed into the following steps:

[0058] 1. Extension of the large-range address offset field, realizing superposition of part of the offset field;

[0059] In SMMUPA: the large-range address offset field is bit[38:17], and part of the offset field is bit[10:9];

[0060] Remapping process: superposition of part of the offset field of SMMUPA to the large-range address offset field, the bit field range of the large-range address offset field in NoCPA is extended to bit[38:15], which not only retains the complete positioning information of the macro address and part of the offset in SMMUPA, but also optimizes the address structure of NoCPA through bit field merging, ensuring that it can cover a more accurate macro memory storage range;

[0061] It should be noted that the superposition here is not decimal addition, but bit field shift splicing, because the bit field of the large-range address offset field is higher, and Bit[10:9] is low, so the value of Bit[10:9] needs to be shifted to the low bit of the large-range address offset, and then spliced with the original large-range address offset.

[0062] 2. Unified remapping of the memory controller identifier;

[0063] In the SMMUPA, the memory controller identifier MC_ID is bit[16:15], which can correspond to multiple different HBMCs, such as 00->HBMC0 and 01->HBMC1.

[0064] The remapping process: the MC_ID of the SMMUPA is uniformly replaced by a fixed preset value (such as binary 00) and written into the bit field range bit[14:13] of the original partition identifier Partition_ID, the bit field range of the MC_ID in the NoCPA is adjusted to bit[14:13] and the value is fixed as 00, so as to ensure that all continuous request NoCPAs carry a uniform target HBMC identifier and only point to HBMC0, thereby realizing centralized routing.

[0065] 3. Conversion between the bit field of the partition identifier and the cache identifier;

[0066] In the SMMUPA, the partition identifier Partition_ID is bit[14:13] and the cache identifier L2ID is bit[12:11].

[0067] The remapping process: the Partition_ID of the SMMUPA is remapped to the bit field range of the original cache identifier L2ID, and the bit field of the Partition_ID in the NoCPA is bit[12:11], and at the same time, the L2ID of the SMMUPA is remapped to the bit field range of the original partial offset field Offset, and the bit field of the L2ID in the NoCPA is bit[10:9].

[0068] 4. Preservation of the byte-level offset field;

[0069] In the SMMUPA and the NoCPA, the bit field range of the byte-level offset field (Byte_offset) is bit[8:0], which remains unchanged in the remapping process, and this design ensures that the NoCPA can still accurately locate the byte-level storage position in the data block, avoiding data reading and writing misalignment caused by remapping.

[0070] As can be seen, the remapping process in the embodiment of the present application realizes bit field extension, identifier unification and field conversion, and on the basis of preserving the complete address positioning information of the SMMUPA, optimizes the NoCPA into an on-chip physical address that is suitable for continuous request centralized routing and on-chip cache dynamic scheduling, thereby realizing the goal of centralized access to the same HBMC and guaranteeing the accuracy and hardware compatibility of the address.

[0071] To better explain the reason why the same HBMC is accessed after remapping, the mapping mode of the prior art traditional mode and the mapping mode of the Burst4 mode of the present application are compared in the embodiment of the present application. The memory access requests in the two modes are of a granularity of 512B, and the PAGEN module receives four continuous memory access requests.

[0072] 1) Remapping logic of the traditional mode:

[0073] Request 1: SMMUPA: 0x100000000→NOC_PA: 0x100000000(bit[14:13]=00)→MC_ID=0→HBMC0;

[0074] Request 2: SMMUPA: 0x100000200→NOC_PA: 0x100000200(bit[14:13]=01)→MC_ID=1→HBMC1;

[0075] Request 3: SMMUPA: 0x100000400→NOC_PA: 0x100000400(bit[14:13]=10)→MC_ID=2→HBMC2;

[0076] Request 4: SMMUPA: 0x100000600→NOC_PA: 0x100000600(bit[14:13]=11)→MC_ID=3→HBMC3.

[0077] For example, in the traditional mode, in the address field of the SMMUPA, the bit field range of the memory controller identifier MC_ID is bit[16:15], and the MC_ID is automatically generated by the high bit of the physical address. The corresponding routing process includes:

[0078] The SMMUPA of the first request is 0x10000000, the value of bit[16:15] is 00, the remapped NoCPA is 0x100000000, at this time bit[14:13]=00, corresponding to MC_ID=0, routed to HBMC0;

[0079] The SMMUPA of the second request is 0x10000200 (increased by 512B, i.e. 0x200, than the first request), the value of bit[16:15] is 01 by carry, the remapped NoCPA is 0x100000200, at this time bit[14:13]=01, corresponding to MC_ID=1, routed to HBMC1;

[0080] The SMMUPA of the 3rd request is 0x10000400, the value of bit[16:15] is 10, the NoCPA after remapping is 0x100000400, at this time bit[14:13]=10, corresponding to MC_ID=2, routed to HBMC2;

[0081] The SMMUPA of the 4th request is 0x10000600, the value of bit[16:15] is 11, the NoCPA after remapping is 0x100000600, at this time bit[14:13]=11, corresponding to MC_ID=3, routed to HBMC3.

[0082] Therefore, in the traditional mode, the bit field of MC_ID is strongly associated with the 512B granularity offset of the physical address, and every increase of 512B (i.e. 0x200) will automatically carry bit[16:15] of the address, such as 00→01→10→11, causing MC_ID to change with the increase of the address of the continuous request, and since the address field content is directly moved in the remapping process, the final request is dispersed to four different HBMCs.

[0083] 2) Remapping logic of the mode of the application:

[0084] Request 1: SMMUPA: 0x100000000→NOC_PA: 0x100000000 (bit[14:13]=00)→MC_ID=0→HBMC0;

[0085] Request 2: SMMUPA: 0x100000200→NOC_PA: 0x100008000 (bit[14:13]=00)→MC_ID=0→HBMC0;

[0086] Request 3: SMMUPA: 0x100000400→NOC_PA: 0x100010000 (bit[14:13]=00)→MC_ID=0→HBMC0;

[0087] Request 4: SMMUPA: 0x100000600→NOC_PA: 0x100018000 (bit[14:13]=00)→MC_ID=0→HBMC0.

[0088] For example, the SMMUPA is remapped by the PAGEN module, the core adjusts the bit field range and generation rule of MC_ID, remaps the MC_ID bit field of bit[16:15] in the original SMMUPA to the bit field of the original partition identifier bit[14:13], and forcibly fixes the value of bit[14:13] as 00, and the corresponding routing process includes:

[0089] The SMMUPA of the first request is 0x10000000, the NoCPA after remapping is 0x100000000, at this time bit[14:13]=00, corresponding to MC_ID=0, routed to HBMC0;

[0090] The SMMUPA of the second request is 0x10000200, the NoCPA after remapping is 0x100008000, at this time bit[14:13] is still fixed as 00, corresponding to MC_ID=0, routed to HBMC0; It should be noted that since the partial offset field of SMMUPA=0x10000200 is Bit[10:9]=01, PAGEN will superimpose this field on the large range address offset field, and the large range address offset of NoCPA will increase the corresponding value, finally NoCPA=0x100008000, in addition, in the traditional mode, the value of Bit[10:9] will trigger the MC_ID bit field Bit[16:15] carry, Bit[10:9]=01 of the second request will cause Bit[16:15] from 00 to 01, MC_ID=1→routed to HBMC1; and in the present application, the value of Bit[10:9] is transferred to the large range address offset, and no longer affects MC_ID, the MC_ID bit field has been migrated to Bit [14:13] and fixed as 00; therefore, the remapping process of the second request is different from the traditional mode, the third and fourth requests are the same;

[0091] The SMMUPA of the third request is 0x10000400, the NoCPA after remapping is 0x100010000, at this time bit[14:13] is fixed as 00, corresponding to MC_ID=0, routed to HBMC0;

[0092] The SMMUPA of the fourth request is 0x10000600, the NoCPA after remapping is 0x100018000, at this time bit[14:13] is fixed as 00, corresponding to MC_ID=0, routed to HBMC0.

[0093] The present application migrates the bit field of MC_ID from bit[16:15] which is strongly associated with 512B granularity to bit[14:13] which is not associated with address increment, and forces the value of bit[14:13] to be fixed as 00, which cuts off the association between MC_ID and address offset, even if the address increments of consecutive requests, MC_ID will not change with the address carry, finally the MC_ID of all requests remains uniform, all routed to the same HBMC0, forming a continuous 2KB data block access.

[0094] It should be noted that the above-mentioned remapping logic of the application mode is described by taking four memory access requests as an example. In actual application, two, three, five or more than five memory access requests can be received, and the remapping mode can refer to the remapping mode of the above-mentioned four memory access requests. No matter how many continuous requests are (as long as more than two), the PAGEN module will keep the remapping logic of migrating the MC_ID bit field to bit[14:13] and fixing it as 00. Even if the number of requests increases to 8, as long as it is in the continuous transmission mode Burst4, the corresponding NoCPA bit[14:13] is always forced to be 00, and the MC_ID is always kept as 0. Finally, all continuous requests will be routed to the HBMC0. For example, when the number of continuous requests is 5, the SMMUPA of request 5 is 0x100000800, the partial offset field Bit[10:9] will continue to increase, but the PAGEN module will still add this field to the large range address offset field during remapping, and keep bit[14:13] as 00. Finally, the large range address offset field of NoCPA is increased accordingly, and the MC_ID is always 0. Request 5 is also routed to the HBMC0.

[0095] In addition, the SMMUPA address of each request in the above-mentioned application mode increases by 512B granularity. This granularity value is not a fixed limit. The remapping logic of the application can flexibly adapt to any continuous granularity, such as 256B, 1KB, 2KB, etc. Only by adjusting the address remapping rule of the PAGEN module can it be realized, that is, by migrating the MC_ID bit field from the address bit strongly associated with the current incremental granularity to the redundant bit field bit[14:13] irrelevant to address increment, the MC_ID bit field after forced migration is a fixed value 00, which ensures that the MC_ID does not change regardless of how the address is incremented.

[0096] Therefore, the remapping logic of the application does not depend on the specific number of requests. As long as the continuous transmission mode is triggered, at least two continuous requests can be concentratedly routed to the same HBMC by fixing the MC_ID bit field, which flexibly adapts to continuous access scenarios of different data amounts, and has strong versatility and expansibility.

[0097] S4, according to the address information of the target position, routing all memory access requests to the target memory controller.

[0098] Exemplarily, the routing port reads the bit field Bit[14:13] corresponding to the target position from the NoCPA address, obtains a unified MC_ID, and the MC_ID and the mapping rule of the HBMC are pre-configured in the chip, for example, when the MC_ID is 0, the hardware port associated with the HBMC0, the routing port forwards all requests carrying the MC_ID from the fixed hardware port to the target HBMC, such as the HBMC0, and after the target HBMC receives all the continuous requests, the target HBMC accesses the HBM-Stack through the dedicated memory channel to complete the centralized reading and writing of data.

[0099] Further, the step S4 specifically comprises: searching the corresponding target cache according to the cache identifier, and routing all memory access requests to the target memory controller by using the target cache; wherein each target cache is associated with at least one memory controller.

[0100] Exemplarily, the cache refers to the on-chip L2 cache, which is an intermediate hardware unit connected between the address remapping module and the memory controller HBMC, and each L2 cache is pre-associated with multiple HBMCs, the routing port reads the cache identifier bit field L2ID from the NoCPA address, and this field is the cache association information reserved in the address remapping process, for example, L2ID=00 corresponds to L20, according to the cache identifier, the routing port forwards the request to the corresponding target L2 cache, and since the target L2 cache is pre-associated with multiple HBMCs and the NoCPA already contains a fixed MC_ID, the L2 cache will directly forward the request to the target HBMC associated with itself based on the MC_ID, such as the HBMC0 associated with L20.

[0101] Exemplarily, referring to Figure 4 , Figure 4 is a schematic diagram of the hierarchical relationship between the memory controller and the memory chip provided by the embodiment of the present application, the PA_Remapping (address remapping) is responsible for remapping the original physical address (SMMUPA) to the optimized NoCPA, which is the starting point of address scheduling, the L2 cache is an on-chip cache unit and is directly connected with multiple HBMCs (HBMC0~HBMC3); each HBMC is connected with the HBM-Stack (memory chip stack) on the right side through an independent memory channel; the HBM-Stack is composed of multiple HBM chips and is a hardware unit for actually storing data, and each HBM chip communicates with the corresponding HBMC through a dedicated memory channel.

[0102] For example, when the PA_Remapping generates a NoCPA, the request is first routed to the corresponding L2 cache, such as L20. Since the MC_ID in the NoCPA is fixed as 00, the L20 forwards the request to the HBMC0 connected thereto, and the HBMC0 accesses the corresponding storage area in the HBM-Stack through a dedicated memory channel. Taking four consecutive requests as an example, the MC_ID in the NoCPA of the first to fourth requests is fixed as 00 by the PA_Remapping. After being forwarded by the L20, all the requests are allocated to the HBMC0, and the HBMC0 continuously accesses the corresponding continuous address area in the HBM-Stack through the same memory channel, forming a high-bandwidth 2KB data stream.

[0103] In the embodiment of the present application, the L2 cache, as an on-chip high-speed storage unit, can temporarily store the data of consecutive requests, reduce the frequency of direct access to the HBM-Stack, and reduce the memory delay. Since the L2 cache is associated with multiple HBMCs and the MC_ID in the NoCPA is fixed, consecutive requests can be concentrated and forwarded through the same L2 cache, avoiding the dispersion of requests among multiple controllers.

[0104] Further, the searching for the corresponding target cache according to the cache identifier includes: when the number of consecutive memory access requests does not exceed a preset request processing threshold, searching for an initial target cache according to the cache identifier; and when the number of consecutive memory access requests exceeds the request processing threshold, the bit field value of the cache identifier is incremented, and another target cache is searched according to the cache identifier after the increment.

[0105] For example, the request processing threshold is a critical value for triggering the increment of the bit field of the cache identifier, and the setting of the request processing threshold needs to meet the following condition: when the number of consecutive requests reaches the threshold, the address offset corresponding to the request accumulates to trigger the increment of the L2ID bit field. When the addresses of consecutive requests increase in granularity, the partial offset field Bit[10:9] corresponding to the requests will increase with the number of requests. When the accumulated amount exceeds the representation range of the bit field, the bit field is naturally incremented. For example, the request processing threshold of the L20 is 8. When the number of consecutive requests does not exceed 8, the bit field value of the cache identifier L2ID remains the initial value, such as Bit[10:9] is always 00, corresponding to the L20 cache, and the request is forwarded to the HBMC0 associated with the L20 by the L20. When the number of consecutive requests exceeds 8, the accumulated amount exceeds the representation range of the bit field, and the bit field of the cache identifier is incremented with the increase of the number of requests, such as Bit[10:9] is incremented from 00 to 01. The cache identifier 01 after the increment corresponds to the HBMC1 connected to the L20, and the request is forwarded to the HBMC1 by the L20. Figure 4In the L21 cache in the L2 cache, the request is automatically routed to the L21, and the L21 is also pre-associated with the corresponding HBMC0~HBMC3, so the request is forwarded by the L21 to the associated HBMC0, and finally, whether using L20 or L21, the continuously accessed request is directed to the same HBMC0 corresponding to the target cache. It should be noted that the memory controllers associated with L20 and L21 are the same, but they are actually different memory controllers, which is to avoid too many memory access requests being directed to the same memory controller.

[0106] In the embodiments of the present application, when the request amount is small, the single L2 cache is used for efficient temporary storage and forwarding; when the request amount exceeds the threshold, the redundant L2 cache is automatically switched to share the pressure, and finally the dual optimization of high-bandwidth centralized access and on-chip cache load balancing is realized, which improves the memory access throughput, and also enhances the running stability and resource utilization efficiency of the on-chip hardware.

[0107] Further, all or part of the flow of the memory access request processing method described in the above embodiments can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. When the processor executes the computer program, the steps of each method embodiment described above can be realized. The computer program includes computer program code, which can be in the form of source code, object code, executable file or some intermediate form, etc. The computer readable medium can include any entity or device, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc. that can carry the computer program code.

[0108] Further, the present application also provides a computer program product, which includes a computer program / instruction, and the computer program / instruction is executed by a processor to realize the memory access request processing method described in any of the above embodiments.

[0109] The above is the preferred embodiment of the present application, and it should be noted that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements are also considered within the protection scope of the present application.

Claims

1. A memory access request processing method, characterized by, The method comprises: receiving at least two continuous memory access requests, and obtaining an enable signal of a continuous transmission mode; if the enable signal is in a trigger state, obtaining a bit field of a physical address corresponding to all memory access requests; remapping a memory controller identifier in the bit field to a target location; wherein the target location points to the same target memory controller; routing all memory access requests to the target memory controller according to address information of the target location.

2. The access request processing method of claim 1, wherein, The bit field value of the target location is a fixed preset value.

3. The access request processing method of claim 1, wherein, The bit field comprises a large range address offset field, a memory controller identifier, a partition identifier, a cache identifier, a partial offset field, and a byte-level offset field; wherein the target location is a bit field where the partition identifier is located.

4. The access request processing method of claim 3, wherein, After obtaining the bit field of the physical address corresponding to all memory access requests, the method further comprises: keeping the bit fields of the large range address offset field and the byte-level offset field unchanged; stacking the partial offset field to the large range address offset field; remapping the partition identifier to a bit field of the cache identifier, and remapping the cache identifier to a bit field of the partial offset field.

5. The access request processing method according to claim 3 or 4, characterized by, The routing all memory access requests to the target memory controller comprises: finding a corresponding target cache according to the cache identifier, and routing all memory access requests to the target memory controller using the target cache; wherein each target cache is associated with at least one memory controller.

6. The access request processing method of claim 5, wherein, The finding a corresponding target cache according to the cache identifier comprises: when the number of continuous memory access requests does not exceed a preset request processing threshold, finding an initial target cache according to the cache identifier; when the number of continuous memory access requests exceeds the request processing threshold, the bit field value of the cache identifier is incremented, and another target cache is found according to the incremented cache identifier.

7. The access request processing method of claim 1, wherein, The method further comprises: when the bandwidth utilization rate of a memory channel is lower than a preset utilization rate threshold, triggering the enable signal of the continuous transmission mode; wherein the memory channel is used to connect the memory controller and a memory chip.

8. A system on chip, characterized by The device comprises a physical address generation module and a routing port, and the physical address generation module is connected to the routing port; wherein the physical address generation module is configured to: receive at least two continuous memory access requests, and obtain an enable signal of a continuous transmission mode; if the enable signal is in a trigger state, obtain a bit field of a physical address corresponding to all memory access requests; and remap a memory controller identifier in the bit field to a target location; wherein the target location points to the same target memory controller; the routing port is configured to: route all memory access requests to the target memory controller according to address information of the target location.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises a stored computer program, wherein when the computer program runs, the computer readable storage medium controls the device where the computer readable storage medium is located to execute the access request processing method in any one of claims 1 to 7.

10. A computer program product, characterised in that, comprising computer instructions that, when executed by a processor, implement the access request processing method of any one of claims 1 to 7.

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