Non-volatile latch with dual-node flip recovery based on mtj, chip

Abstract

The application relates to the field of integrated circuits, in particular to a non-volatile latch based on MTJ double-node flip recovery and a corresponding anti-radiation storage chip. The non-volatile latch comprises an anti-radiation latch circuit, a read-write circuit and a backup recovery circuit. The anti-radiation latch circuit comprises multiple groups of storage nodes which are redundant and reinforced. At least one group of main storage nodes adopts non-polar reinforcement, and the rest are redundant storage nodes. The read-write circuit is used for performing data read-write tasks on the anti-radiation latch circuit. The backup recovery circuit comprises a basic part and a copy part. The basic part completes data backup through two magnetic tunnel junctions and is used for restoring the main storage nodes. The copy part comprises multiple NMOS tubes and is used for restoring the redundant storage nodes. The application improves the anti-SNU or DNU performance of the circuit, optimizes the power consumption and speed of the circuit, and solves the problem of unbalanced performance of the existing circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a dual-node flip-flop self-recovering non-volatile latch based on MTJ and its corresponding radiation-resistant memory chip. Background Technology

[0002] In recent years, advancements in process technology have led to improved circuit integration and performance. However, this has also resulted in smaller transistor sizes and voltages, making CMOS circuits more sensitive to radiation. When radiant particles strike transistors in a switched-off state, it can cause single-node switching (SNU). Furthermore, the sharing mechanisms within the circuit significantly increase the probability of dual-node switching (DNU). Simultaneously, the volatility of traditional CMOS circuits is becoming increasingly severe. Therefore, ensuring the non-volatility of latch circuits and providing radiation protection are pressing issues that need to be addressed in the field of memory devices.

[0003] The existing technologies for SNU or DNU resistant designs of non-volatile latches mainly include the following typical solutions:

[0004] In 2019, Amirany et al. proposed a non-volatile latch structure (simply referred to as the SBRH circuit), the structure of which is as follows: Figure 1 As shown, the SBRH circuit uses two parallel CE cells and two MTJs to design the latch circuit. It has four memory nodes. When subjected to SNU, it can achieve single-node self-recovery by relying on the two CE cells, and the MTJs provide non-volatile functionality. However, this latch uses complementary internal nodes to directly perform write operations to the MTJs, which results in high transmission latency during backup operations and high power consumption during the recovery phase.

[0005] In 2021, ZHANG et al. proposed a non-volatile latch structure (which can be simply referred to as the SEDNUT circuit), the structure of which is as follows: Figure 2 As shown, the SEDNUT circuit uses seven three-input inverters connected in series to increase redundancy. When a SNU (Signal Null Neutral Null) occurs, the error is directly blocked by the three-input inverters, and the erroneous signal is restored to correctness through subsequent memory nodes. When a DNU (Discretionary Null Neutral Null) occurs, the multi-stage series of three-input inverters ensures that the error in the affected memory node does not affect other nodes. Finally, the C-cell isolation prevents the output Q from erroneously flipping. Therefore, this circuit can effectively suppress SNU and DNU, achieving dual-node tolerance. However, this circuit uses a large number of three-input inverters, resulting in a large number of transistors and significant overhead in terms of power consumption and area.

[0006] In 2024, YAN et al. proposed a non-volatile latch structure (which can be simply referred to as the TPDICE circuit), the structure of which is as follows: Figure 3As shown, the TPDICE circuit uses a modified traditional DICE structure with added redundant nodes to design the latch circuit. When a SNU occurs in one of the internal nodes, its erroneous signal will not cause other internal nodes to flip incorrectly, and the erroneous signal can be recovered through the feedback loop. However, when a DNU occurs in the circuit, the feedback loop is insufficient to recover the erroneous signal. But because the output node is a three-input C unit, it can isolate errors, so that the output node Q will not flip incorrectly, thus achieving dual-node flip tolerance of the latch circuit. However, due to its excessive number of redundant nodes and redundant transistors, the power consumption is relatively high, and it can only achieve dual-node tolerance, resulting in poor overall radiation resistance performance.

[0007] In 2024, YAN et al. proposed a non-volatile latch structure (which can be simply referred to as the M-8C circuit), the structure of which is as follows: Figure 4 As shown, the M-8C circuit employs four transmission gates, eight C-cells, and a pair of MTJs. Through the feedback loop coupling of the eight C-cells, it effectively resists DNU (Distributed Noise Nullification), achieves dual-node self-recovery, and exhibits good radiation resistance. The two MTJs, in conjunction with precharge transistors and a readback circuit, implement the non-volatile backup and recovery function. However, due to the excessive use of redundant transistors, the area overhead increases, and the eight internal nodes require eight precharge transistors, leading to increased precharge power consumption and read latency. Summary of the Invention

[0008] To improve the balance between radiation resistance, power consumption, and speed of existing non-volatile latches, this invention provides a dual-node flip-flop self-recovering non-volatile latch based on MTJ and its corresponding radiation-resistant memory chip.

[0009] The technical solution provided by this invention is as follows:

[0010] A dual-node flip-flop self-recovering non-volatile latch based on MTJ includes: a radiation-hardened latch circuit, a read / write circuit, and a backup recovery circuit. The radiation-hardened latch circuit comprises multiple sets of redundant and hardened storage nodes; at least one set of primary storage nodes X1 and X2 is hardened using non-polarity, and the remaining sets are redundant storage nodes. The read / write circuit is electrically connected to each storage node in the radiation-hardened latch circuit and is used to perform data read / write tasks on the radiation-hardened latch circuit.

[0011] The backup and recovery circuit consists of a basic section and a replication section. The basic section comprises four PMOS transistors (P13-P16), three NMOS transistors (N19-N21), two transmission gates (G2 and G3), and two magnetic tunnel junctions (MTJ1 and MTJ2). The sources of P13-P16 are connected to VDD; the drains of P13, P15, and N19, and the gates of P16 and N20 are connected to X1. The drains of P14, P16, and N20, and the gates of P15 and N19 are connected to X2. The gates of P13 and P14 are connected to the precharge signal PRE; the source of N19 is connected to the output of G2 and the free layer of MTJ1; the source of N20 is connected to the output of G3 and the free layer of MTJ2. The input terminal of G2 is connected to the data write signal D, the input terminal of G3 is connected to the inverted write signal DN, and the control terminals of G2 and G3 are connected to the write control signal WR. The fixed layers of MTJ1 and MTJ2 are connected to the drain of N21. The gate of N21 is connected to the reset signal RES, and the source is grounded.

[0012] The replication section includes multiple NMOS transistors corresponding to the number of redundant memory nodes. Half of the NMOS transistors have their sources connected to X1 and their drains connected to one of the redundant memory nodes in each group. The other half of the NMOS transistors have their sources connected to X2 and their drains connected to the other node in each redundant memory node group. The gate of each NMOS transistor in the replication section is connected to the memory recall enable signal TEN.

[0013] As a further improvement of the present invention, the read / write circuit includes a clock-controlled inverting section, a transmission section, and inverters INV1 and INV2. INV1 is used to generate an inverted write signal DN based on the data write signal D; INV2 is used to generate an inverted clock signal NCK based on the clock signal CLK. The clock-controlled inverting section consists of two PMOS transistors P9-P10, two NMOS transistors N13-N14, and a transmission gate G1; and is used to connect X2 to the output port of the data read signal Q when CLK=0.

[0014] The transmission section consists of two PMOS transistors, P11 and P12, and multiple NMOS transistors corresponding to the number of redundant memory nodes. The drain of P11 is connected to X1, and the source of P11 is connected to D; the drain of P12 is connected to X2, and the source of P11 is connected to DN; the gates of P11 and P12 are connected to NCK. The gate of each NMOS transistor is connected to CLK; half of the NMOS transistors have their sources connected to D, and their drains connected to one of the redundant memory nodes in each group; the other half of the NMOS transistors have their sources connected to DN, and their drains connected to the other node in each redundant memory node group.

[0015] As a further improvement of the present invention, in the radiation-hardened latch circuit, the main memory node adopts a C-cell or source isolation hardened circuit structure; each redundant memory node adopts any one of C-cell, source isolation hardening, or polarity hardening.

[0016] As a further improvement of the present invention, the radiation-hardened latch circuit is composed of 8 PMOS transistors P1~P8 and 12 NMOS transistors N1~N12; the radiation-hardened latch circuit includes a set of source-isolated hardened main memory nodes X1 and X2, and two sets of N-polarity hardened redundant memory nodes X3, X4 and X5, X6.

[0017] The circuit connections of the radiation-hardened latch circuit are as follows: the sources of P1~P6 are connected to VDD; the sources of N7~N12 are connected to GND; the drain of P1 is connected to the drain of N1; the drain of P2 is connected to the drain of N2; the drain of P3 is connected to the source of P7; the drain of P4 is connected to the source of P8; the drain of P5 is connected to the drain of N3; the drain of P6 is connected to the drain of N4; the drain of P7 and the source of N5 are connected to the gates of N3 and N10 and serve as storage node X1; the drain of P8 and the source of N6 are connected to the gates of N4 and N9 and serve as storage node X2; N7 The drain of N1 and the source of N1 are connected to the gates of P2, P4, and N8 and form storage node X3; the drain of N8 and the source of N2 are connected to the gates of P1, P3, and N7 and form storage node X4; the drain of N11 and the source of N3 are connected to the gates of P6, P8, N1, and N12 and form storage node X5; the drain of N12 and the source of N4 are connected to the gates of P5, P7, N2, and N11 and form storage node X6; the source of N5 is connected to the drain of N9; the source of N6 is connected to the drain of N10; the gates of N5 and N6 are connected to the memory signal EQ.

[0018] As a further improvement of the present invention, N1, N2, N3, and N4 are low-threshold devices, while the remaining MOS transistors are standard-threshold devices.

[0019] As a further improvement to this invention, the read / write circuit consists of four PMOS transistors P9~P12, six NMOS transistors N13~N18, two inverters INV1 and INV2, and a transmission gate G1. The circuit connection is as follows:

[0020] The source of P9 is connected to the power supply VDD. The gates of P9 and N14, and the drain of P12 are connected to memory node X2. The drain of P9 is connected to the source of P10. The drains of P10 and N13 are connected to the output of G1 and to the data read signal Q. The source of N13 is connected to the drain of N14; the source of N14 is grounded. The inputs of G1 and INV1, the source of P11, and the sources of N15 and N16 are connected to D. The source of P12 and the sources of N17 and N18 are connected to the inverted write signal DN of the INV1 output. The gates of P10, N15~N18, the input of INV2, and the control terminal of G1 are connected to the clock signal CLK. The gates of N13, P11, and P12 are connected to the inverted clock signal NCK of the INV2 output. The drain of P11 is connected to X1; the drain of P12 is connected to X2; the drain of N15 is connected to X3; the drain of N16 is connected to X5; the drain of N17 is connected to X4; and the drain of N18 is connected to X6.

[0021] As a further improvement of the present invention, when CLK=1 and NCK=0, the circuit is in transparent and backup mode;

[0022] At this point, D is directly output to Q via G1; D is written to X1, X3, and X5 via P11, N15, and N16 respectively; DN is written to X2, X4, and X6 via P12, N17, and N18 respectively; thus completing the data latching.

[0023] When CLK=0 and NCK=1, the circuit is in hold mode; at this time, P10 and N13 are turned on, so that X2 is output to Q and the level of Q remains unchanged.

[0024] As a further improvement to this invention, the logic for data backup based on the MTJ-based dual-node flip-over self-recovering non-volatile latch is as follows:

[0025] When WR=1, PRE=0, RES=0, TEN=0, and EQ=0 are set, data backup is initiated. At this time, there is a voltage difference between D and DN, forming a current path through G2, MTJ1, MTJ2, and G3. This causes the resistance state of MTJ1 and MTJ2 to change with the data of D and DN, thereby achieving data backup.

[0026] When VDD=0, the stored data in each storage node of the radiation-resistant latch circuit, characterized by its level state, is lost. However, the magnetic tunnel junctions MTJ1 and MTJ2 in the backup and recovery circuit store data through their resistance state and back up the corresponding data after power failure.

[0027] As a further improvement of this invention, the logic for data recovery using a dual-node flip-over self-recovering non-volatile latch based on MTJ is as follows:

[0028] First, set VDD=1, WR=0, PRE=1, RES=0, TEN=1, and EQ=0 to perform the precharge operation. At this time, P13, P14, N21, N22, N23, and N24 are turned on, and each memory node is precharged to a high level.

[0029] Then set WR=0, PRE=0, RES=1, TEN=1, EQ=1. At this point, the storage node begins to restore the storage voltage before the power loss.

[0030] (1) If D backs up data 1 into MTJ1 and DN backs up data 0 into MTJ2, MTJ1 is in AP state and MTJ2 is in P state. The resistance of MTJ1 is greater than that of MTJ2. Since N19, N20, N25, N21, N22, N23, and N24 are turned on, the path from X1, X3, and X5 to ground passes through the high-resistance MTJ1; the path from X2, X4, and X6 to ground passes through the low-resistance MTJ2. Therefore, X2, X4, and X6 discharge faster than X1, X3, and X5, causing N19 to turn off first and P15 to turn on. Therefore, the voltages of X1, X2, and X4 will stop discharging and return to high level, while X2, X4, and X6 will discharge to low level, and the backup recovery is completed.

[0031] (2) Conversely, if D backs up data 0 into MTJ1 and DN backs up data 1 into MTJ2, at this time, MTJ1 is in the P state and MTJ2 is in the AP state. The resistance of MTJ1 is less than the resistance of MTJ2. Similarly, X1, X2, and X4 can be discharged to a low level. The voltages of X2, X4, and X6 will stop discharging and return to a high level, and the backup recovery is completed.

[0032] The present invention also includes a radiation-resistant memory chip, which uses the aforementioned MTJ-based dual-node flip-flop self-recovering non-volatile latch as the memory cell.

[0033] The present invention has the following beneficial effects:

[0034] The dual-node flip-flop self-recovering non-volatile latch based on MTJ provided by this invention achieves excellent radiation resistance by comprehensively utilizing N-polarity hardening, source isolation, and C-cell structure in the latch circuit, reducing the number of sensitive nodes in the circuit. The backup and recovery circuit designed for the latch circuit can achieve level replication of the recovery signal using only a single NMOS transistor. This, combined with the read / write circuit, enables the circuit to simultaneously possess full SNU and DNU self-recovery capabilities, as well as data backup and recovery functions after power failure, significantly enhancing the circuit's non-volatile capability.

[0035] The circuit design provided by this invention can achieve the most comprehensive circuit performance with fewer transistors and can effectively reduce the circuit area; moreover, the overall circuit has improved performance in terms of power consumption, delay-power product, and comprehensive radiation resistance compared with existing circuits. Attached Figure Description

[0036] Figure 1 The circuit diagram is for the SBRH circuit described in the background section.

[0037] Figure 2 This is a circuit diagram of the SEDNUT circuit described in the background section.

[0038] Figure 3 This is a circuit diagram of the TPDICE circuit described in the background section.

[0039] Figure 4 The circuit diagram is for the M-8C circuit described in the background section.

[0040] Figure 5 This is a circuit diagram of a dual-node flip-and-recovery non-volatile latch based on MTJ provided in Embodiment 1 of the present invention.

[0041] Figure 6 for Figure 5 Detailed circuit diagram of the read / write circuit in the circuit.

[0042] Figure 7 The circuit diagram shows the optimal circuit scheme that includes two sets of N-polarity hardened and one set of source isolation hardened memory nodes.

[0043] Figure 8 For testing experiments Figure 7 The signal flow diagram of the circuit shown is at the power-off recovery node.

[0044] Figure 9 For testing experiments Figure 7 The circuit shown is illustrated with signal recovery timing diagrams for four SNU states.

[0045] Figure 10 For testing experiments Figure 7 The circuit shown is illustrated with signal recovery timing diagrams for six DNU states. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] Example 1

[0049] This embodiment provides a dual-node flip-flop self-recovering non-volatile latch based on MTJ, such as... Figure 5 As shown, the non-volatile latch includes a radiation-hardened latch circuit, a read / write circuit, and a backup / recovery circuit. The radiation-hardened latch circuit includes multiple sets of redundant and hardened storage nodes; each set of storage nodes includes at least one set of primary storage nodes X1 and X2 that are non-polarity hardened; the remaining sets of storage nodes constitute redundant storage nodes. In the radiation-hardened latch circuit of this embodiment, the primary storage node can adopt a C-cell or source isolation hardened circuit structure; while each redundant storage node can adopt any one of C-cell, source isolation hardening, or polarity hardening.

[0050] The read / write circuit is electrically connected to each storage node in the radiation-hardened latch circuit. In this embodiment, the read / write circuit can adjust the overall operating mode of the circuit according to the clock signal CLK and is used to perform data read / write tasks in the radiation-hardened latch circuit.

[0051] The backup and recovery circuit consists of a basic section and a replication section. The basic section uses two magnetic tunnel junctions to back up and restore the stored data of the primary storage nodes X1 and X2, while the replication section uses only a single NMOS transistor to control the voltage levels of the primary storage nodes X1 and X2, and to synchronously execute the data backup and recovery operations of the primary storage nodes to the remaining redundant storage nodes.

[0052] Specifically, in the backup and recovery circuit of this embodiment, the basic part consists of four PMOS transistors P13~P16, three NMOS transistors N19~N21, two transmission gates G2 and G3, and two magnetic tunnel junctions MTJ1 and MTJ2. The circuit connection relationship is as follows:

[0053] The sources of P13~P16 are connected to VDD; the drains of P13, P15, and N19, and the gates of P16 and N20 are connected to X1. The drains of P14, P16, and N20, and the gates of P15 and N19 are connected to X2. The gates of P13 and P14 are connected to the precharge signal PRE; the source of N19 is connected to the output of G2 and the free layer of MTJ1; the source of N20 is connected to the output of G3 and the free layer of MTJ2. The input of G2 is connected to the data write signal D, the input of G3 is connected to the inverted write signal DN, and the control terminals of G2 and G3 are connected to the write control signal WR; the fixed layers of MTJ1 and MTJ2 are connected to the drain of N21; the gate of N21 is connected to the reset signal RES, and its source is grounded.

[0054] In the backup and recovery circuit of this embodiment, PMOS transistors P13-P14 are turned on when PRE=0 and are used to pull up storage nodes X1 and X2 in conjunction with the power supply VDD. NMOS transistors N19-N20 are used to form discharge paths between X1 and MTJ1, and between X2 and MTJ2, respectively; the two magnetic tunnel junctions MTJ1 and MTJ2 can be used to store data in the backup storage nodes. Transmission gates G2 and G3 are used to write the data write signal D and its inverted signal DN to the corresponding backup nodes MTJ1 and MTJ2, respectively; NMOS transistor N21 is used to pull down storage nodes X1 and X2 in conjunction with GND when RES=1.

[0055] The replication section includes multiple NMOS transistors corresponding to the number of redundant memory nodes. For example, when the radiation-hardened latch circuit includes two sets of redundant memory nodes, there are four redundant memory nodes in addition to the main memory node. In this case, the replication section has four NMOS transistors, each corresponding to one of the redundant memory nodes. In the replication section, the source of one half of the NMOS transistors is connected to X1, and the drain is connected to one of the redundant memory nodes in each set. The source of the other half of the NMOS transistors is connected to X2, and the drain is connected to the other of the redundant memory nodes in each set. The gate of each NMOS transistor in the replication section is connected to the data recall enable signal TEN. When TEN=1, all the NMOS transistors in the replication section are turned on, "copying" the level states of the main memory nodes X1 and X2 to the respective redundant memory nodes, thus realizing data recall. Conversely, when TEN=0, all the NMOS transistors in the replication section are turned off, ending the data recall process.

[0056] The circuit scheme in this embodiment reduces the number of sensitive nodes in the circuit by applying a circuit structure to redundant storage nodes reinforced in different ways within the latch circuit. The backup and recovery circuit enables the non-volatile latch to have non-volatile data backup and recovery capabilities; and compared with existing circuit structures, this latch has a lower number of MOS transistors for backup and recovery functions, which can effectively reduce circuit area and power consumption, and significantly improve the data recovery rate of the circuit.

[0057] Based on the aforementioned circuit structure and working principle of the radiation-resistant latch circuit and backup recovery circuit, the read / write circuit in this embodiment can adopt the following... Figure 6 The circuit design shown is as follows. Specifically, the read / write circuit includes a clock-controlled inverting section, a transmission section, and inverters INV1 and INV2. INV1 generates an inverted write signal DN based on the data write signal D; INV2 generates an inverted clock signal NCK based on the clock signal CLK. DN and NCK are internal signals of the circuit. DN can work in conjunction with D to synchronously write data to two inverted memory nodes in each group of redundant memory nodes. To achieve data latching, NCK is used to match the clock signal CLK and switch the operating mode of the non-volatile latch.

[0058] The clock-controlled inverting section consists of two PMOS transistors P9-P10, two NMOS transistors N13-N14, and a transmission gate G1. When CLK=0, transmission gate G1 connects X2 to the output port of the data read signal Q. Conversely, when CLK=0, transmission gate G1 keeps D and Q disconnected, thereby improving the data read rate of the non-volatile latch. In this embodiment, the clock-controlled inverting section actually acts as the execution object for data readout; correspondingly, the transmission section acts as the execution object for data writeout.

[0059] Specifically, in this embodiment, the transmission section of the read / write circuit consists of two PMOS transistors, P11 and P12, and multiple NMOS transistors corresponding to the number of redundant storage nodes. The number of NMOS transistors in the transmission section is exactly the same as the number of NMOS transistors in the replication section of the backup and recovery circuit, and the two are connected accordingly; the circuit connection relationship is as follows:

[0060] The drain of P11 is connected to X1, and the source of P11 is connected to D; the drain of P12 is connected to X2, and the source of P12 is connected to DN; the gates of P11 and P12 are connected to NCK. The gates of each NMOS transistor are connected to CLK; the sources of half of the NMOS transistors are connected to D, and their drains are connected to one of the redundant memory nodes in each group; the sources of the other half of the NMOS transistors are connected to DN, and their drains are connected to the other of the redundant memory nodes in each group.

[0061] Based on the above structure of the read / write circuit, it can be seen that the clock signal in this embodiment can be used to switch the operating mode of the non-volatile latch. Taking a radiation-hardened latch circuit that includes main memory nodes X1 and X2 and two sets of redundant memory nodes X3, X4 and X5, X6, and the transmission section of the read / write circuit that includes NMOS transistors N15, N17, N16, and N18 connected to X3, X4, X5, and X6 respectively as an example, the mode switching logic of the corresponding circuit is as follows:

[0062] (1) When CLK=1 and NCK=0, the circuit is in transparent and backup mode. At this time, P10 and N13 are turned off, while P11, P12 and N15~N18 are all turned on. In this state, the data write signal D can be directly output to the corresponding port of the data read signal Q through the transmission gate G1; in addition, D will also be written to X1, X3 and X5 through P11, N15 and N16 respectively; while DN will be written to X2, X4 and X6 through P12, N17 and N18 respectively; thus completing the data latching.

[0063] (2) When CLK=0 and NCK=1, the circuit is in hold mode; at this time, P10 and N13 are turned on, while P11, P12 and N15~N18 are all turned off. In this state, D and DN cannot rewrite the level state of storage nodes X1~X6, and X2 is output to Q and maintains the level state of Q unchanged.

[0064] Based on the above design principles, and in order to balance the radiation resistance, power consumption, and speed of non-volatile latches, this embodiment ultimately yields a circuit design that optimizes these various performance aspects, as shown below. Figure 7 As shown, in this circuit scheme, the radiation-hardened latch circuit consists of 8 PMOS transistors P1~P8 and 12 NMOS transistors N1~N12; the radiation-hardened latch circuit includes a set of source-isolated hardened main memory nodes X1 and X2, and two sets of N-polarity hardened redundant memory nodes X3, X4 and X5, X6.

[0065] The circuit connections of the radiation-hardened latch circuit are as follows: the sources of P1~P6 are connected to VDD; the sources of N7~N12 are connected to GND; the drain of P1 is connected to the drain of N1; the drain of P2 is connected to the drain of N2; the drain of P3 is connected to the source of P7; the drain of P4 is connected to the source of P8; the drain of P5 is connected to the drain of N3; the drain of P6 is connected to the drain of N4; the drain of P7 and the source of N5 are connected to the gates of N3 and N10 and serve as storage node X1; the drain of P8 and the source of N6 are connected to the gates of N4 and N9 and serve as storage node X2; N7 The drain of N1 and the source of N1 are connected to the gates of P2, P4, and N8 and form storage node X3; the drain of N8 and the source of N2 are connected to the gates of P1, P3, and N7 and form storage node X4; the drain of N11 and the source of N3 are connected to the gates of P6, P8, N1, and N12 and form storage node X5; the drain of N12 and the source of N4 are connected to the gates of P5, P7, N2, and N11 and form storage node X6; the source of N5 is connected to the drain of N9; the source of N6 is connected to the drain of N10; the gates of N5 and N6 are connected to the memory signal EQ.

[0066] In the radiation-hardened latch circuit, PMOS transistors P1-P8 and NMOS transistors N1-N4 form pull-up transistors. These pull-up transistors utilize the power supply VDD to create a charging path, thereby pulling up the voltage levels of memory nodes X1-X6. NMOS transistors N5-N12 act as pull-down transistors, forming a discharge path through grounding, thus pulling down the voltage levels of memory nodes X1-X6. The main memory nodes X1 and X2 employ a source-isolated hardened circuit structure. This structure effectively suppresses transistor charge collection by replacing the traditional inverter's pull-up PMOS transistors with two PMOS transistors connected in series and adding a shallow trench isolation (STI) layer. When a SEU occurs at these two nodes, the generated voltage pulse is insufficient to flip the node from 0 to 1. Therefore, if either of these two nodes stores 0 data, it is not a sensitive node. Redundant storage nodes X3, X4, X5, and X6 employ an N-polarity hardened circuit structure. According to the N-polarity hardening principle, when a SEU occurs at these four nodes, only "1→0" and "0→0" voltage pulses are generated, meaning only negative pulses are produced. Therefore, if the data stored in these storage nodes is 0, the voltage state remains unchanged during an SEU, and they are not considered sensitive nodes.

[0067] Furthermore, to reduce power consumption and mitigate threshold loss, N1, N2, N3, and N4 in the radiation-hardened latch circuit should be low-threshold devices, while the remaining MOSFETs can be standard-threshold devices. In a typical embodiment, the recommended parameter configurations for each MOSFET are as follows: MOSFETs N5, N6, N9, and N10 have a gate length of 30 nm and a gate width of 200 nm; all other MOSFETs have a gate length of 30 nm and a gate width of 100 nm.

[0068] like Figure 7 As shown, the optimal read / write circuit in this embodiment consists of four PMOS transistors P9~P12, six NMOS transistors N13~N18, two inverters INV1 and INV2, and a transmission gate G1. The circuit connection is as follows:

[0069] The source of P9 is connected to the power supply VDD. The gates of P9 and N14, and the drain of P12 are connected to memory node X2. The drain of P9 is connected to the source of P10. The drains of P10 and N13 are connected to the output of G1 and to the data read signal Q. The source of N13 is connected to the drain of N14; the source of N14 is grounded. The inputs of G1 and INV1, the source of P11, and the sources of N15 and N16 are connected to D. The source of P12 and the sources of N17 and N18 are connected to the inverted write signal DN of the INV1 output. The gates of P10, N15~N18, the input of INV2, and the control terminal of G1 are connected to the clock signal CLK. The gates of N13, P11, and P12 are connected to the inverted clock signal NCK of the INV2 output. The drain of P11 is connected to X1; the drain of P12 is connected to X2; the drain of N15 is connected to X3; the drain of N16 is connected to X5; the drain of N17 is connected to X4; and the drain of N18 is connected to X6.

[0070] In the read / write circuit, P11, P12, and N15~N18 constitute transmission transistors. These transistors are turned on when CLK=1 and NCK=0, thereby connecting the data write signal D and its inverted signal DN to each memory node to achieve data writing. Conversely, when CLK=0 and NCK=1, the transmission transistors are turned off, ending the data writing process. Transmission gate G1 is used to connect D to Q through G1 when CLK=1. When CLK=0, the transmission gate keeps D and Q disconnected.

[0071] Based on this, WR, PRE, RES, TEN, and EQ together constitute the key signals for data backup and recovery. The logic for data backup provided in this embodiment using a dual-node flip-flop self-recovering non-volatile latch based on MTJ is as follows:

[0072] When WR=1, PRE=0, RES=0, TEN=0, and EQ=0 are set, data backup is initiated. At this time, transmission gates G2 and G3 are opened. Due to the voltage difference between D and DN, a current path is formed through G2, MTJ1, MTJ2, and G3, causing the resistance states of MTJ1 and MTJ2 to change with the data in D and DN, thereby achieving data backup.

[0073] When the circuit is powered off and VDD=0, the stored data in each storage node of the radiation-resistant latch circuit, characterized by its level state, is lost. However, the magnetic tunnel junctions MTJ1 and MTJ2 in the backup and recovery circuit, characterized by their resistance state, can back up the corresponding data after the power failure.

[0074] Accordingly, the logic for data recovery using a dual-node flip-over self-recovering non-volatile latch based on MTJ is as follows:

[0075] First, set VDD=1, WR=0, PRE=1, RES=0, TEN=1, and EQ=0 to perform a pre-charge operation. At this time, the circuit starts to power on, and P13, P14, N21, N22, N23, and N24 are turned on to pre-charge each storage node to a high level. After the pre-charge is completed, the stored data is restored.

[0076] After the precharge is complete, set WR=0, PRE=0, RES=1, TEN=1, and EQ=1. At this point, the storage node begins to restore the storage voltage before the power outage. The process includes:

[0077] (1) If D backs up data 1 into MTJ1 and DN backs up data 0 into MTJ2, MTJ1 is in AP state and MTJ2 is in P state. The resistance of MTJ1 is greater than that of MTJ2. Since N19, N20, N25, N21, N22, N23, and N24 are turned on, the path from X1, X3, and X5 to ground passes through the high-resistance MTJ1; the path from X2, X4, and X6 to ground passes through the low-resistance MTJ2. Therefore, X2, X4, and X6 discharge faster than X1, X3, and X5, causing N19 to turn off first and P15 to turn on. Therefore, the voltages of X1, X2, and X4 will stop discharging and return to high level, while X2, X4, and X6 will discharge to low level, and the backup recovery is completed.

[0078] (2) Conversely, if D backs up data 0 into MTJ1 and DN backs up data 1 into MTJ2, at this time, MTJ1 is in the P state and MTJ2 is in the AP state. The resistance of MTJ1 is less than the resistance of MTJ2. Similarly, X1, X2, and X4 can be discharged to a low level. The voltages of X2, X4, and X6 will stop discharging and return to a high level, and the backup recovery is completed.

[0079] The MTJ-based dual-node flip-flop self-recovery non-volatile latch provided in this embodiment has good radiation resistance and data recovery performance. External bombardment typically occurs in hold mode. When the storage node is bombarded, the MNVDR circuit in this embodiment can achieve: 1. Full SNU self-recovery; 2. Full DNU self-recovery.

[0080] by Figure 7 Taking the circuit shown as an example, as described above, since the six storage nodes of the non-volatile latch in this embodiment use N-polarity hardening and source isolation technology respectively, when the stored data is 1 (i.e., X1=X3=X5=Q=1, X2=X4=X6=0), there are four sensitive nodes, namely X1, X3, X5, and Q. The circuit principle for implementing SNU and DNU recovery is explained in detail below:

[0081] (1) SNU self-recovery

[0082] In the four sensitive nodes of the circuit, X3 and X5 are symmetrical to each other. Accordingly, SNU contains three cases:

[0083] 1.1 SNU occurs in X1

[0084] In this state, the state of X1 flips from 1 to 0, N3 and N10 are cut off, X2 and X5 are in a high-impedance state, maintaining the original voltage unchanged. Since the states of X4, X6 and X2 are 0 / 0 / 1 respectively, the pull-up path of X1 is open and the pull-down path is cut off, the circuit can automatically restore X1 to state 1.

[0085] 1.2. SNU occurs in X3 or X5.

[0086] Since this part has a symmetrical structure, this embodiment only needs to analyze the situation where one node flips. For example, when X3 experiences SNU, the state of X3 flips from 1 to 0, N8 is cut off, P2 and P4 are turned on, X4 is in a high-impedance state, maintaining the original voltage unchanged. Because the states of X4 and X5 are 0 / 1 respectively, the pull-up path of X3 is open, and the pull-down path is cut off. The circuit can restore X3 to state 1.

[0087] 1.3, SNU occurs in Q.

[0088] In this state, the internal storage nodes of the radiation-resistant latch circuit are not affected by SNU, and therefore remain in the correct state. In this embodiment, the circuit can automatically restore Q to the correct state through the clock-controlled inverter section.

[0089] (2) DNU self-recovery

[0090] In this embodiment of the circuit, based on the distribution of sensitive nodes, the DNU includes the following 6 cases:

[0091] 2.1 DNU occurs<X1,X3> or<X1,X5>

[0092] by<X1,X3> Taking a DNU (Disruption Nullification) event as an example, when X1 and X3 flip from 1 to 0, N3, N8, and N10 are cut off, P2 and P4 are turned on, and X2, X4, and X5 are in a high-impedance state, maintaining their original voltages. Because the states of X4 and X5 are 0 and 1 respectively, the pull-up path of X3 is open, and the pull-down path is closed, restoring to state 1. Because the states of X4, X6, and X2 are 0, 0, and 1 respectively, the pull-up path of X1 is open, and the pull-down path is closed, restoring to state 1. Therefore, X1 and X3 achieve self-recovery.<X1,X5> and<X1,X3> The recovery principle in the event of DNU is similar, and will not be repeated in this embodiment.

[0093] 2.2 DNU occurs<X1,Q>

[0094] When X1 and Q flip from 1 to 0, N3 and N10 are cut off, X2 and X5 are in a high-impedance state, maintaining their original voltages. Since X4, X6, and X2 are in states 0 / 0 / 1 respectively, the pull-up path of X1 is open, and the pull-down path is cut off, returning to state 1. Because X2 remains in state 0, Q returns to state 1. Therefore, X1 and Q achieve self-recovery.

[0095] 2.3 DNU occurs<X3,XQ> or<X5,Q>

[0096] by<X3,Q> Taking a DNU as an example, when the states of X3 and Q flip from 1 to 0, N8 is cut off, P2 and P4 are turned on, X4 is in a high-impedance state, maintaining its original voltage. Because the states of X4 and X5 are 0 / 1 respectively, the pull-up path of X3 is open, and the pull-down path is cut off, returning to state 1. Since the state of X2 remains unchanged at 0, Q returns to state 1. Therefore, X3 and XQ achieve self-recovery.<X5,Q> and<X3,Q> The recovery principle in the event of DNU is similar, and will not be repeated in this embodiment.

[0097] 2.4. DNU occurs<X3,X5>

[0098] When the states of X3 and X5 flip from 1 to 0, N8 and N12 are cut off, and P2, P4, P6, and P8 are turned on. X4 and X6 are in a high-impedance state, maintaining their original voltages. For X2, both the pull-up and pull-down paths are turned on simultaneously. Because N6 and N10 are 200nm transistors with high pull-down drive capability, X2 remains in the 0 state. Since the states of X4 and X5 are 0 and 1 respectively, the pull-up path of X3 is open, and the pull-down path is cut off, returning to state 1. Similarly, the states of X1 and X6 are 0 and 1 respectively, and the pull-up path of X5 is open, and the pull-down path is cut off, returning to state 1. Therefore, X3 and X5 achieve self-recovery.

[0099] Example 2

[0100] Based on the good radiation resistance and data recovery performance of the non-volatile latch provided in Embodiment 1, this embodiment further provides a radiation-resistant memory chip, which uses a dual-node flip-over self-recovering non-volatile latch based on MTJ as described in Embodiment 1 as the memory unit.

[0101] Performance testing

[0102] To verify the advantages of the present invention, technicians used... Figure 7 Taking the circuit scheme with 51 transistors and 2 MTJs as an example, the circuit performance of this scheme is simulated and tested:

[0103] 1. Power outage recovery function

[0104] This experiment first tested the circuit's data backup and recovery functions before and after a power outage. The timing signal streams of the key signals in this process are as follows: Figure 8 As shown.

[0105] respectively Figure 8 As the data shows, this invention enables data backup and recovery, and the backup and recovery speed is relatively fast.

[0106] 2. Resistance to single-node flipping

[0107] This experiment verifies the data recovery performance of the circuit under a single-node switching state (SNU). The test process simulates scenarios where bombardment occurs at X1, X3, X5, and Q, causing the node state to switch from 1 to 0. The final simulation results are shown in Table 1, and the corresponding timing waveforms are as follows. Figure 9 As shown.

[0108] Table 1: SNU Simulation Verification Table

[0109]

[0110] Based on the above data, it can be seen that the circuit of the present invention can correctly achieve data recovery in all four SNU states.

[0111] 3. Anti-double node flipping

[0112] This experiment verifies the data recovery performance of the circuit under dual-node switching state (DNU). The test process is based on the bombardment occurring at...<X1,X3> ,<X1,X5> ,<X1,Q> ,<X3,XQ> ,<X5,Q> and<X3,X5> The simulation was performed with the node state flipped from 1 to 0. The resulting simulation states are shown in Table 2, and the corresponding timing waveforms are as follows. Figure 10 As shown.

[0113] Table 2: DNU Simulation Verification Table

[0114]

[0115] Based on the above data, it can be seen that the circuit of the present invention can correctly achieve data recovery in all 6 DNU states.

[0116] 4. Performance Comparison

[0117] This experiment uses the four circuit schemes described in the background art as control groups and compares them with the circuit scheme of this invention (denoted as MNVDR). The delay time (Tdq) from D to Q, the average power consumption, backup power consumption, recovery power consumption, recovery time, number of transistors, and fault tolerance of the five circuit schemes are tested. The performance comparison table is shown in Table 3.

[0118] Table 3: Performance Comparison Table of the Invention Circuit and the Control Circuit:

[0119]

[0120] Analysis of the data in the table above reveals that: the Tdq of the MNVDR circuit is only 2.3ps, the same as the minimum value of TPDICE; the average power consumption of the MNVDR circuit is only 0.328uW, which is close to the lowest average power consumption (0.246uW of SEDNUT); the backup power consumption of the MNVDR circuit is 48.49uW and the recovery power consumption is 28.78uW, which is at a medium level; the recovery time of the MNVDR circuit is 68.4ps, which is the lowest among the five circuits; the MNVDR uses 51 transistors, second only to the 39 transistors of the SBRH circuit; all five circuits use 2 MTJs; in terms of fault tolerance, the MNVDR can achieve dual-node self-recovery, only comparable to the M-8C. In summary, the MNVDR scheme of this invention uses fewer transistors, has low power consumption and delay, but achieves the best fault tolerance and has good overall performance.

[0121] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A MTJ-based dual-node flip self-restoring non-volatile latch, characterized in that, It includes: Radiation-resistant latch circuit, which includes multiple sets of redundant and hardened storage nodes; It includes at least one set of primary storage nodes X1 and X2 that are non-polar hardened, and the remaining sets are redundant storage nodes. A read / write circuit is electrically connected to each storage node in the radiation-resistant latch circuit and is used to perform data read / write tasks on the radiation-resistant latch circuit. The backup and recovery circuit includes a basic section and a replication section. The basic section consists of four PMOS transistors P13-P16, three NMOS transistors N19-N21, two transmission gates G2 and G3, and two magnetic tunnel junctions MTJ1 and MTJ2. The sources of P13-P16 are connected to VDD. The drains of P13, P15, and N19 and the gates of P16 and N20 are connected to X1. The drains of P14, P16, and N20 and the gates of P15 and N19 are connected to X2. The gates of P13 and P14 are connected to the precharge signal PRE; the source of N19 is connected to the output of G2 and the free layer of MTJ1; the source of N20 is connected to the output of G3 and the free layer of MTJ2; the input of G2 is connected to the data write signal D, the input of G3 is connected to the inverted write signal DN, and the control terminals of G2 and G3 are connected to the write control signal WR; the fixed layers of MTJ1 and MTJ2 are connected to the drain of N21; the gate of N21 is connected to the reset signal RES, and the source is grounded; The replication section includes multiple NMOS transistors corresponding to the number of redundant memory nodes. Half of the NMOS transistors have their sources connected to X1 and their drains connected to one of the redundant memory nodes in each group. The other half of the NMOS transistors have their sources connected to X2 and their drains connected to the other of the redundant memory nodes in each group. The gate of each NMOS transistor in the replication section is connected to the memory recall enable signal TEN.

2. The MTJ-based two-node flip self-restoring non-volatile latch of claim 1, wherein: The read / write circuit includes a clock-controlled inverting section, a transmission section, and inverters INV1 and INV2; INV1 is used to generate an inverted write signal DN based on the data write signal D; INV2 is used to generate an inverted clock signal NCK based on the clock signal CLK. The clock-controlled inverting section consists of two PMOS transistors P9~P10, two NMOS transistors N13~N14, and a transmission gate G1; and is used to connect X2 to the output port of the data readout signal Q when CLK=0. The transmission section consists of two PMOS transistors, P11 and P12, and multiple NMOS transistors corresponding to the number of redundant memory nodes. The drain of P11 is connected to X1, and the source of P11 is connected to D. The drain of P12 is connected to X2, and the source of P12 is connected to DN. The gates of P11 and P12 are connected to NCK. The gates of each NMOS transistor are connected to CLK. Half of the NMOS transistors have their sources connected to D and their drains connected to one of the redundant memory nodes in each group. The sources of the other half of the NMOS transistors are connected to DN, and their drains are connected to the other node in each group of redundant memory nodes.

3. The MTJ-based two-node flip self-restoring non-volatile latch of claim 1, wherein: In the radiation-hardened latch circuit, the main storage node adopts a C-cell or source isolation hardened circuit structure; each redundant storage node adopts any one of C-cell, source isolation hardening, or polarity hardening.

4. The MTJ-based two-node flip self-restoring non-volatile latch of claim 3, wherein: The radiation-resistant latch circuit consists of 8 PMOS transistors P1~P8 and 12 NMOS transistors N1~N12; it includes a set of source-isolated hardened main memory nodes X1 and X2, and two sets of N-polarity hardened redundant memory nodes X3, X4 and X5, X6. In this configuration, the sources of P1 to P6 are connected to VDD; the sources of N7 to N12 are connected to GND; the drain of P1 is connected to the drain of N1; the drain of P2 is connected to the drain of N2; the drain of P3 is connected to the source of P7; the drain of P4 is connected to the source of P8; the drain of P5 is connected to the drain of N3; the drain of P6 is connected to the drain of N4; the drain of P7 and the source of N5 are connected to the gates of N3 and N10 and form memory node X1; the drain of P8 and the source of N6 are connected to the gates of N4 and N9 and form memory node X2; the drain of N7 and the source of N1 are connected to the gates of N1 and N2. The gates of P2, P4, and N8 are connected to form storage node X3; the drain of N8 and the source of N2 are connected to the gates of P1, P3, and N7 and form storage node X4; the drain of N11 and the source of N3 are connected to the gates of P6, P8, N1, and N12 and form storage node X5; the drain of N12 and the source of N4 are connected to the gates of P5, P7, N2, and N11 and form storage node X6; the source of N5 is connected to the drain of N9; the source of N6 is connected to the drain of N10; the gates of N5 and N6 are connected to the memory signal EQ.

5. The MTJ-based two-node flip self-restoring non-volatile latch of claim 4, wherein: N1, N2, N3, and N4 are low-threshold devices, while the remaining MOS transistors are standard-threshold devices.

6. The non-volatile latch based on MTJ with dual-node flip-and-recovery as described in claim 4, characterized in that: The read / write circuit consists of four PMOS transistors P9~P12, six NMOS transistors N13~N18, two inverters INV1 and INV2, and a transmission gate G1. The source of P9 is connected to power supply VDD; the gates of P9 and N14, and the drain of P12 are connected to memory node X2; the drain of P9 is connected to the source of P10; the drains of P10 and N13 are connected to the output of G1 and to the data read signal Q; the source of N13 is connected to the drain of N14; the source of N14 is grounded; the inputs of G1 and INV1, the source of P11, and the sources of N15 and N16 are connected to D; the source of P12 and the sources of N17 and N18 are connected to the inverted write signal DN of the INV1 output; the gates of P10, N15~N18, the input of INV2, and the control terminal of G1 are connected to the clock signal CLK; N13 The gates of P11 and P12 are connected to the inverted clock signal NCK at the output of INV2; the drain of P11 is connected to X1; the drain of P12 is connected to X2; the drain of N15 is connected to X3; the drain of N16 is connected to X5; the drain of N17 is connected to X4; and the drain of N18 is connected to X6.

7. The MTJ-based dual-node flip-and-recovery non-volatile latch according to claim 6, characterized in that: When CLK=1 and NCK=0, the circuit is in transparent and backup mode; At this point, D is directly output to Q via G1; D is written to X1, X3, and X5 via P11, N15, and N16 respectively; DN is written to X2, X4, and X6 via P12, N17, and N18 respectively; thus completing the data latching. When CLK=0 and NCK=1, the circuit is in hold mode; at this time, P10 and N13 are turned on, so that X2 is output to Q and the level of Q remains unchanged.

8. The MTJ-based dual-node flip-and-recovery non-volatile latch according to claim 7, characterized in that, Its data backup logic is as follows: When WR=1, PRE=0, RES=0, TEN=0, and EQ=0 are set, data backup is initiated. At this time, there is a voltage difference between D and DN, forming a current path through G2, MTJ1, MTJ2, and G3. This causes the resistance state of MTJ1 and MTJ2 to change with the data of D and DN, thereby achieving data backup. When VDD=0, the stored data in each storage node of the radiation-resistant latch circuit, characterized by its level state, is lost. However, the magnetic tunnel junctions MTJ1 and MTJ2 in the backup and recovery circuit store data through their resistance state and back up the corresponding data after power failure.

9. The MTJ-based dual-node flip-and-recovery non-volatile latch according to claim 8, characterized in that, The logic for achieving data recovery is as follows: First, set VDD=1, WR=0, PRE=1, RES=0, TEN=1, EQ=0 to perform the precharge operation. At this time, P13, P14, N21, N22, N23, and N24 are turned on, and each memory node is precharged to a high level. Then set WR=0, PRE=0, RES=1, TEN=1, EQ=1. At this point, the storage node begins to restore the storage voltage before the power loss. (1) If D backs up data 1 into MTJ1 and DN backs up data 0 into MTJ2, at this time, MTJ1 is in AP state and MTJ2 is in P state. The resistance of MTJ1 is greater than that of MTJ2. Since N19, N20, N25, N21, N22, N23, and N24 are turned on, the path to ground for X1, X3, and X5 passes through the high-resistance MTJ1; the path to ground for X2, X4, and X6 passes through the low-resistance MTJ2. Therefore, the discharge speed of X2, X4, and X6 is faster than that of X1, X3, and X5, so N19 is turned off first and P15 is turned on. Therefore, the voltage of X1, X2, and X4 will stop discharging and return to high level, and X2, X4, and X6 will discharge to low level. The backup and recovery are completed. (2) Conversely, if D backs up data 0 into MTJ1 and DN backs up data 1 into MTJ2, at this time, MTJ1 is in the P state and MTJ2 is in the AP state. The resistance of MTJ1 is less than the resistance of MTJ2. Similarly, X1, X2, and X4 can be discharged to a low level. The voltages of X2, X4, and X6 will stop discharging and return to a high level, and the backup recovery is completed.

10. A radiation-resistant memory chip, characterized in that, It uses a dual-node flip-and-recovery non-volatile latch based on MTJ as described in any one of claims 1-9 as the storage unit.

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