Laser frequency and power control system for atom magnetometer
By combining a saturated absorption optical path and an acousto-optic modulator with a DDS chip and FPGA circuit control method, the problems of unstable laser power and low-frequency noise interference were solved, the detection accuracy of the atomic magnetometer was improved and miniaturization was achieved.
Patent Information
- Application Number
- CN202511393173.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-27
- Publication Date
- 2026-01-09
AI Technical Summary
Existing technologies cannot achieve rapid amplitude modulation while ensuring stable laser power, which leads to a decrease in the detection accuracy of atomic magnetometers, and the system cannot meet the stringent requirements of miniaturization, low power consumption and low magnetic noise.
Laser frequency stabilization is achieved using a saturated absorption optical path, and laser power is controlled by an acousto-optic modulator. By combining a DDS chip and FPGA circuit to drive the acousto-optic modulator, laser power stabilization and amplitude square wave control are achieved, reducing low-frequency noise interference.
The detection accuracy of the atomic magnetometer has been improved, and the system has been miniaturized and made less noisy, meeting the requirements of miniaturization and low power consumption.
Smart Images
Figure CN121307616A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of optical and signal processing technology, specifically relating to a laser frequency and power control system for an atomic magnetometer. This system achieves laser frequency stabilization through saturated absorption and stabilizes laser power, amplitude square wave control, and frequency control by controlling an acousto-optic modulator. This solves the problem of unstable laser power and reduces low-frequency noise in the laser, thereby greatly improving the detection accuracy of the atomic magnetometer. Furthermore, the driving and control of the acousto-optic modulator are achieved through a DDS chip (Direct Digital Synthesizer) + FPGA (Field-Programmable Gate Array) circuit, which is beneficial for the miniaturization of the atomic magnetometer. Background Technology
[0002] Atomic magnetometers, with their theoretical accuracy advantages and potential for miniaturization and integration, have gained widespread application in fields such as biomedicine, geophysics, and quantum information, attracting significant attention from research institutions both domestically and internationally. In this device, the laser and pump light place extremely high demands on the stability of the light source power and frequency. As the core light source, the semiconductor laser inherently exhibits large power fluctuations, necessitating power stabilization. While laser frequency can be stabilized through saturable absorption technology, power stability cannot be achieved through internal mechanisms. Furthermore, the laser is susceptible to noise interference from other electronic devices, reducing system accuracy; therefore, rapid amplitude modulation is required while ensuring power stability. Existing technologies typically separate power stabilization and amplitude control systems, and the atomic magnetometer itself requires a magnetically shielded environment, making it difficult for current laser power stabilization and control schemes to simultaneously meet the stringent requirements of small size, low power consumption, low magnetic noise, and rapid power modulation. Summary of the Invention
[0003] This invention addresses the deficiencies or shortcomings of existing technologies by providing a laser frequency and power control system for atomic magnetometers. This system achieves laser frequency stabilization through oversaturation absorption and stabilizes laser power, controls amplitude square waves, and controls laser frequency by controlling an acousto-optic modulator. This suppresses laser power fluctuations and low-frequency noise interference, thereby greatly improving the detection accuracy of the atomic magnetometer. Furthermore, the driving and control of the acousto-optic modulator are achieved through a DDS chip + FPGA circuit, which is beneficial for the miniaturization of the atomic magnetometer.
[0004] The technical solution of the present invention is as follows:
[0005] A laser frequency and power control system for an atomic magnetometer is characterized by comprising a laser frequency stabilization control optical path based on a saturable absorption optical path and a laser power control circuit based on an acousto-optic modulator (AOM). The laser power control circuit includes circuitry connected to the AOM, a second photodetector, and a host computer. The output side of the AOM is connected to the input side of a polarizing beam splitter via a third half-wave plate. The input side of the AOM sequentially connects to a polarizer, a second half-wave plate, a first semi-transparent mirror, another half-wave plate, an isolator, and a semiconductor laser. The reflecting side of the polarizing beam splitter is connected to the second optical path. An electrical detector generates a feedback input signal. The transmission side of the polarization beam splitter outputs the incident laser signal used by the atomic magnetometer. The circuit system drives the AOM to achieve laser power control according to the feedback input signal. The laser frequency stabilization control optical path includes a second semi-transparent mirror connected to the reflection side of the first semi-transparent mirror on its input side. The reflection side of the second semi-transparent mirror is connected to a high-transmission, low-reflection mirror through a rubidium atom gas cell. The transmission side of the second semi-transparent mirror is connected to the semiconductor laser in sequence through a first photodetector and a mixer. The rubidium atom gas cell achieves rubidium atom saturation absorption of the laser.
[0006] The circuit system includes an analog-to-digital converter (ADC) whose input is connected to the second photodetector. The output of the ADC is connected to an FPGA chip. The FPGA chip is connected to a power amplifier circuit via an AD9910 chip and a low-pass filter circuit. The power amplifier circuit outputs control signals to the AOM. The FPGA chip is equipped with an ADC driver and an AD9910 driver. The ADC driver is connected to the AD9910 driver via a PID control program and a modulation program.
[0007] The ADC uses an AD7767 chip. The AD7767 chip and the FPGA chip have the following corresponding pin connections: CS pin, MCLK pin, SCLK pin, SYNC pin, DRDY pin, and SDO pin. The second photodetector is connected to one end of a single-ended to differential circuit. The dual outputs of the single-ended to differential circuit are respectively connected to the positive input voltage terminal VIN+ and the negative input voltage terminal VIN- of the AD7767 chip.
[0008] The AD9910 chip includes an enable and configuration register, a Profile0 register, a phase-locked loop (PLL), a DA conversion module, and an ASF amplitude register. The ASF amplitude register is connected to the FPGA module through a parallel data port. The enable and configuration register and the Profile0 register are both connected to the FPGA module through an SPI data port. The ASF amplitude register, the Profile0 register, and the DA conversion module are respectively connected to the DDS core. The DA conversion module is connected to the power amplifier circuit through a low-pass filter circuit.
[0009] The AD9910 chip is connected to an external crystal oscillator, a two-ended to one-ended converter circuit, and a loop filter circuit. The external crystal oscillator provides an external clock to the AD9910. The single-ended output signal of the two-ended to one-ended converter circuit is output to the low-pass filter circuit. The AD9910 chip has the following corresponding pins connected to the FPGA module: D pin, F pin, TxENABLE pin, SCLK pin, CS_n pin, SDIO pin, IO_UPDATE pin, IO_RESET pin, and MASTER_RESET pin.
[0010] The low-pass filter circuit employs a passive LC low-pass filter, comprising an input terminal, a first intermediate node, a second intermediate node, and an output terminal arranged sequentially. The input terminal is connected to one end of a resistor, one end of a 71st capacitor, one end of a 75th capacitor, and one end of a 15th inductor. The other end of the 15th inductor is connected to the first intermediate node. The first intermediate node is connected to one end of a 72nd capacitor, one end of a 76th capacitor, and one end of a 16th inductor. The other end of the 16th inductor is connected to the second intermediate node. The second intermediate node is connected to one end of a 73rd capacitor, one end of a 77th capacitor, and one end of a 17th inductor. The other end of the 17th inductor is connected to the output terminal. The output terminal is connected to one end of a 74th capacitor and one end of a 78th capacitor. The other ends of the resistor, the 71st capacitor, the 75th capacitor, the 72nd capacitor, the 76th capacitor, the 73rd capacitor, the 77th capacitor, the 74th capacitor, and the 78th capacitor are all connected to ground.
[0011] The process of configuring the AD9910 driver for the FPGA chip includes the following steps: Step 1, Start; Step 2, Reset and Initialization; Step 3, Enable I / O Port; Step 4, Configure Serial Port; Step 5, Configure Parallel Port; Step 6, End Configuration; Step 4 includes Step 41, Sending Instructions and Data to the Second Control Function Register CFR2; Step 42, Sending Instructions and Data to the Third Control Function Register CFR3; Step 43, Sending Instructions and Data to Register Profile0; Step 5 includes reconfiguring CFR2 by sending CFR2 instructions and data.
[0012] The semiconductor laser emits polarized light with a wavelength of 780 nm and a power in the milliwatt range. This beam is processed by a first half-wave plate and a polarizer to output linearly polarized light. The output laser intensity can be adjusted by controlling the first half-wave plate. The linearly polarized beam is incident on an acousto-optic modulator to generate Bragg diffraction, separating it into zero-order and first-order diffracted beams. The first-order diffracted beam is used as the experimental laser. The first-order diffracted beam is used as the main beam and enters the second half-wave plate. The beam splitting ratio of the polarizing beam splitter can be adjusted by rotating the second half-wave plate. The polarizing beam splitter separates the beam into a main beam and a sampling beam. The main beam is used as the laser for an atomic magnetometer. The sampling beam is incident on a second photodetector for laser power sampling.
[0013] The technical effects of this invention are as follows: This invention is used for the laser frequency and power control system of an atomic magnetometer. It implements its function based on an AOM (acousto-optic modulator), utilizing an electronic control system and an acousto-optic modulator drive module to achieve continuous and high-frequency control of the laser power. This technology is implemented through external control, having no impact on the semiconductor laser itself, thus having no effect on internal control frequency stabilization. Furthermore, it introduces low magnetic noise. Compared to traditional power stabilization systems based on acousto-optic modulators, this paper designs an acousto-optic modulator drive module based on the DDS chip AD9910, integrating the power stabilization module and the power fast amplitude control module, meeting the requirements of miniaturization and integration.
[0014] This invention relates to a laser frequency and power control system for a magnetometer, comprising a saturated absorption optical path, a laser control optical path based on an acousto-optic modulator (AOM), a circuit system module, and a host computer. The optical path consists of a semiconductor laser, a half-wave plate, a polarizer, an acousto-optic modulator, a polarization beam splitter, a photodetector, a rubidium atom gas cell, and a high-transmittance, low-reflection mirror. The circuit system includes a power supply module, an FPGA module, a data acquisition circuit, an AD (analog-to-digital converter) module, and an acousto-optic modulator driver module. To achieve miniaturization, this invention utilizes the DDS chip AD9910 to design the acousto-optic modulator driver module. By acquiring the laser power and using the circuit system to perform feedback control on the AOM, laser power stability and square wave power control are achieved. This invention can improve the power stability of the laser in a miniature atomic magnetometer, reduce low-frequency noise in the laser, improve the detection accuracy of the atomic magnetometer, and integrate the frequency and power stabilization and control system, which is beneficial for the miniaturization and integration of the atomic magnetometer.
[0015] The advantages of this invention compared to existing technologies are: it uses an external optical path and circuit system to achieve frequency control, power stabilization, and square wave amplitude control of the laser. While ensuring power stability, it eliminates the influence of laser light noise, significantly improving the detection accuracy of the atomic magnetometer. Furthermore, the system is small in size and introduces low noise. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the laser frequency and power control system for an atomic magnetometer, which implements the present invention.
[0017] Figure 2 yes Figure 1 A schematic diagram of the structure and principle of the circuit system 16. Figure 2 The system includes an input interface connecting to the second photodetector 15, an output interface connecting to the acousto-optic modulator AOM 12, and a host computer interface connecting to the host computer 17. The ADC is an analog-to-digital converter module, the FPGA is a field-programmable gate array, the PID is a proportional-integral-differential control program, and the AD9910 is a DDS chip (Direct Digital Synthesizer). The AD9910 chip is connected to a power amplifier circuit via a low-pass filter circuit, and the power amplifier circuit outputs a signal to the AOM.
[0018] Figure 3 yes Figure 2A schematic diagram illustrating the combined structure of the ADC and FPGA chip / acquisition circuit. Figure 3 The AD7767 is an ADC chip. VIN+ is the positive input voltage terminal (corresponding to the first differential output terminal in the differential converter), and VIN- is the negative input voltage terminal (corresponding to the second differential output terminal in the differential converter). The differential converter is a single-ended to differential circuit. The single end of the single-ended to differential circuit receives the input signal from the second photodetector 15. CS, MCLK, SCLK, SYNC, DRDY, and SDO are all pins.
[0019] Figure 4 yes Figure 2 A schematic diagram illustrating the combined structure between the AD9910 and the FPGA module. Figure 4 The device includes an AD9910 initialization module, an amplitude, frequency, and phase initial configuration module, and an amplitude control module, all of which are connected to the FPGA master timing controller. The AD9910 initialization module and the amplitude, frequency, and phase initial configuration module are all connected to the SPI data port (SPI, Serial Peripheral Interface), and the amplitude control module is connected to the parallel data port. The AD9910 includes registers (enable and configuration register, Profile0 register), a phase-locked loop (PLL), a digital-to-analog (DA) converter module, and an amplitude scale factor (ASF) register. The ASF register is connected to the FPGA module via a parallel data port. The enable and configuration register and the Profile0 register are both connected to the FPGA module via an SPI data port. The ASF register, the Profile0 register, and the DA converter module are all connected to the DDS core (Profile0 is the 0th internal programming register). The DA converter module is connected to the power amplifier module via a low-pass filter (LPF).
[0020] Figure 5 Yes, yes Figure 2 A schematic diagram illustrating the connection structure between the DDS module (AD9910) and the FPGA module. Figure 5The AD9910 is connected to the FPGA, an external crystal oscillator, a single-ended converter, and a loop filter circuit. The external crystal oscillator provides an external clock to the AD9910. The loop filter circuit is connected to the PLL_LOOP_FILTER pin of the AD9910. The single-ended converter is a two-ended to one-ended circuit. VOUT+ is the positive output voltage terminal (VOUT+ is output from the AD9910 and corresponds to the first input terminal of the two-ended to one-ended circuit), and VOUT- is the negative output voltage terminal (VOUT- is output from the AD9910 and corresponds to the second input terminal of the two-ended to one-ended circuit). The single-ended output signal of the two-ended to one-ended circuit is output to the low-pass filter. D, F, TxENABLE, SCLK, CS_n, SDIO, IO_UPDATE, IO_RESET, and MASTER_RESET are all pins. The AD9910 integrates a PLL.
[0021] Figure 6 yes Figure 2 A schematic diagram of a low-pass filter circuit. Figure 6 The low-pass filter circuit uses a passive LC low-pass filter with a cutoff frequency of 400MHz. Figure 6 AGND is the ground terminal, SECOMDARY is the input terminal, C65~C68 are capacitors 65 to 68 (pF level), C71~C78 are capacitors 71 to 78, L15~L17 are inductors 15 to 17 (nH level), R37 is a resistor (51 ohm).
[0022] Figure 7 This is a flowchart illustrating the program flow for configuring the AD9910 on an FPGA. Figure 7 The process includes steps 1, Start; 2, Reset and Initialization; 3, Enable I / O Ports; 4, Configure Serial Ports; 5, Configure Parallel Ports; and 6, End Configuration. Step 4 includes steps 41, Sending instructions and data to the Second Control Function Register (CFR2); 42, Sending instructions and data to the Third Control Function Register (CFR3); and 43, Sending instructions and data to Register Profile0 (Profile0 is internal programming register number 0). Step 5 includes reconfiguring CFR2 by sending CFR2 instructions and data.
[0023] The reference numerals in the attached figures are explained as follows: 1-Semiconductor laser; 2-Isolator; 3-First half-wave plate; 4-First semi-transparent and semi-reflective mirror; 5-Second semi-transparent and semi-reflective mirror; 6-Rubydium atom gas cell; 7-High-transparency and low-reflection mirror; 8-First photodetector; 9-Mixer; 10-Second half-wave plate; 11-Polarizer; 12-Acousto-optic modulator (AOM); 13-Third half-wave plate; 14-Polarizing beam splitter prism; 15-Second photodetector; 16-Circuit system; 17-Host computer. Detailed Implementation
[0024] The following is in conjunction with the attached diagram ( Figures 1-7 The invention will be described in the following sections and examples.
[0025] Figure 1 This is a schematic diagram of the laser frequency and power control system for an atomic magnetometer, which implements the present invention. Figure 2 yes Figure 1 A schematic diagram of the structure and principle of the circuit system 16. Figure 3 yes Figure 2 A schematic diagram illustrating the combined structure of the ADC and FPGA chip / acquisition circuit. Figure 4 yes Figure 2 A schematic diagram illustrating the combined structure between the AD9910 and the FPGA module. Figure 5 Yes, yes Figure 2 A schematic diagram illustrating the connection structure between the DDS module (AD9910) and the FPGA module. Figure 6 yes Figure 2 A schematic diagram of a low-pass filter circuit. Figure 7 This is a flowchart illustrating the program flow for configuring the AD9910 on an FPGA. (Reference) Figures 1 to 7As shown, the laser frequency and power control system for an atomic magnetometer includes a laser frequency stabilization control optical path based on a saturable absorption optical path and a laser power control circuit based on an acousto-optic modulator AOM12. The laser power control circuit includes a circuit system 16 connected to AOM12, a second photodetector 15, and a host computer 17. The output side of AOM12 is connected to the input side of a polarizing beam splitter 14 via a third half-wave plate 13. The input side of AOM12 is sequentially connected to a polarizer 11, a second half-wave plate 10, a first semi-transparent mirror 4, a first half-wave plate 3, an isolator 2, and a semiconductor laser 1. The reflection side of the polarizing beam splitter 14 is connected to... The second photodetector 15 generates a feedback input signal. The transmission side of the polarization beam splitter 14 outputs the incident laser signal for the atomic magnetometer. The circuit system 16 drives the AOM 12 to achieve laser power control according to the feedback input signal. The laser frequency stabilization control optical path includes a second semi-transparent mirror 5 connected to the reflection side of the first semi-transparent mirror 4 at its input side. The reflection side of the second semi-transparent mirror 5 is connected to a high-transmission, low-reflection mirror 7 through a rubidium atom gas cell 6. The transmission side of the second semi-transparent mirror 5 is connected to the semiconductor laser 1 in sequence through a first photodetector 8 and a mixer 9. The rubidium atom gas cell 6 achieves rubidium atom saturation absorption of the laser.
[0026] The circuit system 16 includes an analog-to-digital converter (ADC) module whose input is connected to the second photodetector 15. The output of the ADC is connected to an FPGA chip. The FPGA chip is connected to a power amplifier circuit via an AD9910 chip and a low-pass filter circuit. The power amplifier circuit outputs control signals to the AOM. The FPGA chip is configured with an ADC driver and an AD9910 driver. The ADC driver is connected to the AD9910 driver via a PID control program and a modulation program. The ADC uses an AD7767 chip. The AD7767 chip and the FPGA chip have the following corresponding pin connections: CS pin, MCLK pin, SCLK pin, SYNC pin, DRDY pin, and SDO pin. The second photodetector 15 is connected to one end of a single-ended to differential converter circuit. The dual outputs of the single-ended to differential converter circuit are respectively connected to the positive input voltage terminal VIN+ and the negative input voltage terminal VIN- of the AD7767 chip.
[0027] The AD9910 chip includes an enable and configuration register, a Profile0 register, a phase-locked loop (PLL), a DA conversion module, and an ASF amplitude register. The ASF amplitude register is connected to the FPGA module via a parallel data port. Both the enable and configuration register and the Profile0 register are connected to the FPGA module via SPI data ports. The ASF amplitude register, the Profile0 register, and the DA conversion module are all connected to the DDS core. The DA conversion module is connected to the power amplifier circuit via a low-pass filter circuit. The AD9910 chip is connected to an external crystal oscillator, a two-ended to one-ended converter, and a loop filter circuit. The external crystal oscillator provides an external clock to the AD9910. The single-ended output signal of the two-ended to one-ended converter is output to the low-pass filter circuit. The AD9910 chip and the FPGA module have the following corresponding pin connections: D pin, F pin, TxENABLE pin, SCLK pin, CS_n pin, SDIO pin, IO_UPDATE pin, IO_RESET pin, and MASTER_RESET pin.
[0028] The low-pass filter circuit employs a passive LC low-pass filter, comprising an input terminal SECOMDARY, a first intermediate node, a second intermediate node, and an output terminal arranged sequentially. The input terminal is connected to one end of resistor R37, one end of capacitor C71 (71st), one end of capacitor C75 (75th), and one end of inductor L15 (15th). The other end of inductor L15 is connected to the first intermediate node. The first intermediate node is connected to one end of capacitor C72 (72nd), one end of capacitor C76 (76th), and one end of inductor L16 (16th). The other end of inductor L16 is connected to the second intermediate node. The second intermediate node is connected to... Connect one end of capacitor C73 (73rd), one end of capacitor C77 (77th), and one end of inductor L17 (17th). Connect the other end of inductor L17 to the output terminal. Connect the output terminal to one end of capacitor C74 (74th) and one end of capacitor C78 (78th). Connect the other ends of resistor R37, capacitor C71 (71st), capacitor C75 (75th), capacitor C72 (72nd), capacitor C76 (76th), capacitor C73 (73rd), capacitor C77 (77th), capacitor C74 (74th), and capacitor C78 (78th) to ground terminal AGND.
[0029] The process of configuring the AD9910 driver for the FPGA chip includes the following steps: Step 1, Start; Step 2, Reset and Initialization; Step 3, Enable I / O Port; Step 4, Configure Serial Port; Step 5, Configure Parallel Port; Step 6, End Configuration; Step 4 includes Step 41, Sending Instructions and Data to the Second Control Function Register CFR2; Step 42, Sending Instructions and Data to the Third Control Function Register CFR3; Step 43, Sending Instructions and Data to Register Profile0; Step 5 includes reconfiguring CFR2 by sending CFR2 instructions and data.
[0030] The semiconductor laser 1 emits polarized light with a wavelength of 780 nm and a power in the milliwatt range. This beam is processed by the first half-wave plate 3 and the polarizer 11 to output linearly polarized light. The output laser intensity can be adjusted by controlling the first half-wave plate 3. The linearly polarized beam is incident on the acousto-optic modulator AOM 12 to generate Bragg diffraction, separating the zero-order and first-order diffracted beams. The first-order diffracted beam is used as the experimental laser. The first-order diffracted beam is used as the main beam and enters the second half-wave plate 10. The beam splitting ratio of the polarization beam splitter 14 can be adjusted by rotating the second half-wave plate 10. The polarization beam splitter 14 separates the beam into the main beam and the sampling beam. The main beam is used as the laser for the atomic magnetometer. The sampling beam is incident on the second photodetector 15 for laser power sampling.
[0031] This invention relates to a laser frequency and power control system for an atomic magnetometer. The system achieves laser frequency stabilization through saturated absorption and stabilizes laser power, controls amplitude square waves, and controls laser frequency by controlling an acousto-optic modulator, thereby suppressing laser power fluctuations and low-frequency noise interference, significantly improving the detection accuracy of the atomic magnetometer. Furthermore, the driving and control of the acousto-optic modulator are achieved through a DDS (Direct Digital Synthesizer) chip + FPGA (Field-Programmable Gate Array) circuit, which is beneficial for the miniaturization of the atomic magnetometer.
[0032] This invention relates to a laser frequency and power control system for an atomic magnetometer, comprising a laser frequency stabilization control optical path based on a saturable absorption optical path and a laser control circuit based on an acousto-optic modulator (AOM). The saturable absorption optical path includes a rubidium atom gas cell that achieves rubidium atom saturable absorption of the laser. The right side of the rubidium atom gas cell serves as the laser optical path. A semi-transparent mirror splits the laser into transmitted and reflected light. A mixer inputs the obtained signal to a subsequent mixer for mixing, phase detection, and filtering with a reference signal. The control circuit includes an acousto-optic modulator (AOM) connection circuit system. This circuit system is connected to a photodetector and a host computer. The right input optical path of the AOM is connected to a semiconductor laser. The photodetector collects the optical signal through a polarizing beam splitter prism positioned on the left output optical path of the AOM. An FPGA module in the circuit system performs feedback control on the AOM through an AOM driver module containing a DDS module to achieve laser power stabilization and power square wave control. The FPGA module is connected to the photodetector through an analog-to-digital converter (ADC).
[0033] The laser beam emitted from the laser passes through an optical isolator, a half-wave plate, a mirror, a semi-transparent mirror, and a rubidium atom gas cell. After being reflected by the mirror, it passes through the rubidium atom gas cell and the semi-transparent mirror again before finally entering a photodetector for saturation absorption measurement. The signal measured by the photodetector is then input into a mixer for mixing, phase detection, and filtering with a reference signal to obtain the error signal required for laser saturation absorption. This error signal is then stabilized by PI control.
[0034] The DDS module uses the AD9910 chip; the waveform output by the chip is connected to the input of the acousto-optic modulator (AOM) through a low-pass filter circuit and a power amplifier circuit; the FPGA module is configured with a control program to drive the AD9910, which is connected to the input of the digital-to-analog converter (ADC) driver through the output of the PID (Proportion Integration Differentiation) control program and the modulation program to complete the output modulation of the waveform.
[0035] The AD9910 chip is connected to an external clock, and its PLL_LOOP_FILTER pin is connected to an external loop filter circuit. The differential outputs VOUT+ and VOUT- of the chip are connected to the dual-ended inputs of a dual-ended to single-ended converter circuit, and the single-ended output of the converter circuit is connected to the low-pass filter circuit to generate a waveform.
[0036] The FPGA communicates with the AD9910 chip through the SCLK, CS_n, IO_UPDATE, IO_RESET, SDIO, MASTER_RESET, D[15:0], F[1:0], and TxENABLE pins. Among them, MASTER_RESET, SDIO, IO_RESET, IO_UPDATE, CS_n, and SCLK constitute a serial interface, which is used by the FPGA to initialize and configure the AD9910 chip and set the phase and frequency of the output signal. D[15:0], F[1:0], and TxENABLE constitute a parallel interface, which is used by the FPGA to control the amplitude of the output signal of the AD9910 chip. The AD9910 integrates a phase-locked loop (PLL).
[0037] The analog-to-digital converter (ADC) uses an AD7767 chip. This chip is connected to the photodetector via a data acquisition circuit, which is a single-ended to differential circuit. The +2.5V digital and +2.5V analog terminals of the AD7767 chip are connected to the power supply, and its +5V and +3.3V terminals are connected to the reference power supply. The differential input terminals VIN+ and VIN- of the AD7767 are connected to the output of the single-ended to differential circuit, which receives the analog signal from the photodetector and converts the analog signal into a digital signal.
[0038] The AD7767 chip communicates with the FPGA via the SDO, DRDY, CS, MCLK, SCLK, and SYNC pins. SDO is used to transmit digital signals to the FPGA. The CS and SYNC pins are kept low. The MCLK frequency is set to one-eighth of the sampling rate; adjusting the MCLK frequency changes the AD7767's sampling rate. SCLK is the analog-to-digital conversion clock; to avoid timing errors, data is acquired on the SDO pin at the falling edge of SCLK. When a high level of pulsed light is acquired, the FPGA retains the data; when data is acquired at other locations, the FPGA determines and deletes the current data.
[0039] The low-pass filter circuit uses a passive LC low-pass filter with a cutoff frequency of 400MHz.
[0040] The FPGA module includes an AD9910 initialization module, a frequency / phase control module, and an amplitude control module, all three of which are connected to the FPGA master timing controller. The AD9910 initialization module and the frequency / phase control module are connected to the Serial Peripheral Interface (SPI) data port, and the amplitude control module is connected to the parallel data port. The AD9910 chip internally includes an enable and configuration register, a Profile0 register, a DDS core, a DA conversion module, and an ASF amplitude register. The ASF amplitude register is connected to the parallel data port. The enable and configuration register and the Profile0 register are connected to the SPI data port. The ASF amplitude register, Profile0 register, and DA conversion module are connected to the parallel data port. The modules are connected to the DDS core respectively; the DA conversion module is connected to the power amplifier module via a low-pass filter (LPF); the AD9910 driver includes the following steps: Step 1: Start; Step 2: Reset and initialization; Step 3: Enable IO port; Step 4: Send instructions and data to the second control function register (CFR2); Step 5: Send instructions and data to the third control function register (CFR3); Step 6: Send instructions and data to the Profile0 register; Step 7: Reconfigure CFR2, send CFR2 instructions and data; Step 8: End configuration; wherein, steps 4 to 6 adopt serial port configuration mode, and steps 7 to 8 adopt parallel port configuration mode to generate the corresponding sine wave signal.
[0041] Step 4, configuring CFR2, includes setting its value to enable Profile amplitude under single-frequency control; Step 5, configuring CFR3, includes setting its value to generate a 1GHz signal from a 50MHz clock via an internal phase-locked loop (PLL), with a division factor of 20; Step 6, configuring the Profile0 register, includes writing the frequency control word, phase control word, and initial amplitude control word into the buffer; Step 7, reconfiguring CFR2, includes writing the data 0x01400810 to enable its parallel data port, thereby enabling the AD9910 chip to generate a sine wave with a frequency of 80MHz and an amplitude controlled by the parallel port, thus achieving control of the output signal amplitude.
[0042] The semiconductor laser emits polarized light with a wavelength of 780 nm and a power in the milliwatt range. This beam is processed by a first half-wave plate and a polarizer to output linearly polarized light. The output laser intensity can be adjusted by controlling the first half-wave plate. The linearly polarized beam is incident on an acousto-optic modulator to generate Bragg diffraction, separating it into zero-order and first-order diffracted beams. The first-order diffracted beam is used as the experimental laser. The first-order diffracted beam is used as the main beam and enters the second half-wave plate. The beam splitting ratio of the polarizing beam splitter can be adjusted by rotating the second half-wave plate. The polarizing beam splitter separates the beam into a main beam and a sampling beam. The main beam is used as the laser for an atomic magnetometer. The sampling beam is incident on a photodetector for laser power sampling.
[0043] A laser frequency and power control system for a small atomic magnetometer includes a laser frequency stabilization saturated absorption optical path and a laser power control optical path based on an acousto-optic modulator (AOM). The acousto-optic modulator 12 is connected to a circuit system 16, which is connected to a second photodetector 15 and a host computer 17. The left input optical path of the acousto-optic modulator 12 is connected to a semiconductor laser 1. The second photodetector 15 collects optical signals through a polarization beam splitter prism 14 located on the right output optical path of the acousto-optic modulator 12. The FPGA module in the circuit system 16 performs feedback control on the acousto-optic modulator 12 through an AOM driver module containing a DDS module to achieve laser power stabilization and power square wave control. The FPGA module is connected to the second photodetector 15 through an analog-to-digital converter (ADC).
[0044] The DDS module uses an AD9910 DDS chip. This chip is connected to the acousto-optic modulator (AOM) via a low-pass filter circuit and a power amplifier circuit. The FPGA module is configured with an AD9910 driver program, which is connected to the ADC driver program via a PID control program and a DSP program. The AD9910 chip is connected to a clock signal and to a loop filter circuit via the PLL_LOOP_FILTER pin. The differential outputs VOUT+ and VOUT- of the AD9910 chip are connected to a dual-ended to single-ended converter circuit, and the output of this circuit is connected to the low-pass filter circuit. The FPGA communicates with the AD9910 through the SCLK pin, CS_n pin, IO_UPDATE pin, IO_RESET pin, SDIO pin, MASTER_RESET pin, D[15:0] pin, F[1:0] pin, and TxENABLE pin. Among them, the MSATER_RESET, SDIO, IO_RESET, IO_UPDATE, CS_n, and SCLK pins are serial interfaces, which realize the FPGA's initialization configuration of the AD9910 and the setting of the phase and frequency of the output signal. D[15:0], F[1:0], and TxENABLE are parallel interfaces, which realize the FPGA's amplitude control of the AD9910 output signal. The AD9910 integrates a phase-locked loop (PLL).
[0045] The analog-to-digital converter (ADC) module uses an AD7767 ADC chip. The ADC chip is connected to the photodetector through a data acquisition circuit, which is a single-ended to differential circuit. The AD7767 is connected to the power supply via a +2.5V digital terminal and a +2.5V analog terminal, respectively. The AD7767 is connected to the reference power supply via a +5V terminal and a +3.3V terminal, respectively. The AD7767 is connected to the single-ended to differential circuit via a VIN+ terminal and a VIN- terminal, respectively. The single-ended to differential circuit receives the analog signal from the photodetector. The AD7767 chip communicates with the FPGA via the SDO, DRDY, CS, MCLK, SCLK, and SYNC pins. SDO sends digital signals to the FPGA. CS and SYNC are always low. MCLK's frequency is one-eighth of the sampling rate; changing MCLK alters the AD7767's sampling rate. SCLK is the clock for the AD7767's analog-to-digital conversion. To avoid timing errors, the falling edge of SCLK is used to sample the SDO pin. When a high-level pulse light is detected, the FPGA retains the data; otherwise, it determines and deletes the current data. The low-pass filter circuit uses a passive LC low-pass filter with a cutoff frequency of 400MHz.
[0046] The FPGA module includes an AD9910 initialization module, a frequency / phase control module, and an amplitude control module, all connected to the FPGA master timing controller. The AD9910 initialization module and the frequency / phase control module are both connected to the SPI data port, and the amplitude control module is connected to the parallel data port. The AD9910 includes an enable and configuration register, a Profile0 register, a DDS core, a DA conversion module, and an ASF amplitude register. The ASF amplitude register is connected to the parallel data port. The enable and configuration register and the Profile0 register are both connected to the SPI data port. The ASF amplitude register, the Profile0 register, and the DA conversion module... The conversion modules are connected to the DDS core, and the DA conversion module is connected to the power amplifier module through a low-pass filter (LPF). The AD9910 driver configured on the FPGA module includes the following steps: Step 1, Start; Step 2, Reset and Initialization; Step 3, Enable the IO port; Step 4, Send the instruction and data to the second control function register CFR2; Step 5, Send the instruction and data to the third control function register CFR3; Step 6, Send the instruction and data to register Profile0; Step 7, Reconfigure CFR2, and send the CFR2 instruction and data; Step 8, End Configuration; Steps 4 to 6 are serial port configurations, and steps 7 to 8 are parallel port configurations. Step 4, configuring CFR2, includes configuring the CFR2 setting value to enable single-frequency control Profile amplitude; Step 5, configuring CFR3, includes configuring the CFR3 setting value to enable a 50MHz clock to generate a 1GHz signal through a phase-locked loop (PLL) with a frequency division factor of 20; Step 6, configuring register Profile0, includes writing the frequency control word, phase control word, and initialized amplitude control word into the buffer; Step 7, reconfiguring CFR2, includes writing the data 0x01400810 to enable the parallel data port of CFR2, so that the AD9910 can generate a sine wave with a frequency of 80MHz and an amplitude controlled by the parallel port, thus completing the amplitude control of the AD9910 output signal. The semiconductor laser generates polarized light with a wavelength of 780 nm and a power in the milliwatt range. After passing through a first half-wave plate and a polarizer, it outputs linearly polarized light. The intensity of the output laser is adjusted by regulating the first half-wave plate. The linearly polarized light beam enters the acousto-optic modulator and undergoes Bragg diffraction, splitting into two diffracted beams: a zero-order diffracted beam and a first-order diffracted beam. The first-order diffracted beam serves as the main beam and enters the second half-wave plate. Rotating the second half-wave plate changes the splitting ratio of the polarization beam splitter. The polarization beam splitter separates a detection main beam and a sampling beam. The detection main beam serves as the laser for the atomic magnetometer, and the sampling beam enters the photodetector for sampling the laser power.
[0047] like Figure 1 As shown, this invention discloses a laser frequency and power control system for a small atomic magnetometer, comprising a laser frequency-stabilized saturated absorption optical path and a laser control optical path and circuit system based on an AOM (acousto-optic modulator). The optical path includes a semiconductor laser 1, an isolator 2, a half-wave plate 3, a semi-transparent mirror 4, a semi-transparent mirror 5, a rubidium atom gas cell 6, a high-transparency, low-reflection mirror 7, a photodetector 8, a mixer 9, a half-wave plate 10, a polarizer 11, an acousto-optic modulator 12, a half-wave plate 13, a polarizing beam splitter prism 14, and a photodetector 15. The semiconductor laser 1 generates 780nm, milliwatt-level polarized light; the half-wave plate 3 and half-wave plate 10 adjust the intensity of subsequent laser beams; the polarizer 11 adjusts the direction of the linearly polarized light; the acousto-optic modulator 12 generates Bragg diffraction and controls the power of the diffracted laser light; the polarizing beam splitter prism 14 splits the laser beam. Part of the signal is used as a feedback input signal, and another part is used as the input laser signal for the atomic magnetometer; photodetectors 8 and 15 convert the optical signal into an electrical signal; the power supply module in the electronic control unit 16 is used to provide the power supply voltage for the circuit system; the FPGA module is responsible for communicating with the AD (analog-to-digital) module to read the electrical signal of the optical power, and after a series of digital signal processing, it is subtracted from the set value, and the control program is executed to generate the corresponding amplitude control word of AD9910, and communicates with the DDS chip AD9910 in the AOM driver module to change the amplitude of the AD9910 output signal; after low-pass filtering and power amplification, it drives the acousto-optic modulator 12.
[0048] The acquisition module pre-amplifies the electrical signal converted by the photodetector 15; the AD (analog-to-digital converter) module is powered by a reference voltage source with a reference voltage of 5V and a power supply module; the electrical signal acquired and converted by the PD (photodetector) is buffered by a voltage follower and then sent to the AD chip for analog-to-digital conversion; the AOM drive module consists of a DDS chip AD9910, a low-pass filter circuit module, and a power amplifier circuit module; the AD9910 generates a radio frequency signal with a fixed frequency and controllable amplitude, which drives the AOM after low-pass filtering and power amplification.
[0049] The host computer module 17 communicates with the circuit system to adjust the parameters required in the circuit system program and displays the collected signals, facilitating circuit system debugging. The semiconductor laser 1 generates 780nm, milliwatt-level polarized light. After passing through the first half-wave plate 3 and polarizer 11, linearly polarized light is output. The intensity of the output laser can be adjusted by adjusting the first half-wave plate 3. The beam enters the acousto-optic modulator 12 and undergoes Bragg diffraction, splitting into two diffracted beams: a zero-order diffracted beam and a first-order diffracted beam. The first-order diffracted beam, as the main beam, enters the second half-wave plate. Rotating the second half-wave plate changes the splitting ratio of the polarization beam splitter 14, which then splits the beam into two beams. The other beam enters the photodetector 15 for laser power sampling. In the circuit system module 16, the photodetector 15 converts the collected optical signal into an electrical signal. The signal is pre-amplified in the acquisition circuit module, and then enters the AD (analog-to-digital converter) module. The AD module converts the amplified electrical signal into a digital signal and transmits it to the FPGA. After digital signal processing such as digital RC filtering, downsampling and smoothing, the signal is subtracted from the power setting voltage value and then used for control algorithm calculation. The output control signal controls the amplitude of the output signal of the DDS chip AD9910 in the acousto-optic modulator driver module. The FPGA communicates with the AD9910 to control the AD9910 to generate a radio frequency signal. After low-pass filtering and power amplification, the signal controls the acousto-optic modulator (12), thereby stabilizing and controlling the laser power. The parameters are set through the host computer 17 and the acquired optical power signal is displayed to evaluate the stability of the system. To suppress noise or reduce crosstalk, a zero-ohm resistor is used to connect the digital ground and the analog ground.
[0050] Preferably, a DBR type semiconductor laser is used as the laser source; the acousto-optic modulation unit adopts an acousto-optic modulator based on Bragg diffraction. The power supply section consists of a voltage regulator chip and a resistor-capacitor network, outputting analog levels of ±5V, +12V, 2.5V, +3.3V, and +1.8V, and digital levels of +3.3V, +2.5V, +1.2V, +1.5V, and +1.8V. The analog-to-digital converter module uses a 24-bit high-precision ADC with built-in anti-aliasing filtering and a reference provided by a serial reference source. The FPGA core board is a minimal system architecture, integrating chips, clock, reset button, JTAG download port, power management, RS-232 interface, and external storage. In the acousto-optic drive link, the DDS is selected as AD9910, with a 14-bit amplitude resolution; the FPGA controls its output to drive the AOM after passive LC low-pass filtering and broadband power amplification, completing laser power amplitude stabilization and square wave modulation. The filtering stage employs an LC passive low-pass topology. The power amplifier bandwidth must cover the AOM RF range, and the maximum output power must match the AOM requirements. All analog I / O ports use SMA connectors. The host computer and FPGA interact via serial port, and the host computer software is developed based on LabVIEW.
[0051] like Figure 2 As shown, the circuit system in this diagram includes an analog-to-digital converter module, an FPGA control module, an AD9910 DDS chip module, a low-pass filter circuit module, and a power amplifier module. The FPGA program consists of four parts: first, the AD7767 sampling program, which drives the AD7767 and saves the signals acquired by the AD7767 to the FPGA; second, the PID program, which implements closed-loop control of the laser power; third, the modulation program, which mainly implements pulse modulation and sinusoidal modulation of the laser; and fourth, the AD9910 driver program, which implements real-time control of the AD9910.
[0052] like Figure 3 As shown, the AD7767 chip is used in the analog-to-digital conversion stage of this design. The analog signal is first converted from single-ended to differential and then sent to the analog input of the AD7767. The reference is provided by a 5V analog power supply and a 3.3V digital power supply, and the core voltage of the chip is 2.5V. The AD7767 and the FPGA communicate via 7 wires: after a conversion is completed, DRDY outputs a low pulse to notify the FPGA; then the data is serially shifted into the FPGA via SDO. CS and SYNC are always pulled low. MCLK is set to 1 / 8 of the sampling rate, and the sampling rate can be adjusted by adjusting MCLK. SCLK is the conversion clock. To avoid timing conflicts, the FPGA latches SDO on the falling edge of SCLK. Since the light under test is in pulse form, in order to ensure that only the stable high level at the top of the pulse is retained, the system adopts an undersampling strategy, making the sampling rate much lower than the pulse control frequency; the FPGA determines whether the current sampling point is in the high-level region of the pulse, and data in the non-target region is discarded.
[0053] Figure 4 The diagram shows the overall architecture of the acousto-optic modulator driver module: the FPGA enables the AD9910 and configures its registers via a serial interface, and sets the output frequency, phase, and amplitude; the parallel interface is used to adjust the signal amplitude; the resulting signal is low-pass filtered and amplified before being sent to the acousto-optic modulator driver.
[0054] Figure 5 The diagram shows the DDS circuit of the AD9910 in the acousto-optic modulator driver module: a 50MHz FPGA clock is used as the external clock; the chip's internal PLL is used, so a loop filter needs to be placed on pin 2 (PLL_LOOP_FILTER); the differential output is converted from dual to single network to suppress common-mode noise. Communication between the FPGA and AD9910 is accomplished through two channels: the serial data port (MASTER_RESET, SDIO, IO_RESET, IO_UPDATE, CS_n, SCLK) is used for initialization and frequency and phase setting; the parallel data port (D, F, TxENABLE) is used for amplitude control.
[0055] like Figure 6As shown in the figure, this diagram represents the low-pass filter circuit in the acousto-optic modulator driver module. This invention employs a passive LC low-pass filter with a cutoff frequency of 400MHz.
[0056] Figure 7 The flowchart shown is a sequence diagram for configuring the AD9910 on the FPGA. The first step is to perform a reset and enable the IO port; the second step is to write the register: first set CFR2 to enable the Profile amplitude by setting the 24th bit; then set CFR3: CFR3[29:28] is set to 01 to make REFCLK_OUT low current; CFR3[26:24] is set to 101 to lock VCO5 (820–1150MHz) to support 1GHz; CFR3[21:19] is set to 111 to get a 387μA charge pump; CFR3[8] is set to 1 to start the PLL; CFR3[7:1] is set to 20 to multiply the 50MHz clock to 1GHz. The third step is to write the frequency word, phase word, and amplitude word into the Profile0 buffer; the fifth step is to enter parallel mode to dynamically control the amplitude. Therefore, CFR2 = 0x01400810 is rewritten first, and only CFR2[4] is set to 1 to open the parallel port. Then AD9910 outputs an 80MHz sine wave, the amplitude of which is adjusted in real time by the parallel bus.
[0057] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.
Claims
1. A laser frequency and power control system for an atomic magnetometer, characterized in that, The system includes a laser frequency stabilization control optical path based on a saturable absorption optical path and a laser power control circuit based on an acousto-optic modulator (AOM). The laser power control circuit includes circuit systems connected to the AOM, a second photodetector, and a host computer. The output side of the AOM is connected to the input side of a polarizing beam splitter via a third half-wave plate. The input side of the AOM sequentially connects to a polarizer, a second half-wave plate, a first semi-transparent mirror, another half-wave plate, an isolator, and a semiconductor laser. The reflecting side of the polarizing beam splitter is connected to the second photodetector to generate a feedback input signal. The polarization beam splitter outputs the incident laser signal for the atomic magnetometer from its transmission side. The circuit system drives the AOM to control the laser power according to the feedback input signal. The laser frequency stabilization control optical path includes a second semi-transparent mirror connected to the reflection side of the first semi-transparent mirror from its input side. The reflection side of the second semi-transparent mirror is connected to a high-transmission, low-reflection mirror through a rubidium atom gas cell. The transmission side of the second semi-transparent mirror is connected to the semiconductor laser in sequence through a first photodetector and a mixer. The rubidium atom gas cell achieves rubidium atom saturation absorption of the laser.
2. The laser frequency and power control system for an atomic magnetometer according to claim 1, characterized in that, The circuit system includes an analog-to-digital converter (ADC) whose input is connected to the second photodetector. The output of the ADC is connected to an FPGA chip. The FPGA chip is connected to a power amplifier circuit via an AD9910 chip and a low-pass filter circuit. The power amplifier circuit outputs control signals to the AOM. The FPGA chip is equipped with an ADC driver and an AD9910 driver. The ADC driver is connected to the AD9910 driver via a PID control program and a modulation program.
3. The laser frequency and power control system for an atomic magnetometer according to claim 2, characterized in that, The ADC uses an AD7767 chip. The AD7767 chip and the FPGA chip have the following corresponding pin connections: CS pin, MCLK pin, SCLK pin, SYNC pin, DRDY pin, and SDO pin. The second photodetector is connected to one end of a single-ended to differential circuit. The dual outputs of the single-ended to differential circuit are respectively connected to the positive input voltage terminal VIN+ and the negative input voltage terminal VIN- of the AD7767 chip.
4. The laser frequency and power control system for an atomic magnetometer according to claim 2, characterized in that, The AD9910 chip includes an enable and configuration register, a Profile0 register, a phase-locked loop (PLL), a DA conversion module, and an ASF amplitude register. The ASF amplitude register is connected to the FPGA module through a parallel data port. The enable and configuration register and the Profile0 register are both connected to the FPGA module through an SPI data port. The ASF amplitude register, the Profile0 register, and the DA conversion module are respectively connected to the DDS core. The DA conversion module is connected to the power amplifier circuit through a low-pass filter circuit.
5. The laser frequency and power control system for an atomic magnetometer according to claim 2, characterized in that, The AD9910 chip is connected to an external crystal oscillator, a two-ended to one-ended converter circuit, and a loop filter circuit. The external crystal oscillator provides an external clock to the AD9910. The single-ended output signal of the two-ended to one-ended converter circuit is output to the low-pass filter circuit. The AD9910 chip has the following corresponding pins connected to the FPGA module: D pin, F pin, TxENABLE pin, SCLK pin, CS_n pin, SDIO pin, IO_UPDATE pin, IO_RESET pin, and MASTER_RESET pin.
6. The laser frequency and power control system for an atomic magnetometer according to claim 2, characterized in that, The low-pass filter circuit employs a passive LC low-pass filter, comprising an input terminal, a first intermediate node, a second intermediate node, and an output terminal arranged sequentially. The input terminal is connected to one end of a resistor, one end of a 71st capacitor, one end of a 75th capacitor, and one end of a 15th inductor. The other end of the 15th inductor is connected to the first intermediate node. The first intermediate node is connected to one end of a 72nd capacitor, one end of a 76th capacitor, and one end of a 16th inductor. The other end of the 16th inductor is connected to the second intermediate node. The second intermediate node is connected to one end of a 73rd capacitor, one end of a 77th capacitor, and one end of a 17th inductor. The other end of the 17th inductor is connected to the output terminal. The output terminal is connected to one end of a 74th capacitor and one end of a 78th capacitor. The other ends of the resistor, the 71st capacitor, the 75th capacitor, the 72nd capacitor, the 76th capacitor, the 73rd capacitor, the 77th capacitor, the 74th capacitor, and the 78th capacitor are all connected to ground.
7. The laser frequency and power control system for an atomic magnetometer according to claim 2, characterized in that, The process of configuring the AD9910 driver for the FPGA chip includes the following steps: Step 1, Start; Step 2, Reset and Initialization; Step 3, Enable I / O Port; Step 4, Configure Serial Port; Step 5, Configure Parallel Port; Step 6, End Configuration; Step 4 includes Step 41, Sending Instructions and Data to the Second Control Function Register CFR2; Step 42, Sending Instructions and Data to the Third Control Function Register CFR3; Step 43, Sending Instructions and Data to Register Profile0; Step 5 includes reconfiguring CFR2 by sending CFR2 instructions and data.
8. The laser frequency and power control system for an atomic magnetometer according to claim 1, characterized in that, The semiconductor laser emits polarized light with a wavelength of 780 nm and a power in the milliwatt range. This beam is processed by a first half-wave plate and a polarizer to output linearly polarized light. The output laser intensity can be adjusted by controlling the first half-wave plate. The linearly polarized beam is incident on an acousto-optic modulator to generate Bragg diffraction, separating it into zero-order and first-order diffracted beams. The first-order diffracted beam is used as the experimental laser. The first-order diffracted beam is used as the main beam and enters the second half-wave plate. The beam splitting ratio of the polarizing beam splitter can be adjusted by rotating the second half-wave plate. The polarizing beam splitter separates the beam into a main beam and a sampling beam. The main beam is used as the laser for an atomic magnetometer. The sampling beam is incident on a second photodetector for laser power sampling.