Three-level power module

Abstract

The invention discloses a three-level power module which comprises a three-level power circuit, a positive electrode leading-out endpoint of a positive electrode layer of the three-level power circuit is arranged close to a first high-voltage outer side chip, a first midpoint electrode leading-out endpoint of a first midpoint potential electrode layer is arranged close to a first midpoint clamping chip, and a second midpoint electrode leading-out endpoint of a second midpoint potential electrode layer is arranged close to a second high-voltage outer side chip. A second midpoint electrode leading-out endpoint of the second midpoint potential electrode layer is arranged close to the second midpoint clamping chip, a negative electrode leading-out endpoint of the negative electrode layer is arranged close to the second high-voltage outer-side chip, and the upper bridge arm inner-side chip and the lower bridge arm inner-side chip are located in the center area of the substrate in the first direction. The second midpoint clamping chip and the first midpoint clamping chip are respectively located at the peripheral areas of the two sides of the substrate, and the second midpoint clamping chip, the first high-voltage outer side chip, the upper bridge arm inner side chip, the lower bridge arm inner side chip, the second high-voltage outer side chip and the first midpoint clamping chip in the three-level power circuit are arranged in sequence.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a three-level power module. Background Technology

[0002] With the rapid development of modern transportation, aerospace and other fields, power electronic power modules (hereinafter referred to as power modules) have been widely used. This has also placed higher demands on the performance of power modules.

[0003] To improve the efficiency of power modules, higher switching frequencies are required. However, traditional power module layouts have high parasitic inductance, causing the power chip to withstand higher overvoltages during switching, increasing the risk of overvoltage breakdown. Therefore, in high-frequency, high-power applications, parasitic inductance is a challenge that power modules need to overcome, and its reduction is necessary to ensure reliable operation.

[0004] Traditional three-level power modules have a large commutation circuit area and high parasitic inductance, which increases the risk of overvoltage breakdown of the power chip. Summary of the Invention

[0005] This application provides a three-level power module to reduce parasitic inductance and improve switching performance.

[0006] To address the aforementioned technical problems, this application proposes a three-level power module. The three-level power module includes: a substrate; and a three-level power circuit disposed on the substrate. The three-level power circuit includes: a first high-voltage outer chip, an upper bridge arm inner chip, a lower bridge arm inner chip, a second high-voltage outer chip, a first midpoint clamping chip, a second midpoint clamping chip, a positive electrode layer, an AC side electrode layer, a second midpoint potential electrode layer, a first midpoint potential electrode layer, a negative electrode layer, a first midpoint clamping electrode layer, and a second midpoint clamping electrode layer. The positive electrode lead-out terminal of the positive electrode layer is disposed near the first high-voltage outer chip, and the first midpoint electrode lead-out terminal of the first midpoint potential electrode layer is disposed near the first midpoint clamping chip. The second midpoint electrode lead-out terminal of the second midpoint potential electrode layer is located near the second midpoint clamping chip, and the negative electrode lead-out terminal of the negative electrode layer is located near the second high voltage outer chip. Along the first direction, the inner chip of the upper bridge arm and the inner chip of the lower bridge arm are located in the central region of the substrate, and the second midpoint clamping chip and the first midpoint clamping chip are located in the peripheral regions on both sides of the substrate, respectively. The second midpoint clamping chip, the first high voltage outer chip, the inner chip of the upper bridge arm, the inner chip of the lower bridge arm, the second high voltage outer chip, and the first midpoint clamping chip in the three-level power circuit are arranged in sequence.

[0007] Unlike existing technologies, the positive electrode lead-out point of the positive electrode layer of the three-level power circuit in this application is located near the first high-voltage outer chip, the first midpoint electrode lead-out point of the first midpoint potential electrode layer is located near the first midpoint clamping chip, the second midpoint electrode lead-out point of the second midpoint potential electrode layer is located near the second midpoint clamping chip, and the negative electrode lead-out point of the negative electrode layer is located near the second high-voltage outer chip. Furthermore, along the first direction, the inner chips of the upper and lower bridge arms are located in the central region of the substrate, while the second and first midpoint clamping chips are located in the peripheral regions on both sides of the substrate. The second midpoint clamping chip, the first high-voltage outer chip, the inner chip of the upper and lower bridge arms, the second high-voltage outer chip, and the first midpoint clamping chip are arranged sequentially. This structure allows for a compact layout, reduces the commutation loop area, thereby reducing the parasitic inductance of the three-level power module, further reducing switching losses and voltage spikes during switching, improving the switching performance of the power module, and lowering the risk of breakdown of the power chips in the three-level power module. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0009] Figure 1 This is a schematic diagram of the structure of an embodiment of the three-level power module of this application;

[0010] Figure 2 This is a schematic diagram of an embodiment of the three-level power circuit and its first commutation loop in the three-level power module of this application;

[0011] Figure 3 This is a schematic diagram of an embodiment of the three-level power circuit and its second commutation loop in the three-level power module of this application;

[0012] Figure 4 This is a schematic diagram of another embodiment of the three-level power module of this application;

[0013] Figure 5 This is a schematic diagram of another embodiment of the three-level power module of this application;

[0014] Figure 6 This is a schematic diagram of the structure of a substrate in an embodiment of the three-level power module of this application;

[0015] Figure 7 This is a schematic diagram of another embodiment of the three-level power module of this application;

[0016] Figure 8 This is a schematic diagram of the structure of an embodiment of the first heat sink in the three-level power module of this application;

[0017] Figure 9 This is a schematic diagram of another embodiment of the first heat sink in the three-level power module of this application;

[0018] Figure 10 This is a schematic diagram of another embodiment of the first heat sink in the three-level power module of this application;

[0019] Figure 11 This is a schematic diagram of another embodiment of the first heat sink in the three-level power module of this application. Detailed Implementation

[0020] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0021] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0022] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0023] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0024] This application first proposes a three-level power module, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a three-level power module according to an embodiment of this application. The three-level power module of this embodiment includes: a substrate 1 and a three-level power circuit (not shown in the figure); the three-level power circuit is disposed on the substrate 1 and includes: a first high-voltage outer chip 15, an upper bridge arm inner chip 17, a lower bridge arm inner chip 18, a second high-voltage outer chip 19, a first midpoint clamping chip 21, a second midpoint clamping chip 23, a positive electrode layer 2, an AC side electrode layer 4, a second midpoint potential electrode layer 6, a first midpoint potential electrode layer 7, a negative electrode layer 8, a first midpoint clamping electrode layer 3, and a second midpoint clamping electrode layer 5; wherein, the positive electrode lead-out terminal A of the positive electrode layer 2 is disposed close to the first high-voltage outer chip 15, and the first midpoint potential electrode layer... The first midpoint electrode lead-out terminal B of the 7 is located near the first midpoint clamping chip 21, the second midpoint electrode lead-out terminal C of the second midpoint potential electrode layer 6 is located near the second midpoint clamping chip 23, the negative electrode lead-out terminal D of the negative electrode layer 8 is located near the second high voltage outer chip 19, the upper bridge arm inner chip 17 and the lower bridge arm inner chip 18 are located in the central region of the substrate 1, the second midpoint clamping chip 23 and the first midpoint clamping chip 21 are located in the peripheral regions on both sides of the substrate 1, and along the first direction x, the second midpoint clamping chip 23, the first high voltage outer chip 15, the upper bridge arm inner chip 17, the lower bridge arm inner chip 18, the second high voltage outer chip 19 and the first midpoint clamping chip 21 in the three-level power circuit 220 are arranged in sequence.

[0025] like Figure 1 and Figure 2 As shown, the first commutation loop of the three-level power circuit is: positive electrode layer 2 → first high voltage outer chip 15 → first midpoint clamping electrode layer 3 → upper bridge arm inner chip 17 → AC side electrode layer 4 → lower bridge arm inner chip 18 → second midpoint clamping electrode layer 5 → second midpoint clamping chip 23 → second midpoint potential electrode layer 6.

[0026] like Figure 1 and Figure 3 As shown, the second commutation loop of the three-level power circuit is as follows: first midpoint potential electrode layer 7 → first midpoint clamping chip 21 → first midpoint clamping electrode layer 3 → upper bridge arm inner chip 17 → AC side electrode layer 4 → lower bridge arm inner chip 18 → second midpoint clamping electrode layer 5 → second high voltage outer chip 19 → negative electrode layer 8.

[0027] The layout described in this embodiment enables a compact layout, reduces the commutation loop area, thereby reducing the parasitic inductance of the three-level power module, which in turn reduces switching losses and voltage spikes during switching, and improves the switching performance of the three-level power module.

[0028] In some embodiments, the three-level power module includes at least one set of three-level power circuits, each set of three-level power circuits including two three-level power circuits, which are spaced apart on both sides of the substrate 1 along the second direction y; wherein, for each set of three-level power circuits, the AC lead-out terminal E of the AC side electrode layer 4 is located on the vertical line connecting the two lower bridge arm inner chips 18; the positive electrode lead-out terminal A is located on the vertical line connecting the two first high voltage outer chips 15; the negative electrode lead-out terminal D is located on the vertical line connecting the two second high voltage outer chips 19; the first midpoint electrode lead-out terminal B is located on the vertical line between the two first midpoint clamping chips 21; and the second midpoint electrode lead-out terminal C is located on the vertical line between the two second midpoint clamping chips 23; wherein, the second direction y is perpendicular to the first direction x.

[0029] In this embodiment, the AC lead-out terminal E of the AC side electrode layer 4 is positioned on the vertical line connecting the two lower bridge arm inner chips 18. This ensures that the two lower bridge arm inner chips 18 are symmetrical with respect to the AC lead-out terminal E, reducing the difference in commutation loop area between the two upper bridge arm inner chips 17 and the two adjacent lower bridge arm inner chips 18, thereby maintaining consistent operating conditions and lifespan for each power chip (upper and lower bridge arm chips). Similarly, in this embodiment, the positive electrode lead-out terminal A is positioned on the vertical line connecting the two first high-voltage outer chips 15. This ensures that the two first high-voltage outer chips 15 are symmetrical with respect to the positive electrode lead-out terminal A, reducing the difference in commutation loop area between the two first high-voltage outer chips 15, thereby maintaining consistent operating conditions and lifespan for each first high-voltage outer chip 15. Finally, in this embodiment, the negative electrode lead-out terminal D is positioned on the vertical line connecting the two second high-voltage outer chips 19. This ensures that the two second high-voltage outer chips 19 are symmetrical with respect to the AC lead-out terminal E. The symmetrical negative electrode lead-out terminal D reduces the difference in commutation circuit area between the two second high-voltage outer chips 19, thereby ensuring consistent operating conditions and lifespan for each first midpoint clamping chip 21. In this embodiment, the first midpoint electrode lead-out terminal B is positioned on the vertical line between the two first midpoint clamping chips 21, making them symmetrical with respect to the lead-out terminal B. This reduces the difference in commutation circuit area between the two first midpoint clamping chips 21, ensuring consistent operating conditions and lifespan for each first midpoint clamping chip 21. Similarly, the symmetrical second midpoint electrode lead-out terminal C is positioned on the vertical line between the two second midpoint clamping chips 23, making them symmetrical with respect to the lead-out terminal C. This reduces the difference in commutation circuit area between the two second midpoint clamping chips 23, ensuring consistent operating conditions and lifespan for each second midpoint clamping chip 23. Therefore, the above structure improves the switching performance of the three-level power module.

[0030] In some embodiments, such as Figure 1As shown, in each group of three-level power circuits, two three-level power circuits are symmetrically arranged along the second direction y, and the AC lead-out terminal E, positive electrode lead-out terminal A, negative electrode lead-out terminal D, first midpoint electrode lead-out terminal B, and second midpoint electrode lead-out terminal C are all located on the corresponding axis of symmetry. In this way, the symmetry of the above structure can be further improved, and the differences in commutation loop areas between the two first high-voltage outer chips 15, the two second high-voltage outer chips 19, the two first midpoint clamping chips 21, the two second midpoint clamping chips 23, the two upper bridge arm inner chips 17, and the two lower bridge arm inner chips 18 in each group of three-level power circuits can be further reduced, thereby further improving the switching performance of the three-level power module.

[0031] In some embodiments, such as Figure 1 As shown, in each group of three-level power circuits, the two three-level power circuits share the same AC output terminal E, the same positive electrode output terminal A, the same negative electrode output terminal D, the same first midpoint electrode output terminal B, and the same second midpoint electrode output terminal C. In this way, the two three-level power circuits are connected in parallel, which increases the output power or output voltage and reduces the structural differences between the two three-level power circuits and the differences in commutation loop area between the power chips.

[0032] This embodiment can reduce the length of the first and second converter circuits, making the layout more compact and reducing the converter circuit area. This reduces the parasitic inductance of the three-level power module, thereby reducing switching losses and voltage spikes during switching and improving the switching performance of the power module.

[0033] In some embodiments, each group of three-level power circuits is symmetrically distributed on both sides of the substrate 1, forming two symmetrical commutation paths with the corresponding electrode layers. This ensures that the operating conditions and lifespan of each power chip remain consistent, improves the dynamic current sharing of parallel chips, and enhances the switching performance of the power module.

[0034] In some embodiments, the three-level power module may include two or more sets of the above-described three-level power circuits, all of which may adopt the above structure. Different sets of three-level power circuits may share the corresponding electrode layer and electrode lead-out terminals, so that multiple three-level power circuits located on one side of the substrate can be arranged in parallel, which can improve the output power, simplify the structure, and improve the symmetry of the commutation path.

[0035] This application utilizes a symmetrical layout of multiple parallel chips divided into two groups to form two highly symmetrical commutation circuits, reducing the parasitic inductance differences between the circuits of each chip and improving the current sharing effect of the parallel chips.

[0036] In some embodiments, such as Figures 1 to 3 As shown, the three-level power circuit further includes: a first high-voltage outer driving metal layer 9, an upper bridge arm inner driving metal layer 10, a lower bridge arm inner driving metal layer 11, a second high-voltage outer driving metal layer 12, a first midpoint clamping driving metal layer 13, and a second midpoint clamping driving metal layer 14; the first high-voltage outer driving metal layer 9 is electrically connected to the control terminal of the first high-voltage outer chip 15, the first midpoint clamping electrode layer 3 is electrically connected to one switch terminal of the first high-voltage outer chip 15, and the positive electrode layer 2 is connected to the other switch terminal of the first high-voltage outer chip 15; the upper bridge arm inner driving metal layer 10 is electrically connected to the control terminal of the upper bridge arm inner chip 17, the AC side electrode layer 4 is electrically connected to one switch terminal of the upper bridge arm inner chip 17, and the first midpoint clamping electrode layer 3 is electrically connected to the other switch terminal of the upper bridge arm inner chip 17; the lower bridge arm inner driving metal layer 11 is electrically connected to the control terminal of the lower bridge arm inner chip 18, and the second midpoint clamping electrode layer 5 is electrically connected to the lower bridge arm inner chip 18. One switch terminal of the side chip 18 is electrically connected, and the AC side electrode layer 4 is electrically connected to the other switch terminal of the inner side chip 18 of the lower bridge arm; the second high voltage outer drive metal layer 12 is electrically connected to the control terminal of the second high voltage outer chip 19, the negative electrode layer 8 is electrically connected to one switch terminal of the second high voltage outer chip 19, and the second midpoint clamping electrode layer 5 is connected to the other switch terminal of the second high voltage outer chip 19; the first midpoint clamping drive metal layer 13 is electrically connected to the control terminal of the first midpoint clamping chip 21, the first midpoint potential electrode layer 7 is electrically connected to one switch terminal of the first midpoint clamping chip 21, and the first midpoint clamping electrode layer 3 is connected to the other switch terminal of the first midpoint clamping chip 21; the second midpoint clamping drive metal layer 14 is electrically connected to the control terminal of the second midpoint clamping chip 23, the second midpoint clamping electrode layer 5 is electrically connected to one switch terminal of the second midpoint clamping chip 23, and the second midpoint potential electrode layer 6 is connected to the other switch terminal of the second midpoint clamping chip 23.

[0037] In one application scenario, the inner chip 17 of the upper bridge arm and the inner chip 18 of the lower bridge arm in this embodiment may include IGBTs, etc., and the specific circuit structure is as follows: Figure 2 and Figure 3 As shown. In other embodiments, other switching transistors, such as transistors or MOSFETs, can be used instead of the IGBTs described above.

[0038] In one application scenario, the first high-voltage outer chip 15, the second high-voltage outer chip 19, the first midpoint clamping chip 21, and the second midpoint clamping chip 23 in this embodiment can be MOSFETs, etc., and the specific circuit structure is as follows: Figure 2 and Figure 3 As shown. In other embodiments, other switching transistors, such as transistors or IGBTs, can be used instead of the MOSFETs described above.

[0039] In some embodiments, such as Figure 1 As shown, the first high-voltage outer driving metal layer 9, the upper bridge arm inner driving metal layer 10, the lower bridge arm inner driving metal layer 11, the second high-voltage outer driving metal layer 12, the first midpoint clamping driving metal layer 13, the second midpoint clamping driving metal layer 14, the first midpoint clamping electrode layer 3, the second midpoint clamping electrode layer 5, the positive electrode layer 2, the AC side electrode layer 4, the second midpoint potential electrode layer 6, the first midpoint potential electrode layer 7, and the negative electrode layer 8 are disposed on the substrate 1 in the same layer. In this embodiment, the co-location of these multiple electrode layers facilitates the connection between each electrode layer and the corresponding power chip, and also facilitates the distribution and heat dissipation of the power chips.

[0040] In some embodiments, such as Figure 1 As shown, the first midpoint clamping electrode layer 3 includes a first sub-electrode layer 3a, a second sub-electrode layer 3b, and a third sub-electrode layer 3c arranged and electrically connected along the first direction x; the second midpoint clamping electrode layer 5 includes a fourth sub-electrode layer 5a, a fifth sub-electrode layer 5b, and a sixth sub-electrode layer 5c arranged and electrically connected along the first direction x; wherein, the second midpoint clamping chip 23 is disposed on the side of the second midpoint potential electrode layer 6 away from the substrate 1, the first high voltage outer chip 15 is disposed on the side of the positive electrode layer 2 away from the substrate 1, the upper bridge arm inner chip 17 is disposed on the side of the second sub-electrode layer 3b away from the substrate 1, the lower bridge arm inner chip 18 is disposed on the side of the AC side electrode layer 4 away from the substrate 1, and the second high voltage outer chip 19 is disposed on the sixth sub-electrode layer 5c away from the substrate 1. On one side, the first midpoint clamping chip 21 is disposed on the side of the third sub-electrode layer 3c away from the substrate 1; along the first direction x, the second midpoint potential electrode layer 6, the fifth sub-electrode layer 5b, the positive electrode layer 2, the first sub-electrode layer 3a, the second sub-electrode layer 3b, the sixth sub-electrode layer 5c, the negative electrode layer 8, the first midpoint potential electrode layer 7, and the third sub-electrode layer 3c are arranged in sequence; along the second direction y, the second midpoint clamping driving metal layer 14 is located between adjacent second midpoint potential electrode layers 6, the second high voltage outer driving metal layer 12 is located between adjacent second high voltage outer chips 19, the first midpoint clamping driving metal layer 13 is located between adjacent first midpoint potential electrode layers 7, and the first high voltage outer driving metal layer 9 is located between adjacent first high voltage outer chips 15.

[0041] This embodiment can reduce the length of the commutation loop from positive electrode layer 2 → first high voltage outer chip 15 → first midpoint clamping electrode layer 3 → upper bridge arm inner chip 17 → AC side electrode layer 4 → lower bridge arm inner chip 18 → second midpoint clamping electrode layer 5 → second midpoint clamping chip 23 → second midpoint potential electrode layer 6; and this embodiment can also reduce the length of the commutation loop from first midpoint potential electrode layer 7 → first midpoint clamping chip 21 → first midpoint clamping electrode layer 3 → upper bridge arm inner chip 17 → AC side electrode layer 4 → lower bridge arm inner chip 18 → second midpoint clamping electrode layer 5 → second high voltage outer chip 19 → negative electrode layer 8, which can make the layout more compact and reduce the commutation loop area.

[0042] In this embodiment, the first high-voltage outer chip 15 and the positive electrode layer 2 are stacked, which not only reduces the area of ​​the substrate 1, but also shortens the connection path between the first high-voltage outer chip 15 and the positive electrode layer 2, further reducing the area of ​​the converter circuit.

[0043] In this embodiment, the second midpoint clamping chip 23 and the second midpoint potential electrode layer 6 are stacked, which not only reduces the area of ​​the substrate 1, but also shortens the connection path between the second midpoint clamping chip 23 and the second midpoint potential electrode layer 6, further reducing the commutation loop area.

[0044] In this embodiment, the inner chip 17 of the upper bridge arm and the second sub-electrode layer 3b are stacked, which not only reduces the area of ​​the substrate 1, but also shortens the connection path between the inner chip 17 of the upper bridge arm and the second sub-electrode layer 3b, further reducing the area of ​​the commutation loop.

[0045] In this embodiment, the inner chip 18 of the lower bridge arm and the AC side electrode layer 4 are stacked, which not only reduces the area of ​​the substrate 1, but also shortens the connection path between the inner chip 18 of the lower bridge arm and the AC side electrode layer 4, further reducing the area of ​​the commutation loop.

[0046] In this embodiment, the second high-voltage outer chip 19 and the sixth sub-electrode layer 5c are stacked, which not only reduces the area of ​​the substrate 1, but also shortens the connection path between the second high-voltage outer chip 19 and the sixth sub-electrode layer 5c, further reducing the area of ​​the converter circuit.

[0047] In this embodiment, the first midpoint clamping chip 21 and the third sub-electrode layer 3c are stacked, which not only reduces the area of ​​the substrate 1, but also shortens the connection path between the first midpoint clamping chip 21 and the third sub-electrode layer 3c, further reducing the commutation loop area.

[0048] The second midpoint clamping driving metal layer 14, the second midpoint potential electrode layer 6, the positive electrode layer 2, the first high voltage outer driving metal layer 9, the upper bridge arm inner driving metal layer 10, the lower bridge arm inner driving metal layer 11, the AC side electrode layer 4, the second high voltage outer driving metal layer 12, the negative electrode layer 8, the first midpoint potential electrode layer 7, and the first midpoint clamping driving metal layer 13 are arranged adjacent to each other along the first direction x of the substrate 1, so that the first midpoint clamping electrode layer 7 and the second midpoint clamping electrode layer 14 are located in the outer region of the substrate 1. This facilitates the placement of the second midpoint clamping chip 23 and the first midpoint clamping chip 21 in the peripheral regions on both sides of the substrate 1, shortening the connection path and reducing the commutation loop area.

[0049] In some embodiments, such as Figures 1 to 3 As shown, the three-level power circuit also includes: a first high-voltage outer diode 16, a second high-voltage outer diode 20, a first midpoint clamping diode 22, and a second midpoint clamping diode 24; the first midpoint clamping electrode layer 3 is electrically connected to one switching terminal of the first high-voltage outer diode 16, and the positive electrode layer 2 is connected to the other switching terminal of the first high-voltage outer diode 16; the negative electrode layer 8 is electrically connected to one switching terminal of the first high-voltage outer diode 20, and the second midpoint clamping electrode layer 5 is connected to the other switching terminal of the second high-voltage outer diode 20; the first midpoint potential electrode layer 7 is electrically connected to one switching terminal of the first midpoint clamping diode 22, and the first midpoint clamping electrode layer 3 is connected to the first midpoint clamping diode 24. The other switch terminal of 2 is connected; the second midpoint clamping electrode layer 5 is electrically connected to one switch terminal of the second midpoint clamping diode 24, and the second midpoint potential electrode layer 6 is connected to the other switch terminal of the second midpoint clamping diode 24; wherein, the first high voltage outer chip 15 is positioned relative to the first high voltage outer diode 16 near the positive electrode lead-out terminal A; the second midpoint clamping chip 23 is positioned relative to the second midpoint clamping diode 24 near the second midpoint electrode lead-out terminal C; the second high voltage outer chip 19 is positioned relative to the second high voltage outer diode 20 near the negative electrode lead-out terminal D; and the first midpoint clamping chip 21 is positioned relative to the first midpoint clamping diode 22 near the first midpoint electrode lead-out terminal B.

[0050] Specifically, the sixth sub-electrode layer 5c is connected to another switch terminal of the second high-voltage outer diode 20, the first sub-electrode layer 3a is electrically connected to one switch terminal of the first high-voltage outer diode 16, the third sub-electrode layer 3c is connected to another switch terminal of the first midpoint clamping diode 22, and the fifth sub-electrode layer 5b is electrically connected to one switch terminal of the second midpoint clamping diode 24.

[0051] In this embodiment, the diode is used to protect the corresponding power chip (i.e., each of the chips) when there is a sudden change in voltage or current.

[0052] In some embodiments, the three-level power circuit 220 further includes: an upper bridge arm diode 271 and a lower bridge arm diode 281, a first midpoint clamping electrode layer 3 electrically connected to one switching terminal of the upper bridge arm diode 271, and a negative electrode layer 8 connected to the other switching terminal of the upper bridge arm diode 271; a second midpoint clamping electrode layer 5 electrically connected to one switching terminal of the lower bridge arm diode 281, and a positive electrode layer 2 connected to the other switching terminal of the lower bridge arm diode 281.

[0053] Specifically, the second sub-electrode layer 3b is electrically connected to a switching terminal of the upper bridge arm diode 271, and the fourth sub-electrode layer 5a is electrically connected to a switching terminal of the lower bridge arm diode 281.

[0054] In this embodiment, the diode is used to protect the corresponding bridge arm chip when there is a sudden change in voltage or current.

[0055] In some embodiments, the first high-voltage outer chip 15, the upper bridge arm inner chip 17, the lower bridge arm inner chip 18, the second high-voltage outer chip 19, the first midpoint clamping chip 21, and the second midpoint clamping chip 23 can adopt a Kelvin connection method, which reduces the common source inductance, decouples the drive circuit and the power circuit, and reduces the electromagnetic interference of the power circuit to the drive circuit.

[0056] The aforementioned sub-electrode layers can also be connected using the Kelvin connection method.

[0057] In some embodiments, the above connection can also be achieved using other bonding methods or connecting pieces.

[0058] In some embodiments, such as Figure 4 As shown, the three-level power module further includes: a first terminal 29, a second terminal 25, a third terminal 28, a fourth terminal 27, and a fifth terminal 26; one end of the first terminal 29 is connected to the AC lead-out terminal E, and the other end extends outward from the substrate 1; one end of the second terminal 25 is connected to the positive electrode lead-out terminal A, and the other end extends outward from the substrate 1; one end of the third terminal 28 is connected to the negative electrode lead-out terminal D, and the other end extends outward from the substrate 1; one end of the fourth terminal 27 is electrically connected to the second midpoint potential lead-out terminal C, and the other end extends outward from the substrate 1; one end of the fifth terminal 26 is connected to the first midpoint potential lead-out terminal B, and the other end extends outward from the substrate 1. These terminals facilitate the connection of each lead-out terminal to external devices.

[0059] In some embodiments, the first terminal 29, the second terminal 25, the third terminal 28, the fourth terminal 27, and the fifth terminal 26 are all led out from a plane parallel to or perpendicular to the substrate 1 to facilitate the connection of the three-level power module with external devices.

[0060] In some embodiments, such as Figure 4 As shown, the second terminal 25, the third terminal 28, the fourth terminal 27, and the fifth terminal 26 extend from opposite sides of the first terminal 29 on the substrate 1, which reduces mutual interference and improves the reliability of the three-level power module. It also provides sufficient space on the sides of the substrate 1 for the terminal components and facilitates packaging.

[0061] The aforementioned terminal components can be metal sheets, which can further reduce parasitic inductance.

[0062] In some embodiments, such as Figure 4 As shown, the aforementioned terminal components extend from a plane parallel to the substrate 1. This lead-out layout facilitates the connection between the three-level power module and the circuit board carrying the power module, shortening the connection path between them.

[0063] In some embodiments, the second terminal 25 and the fourth terminal 27 are stacked and extended from the same side of the substrate 1; the third terminal 28 and the fifth terminal 26 are stacked and extended from the same side of the substrate 1. With this structure, the area of ​​the aforementioned terminal members on the plane of the substrate 1 can be reduced, thereby reducing interference with other terminal members or fixed terminals, etc.

[0064] Furthermore, the stacked structure in this embodiment facilitates the reduction of inductance introduced by the terminal components; the second terminal component 25 and the third terminal component 28 are led out from the same side of the substrate 1, which facilitates connection with the positive and negative terminals of the same power supply device and shortens the connection path; and the fourth terminal component 27 and the fifth terminal component 26 are led out from the same side of the substrate 1, which facilitates connection with the positive and negative terminals of the same power supply device and shortens the connection path.

[0065] The aforementioned terminal components can be metal connectors, such as copper connectors or copper-aluminum alloy connectors.

[0066] In the above-described embodiment of the three-level power circuit of this application, the positive electrode lead-out terminal of the positive electrode layer is located near the first high-voltage outer chip, the first midpoint electrode lead-out terminal of the first midpoint potential electrode layer is located near the first midpoint clamping chip, the second midpoint electrode lead-out terminal of the second midpoint potential electrode layer is located near the second midpoint clamping chip, and the negative electrode lead-out terminal of the negative electrode layer is located near the second high-voltage outer chip. Furthermore, along the first direction, the inner chips of the upper and lower bridge arms are located in the central region of the substrate, while the second midpoint clamping chip and the first midpoint clamping chip are located in the peripheral regions on both sides of the substrate. The second midpoint clamping chip, the first high-voltage outer chip, the inner chip of the upper and lower bridge arms, the second high-voltage outer chip, and the first midpoint clamping chip are arranged sequentially. This structure enables a compact layout, reduces the commutation loop area, thereby reducing the parasitic inductance of the three-level power module, further reducing switching losses and voltage spikes during switching, improving the switching performance of the power module, and lowering the risk of breakdown of the power chips in the three-level power module.

[0067] In some embodiments, such as Figure 5 and Figure 6 As shown, Figure 5 This is a schematic diagram of another embodiment of the three-level power module of this application; Figure 6 This is a schematic diagram of the structure of a substrate in an embodiment of the three-level power module of this application. The three-level power module of this embodiment includes: a substrate 1, a three-level power circuit 220, and a heat dissipation assembly 30; the substrate 1 has a first side and a second side disposed opposite to each other; the three-level power circuit 220 is disposed on the first side, and the three-level power circuit 220 (refer to the above embodiment) includes: a first high-voltage outer chip 15, an upper bridge arm inner chip 17, a lower bridge arm inner chip 18, a second high-voltage outer chip 19, a first midpoint clamping chip 21, and a second midpoint clamping chip 23, wherein, along the first direction x, the upper bridge arm inner chip 17 and the lower bridge arm inner chip 18 are disposed... In the central region of substrate 1, a first high-voltage outer chip 15, a second high-voltage outer chip 19, a first midpoint clamping chip 21, and a second midpoint clamping chip 23 are disposed on the side region of substrate 1; a heat dissipation assembly 30 is disposed on the second side of substrate 1 to form a first heat dissipation area 31 arranged along the first direction x and two second heat dissipation areas 32 located on both sides of the first heat dissipation area 31; wherein, the heat dissipation capacity of the first heat dissipation area 31 is greater than the heat dissipation capacity of the second heat dissipation area 32, and the first heat dissipation area 31 is correspondingly disposed with the inner chip 17 of the upper bridge arm and the inner chip 18 of the lower bridge arm.

[0068] The upper bridge arm inner chip 17 and lower bridge arm inner chip 18, located in the central region of substrate 1, have much higher losses and heat dissipation pressures than other power chips (such as the first high voltage outer chip 15, the second high voltage outer chip 19, the first midpoint clamping chip 21, and the second midpoint clamping chip 23) located on both sides of substrate 1 due to their high switching frequency. Therefore, placing the first heat dissipation area with a large heat dissipation capacity in the central region of substrate 1, corresponding to the upper bridge arm inner chip 17 and the lower bridge arm inner chip 18, can improve the heat dissipation effect in the central region of substrate 1, thereby improving the heat dissipation effect on the upper bridge arm inner chip 17 and the lower bridge arm inner chip 18, balancing the heat dissipation effect in different regions of substrate 1, effectively reducing the temperature rise of hot spots with high heat load, and thus improving the overall heat dissipation effect and reliability of the three-level power module.

[0069] In some embodiments, such as Figure 5 and Figure 6 , Figures 8 to 11 As shown, Figure 8 This is a schematic diagram of an embodiment of the first heat sink in the three-level power module of this application. Figure 9 This is a schematic diagram of another embodiment of the first heat sink in the three-level power module of this application. Figure 10 This is a schematic diagram of another embodiment of the first heat sink in the three-level power module of this application. Figure 11 This is a schematic diagram of another embodiment of the first heat sink in the three-level power module of this application. The first heat dissipation area 31 is provided with a first heat sink 311, which has a major axis (not shown) and a minor axis (not shown).

[0070] The first heat dissipation column 311 has a major axis and a minor axis in its cross-section perpendicular to its axial direction, so that the cooling fluid in the first heat dissipation area 31 can flow more closely and smoothly along the outer wall of the first heat dissipation column 311, increasing the contact area between the cooling fluid and the first heat dissipation column 311, thereby increasing the heat dissipation effect of the first heat dissipation area 31.

[0071] In some embodiments, such as Figure 7 As shown, Figure 7 This is a schematic diagram of another embodiment of the three-level power module of this application. In this embodiment, a cooling cavity A1 is formed on the second side of the substrate 1 for filling with coolant, and the first heat dissipation column 311 is at least partially located in the cooling cavity A1.

[0072] This embodiment achieves liquid cooling of the three-level power module by setting up a cooling chamber A1 and coolant. Of course, in other embodiments, a cooling chamber may not be provided, and air cooling of the three-level power module can be achieved. Alternatively, a cooling chamber may be provided, forming an airflow channel for air cooling.

[0073] In this embodiment, some of the heat from the first heat dissipation zone 31 can be directly exchanged with the coolant in the cooling chamber A1, and can also be indirectly exchanged with the coolant in the cooling chamber A1 through the first heat dissipation column 311.

[0074] In other embodiments, independent cooling chambers can be provided for the first heat dissipation area and the second heat dissipation area. The heat dissipation capacity of the first heat dissipation area can be made greater than that of the second heat dissipation area by providing a coolant with a lower temperature or a faster flow rate to the cooling chamber corresponding to the first heat dissipation area (relative to the cooling chamber corresponding to the second heat dissipation area).

[0075] In some embodiments, the cooling chamber A1 is provided with a fluid inlet (not shown) and a fluid outlet (not shown). The arrangement direction of the fluid inlet and the fluid outlet (not shown) is parallel or approximately parallel to the long axis, meaning that the flow direction of the coolant in the cooling chamber A1 is approximately parallel to the long axis of the first heat dissipation column. In this way, the coolant can flow more closely and smoothly along the outer wall of the first heat dissipation column 311, reducing turbulence and increasing the contact area between the cooling fluid and the first heat dissipation column 311, thereby increasing the heat dissipation effect of the first heat dissipation area 31.

[0076] In some embodiments, the cross-section of the first heat dissipation column 311 is shaped like a tai chi symbol (e.g., ...). Figure 11 As shown), rhombus (as shown) Figure 9 As shown), elliptical (as shown) Figure 8 (as shown) or teardrop-shaped (such as) Figure 10 (As shown in the image) settings.

[0077] The first heat dissipation zone 31 may be provided with multiple spaced first heat dissipation columns 311, and the cross-sectional shapes of the multiple first heat dissipation columns 311 may be all the same, partially the same, or all different.

[0078] In some embodiments, such as Figures 8 to 11 As shown, the first heat dissipation area 311 has a first direction x and a second direction y perpendicular to the first direction x. Multiple first heat dissipation columns 311 are arranged in an array to improve the uniformity of the arrangement, thereby improving the uniformity of heat dissipation and enhancing the heat dissipation effect.

[0079] In some embodiments, such as Figures 8 to 10 As shown, multiple columns of first heat dissipation columns 311, arranged at intervals along the first direction x, are staggered along the second direction y, and adjacent columns of first heat dissipation columns 311 partially overlap along the second direction y. This method increases the density of the first heat dissipation columns 311 and improves the heat dissipation effect.

[0080] In some embodiments, such as Figure 11As shown, multiple rows of first heat dissipation columns 311 are spaced apart along the first direction x and spaced apart along the second direction y, with adjacent rows of first heat dissipation columns 311 not overlapping along the second direction y. In this way, the density of the first heat dissipation columns 31 can be reduced, flow resistance can be reduced, and heat dissipation effect can be improved.

[0081] In some embodiments, the second heat dissipation area 32 is provided with a second heat dissipation column 312, the cross-section of which is circular. This embodiment improves the heat dissipation effect of the second heat dissipation area 32 through the second heat dissipation column 312, thereby improving the heat dissipation effect and reliability of the three-level power module.

[0082] In some embodiments, the second heat dissipation column 312 is at least partially located within the cooling chamber A1, and part of the heat from the second heat dissipation area 32 can directly exchange heat with the coolant in the cooling chamber A1, and can also indirectly exchange heat with the coolant in the cooling chamber A1 through the second heat dissipation column 312.

[0083] In some embodiments, the heat dissipation performance of the two second heat dissipation areas 32 is consistent or approximately consistent. In this way, the heat dissipation effect on both sides of the substrate 1 can be balanced, thereby improving the heat dissipation effect of the three-level power module.

[0084] In some embodiments, the second heat sink 312 may also adopt a structure similar to that of the first heat sink 311. The heat dissipation capacity of the first heat sink 31 can be made greater than that of the second heat sink 32 by using parameters such as the density and radius of the corresponding heat sinks in different heat dissipation areas.

[0085] In some embodiments, substrate 1 includes a copper substrate to increase structural strength and heat dissipation. Of course, in other embodiments, substrate 1 may also be made of other materials.

[0086] In some embodiments, such as Figure 1As shown, the three-level power circuit also includes: a positive electrode layer 2, an AC side electrode layer 4, a second midpoint potential electrode layer 6, a first midpoint potential electrode layer 7, a negative electrode layer 8, a first midpoint clamping electrode layer 3, and a second midpoint clamping electrode layer 5; wherein, the positive electrode lead-out terminal A of the positive electrode layer 2 is located near the first high-voltage outer chip 15, the first midpoint electrode lead-out terminal B of the first midpoint potential electrode layer 7 is located near the first midpoint clamping chip 21, and the second midpoint electrode lead-out terminal C of the second midpoint potential electrode layer 6 is located near the second midpoint clamping chip 23. The negative electrode lead-out terminal D of the negative electrode layer 8 is located near the second high voltage outer chip 19. The upper bridge arm inner chip 17 and the lower bridge arm inner chip 18 are located in the central region of the substrate 1. The second midpoint clamping chip 23 and the first midpoint clamping chip 21 are located in the peripheral regions on both sides of the substrate 1, respectively. Along the first direction x, the second midpoint clamping chip 23, the first high voltage outer chip 15, the upper bridge arm inner chip 17, the lower bridge arm inner chip 18, the second high voltage outer chip 19 and the first midpoint clamping chip 21 in the three-level power circuit 220 are arranged in sequence.

[0087] The layout described in this embodiment enables a compact layout, reduces the commutation loop area, thereby reducing the parasitic inductance of the three-level power module, which in turn reduces switching losses and voltage spikes during switching, and improves the switching performance of the three-level power module.

[0088] In some embodiments, the three-level power module includes at least one set of three-level power circuits, each set of three-level power circuits including two three-level power circuits, which are spaced apart on both sides of the substrate 1 along the second direction y; wherein, for each set of three-level power circuits, the AC lead-out terminal E of the AC side electrode layer 4 is located on the vertical line connecting the two lower bridge arm inner chips 18; the positive electrode lead-out terminal A is located on the vertical line connecting the two first high voltage outer chips 15; the negative electrode lead-out terminal D is located on the vertical line connecting the two second high voltage outer chips 19; the first midpoint electrode lead-out terminal B is located on the vertical line between the two first midpoint clamping chips 21; and the second midpoint electrode lead-out terminal C is located on the vertical line between the two second midpoint clamping chips 23; wherein, the second direction y is perpendicular to the first direction x.

[0089] In this embodiment, the AC lead-out terminal E of the AC side electrode layer 4 is positioned on the vertical line connecting the two lower bridge arm inner chips 18. This ensures that the two lower bridge arm inner chips 18 are symmetrical with respect to the AC lead-out terminal E, reducing the difference in commutation loop area between the two upper bridge arm inner chips 17 and the two adjacent lower bridge arm inner chips 18, thereby maintaining consistent operating conditions and lifespan for each power chip (upper and lower bridge arm chips). Similarly, in this embodiment, the positive electrode lead-out terminal A is positioned on the vertical line connecting the two first high-voltage outer chips 15. This ensures that the two first high-voltage outer chips 15 are symmetrical with respect to the positive electrode lead-out terminal A, reducing the difference in commutation loop area between the two first high-voltage outer chips 15, thereby maintaining consistent operating conditions and lifespan for each first high-voltage outer chip 15. Finally, in this embodiment, the negative electrode lead-out terminal D is positioned on the vertical line connecting the two second high-voltage outer chips 19. This ensures that the two second high-voltage outer chips 19 are symmetrical with respect to the AC lead-out terminal E. The symmetrical negative electrode lead-out terminal D reduces the difference in commutation circuit area between the two second high-voltage outer chips 19, thereby ensuring consistent operating conditions and lifespan for each first midpoint clamping chip 21. In this embodiment, the first midpoint electrode lead-out terminal B is positioned on the vertical line between the two first midpoint clamping chips 21, making them symmetrical with respect to the lead-out terminal B. This reduces the difference in commutation circuit area between the two first midpoint clamping chips 21, ensuring consistent operating conditions and lifespan for each first midpoint clamping chip 21. Similarly, the symmetrical second midpoint electrode lead-out terminal C is positioned on the vertical line between the two second midpoint clamping chips 23, making them symmetrical with respect to the lead-out terminal C. This reduces the difference in commutation circuit area between the two second midpoint clamping chips 23, ensuring consistent operating conditions and lifespan for each second midpoint clamping chip 23. Therefore, the above structure improves the switching performance of the three-level power module.

[0090] In some embodiments, the two three-level power circuits in each group of three-level power circuits are symmetrically arranged along the second direction y, and the AC lead-out terminal E, positive electrode lead-out terminal A, negative electrode lead-out terminal D, first midpoint electrode lead-out terminal B, and second midpoint electrode lead-out terminal C are all located on the corresponding axis of symmetry; the two three-level power circuits in each group of three-level power circuits share the same AC lead-out terminal E, the same positive electrode lead-out terminal A, the same negative electrode lead-out terminal D, the same first midpoint electrode lead-out terminal B, and the same second midpoint electrode lead-out terminal C. In this way, the symmetry of the above structure can be further improved, and the differences in commutation loop areas between the two first high-voltage outer chips 15, the two second high-voltage outer chips 19, the two first midpoint clamping chips 21, the two second midpoint clamping chips 23, the two upper bridge arm inner chips 17, and the two lower bridge arm inner chips 18 in each group of three-level power circuits can be further reduced, thereby further improving the switching performance of the three-level power module.

[0091] For details regarding the specific circuit structure and principle of the three-level power circuit 220, please refer to the above embodiments.

[0092] In some embodiments, the first high-voltage outer diode 16, the second high-voltage outer diode 20, the first midpoint clamping diode 22 and the second midpoint clamping diode 24 are located in the two side regions of the substrate 1, and the upper bridge arm diode 271 and the lower bridge arm diode 281 are located in the central region of the substrate 1.

[0093] The heat generated in the middle region of the three-level power module of this application is less than that in the middle region of the traditional structure, resulting in better heat dissipation and better heat dissipation uniformity in each region, which can improve the heat dissipation effect and reliability of the three-level power module.

[0094] In some embodiments, the heat dissipation pillars are integrally formed with the substrate 1, for example, a copper substrate and copper pillars. The heat dissipation pillars of the substrate are divided into a second heat dissipation area 32, a first heat dissipation area 31, and another second heat dissipation area 32 sequentially from the coolant inlet direction to the coolant outlet direction. The first heat dissipation pillar 311 of the first heat dissipation area 31 is shaped like a tai chi symbol, a rhombus, or a teardrop, etc. By optimizing its shape, the heat dissipation effect of the first heat dissipation area 31 is improved. After optimization, the maximum hot spot temperature rise of the power chip of the three-level power module under actual operating conditions is reduced from 127°C to 108°C, and the junction-coolant thermal resistance of the power chip in the first heat dissipation area 31 is reduced by 33%.

[0095] This application provides a heat dissipation carrier for the aforementioned three-level power module. The heat dissipation carrier includes a substrate 1 and a heat dissipation assembly 30. The substrate 1 has a first side and a second side disposed opposite to each other. The three-level power circuit 220 is disposed on the first side. The heat dissipation assembly 30 is disposed on the second side of the substrate 1 to form a first heat dissipation area 31 arranged along a first direction x and two second heat dissipation areas 32 located on both sides of the first heat dissipation area 31. The heat dissipation capacity of the first heat dissipation area 31 is greater than that of the second heat dissipation areas 32. The first heat dissipation area 31 is correspondingly disposed with the inner chip 17 of the upper bridge arm and the inner chip 18 of the lower bridge arm. Further details about the substrate 1 can be found in the above embodiments.

[0096] In this application's three-level power module, a heat dissipation component is provided on the side of the substrate away from the three-level power circuit. A first heat dissipation area arranged along a first direction x and two second heat dissipation areas located on both sides of the first heat dissipation area are formed on the substrate. The heat dissipation capacity of the first heat dissipation area is greater than that of the second heat dissipation areas. The first heat dissipation area is correspondingly arranged with the inner chips of the upper and lower bridge arms. Due to their high switching frequency, the inner chips of the upper and lower bridge arms located in the central region of the substrate have much higher losses and heat dissipation pressure than other power chips on both sides. Therefore, placing the first heat dissipation area with a large heat dissipation capacity in the central region of the substrate, corresponding to the inner chips of the upper and lower bridge arms, can improve the heat dissipation effect in the central region of the substrate, thereby improving the heat dissipation effect of the inner chips of the upper and lower bridge arms, balancing the heat dissipation effect in different regions of the substrate, effectively reducing the temperature rise of hot spots with high heat load, and thus improving the overall heat dissipation effect and reliability of the three-level power module.

[0097] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A three-level power module, characterized in that, include: substrate; A three-level power circuit is disposed on the substrate. The three-level power circuit includes: a first high-voltage outer chip, an upper bridge arm inner chip, a lower bridge arm inner chip, a second high-voltage outer chip, a first midpoint clamping chip, a second midpoint clamping chip, a positive electrode layer, an AC side electrode layer, a second midpoint potential electrode layer, a first midpoint potential electrode layer, a negative electrode layer, a first midpoint clamping electrode layer, and a second midpoint clamping electrode layer. Wherein, the positive electrode lead-out end of the positive electrode layer is located near the first high voltage outer chip, the first midpoint electrode lead-out end of the first midpoint potential electrode layer is located near the first midpoint clamping chip, the second midpoint electrode lead-out end of the second midpoint potential electrode layer is located near the second midpoint clamping chip, and the negative electrode lead-out end of the negative electrode layer is located near the second high voltage outer chip. Along the first direction, the inner chip of the upper bridge arm and the inner chip of the lower bridge arm are located in the central region of the substrate, and the second midpoint clamping chip and the first midpoint clamping chip are located in the peripheral regions on both sides of the substrate, and the second midpoint clamping chip, the first high voltage outer chip, the inner chip of the upper bridge arm, the inner chip of the lower bridge arm, the second high voltage outer chip and the first midpoint clamping chip in the three-level power circuit are arranged in sequence.

2. The three-level power module according to claim 1, characterized in that, The three-level power module includes at least one set of the three-level power circuits; each set of the three-level power circuits includes two three-level power circuits, which are arranged at intervals on both sides of the substrate in the second direction. Specifically, for each group of the three-level power circuits, the AC lead-out terminal of the AC side electrode layer is located on the vertical line connecting the two inner chips of the lower bridge arm; the positive electrode lead-out terminal is located on the vertical line connecting the two outer first high-voltage chips; the negative electrode lead-out terminal is located on the vertical line connecting the two outer second high-voltage chips; the first midpoint electrode lead-out terminal is located on the vertical line between the two first midpoint clamping chips; and the second midpoint electrode lead-out terminal is located on the vertical line between the two second midpoint clamping chips. The second direction is perpendicular to the first direction.

3. The three-level power module according to claim 2, characterized in that, In each group of three-level power circuits, two three-level power circuits are symmetrically arranged along the second direction, and the AC lead-out terminal, the positive electrode lead-out terminal, the negative electrode lead-out terminal, the first midpoint electrode lead-out terminal, and the second midpoint electrode lead-out terminal are all located on the corresponding axis of symmetry.

4. The three-level power module according to claim 3, characterized in that, In each group of three-level power circuits, the two three-level power circuits share the same AC lead-out terminal, the same positive electrode lead-out terminal, the same negative electrode lead-out terminal, the same first midpoint electrode lead-out terminal, and the same second midpoint electrode lead-out terminal.

5. The three-level power module according to claim 1, characterized in that, The three-level power circuit further includes: a first high-voltage outer driving metal layer, an upper bridge arm inner driving metal layer, a lower bridge arm inner driving metal layer, a second high-voltage outer driving metal layer, a first midpoint clamping driving metal layer, and a second midpoint clamping driving metal layer. The first high-voltage outer driving metal layer is electrically connected to the control terminal of the first high-voltage outer chip; the first midpoint clamping electrode layer is electrically connected to one switch terminal of the first high-voltage outer chip; and the positive electrode layer is connected to the other switch terminal of the first high-voltage outer chip. The upper bridge arm inner driving metal layer is electrically connected to the control terminal of the upper bridge arm inner chip; the AC side electrode layer is electrically connected to one switch terminal of the upper bridge arm inner chip; and the first midpoint clamping electrode layer is electrically connected to the other switch terminal of the upper bridge arm inner chip. The lower bridge arm inner driving metal layer is electrically connected to the control terminal of the lower bridge arm inner chip; the second midpoint clamping electrode layer is electrically connected to one switch terminal of the lower bridge arm inner chip; and the AC side electrode layer is electrically connected to the other switch terminal of the lower bridge arm inner chip. The second high-voltage... The outer driving metal layer is electrically connected to the control terminal of the second high-voltage outer chip, the negative electrode layer is electrically connected to one switch terminal of the second high-voltage outer chip, and the second midpoint clamping electrode layer is connected to the other switch terminal of the second high-voltage outer chip; the first midpoint clamping driving metal layer is electrically connected to the control terminal of the first midpoint clamping chip, the first midpoint potential electrode layer is electrically connected to one switch terminal of the first midpoint clamping chip, and the first midpoint clamping electrode layer is connected to the other switch terminal of the first midpoint clamping chip; the second midpoint clamping driving metal layer is electrically connected to the control terminal of the second midpoint clamping chip, the second midpoint clamping electrode layer is electrically connected to one switch terminal of the second midpoint clamping chip, and the second midpoint potential electrode layer is connected to the other switch terminal of the second midpoint clamping chip.

6. The three-level power module according to claim 5, characterized in that, The first high-voltage outer driving metal layer, the upper bridge arm inner driving metal layer, the lower bridge arm inner driving metal layer, the second high-voltage outer driving metal layer, the first midpoint clamping driving metal layer, the second midpoint clamping driving metal layer, the first midpoint clamping electrode layer, the second midpoint clamping electrode layer, the positive electrode layer, the AC side electrode layer, the second midpoint potential electrode layer, the first midpoint potential electrode layer, and the negative electrode layer are disposed on the substrate in the same layer.

7. The three-level power module according to claim 6, characterized in that, The first midpoint clamping electrode layer includes a first sub-electrode layer, a second sub-electrode layer, and a third sub-electrode layer arranged and electrically connected along the first direction; the second midpoint clamping electrode layer includes a fourth sub-electrode layer, a fifth sub-electrode layer, and a sixth sub-electrode layer arranged and electrically connected along the first direction. The second midpoint clamping chip is disposed on the side of the second midpoint potential electrode layer away from the substrate, the first high voltage outer chip is disposed on the side of the positive electrode layer away from the substrate, the upper bridge arm inner chip is disposed on the side of the second sub-electrode layer away from the substrate, the lower bridge arm inner chip is disposed on the side of the AC side electrode layer away from the substrate, the second high voltage outer chip is disposed on the side of the sixth sub-electrode layer away from the substrate, and the first midpoint clamping chip is disposed on the side of the third sub-electrode layer away from the substrate. Along the first direction, the second midpoint potential electrode layer, the fifth sub-electrode layer, the positive electrode layer, the first sub-electrode layer, the second sub-electrode layer, the sixth sub-electrode layer, the negative electrode layer, the first midpoint potential electrode layer, and the third sub-electrode layer are arranged sequentially; Along the second direction, the second midpoint clamping drive metal layer is located between adjacent second midpoint potential electrode layers, the second high voltage outer drive metal layer is located between adjacent second high voltage outer chips, the first midpoint clamping drive metal layer is located between adjacent first midpoint potential electrode layers, and the first high voltage outer drive metal layer is located between adjacent first high voltage outer chips.

8. The three-level power module according to claim 5, characterized in that, The three-level power circuit also includes: The first high-voltage outer diode has a first midpoint clamping electrode layer electrically connected to one switching terminal of the first high-voltage outer diode, and a positive electrode layer connected to the other switching terminal of the first high-voltage outer diode. The second high-voltage outer diode has its negative electrode layer electrically connected to one switching terminal of the first high-voltage outer diode, and its second midpoint clamping electrode layer is connected to the other switching terminal of the second high-voltage outer diode. The first midpoint clamping diode has a first midpoint potential electrode layer electrically connected to one switching terminal of the first midpoint clamping diode, and the first midpoint clamping electrode layer is connected to the other switching terminal of the first midpoint clamping diode. The second midpoint clamping diode has a second midpoint clamping electrode layer electrically connected to one switching terminal of the second midpoint clamping diode, and a second midpoint potential electrode layer connected to the other switching terminal of the second midpoint clamping diode. Wherein, the first high-voltage outer chip is positioned relative to the first high-voltage outer diode and close to the positive electrode lead-out end; the second midpoint clamping chip is positioned relative to the second midpoint clamping diode and close to the second midpoint electrode lead-out end; the second high-voltage outer chip is positioned relative to the second high-voltage outer diode and close to the negative electrode lead-out end; and the first midpoint clamping chip is positioned relative to the first midpoint clamping diode and close to the first midpoint electrode lead-out end.

9. The three-level power module according to claim 4, characterized in that, The three-level power circuit also includes: The upper bridge arm diode has a first midpoint clamping electrode layer electrically connected to one switching terminal of the upper bridge arm diode, and a negative electrode layer connected to the other switching terminal of the upper bridge arm diode. The lower bridge arm diode has a second midpoint clamping electrode layer electrically connected to one switching terminal of the lower bridge arm diode, and the positive electrode layer is connected to the other switching terminal of the lower bridge arm diode.

10. The three-level power module according to claim 1, characterized in that, The three-level power module also includes: The first terminal piece has one end connected to the AC lead-out terminal and the other end extending out of the outer side of the substrate; The second terminal has one end connected to the positive electrode lead-out end and the other end extending out of the outer side of the substrate; The third terminal has one end connected to the negative electrode lead-out end and the other end extending out of the outer side of the substrate; The fourth terminal has one end connected to the second midpoint potential lead-out terminal and the other end extending out of the outer side of the substrate; The fifth terminal has one end connected to the first midpoint potential lead-out terminal and the other end extending out of the outer side of the substrate.

11. The three-level power module according to claim 10, characterized in that, The second terminal and the fourth terminal are stacked together and extended from the same side of the substrate; The third terminal and the fifth terminal are stacked together and extended from the same side of the substrate.

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