A smart substation clock synchronization monitoring method and system

Abstract

The application relates to the technical field of substation monitoring, in particular to a smart substation clock synchronization monitoring method and system. The method comprises the following steps: acquiring clock deviation values of electronic devices of a substation at different time instants within a preset time window, and determining an average deviation sequence according to the clock deviation values of the multiple electronic devices within the preset time window; determining a change trend stability value and a change amount stability value according to the average deviation sequence, and taking the product of the change trend stability value and the change amount stability value as an evaluation value; determining a difference degree value according to the clock deviation values of the multiple electronic devices, and constructing a monitoring feature vector of a target time instant by using the difference degree value and the evaluation value; and monitoring a clock deviation type of a clock synchronization state of the substation by using the monitoring feature vectors of the substation at multiple continuous time instants. Through the above technical scheme, the clock synchronization process of the smart substation can be monitored.

Description

Technical Field

[0001] This application relates to the field of substation monitoring technology, and in particular to a method and system for clock synchronization monitoring in intelligent substations. Background Technology

[0002] Intelligent substations are an important component of modern power systems. The structure of an intelligent substation is mainly divided into process layer, bay layer and station control layer. The process layer includes intelligent terminals, merging units and electronic instrument transformers, which are responsible for data acquisition, conversion and execution of control commands, converting traditional analog signals into digital signals.

[0003] The bay layer consists of protection devices, measurement and control devices, and metering equipment, and undertakes the functions of protection, measurement, control and monitoring of the power system by the intelligent substation; the station control layer includes monitoring host, remote communication device and human-machine interface, and undertakes the tasks of centralized management of data of intelligent substation, remote communication, dispatching command issuance and operation status display.

[0004] Clock synchronization is fundamental to ensuring the coordinated operation of various devices in a smart substation. Smart substations involve the real-time acquisition, transmission, and processing of a large amount of data. Clock synchronization ensures that all devices operate under a unified time reference, thereby enabling accurate event sequence recording, fault location, protection action coordination, and data synchronization analysis.

[0005] For example, when a short-circuit fault occurs, the timing of each protection device and the measurement and control unit must be consistent in order to accurately determine the time, location and cause of the fault, thereby providing a basis for quickly restoring power supply. Clock synchronization is also crucial for the realization of key functions such as differential protection and synchronous closing. Therefore, it is necessary to monitor the clock synchronization process of smart substations. Summary of the Invention

[0006] To monitor the clock synchronization process of a smart substation, this application provides a method and system for monitoring clock synchronization in a smart substation.

[0007] According to a first aspect of the embodiments of this application, a method for monitoring clock synchronization in a smart substation is provided, comprising: acquiring clock deviation values ​​of electronic devices in the substation at different times within a preset time window; determining an average deviation sequence based on the clock deviation values ​​of multiple electronic devices within the preset time window; the clock deviation value being equal to the time deviation between the electronic device and the master clock; determining a trend stability value based on the first-order difference sequence of the average deviation sequence, and determining a change amount stability value based on the second-order difference sequence of the average deviation sequence, using the product of the trend stability value and the change amount stability value as an evaluation value; determining a degree of difference value based on the clock deviation values ​​of multiple electronic devices at a target time, and constructing a monitoring feature vector for the target time using the degree of difference value and the evaluation value; the degree of difference value being used to characterize the degree of difference in clock deviation values ​​of different electronic devices at the target time; using the monitoring feature vectors of the substation at multiple consecutive times, determining the monitoring result of the clock deviation type of the clock synchronization state of the substation, and outputting monitoring prompt information based on the monitoring result.

[0008] This enables the monitoring of clock deviation types in the clock synchronization status of substations.

[0009] Optionally, the stability value of the trend is determined based on the first-order difference sequence of the average deviation sequence, including: ,in, This represents the stability value of the changing trend, where M is the number of sampling points within a preset time window. Let be the j-th value in the first-order difference sequence, and ln be the logarithmic function with the natural constant as the base; ,like equal ,but ;like Not equal to ,but ; For symbolic functions, To avoid using a preset positive number with a denominator of 0, To take the absolute value.

[0010] In this way, based on the values ​​at different times in the first-order difference sequence of the average deviation sequence, a trend stability value can be obtained to reflect the stability of the overall clock deviation between the master clock and electronic equipment within a preset time window.

[0011] Optionally, the stability value of the change is determined based on the second-order difference sequence of the average deviation sequence, including: , This is the stability value of the change. Let M be an exponential function with the natural constant as the base, and M be the number of sampling points within the preset time window. Let be the absolute value of the j-th value in the second-order difference sequence. The standard deviation of the first-order difference sequence of the mean deviation sequence. This is a preset positive number used to avoid denominators of 0.

[0012] Optionally, the average deviation sequence is determined by taking the average value of the clock deviation values ​​of multiple electronic devices at the same moment as the value of the corresponding moment in the average deviation sequence, so as to obtain the average deviation sequence including the values ​​of different moments within a preset time window.

[0013] In this way, the average deviation sequence obtained for the corresponding preset time window can reflect the overall clock deviation between the master clock and multiple electronic devices at different times within the preset time window.

[0014] Optionally, a difference degree value is determined based on the clock deviation values ​​of multiple electronic devices at the target time, including: sorting the clock deviation values ​​of multiple electronic devices at the target time in ascending order to obtain a sorted sequence, and performing nonnegation processing on the elements in the sorted sequence to obtain a nonnegative sorted sequence; difference degree value Where N is the number of elements in the non-negative sorted sequence. It represents the i-th clock offset value in the non-negative sorted sequence.

[0015] Optionally, the degree of difference is determined based on the clock deviation values ​​of multiple electronic devices at the target time, including: the frequency proportion of different clock deviation values ​​among the clock deviation values ​​of multiple electronic devices at the target time, determining the information entropy of the clock deviation values ​​with different frequency proportions, and using the information entropy as the degree of difference.

[0016] Optionally, the monitoring results of the clock deviation type of the substation's clock synchronization state are determined by using the monitoring feature vectors of the substation at multiple consecutive moments, including: obtaining a pre-constructed fault model library; the fault model library includes multiple reference feature matrices corresponding to different clock deviation types; different clock deviation types include normal clock deviation, master clock drift fault, and network congestion fault; the monitoring feature vectors of the substation at multiple consecutive moments are combined into a monitoring feature matrix, and the monitoring feature matrix is ​​compared with the reference feature matrix in the fault model library to obtain the target clock deviation type of the substation's clock deviation state.

[0017] Optionally, if the target clock deviation type of the substation's clock deviation state is determined to be a network congestion fault, the method further includes: obtaining the substation's network topology, grouping multiple electronic devices according to the network topology, determining the within-group variance of the clock deviation values ​​of the electronic devices within the group, and the deviation value between the mean of the clock deviation values ​​of the electronic devices within the group and the overall mean; determining the congestion index of the group based on the within-group variance and the deviation value, and identifying the network area corresponding to the group with the largest congestion index among the multiple groups as the congestion source area.

[0018] In this way, if the target clock deviation type of the substation's clock deviation status is determined to be a network congestion fault, the source area of ​​the congestion can be further identified.

[0019] Optionally, the monitoring results of the clock deviation type of the clock synchronization state of the substation are determined by using the monitoring feature vectors of the substation at multiple consecutive times, including: inputting the monitoring feature vectors of the substation at multiple consecutive times into a pre-trained SVM classifier to obtain the clock deviation type output by the SVM classifier; the SVM classifier is used to output the clock deviation type of the clock synchronization state of the substation.

[0020] In this way, the monitoring results of the clock deviation type of the clock synchronization status of the substation can be automatically determined based on the monitoring feature vectors of the substation at multiple consecutive moments.

[0021] According to a second aspect of the present application, a smart substation clock synchronization monitoring system is provided, comprising: a processor and a memory, wherein the memory stores computer program instructions, and the computer program instructions, when executed by the processor, implement the steps of the smart substation clock synchronization monitoring method provided in the first aspect of the present application.

[0022] The technical solutions provided by the embodiments of this application may include the following beneficial effects: obtaining the clock deviation values ​​of electronic equipment in a substation at different times within a preset time window, and determining the average deviation sequence based on the clock deviation values ​​of multiple electronic devices within the preset time window; determining the trend stability value and the change stability value based on the first-order difference sequence and the second-order difference sequence of the average deviation sequence, respectively; combining the clock deviation values ​​of multiple electronic devices at the target time, obtaining a monitoring feature vector describing the clock synchronization state of the substation; and obtaining a relatively accurate monitoring result of the clock deviation type of the clock synchronization state of the substation based on the monitoring feature vectors of multiple consecutive times.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating a smart substation clock synchronization monitoring method according to an exemplary embodiment;

[0025] Figure 2 A schematic diagram of the average deviation sequence within a preset time window under network congestion failure;

[0026] Figure 3 A schematic diagram showing the clock deviation values ​​of different electronic devices under network congestion faults;

[0027] Figure 4 This is a schematic diagram illustrating the structure of an intelligent substation clock synchronization monitoring system according to an exemplary embodiment. Detailed Implementation

[0028] To monitor the clock synchronization process of smart substations, embodiments of this application provide a method and system for monitoring clock synchronization in smart substations. Figure 1 This is a flowchart illustrating a smart substation clock synchronization monitoring method according to an exemplary embodiment, such as... Figure 1 As shown, the method includes the following steps.

[0029] In step S101, the clock deviation values ​​of the electronic equipment in the substation at different times within a preset time window are obtained, and the average deviation sequence is determined based on the clock deviation values ​​of multiple electronic devices within the preset time window.

[0030] The substation is equipped with a master clock and several other electronic devices. The master clock can receive external time signals from GPS (Global Positioning System) or Beidou satellites. By exchanging messages with the electronic devices in the substation, the master clock can synchronize the time signals of the electronic devices in the substation and complete the clock synchronization process of the entire substation.

[0031] The same master clock in a substation can synchronize the clocks of multiple electronic devices. In this application embodiment, the multiple electronic devices can refer to different electronic devices in the substation that are synchronized by the same master clock.

[0032] The master clock can send a synchronization message to the electronic device to instruct the electronic device to synchronize its clock, and record the timestamp T1 of the transmission. The electronic device receives the synchronization message sent by the master clock and records the timestamp T2 of the received message. The master clock then sends a follow-up message to the electronic device carrying timestamp T1.

[0033] The electronic device can send a delay request message to the master clock and record the timestamp T3 of the transmission; the master clock receives the delay request message from the electronic device and records the timestamp T4 of the received delay request message, and then sends a delay response message carrying the timestamp T4 to the electronic device; the clock deviation between the electronic device and the master clock is equal to... .

[0034] When the master clock experiences drift faults due to crystal aging, the timestamps recorded by the master clock will be inaccurate. When there is network congestion fault in the network between the electronic equipment and the master clock, the duration of message transmission between the electronic equipment and the master clock will fluctuate, causing the clock deviation value between the electronic equipment and the master clock to change. Therefore, obtaining the clock deviation value of the electronic equipment in the substation at different times within a preset time window can help determine the type of clock deviation in the clock synchronization state of the substation.

[0035] The multiple electronic devices that the master clock synchronizes with can include merging units, smart terminals, and protection devices, as well as other devices that require precise time synchronization. The clock deviation value between each electronic device and the master clock is obtained at different times within a preset time window. The preset time window can be set according to the real-time requirements of the monitoring, for example, the most recent 10 minutes can be used as the preset time window.

[0036] The clock deviation status of the substation at different monitoring times can be monitored by using preset time windows corresponding to different monitoring times. The preset time window corresponding to the monitoring time ends at the monitoring time, and the duration of different preset time windows is the same.

[0037] In one embodiment, the average deviation sequence is determined by taking the average of the clock deviation values ​​of multiple electronic devices at the same moment as the value of the corresponding moment in the average deviation sequence, so as to obtain an average deviation sequence that includes the values ​​of different moments within a preset time window.

[0038] The average clock deviation of multiple electronic devices at the same time can reflect the overall clock deviation of the multiple electronic devices in the substation relative to the master clock at the same time. Using the obtained average deviation sequence, it is possible to reflect the change of the overall clock deviation of multiple electronic devices relative to the master clock at different times within a preset time window.

[0039] In step S102, the trend stability value is determined based on the first-order difference sequence of the average deviation sequence, and the change stability value is determined based on the second-order difference sequence of the average deviation sequence. The product of the trend stability value and the change stability value is used as the evaluation value.

[0040] The trend stability value can characterize the stability of the trend of change of elements in the average deviation sequence within a preset time window; the change amount stability value can characterize the stability of the change amount of elements in the average deviation sequence within a preset time window.

[0041] When there are fluctuations in the network between the substation's main clock and electronic equipment, the duration of signal transmission between the main clock and electronic equipment will fluctuate, and the direction of this fluctuation is usually more random. When the substation's main clock drifts due to crystal aging, it will usually change in the direction that increases the clock deviation between the main clock and electronic equipment, making the direction of change of the clock deviation more consistent in the event of a clock drift fault.

[0042] The first-order difference sequence of the average deviation sequence includes the difference between every two adjacent elements in the average deviation sequence. The first-order difference sequence can better reflect the stability of the changing trend of the elements in the average deviation sequence.

[0043] The stability of the average deviation sequence changes under the two clock synchronization states of network fluctuation caused by network congestion faults and clock drift faults is different. Therefore, using the stability value of the change trend can help distinguish between the two clock synchronization states of network congestion faults and clock drift faults in substations.

[0044] In one embodiment, determining the trend stability value based on the first-order difference sequence of the average deviation sequence includes: ,in, This represents the stability value of the changing trend, where M is the number of sampling points within a preset time window. Let be the j-th value in the first-order difference sequence, and ln be the logarithmic function with the natural constant as the base; ,like equal ,but ;like Not equal to ,but ; For symbolic functions, To avoid using a preset positive number with a denominator of 0, To take the absolute value.

[0045] The sign function is used to make the result 1 for non-negative numbers and -1 for negative numbers. The result of the sign function can reflect the positive or negative nature of the numerical value. Since the object of the sign function is the numerical value in the first difference sequence of the mean deviation sequence, the result of the sign function can reflect the direction of change of the mean deviation sequence.

[0046] The value of is greater than or equal to 1, such that The value of is greater than or equal to 0, and the denominator of the formula for calculating the stability value of the trend is . The summation of these terms ensures that the denominator of the trend stability value calculation formula is greater than 0, and that the denominator is greater than the numerator, guaranteeing that the trend stability value will be between 0 and 1. To avoid using a preset positive number with a denominator of 0, for example, the value of the preset positive number could be equal to... .

[0047] When the overall clock deviation of different equipment in a substation and the master clock changes in a relatively consistent direction within a preset time window, the positive and negative signs of adjacent elements in the first-order difference sequence of the average deviation sequence are more consistent, making... The sum of the sums and The sums of these two sums are closer together, which makes the value of the stability value of the trend larger.

[0048] Conversely, when the direction of change of the overall clock deviation between different devices in the substation and the master clock changes frequently within a preset time window, the difference in the sign of adjacent elements in the first-order difference sequence of the average deviation sequence is even greater. The sum of contains both positive and negative values, making ... The sum of these values ​​is closer to 0, and the value of the trend stability value is smaller.

[0049] like equal This indicates that the (j+1)th element and the jth element in the first-order difference sequence have the same sign; for example, the (j+1)th element and the jth element are both non-negative. It can accumulate quantities in the same direction of change.

[0050] In one embodiment, determining the stability value of the change based on the second-order difference sequence of the average deviation sequence includes: , This is the stability value of the change. Let M be an exponential function with the natural constant as the base, and M be the number of sampling points within the preset time window. Let be the absolute value of the j-th value in the second-order difference sequence. The standard deviation of the first-order difference sequence of the mean deviation sequence. This is a preset positive number used to avoid denominators of 0.

[0051] The larger the stability value of the change determined by the second-order difference sequence of the average deviation sequence, the more stable the change of the overall clock deviation value of different electronic devices in the substation at different times within the preset time window. When there are fluctuations in the network state of the message exchange between the substation's master clock and electronic devices, the change of the overall clock deviation value of different electronic devices at different times within the preset time window will be more random. Therefore, the larger the stability value of the change at a certain moment, the lower the probability that the clock synchronization state between the substation's master clock and electronic devices is affected by fluctuations in the network state.

[0052] The absolute value of the j-th value in the second-order difference sequence reflects the rate of change of the average deviation sequence of the substation. The standard deviation of the first-order difference sequence of the average deviation sequence is used as... The elements in the denominator of this term can achieve [the following]: The normalization process is performed, and the presence of a pre-defined positive number can prevent the denominator from being 0.

[0053] The smaller the absolute value of the j-th value in the second-order difference sequence, the more stable the change in the average deviation sequence of the substation at different times. Therefore, the stability value of the change in larger values ​​can be determined by the reciprocal of the exponential function.

[0054] The trend stability value at the target time is used to characterize the stability of the overall clock deviation trend between the substation's master clock and different electronic devices. The change amount stability value at the target time is used to characterize the stability of the change amount of the overall clock deviation between the substation's master clock and different electronic devices. The evaluation value is obtained by multiplying the trend stability value and the change amount stability value. The evaluation value can comprehensively reflect the change amount and trend stability of the overall clock deviation between the substation's master clock and different electronic devices, so as to determine the type of clock deviation of the substation based on the evaluation value.

[0055] In step S103, the degree of difference is determined based on the clock deviation values ​​of multiple electronic devices at the target time, and the degree of difference and the evaluation value are used to construct the monitoring feature vector of the target time.

[0056] The degree of difference value is used to characterize the degree of difference in clock deviation values ​​between different electronic devices at the target time. The larger the degree of difference value at the target time, the greater the degree of difference in clock deviation values ​​between different electronic devices at the target time, and the more likely there is network fluctuation in the network between the master clock and the electronic devices at the target time.

[0057] Conversely, the smaller the difference value at the target time, the smaller the difference in clock deviation values ​​between different electronic devices at the target time, the more consistent the clock deviation values ​​between different electronic devices at the target time, and the higher the probability that the message exchange between the master clock and the electronic devices is in a stable state.

[0058] In one embodiment, determining the degree of difference value based on the clock deviation values ​​of multiple electronic devices at a target time includes: sorting the clock deviation values ​​of the multiple electronic devices at the target time in ascending order to obtain a sorted sequence, and performing nonnegation processing on the elements in the sorted sequence to obtain a nonnegative sorted sequence; degree of difference value Where N is the number of elements in the non-negative sorted sequence. It represents the i-th clock offset value in the non-negative sorted sequence.

[0059] For example, if the clock offset values ​​of five electronic devices are 1 microsecond, 2 microseconds, 1 microsecond, 1 microsecond, and 0 microseconds, then the ranking result of the clock offset values ​​of the different electronic devices is 0 microseconds, 1 microsecond, 1 microsecond, 1 microsecond, and 2 microseconds, and the degree of difference is taken as... =0.067.

[0060] If the clock deviation value of all five electronic devices is 1 microsecond, then the ranking result of the clock deviation values ​​of the different electronic devices is 1 microsecond, 1 microsecond, 1 microsecond, 1 microsecond, and 1 microsecond, with the degree of difference value being [value missing]. =0.

[0061] Obtaining a non-negative sorted sequence by denegating the elements in a sorted sequence can refer to subtracting the smallest negative number in the sorted sequence from each element to obtain the non-negative sorted sequence after denegation.

[0062] The greater the difference in clock deviation values ​​among multiple electronic devices at the same time, the greater the value of the degree of difference. Therefore, the degree of difference value at the target time can better characterize the degree of difference in clock deviation values ​​among multiple electronic devices at the target time.

[0063] When there are fluctuations in the network through which the substation's master clock and electronic equipment transmit messages, the clock deviation between different electronic devices and the master clock at the same time will vary, resulting in a greater degree of difference.

[0064] When the clock deviation between the main clock of the substation and the electronic equipment changes due to the aging of the crystal oscillator, although there are clock deviation values ​​between different electronic equipment and the main clock, the clock deviation values ​​between different electronic equipment and the main clock at the same time are closer, showing a smaller degree of difference.

[0065] The main clock in a substation exhibits different degrees of difference due to two types of clock deviation: aging of the crystal oscillator and fluctuations in the network used for message transmission. Therefore, by determining the degree of difference in clock deviation values ​​of different electronic devices at the same time, it is easier to identify different types of clock deviation.

[0066] In one embodiment, determining the degree of difference based on the clock deviation values ​​of multiple electronic devices at a target time includes: determining the frequency proportion of different clock deviation values ​​among the clock deviation values ​​of multiple electronic devices at the target time, determining the information entropy of the clock deviation values ​​with different frequency proportions, and using the information entropy as the degree of difference value.

[0067] The more diverse the number of different clock deviation values ​​of multiple electronic devices at the same target time, or the greater the difference in the frequency proportion of different clock deviation values ​​of multiple electronic devices at the same target time, the greater the value of information entropy obtained, and the greater the degree of difference can be determined.

[0068] The greater the difference in clock deviation values ​​among multiple electronic devices at the same target time, the larger the difference value can be obtained. Therefore, the difference value can be used to better characterize the difference in clock deviation values ​​among multiple electronic devices at the same target time.

[0069] The greater the difference in clock deviation values ​​among multiple electronic devices at the same target time, the more likely the electronic devices in the substation are to experience network fluctuations at the target time, and the more likely the clock synchronization process between the master clock and the electronic devices is to be actually affected by network fluctuations. Conversely, the smaller the difference in clock deviation values ​​among multiple electronic devices at the same target time, the more likely the electronic devices in the substation are to be in a stable network state at the target time.

[0070] The difference degree value and the evaluation value can describe the clock synchronization performance of the substation at the target time from two different dimensions. By constructing the monitoring feature vector at the target time using the difference degree value and the evaluation value, a more comprehensive description of the clock synchronization behavior of the substation can be achieved.

[0071] The monitoring feature vector can include two components: the degree of difference and the evaluation value. For different times when the main clock of the substation is synchronized with the electronic equipment, the corresponding monitoring feature vectors for different times can be determined.

[0072] In step S104, the monitoring characteristic vectors of the substation at multiple consecutive moments are used to determine the monitoring results of the clock deviation type of the clock synchronization status of the substation, and monitoring prompt information is output based on the monitoring results.

[0073] The monitoring feature vector at the target time can describe the clock synchronization behavior of the substation. By using the monitoring feature vectors of the substation at multiple consecutive times, the isolation that may exist in the monitoring feature vector at a single time can be avoided, thereby achieving more accurate monitoring of the clock synchronization behavior of the substation.

[0074] Referring to the process of determining the monitoring feature vector at the target time, the monitoring feature vectors of the substation at other times besides the target time can be determined separately. When monitoring the clock synchronization behavior between the substation's master clock and electronic equipment at the target time, the multiple consecutive times of the substation can refer to multiple consecutive historical times adjacent to the target time.

[0075] In one embodiment, the monitoring results of the clock deviation type of the substation's clock synchronization state are determined by using the monitoring feature vectors of the substation at multiple consecutive moments. This includes: acquiring a pre-built fault model library; the fault model library includes multiple reference feature matrices corresponding to different clock deviation types; different clock deviation types include normal clock deviation, master clock drift fault, and network congestion fault; forming a monitoring feature matrix from the monitoring feature vectors of the substation at multiple consecutive moments; comparing the monitoring feature matrix with the reference feature matrices in the fault model library to obtain the target clock deviation type of the substation's clock deviation state.

[0076] The reference feature matrix in the fault model library is constructed in the same way as the monitoring feature matrix is ​​constructed based on the monitoring feature vectors of the substation at multiple consecutive moments. The reference feature matrix can be constructed based on the historical monitoring feature vectors of the substation at multiple historical moments within a historical time period.

[0077] Data samples of the clock synchronization status between the substation's main clock and electronic equipment can be collected in advance, and the different collected data samples can be classified. Based on the classified data samples, reference feature matrices of the substation under different clock deviation types can be obtained.

[0078] Different clock skew types can correspond to at least one reference feature matrix, and the same clock skew type can correspond to multiple reference feature matrices with different clock skew degrees under the corresponding clock skew type, so as to further determine the clock skew degree based on the determination of the clock skew type.

[0079] By comparing the monitoring feature matrix with the reference feature matrix in the fault model library, the clock deviation type of the reference feature matrix that best matches the monitoring feature matrix in the fault model library can be used as the target clock deviation type for obtaining the clock deviation status of the substation.

[0080] The comparison between the monitoring feature matrix and the reference feature matrix in the fault model library can be achieved through Euclidean distance, cosine similarity, and dynamic time warping, and the embodiments of this application do not constitute a limitation.

[0081] By comparing the monitoring feature matrix with the reference feature matrix in the fault model library, it is possible to determine whether the clock synchronization status between the substation's main clock and electronic equipment is normal, main clock drift fault, or network congestion fault, which can help maintenance personnel achieve automated fault classification.

[0082] For example, if the clock deviation type of the clock synchronization status of the substation is determined to be a master clock drift fault, a prompt message can be output stating "Master clock drift fault exists, please check"; compared to simply indicating that the clock deviation value between the electronic equipment and the master clock is abnormal, this can better help reduce the difficulty and workload of operation and maintenance personnel in monitoring.

[0083] Figure 2 This diagram illustrates the average deviation sequence within a preset time window under network congestion fault conditions. The elements in the average deviation sequence reflect the overall clock deviation of different electronic devices with the same master clock in the substation at the same moment. The average deviation sequence reflects the fluctuation of the overall clock deviation within the preset time window. Figure 2 As shown, the overall clock skew fluctuated irregularly under network congestion faults.

[0084] Figure 3 This diagram illustrates the clock deviation values ​​of different electronic devices under network congestion. When there is network congestion in the network through which the master clock interacts with electronic devices, the clock deviation values ​​of different electronic devices at the same time may show significant differences.

[0085] In one embodiment, if the target clock deviation type of the substation's clock deviation state is determined to be a network congestion fault, the substation's network topology can be obtained, and multiple electronic devices can be grouped according to the network topology. The within-group variance of the clock deviation values ​​of the electronic devices in the group and the deviation of the mean of the clock deviation values ​​of the electronic devices in the group from the overall mean can be determined. The congestion index of the group can be determined based on the within-group variance and the deviation value, and the network area corresponding to the group with the largest congestion index among the multiple groups can be determined as the congestion source area.

[0086] When the target clock deviation type of the substation's clock deviation state is determined to be a network congestion fault, in order to facilitate the understanding that different electronic devices that trigger the master clock have different sources of clock deviation values, the substation's network topology can be obtained. The network topology includes the communication links between different electronic devices in the substation.

[0087] When grouping multiple electronic devices according to the network topology, for example, devices belonging to the same subnet of the network topology can be grouped into the same group, or multiple electronic devices belonging to the same spatial area in the network topology can be grouped into the same group.

[0088] The deviation of the mean clock deviation of electronic devices within a group from the overall mean can be equal to the absolute value of the difference between the mean clock deviation of electronic devices within the same group and the mean clock deviation of all electronic devices synchronized with the master clock.

[0089] Based on the within-group variance and deviation value of the group, the within-group variance and deviation value can be normalized respectively, and the mean of the normalized within-group variance and deviation value is used as the congestion index of the group.

[0090] The congestion index of a group can reflect the probability that it belongs to the source of network congestion in the entire network topology. The network area corresponding to the group with the largest congestion index among multiple groups can be identified as the congestion source area, which can be used to locate the congestion source area simply and effectively.

[0091] In one embodiment, the monitoring result of the clock deviation type of the clock synchronization state of the substation is determined by using the monitoring feature vectors of the substation at multiple consecutive moments, including: inputting the monitoring feature vectors of the substation at multiple consecutive moments into a pre-trained SVM classifier to obtain the clock deviation type output by the SVM classifier; the SVM classifier is used to output the clock deviation type of the clock synchronization state of the substation.

[0092] The monitoring feature vectors of a substation at multiple consecutive moments can describe the clock synchronization status between the substation's main clock and electronic equipment. SVM (Support Vector Machine) can effectively learn and classify the features of the vectors. Therefore, by inputting the monitoring feature vectors of the substation at multiple consecutive moments into a pre-trained SVM classifier, the pre-trained SVM can learn the correspondence between the clock deviation type of the main clock in historical time periods and multiple monitoring feature vectors. Thus, the SVM can output the classification result of the clock deviation type of the substation's clock synchronization status.

[0093] The SVM classifier can be trained in the following way: obtain the monitoring feature samples of the substation's master clock at multiple historical moments and the clock deviation type label. The monitoring feature samples include the historical monitoring feature vectors of multiple adjacent moments before the corresponding historical moment, and the clock deviation type label is the annotation result of the clock deviation type of the clock synchronization status between the substation's master clock and electronic equipment at the corresponding historical moment.

[0094] The clock skew type label can include multiple labels corresponding to normal clock skew, master clock drift fault, and network congestion fault, respectively. By using the monitoring feature sample as the input of the pre-built initial SVM classifier and the clock skew type label corresponding to the monitoring feature sample as the output of the initial SVM classifier, the initial SVM classifier can be trained to obtain a pre-trained SVM classifier, so as to output the clock skew type using the pre-trained SVM classifier.

[0095] In this way, by training the initial SVM classifier to obtain a pre-trained SVM classifier, it is easier to automatically output the clock deviation type between the substation's main clock and electronic equipment.

[0096] Figure 2 This is a schematic diagram illustrating the structure of an intelligent substation clock synchronization monitoring system 1000 according to an exemplary embodiment. (Refer to...) Figure 2 The intelligent substation clock synchronization monitoring system 1000 includes a processor 1100 and a memory 1200. The memory 1200 stores computer program instructions, which, when executed by the processor 1100, implement all or part of the steps of the intelligent substation clock synchronization monitoring method in this application.

[0097] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only.

[0098] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A method for monitoring clock synchronization in a smart substation, characterized in that, include: The clock deviation values ​​of electronic equipment in the substation at different times within a preset time window are obtained, and the average deviation sequence is determined based on the clock deviation values ​​of multiple electronic devices within the preset time window. The clock deviation value is equal to the time deviation between the electronic device and the master clock; The trend stability value is determined based on the first difference sequence of the average deviation sequence, and the change stability value is determined based on the second difference sequence of the average deviation sequence. The product of the trend stability value and the change stability value is used as the evaluation value. Determining the degree of difference based on the clock deviation values ​​of multiple electronic devices at a target time includes: sorting the clock deviation values ​​of multiple electronic devices at the target time in ascending order to obtain a sorted sequence, and performing nonnegation processing on the elements in the sorted sequence to obtain a nonnegative sorted sequence; degree of difference value Where N is the number of elements in the non-negative sorted sequence. This represents the i-th clock offset value in the non-negative sorted sequence; A monitoring feature vector for the target time is constructed using the degree of difference value and the evaluation value; the degree of difference value is used to characterize the degree of difference in clock deviation values ​​of different electronic devices at the target time; By utilizing the monitoring feature vectors of the substation at multiple consecutive moments, the monitoring results of the clock deviation type of the substation's clock synchronization status are determined, and monitoring prompt information is output based on the monitoring results.

2. The intelligent substation clock synchronization monitoring method according to claim 1, characterized in that, Determining the stability value of the trend based on the first-order difference sequence of the average deviation sequence includes: ,in, This represents the stability value of the changing trend, where M is the number of sampling points within a preset time window. Let be the j-th value in the first-order difference sequence, and ln be the logarithmic function with the natural constant as the base; ,like equal ,but ;like Not equal to ,but ; For symbolic functions, To avoid using a preset positive number with a denominator of 0, To take the absolute value.

3. The intelligent substation clock synchronization monitoring method according to claim 1, characterized in that, Determining the stability value of the change based on the second-order difference sequence of the average deviation sequence includes: , For the stability value of the change, Let M be an exponential function with the natural constant as the base, and M be the number of sampling points within the preset time window. Let be the absolute value of the j-th value in the second-order difference sequence. The standard deviation of the first-order difference sequence of the mean deviation sequence. This is a preset positive number used to avoid denominators of 0.

4. The intelligent substation clock synchronization monitoring method according to claim 1, characterized in that, The average deviation sequence is determined in the following way: The average value of the clock deviation values ​​of multiple electronic devices at the same moment is used as the value of the corresponding moment in the average deviation sequence to obtain the average deviation sequence including the values ​​of different moments within a preset time window.

5. The intelligent substation clock synchronization monitoring method according to claim 1, characterized in that, The degree of difference is determined based on the clock deviation values ​​of multiple electronic devices at the target time, including: The frequency proportion of different clock deviation values ​​among multiple electronic devices at a target time is used to determine the information entropy of clock deviation values ​​with different frequency proportions, and the information entropy is used as the difference degree value.

6. The intelligent substation clock synchronization monitoring method according to claim 1, characterized in that, By utilizing the monitoring feature vectors of the substation at multiple consecutive moments, the monitoring results for the clock deviation type of the substation's clock synchronization status are determined, including: Obtain a pre-built fault model library; the fault model library includes multiple reference feature matrices corresponding to different clock skew types; the different clock skew types include normal clock skew, master clock drift fault, and network congestion fault; The monitoring feature vectors of the substation at multiple consecutive moments are used to form a monitoring feature matrix. The monitoring feature matrix is ​​then compared with the reference feature matrix in the fault model library to obtain the target clock deviation type of the substation's clock deviation state.

7. The intelligent substation clock synchronization monitoring method according to claim 6, characterized in that, When the target clock skew type of the substation's clock skew status is determined to be a network congestion fault, the method further includes: Obtain the network topology of the substation, and group multiple electronic devices according to the network topology. Determine the within-group variance of the clock deviation values ​​of the electronic devices in the group, as well as the deviation of the mean of the clock deviation values ​​of the electronic devices in the group from the overall mean. The congestion index of a group is determined based on its within-group variance and deviation value, and the network region corresponding to the group with the largest congestion index among multiple groups is identified as the congestion source region.

8. The intelligent substation clock synchronization monitoring method according to claim 1, characterized in that, By utilizing the monitoring feature vectors of the substation at multiple consecutive moments, the monitoring results for the clock deviation type of the substation's clock synchronization status are determined, including: The monitoring feature vectors of the substation at multiple consecutive moments are input into a pre-trained SVM classifier to obtain the clock deviation type output by the SVM classifier; the SVM classifier is used to output the clock deviation type of the clock synchronization state of the substation.

9. A smart substation clock synchronization monitoring system, characterized in that, include: A processor and a memory, the memory storing computer program instructions, which, when executed by the processor, implement the smart substation clock synchronization monitoring method according to any one of claims 1-8.

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