Logarithmic pixel signal quantization method and module based on gain dynamic adjustment, and image sensor

Abstract

The invention discloses a logarithmic pixel signal quantization method and module based on gain dynamic adjustment, and an image sensor. The logarithmic pixel signal quantization method comprises the following steps of: converting light current into logarithmic voltage by logarithmic amplification by using a logarithmic response unit; the voltage type comparator compares the logarithmic voltage with a threshold voltage, outputs a gain regulation and control signal for gain configuration of the programmable gain amplifier and input reference voltage switching, enables the programmable gain amplifier to work in different gain modes, and inputs a flag bit to the N-bit analog-to-digital converter; based on the current gain mode, the programmable gain amplifier amplifies the logarithmic voltage and translates the logarithmic voltage into the quantization range of the N-bit analog-to-digital converter to be output; the N-bit analog-to-digital converter samples an output voltage signal of the programmable gain amplifier, combines the output voltage signal with a flag bit, and outputs an N + 1-bit equivalent digital code value signal. According to the invention, high-sensitivity quantization of low-light-intensity signals and high-precision conversion of high-light-intensity signals are realized at the same time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of CMOS image sensor, and particularly relates to a logarithmic pixel signal quantization method and module based on gain dynamic adjustment and an image sensor. BACKGROUND

[0002] CMOS image sensors have been pursuing wide dynamic range and high sensitivity performance in strong light and dark light. If the slope of the photoelectric conversion characteristic curve (i.e. the light intensity-output signal relationship curve) of the pixel is large, the image sensor can have high sensitivity, but narrow dynamic range. This is because a larger slope indicates that a unit light intensity change can produce a larger signal output change, but at the same time it will also reach saturation faster. Pixels with wide dynamic range require a gentle response slope, and the corresponding sensitivity will deteriorate. Due to the linear characteristics of the light response of traditional pixels, the dynamic range and sensitivity have a trade-off relationship. In order to achieve wide dynamic range and high sensitivity, CMOS image sensors have applied multiple sampling, multiple exposure and other technologies, but these technologies also have disadvantages: introducing noise, increasing power consumption, increasing area, etc.

[0003] In the wide dynamic range technology, the logarithmic pixel has a nonlinear characteristic, the output signal has a logarithmic response, the photoelectric current is fed into a transistor with a logarithmic current-voltage characteristic, and the transistor works in the weak inversion region. The continuously working transistor directly converts the photoelectric current into the corresponding voltage without using any integration process. In this way, the dynamic range is significantly expanded with simple operation and lower cost, and a dynamic range of more than 120dB can be usually presented. The logarithmic response maintains the sensitivity of the approximate linear response at low illumination, and compresses the high illumination image with logarithmic response, effectively preventing image lag at low illumination, and expanding the dynamic range by preserving the details of dark and overexposed areas. However, the output swing of the pixel is generally a few hundred millivolts, the sensitivity is low, and the limited voltage swing also reduces the signal-to-noise ratio, which seriously affects the image quality. But in terms of dynamic range, this method is the most effective technology.

[0004] For the quantization of the pixel light intensity voltage output, the single-slope analog-to-digital converter (SS-ADC) has been widely used in CMOS image sensors with column-parallel architecture, which is composed of a ramp generator, a comparator, and a counter. The SS-ADC generates a linear ramp signal, and the counter quantizes at a constant frequency, so the normal SS-ADC has a linear response. In order to achieve wide dynamic range imaging, existing research has used an exponential type ramp signal, or a logarithmic type counter frequency, but this method has the disadvantages of steep conversion rate, complex compensation circuit, etc. The traditional fixed gain quantization scheme cannot meet the quantization requirements of the high slope region (easy to saturate) and the low slope region (insufficient resolution) of the logarithmic curve at the same time.

[0005] Therefore, how to achieve high linearity and low power consumption quantization of logarithmic voltage with a wide dynamic range and low power consumption while maintaining hardware efficiency with a limited number of ADC bits has become an urgent problem to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide a logarithmic pixel signal quantization method and module, as well as an image sensor, based on dynamic gain adjustment to address the signal quantization problem in wide dynamic range imaging scenarios. Through an adaptive gain switching mechanism, it simultaneously achieves high-sensitivity quantization of low-intensity signals and high-precision conversion of high-intensity signals, effectively expanding the dynamic range of the imaging system.

[0007] In a first aspect, the present invention provides a logarithmic pixel signal quantization method based on dynamic gain adjustment, comprising:

[0008] Using a logarithmic response unit to convert photocurrent I ph Logarithmic amplification to logarithmic voltage V log Post-input voltage comparator and programmable gain amplifier;

[0009] The voltage comparator converts the logarithmic voltage V log With the preset threshold voltage V th A comparison is performed, and based on the comparison result, a gain control signal is output for the gain configuration and input reference voltage switching of the programmable gain amplifier, enabling the programmable gain amplifier to operate in different gain modes, and a flag bit is input to the N-bit analog-to-digital converter; the programmable gain amplifier, based on the current gain mode, adjusts the logarithmic voltage V... log Amplify and shift the output to the quantization range of the N-bit analog-to-digital converter;

[0010] The N-bit analog-to-digital converter samples the output voltage signal of the programmable gain amplifier and combines it with the flag bit to output an N+1-bit equivalent digital code value signal.

[0011] Where, if the logarithmic voltage V log <threshold voltage V th The programmable gain amplifier operates in the first gain mode; if the logarithmic voltage V log Threshold voltage V th The programmable gain amplifier operates in the second gain mode.

[0012] The first gain mode is a low gain mode, and the second gain mode is a high gain mode.

[0013] In the first gain mode, the programmable gain amplifier receives a first input reference voltage; in the second gain mode, the programmable gain amplifier receives a second input reference voltage.

[0014] The voltage comparator is connected to the programmable gain amplifier via a complementary switch controlled by complementary signals amp_low and amp_high, and inputs a gain control signal to the programmable gain amplifier.

[0015] The programmable gain amplifier includes a sampling capacitor C formed by a configurable array of n minimum unit capacitors C0. s The holding capacitance C is formed by a single smallest unit capacitor C0. h Sampling capacitor C s One end of the smallest unit capacitor C0 in the array is connected to the source of the first switch, the drain of switch SW2, and the drain of switch SW3. The other end is connected to one end of the other n-1 smallest unit capacitors C0 connected in parallel, and the holding capacitor C h One end of the capacitor is connected to the source of switch SW1 and the negative input terminal of OPA; the other end of the other n-1 parallel smallest unit capacitors C0 is connected to the drain of the first switch; the holding capacitor C h The other end is connected to the drain of switch SW1, the output of OPA, and the source of switch SW4. The drain of switch SW4 is grounded through a capacitor. The non-inverting input of OPA is connected to the reset voltage V. res The source of switch SW3 is connected to the logarithmic voltage V. log The source of switch SW2 is connected to the drain of the third switch and the second switch, and the sources of the third switch and the second switch are each connected to the first input reference voltage V. in_cm1 The second input reference voltage V in_cm2 The complementary switching signal output by the voltage comparator is connected to the gate of the third switch, and the signal amp_high is connected to the gates of the first and second switches.

[0016] The gain of the programmable gain amplifier is determined by the sampling capacitor C. s With holding capacitor C h The ratio determines G=C s / C h When the voltage comparator outputs 0, the first switch is turned off, causing the sampling capacitor C to... s Part of the capacitor is connected to form a low-gain G1=C s1 / C h At the same time, the third switch closes, selecting the first input reference voltage V. in_cm1 When the voltage comparator outputs 1, the first and second switches close, causing the sampling capacitor C to... s High gain G2 = C is achieved by connecting all capacitors in the middle. s2 / C h And switch to the second input reference voltage V in_cm2 .

[0017] The programmable gain amplifier alternately works between a reset mode and an amplification mode.

[0018] In the reset mode, switches sw1 and sw2 are closed, sw3 is disconnected, the gain of the programmable gain amplifier and an input reference voltage are determined; switch sw1 is closed, a reset switch connected across the OPA is turned on, and a holding capacitor C h is emptied, and the output voltage of the programmable gain amplifier is equal to a reset voltage Vres; switch sw2 is closed, a first input reference voltage V in_cm1 / a second input reference voltage V in_cm2 is accessed to a circuit; when the output in the reset mode is stable, switch sw4 is closed, and the reset voltage Vres of the programmable gain amplifier is output and sampled by an N-bit analog-to-digital converter.

[0019] In the amplification mode, switch sw3 is closed, and switches sw1 and sw2 are disconnected; the state of switches (low-gain switches and two high-gain switches or a first switch, a second switch and a third switch) controlled by complementary signals amp_low and amp_high remains unchanged; a logarithmic voltage is connected to a sampling capacitor left plate, and the voltage across the holding capacitor dynamically changes with an input signal; when the output in the amplification mode is stable, switch sw4 remains closed, and the amplification voltage V sig of the PGA is output and sampled by an SS-ADC; the reset voltage Vres is output in the reset mode, and the amplification voltage Vsig is output in the amplification mode.

[0020] The output voltage of the programmable gain amplifier in the amplification mode is calculated according to the following formula:

[0021]

[0022] In a second aspect of the present application, a logarithmic pixel signal quantization module based on gain dynamic adjustment is provided, which comprises:

[0023] a logarithmic response unit, configured to convert a photoelectric current I ph into a logarithmic voltage V log ;

[0024] a voltage-type comparator, configured to compare the logarithmic voltage V log with a preset threshold voltage V th , and output a gain control signal for gain configuration and input reference voltage switching of a programmable gain amplifier according to a comparison result, so that the programmable gain amplifier works in different gain modes and inputs a flag bit to an N-bit analog-to-digital converter;

[0025] the programmable gain amplifier, configured to amplify and shift the logarithmic voltage V log to an output within a quantization range of the N-bit analog-to-digital converter based on a current gain mode.

[0026] The N-bit analog-to-digital converter is used for sampling the output voltage signal of the programmable gain amplifier in different gain modes, and the N+1-bit equivalent digital code value signal is output in combination with the flag bit.

[0027] In a third aspect, the present application provides an image sensor comprising the log pixel signal quantization module based on dynamic gain adjustment.

[0028] The present application divides the log voltage into intervals by using a voltage comparator, dynamically adjusts the gain, and uses a programmable gain amplifier (PGA) to dynamically amplify the log voltage, so as to realize log pixel signal quantization processing based on dynamic gain adjustment. Through the adaptive switching mechanism of the gain, high-sensitivity quantization of low-light intensity signals and high-precision conversion of high-light intensity signals are realized at the same time, and the dynamic range of the imaging system is effectively expanded. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 FIG. 1 is a schematic diagram of a circuit module of a log pixel signal quantization method based on dynamic gain adjustment according to an embodiment of the present application.

[0030] Figure 2 FIG. 2 is a specific implementation schematic diagram of voltage comparator preprocessing according to an embodiment of the present application.

[0031] Figure 3 FIG. 3 is a circuit diagram of a programmable gain amplifier according to an embodiment of the present application.

[0032] Figure 4 FIG. 4 is a working timing diagram of a programmable gain amplifier according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] The present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0034] In exemplary embodiments of the present application, the proposed log pixel signal quantization method based on dynamic gain adjustment is based on Figure 1 The circuit module or structure shown in FIG. 1 is implemented, and the processing steps are as follows:

[0035] First, the log response unit (log I / V) converts the photocurrent I ph into a log voltage V log Then, enter the interval discrimination stage, use a voltage comparator to compare the log voltage V log with the preset threshold voltage V th , and perform interval discrimination, such as discriminating the log voltage V logIn the first interval or the second interval; after the interval discrimination stage is completed, the gain adjustment stage is entered, and the input log voltage V log identified in a discrimination interval, according to the output control of the voltage comparator, the programmable gain amplifier PGA works in the first gain mode or the second gain mode, and the programmable gain amplifier is set as a fixed multiple gain amplifier, which amplifies the log voltage V log and shifts to the quantization range of the SS-ADC (N-bit digital-to-analog converter), and finally enters the analog-to-digital conversion stage, and the voltage of the PGA output is sampled by the SS-ADC, and the output of the voltage comparator is used as a flag bit combined with the output of the N-bit ADC, and an N+1-bit digital code value is output.

[0036] Taking two gain stages as an example, if the log voltage V log <Threshold voltage V th , the PGA adopts the first gain, if V log >V th , the PGA adopts the second gain, corresponding to different gains, the input reference voltage V in_cm of the PGA needs to change accordingly, so as to scale V log in different input ranges to the same output range for AD quantization.

[0037] Figure 2 is a specific implementation diagram of the voltage comparator preprocessing of the embodiment of the application. In the interval discrimination stage, the voltage comparator adjusts the PGA circuit structure through a pair of complementary switches controlled by complementary signals amp_low and amp_high. The voltage comparator has two inputs, which are the input log voltage V log and the set threshold voltage V th . The two are compared, when V log <V th , the voltage comparator outputs 0, so that the PGA works in the first gain mode, adopts low gain and the first input reference voltage V in_cm1 , avoids ADC saturation caused by high slope of the log curve in the low light intensity interval; when V log >V th , the voltage comparator outputs 1, switches to the second gain mode, adopts high gain and the second input reference voltage V in_cm2 , solves the problem of insufficient resolution caused by low slope of the log curve in the high light intensity interval. Through the dynamic gain-common mode collaborative adjustment mechanism, it is ensured that the signals in each interval can be accurately matched after being amplified. The first gain is low gain, which is significantly lower than the design of the second gain, which not only retains the inherent sensitivity in the low light intensity interval, but also improves the quantization accuracy in the high light intensity interval.

[0038] Specifically, as Figure 2The graph shows the quantization response of the logarithmic voltage (V log ) under different gain modes. The horizontal axis represents the input light intensity (corresponding to the logarithmic voltage V log ), and the vertical axis represents the signal quantity (or the final quantization effect) after PGA amplification. The gain switching point Gain Switch Point corresponds to the position of the threshold voltage V th , which is the demarcation point between the low gain region Low Gain Region and the high gain region High Gain Region, i.e., at V log = V th .

[0039] In the low gain region, when V log <V th (low light intensity scenario), the voltage comparator outputs 0, the switch controlled by the signal amp_low is closed, and the PGA works in the low gain mode (first gain). The slope of the line in this region is small, which avoids ADC saturation caused by the high slope of the logarithmic curve under low light intensity, and preserves the sensitivity of the low light intensity signal.

[0040] In the high gain region, when V log >V th (high light intensity scenario), the voltage comparator outputs 1, the switch controlled by the signal amp_high is closed, and the PGA switches to the high gain mode (second gain). The slope of the line in this region is larger, which is used to improve the resolution deficiency caused by the low slope of the logarithmic curve under high light intensity.

[0041] Figure 3 The circuit diagram of the programmable gain amplifier of the embodiment of the present application is shown to further illustrate how the voltage comparator adjusts the gain through the switch controlled by the complementary signals amp_low and amp_high. In the figure, V log represents the logarithmic voltage, V res represents the reset voltage, V in_cm1 represents the first input reference voltage, and V in_cm2 represents the second input reference voltage. The gain is determined by the ratio of the sampling capacitance C s to the holding capacitance C h (G=C s / C h ), where the holding capacitance C h is fixed as the minimum unit C0, and the sampling capacitance C s is designed as a configurable array. The complementary switch signals amp_low and amp_high output by the voltage comparator synchronously control the gain configuration and input reference voltage switching of the PGA: when the comparator outputs 0 (low light intensity interval), the first switch controlled by the signal amp_high is closed, which makes C sPartial access to form low gain G1=C s1 / C h , signal amp_low control switch closed, the first input reference voltage V in_cm1 ; when the comparator output 1 (high light intensity interval), signal amp_high control switch closed, C s full access to achieve high gain G2=C s2 / C h , and switch to the second input reference voltage V in_cm2 .

[0042] In the analog-to-digital conversion phase, the output of the voltage comparator is used as a flag bit to indicate whether the current logarithmic voltage is in the first interval or the second interval. Although the code value range of the ADC output in each interval is the same, the N-bit ADC output N+1-bit digital code value is equivalent to twice the quantization code value range due to the combination of the flag bit.

[0043] Figure 4 The working timing diagram of the PGA of the embodiment of the application is shown.

[0044] The voltage comparator works first to compare the input logarithmic voltage V log and the threshold voltage V th . After the comparison, the result is transmitted to the PGA, and the gain and input reference voltage V in_cm of the PGA are dynamically adjusted by the switches controlled by the complementary signals amp_low and amp_high. The PGA alternately works between the reset mode and the amplification mode.

[0045] In the reset mode, the switches sw1 and sw2 are closed, and sw3 is open. The switches controlled by the complementary signals amp_low and amp_high remain in a stable state during this period, that is, the gain and input reference voltage V in_cm of the PGA are determined. The switch sw1 is closed, the reset switch connected across the operational amplifier (OPA) is turned on, the charge of the capacitor C h is emptied, and the PGA output voltage is equal to the reset voltage Vres. The switch sw2 is closed, and V in_cm1 or V in_cm2 access circuit determined by the voltage comparator preprocessing is connected to the left plate of the sampling capacitor. After the output of the reset mode is stable, the switch sw4 is closed, and the PGA reset voltage Vres output is sampled by the SS-ADC.

[0046] In the amplification mode, switch sw3 is closed, switches sw1 and sw2 are disconnected, and switches (low-gain switch and two high-gain switches, or first switch, second switch, and third switch) controlled by complementary signals amp_low and amp_high remain unchanged, that is, the state in the reset mode is maintained. Due to the closure of sw3 and the disconnection of sw2, the logarithmic voltage is connected to the left plate of the sampling capacitor; sw1 is disconnected, and the voltage across the capacitor dynamically changes with the input signal. After the output in the amplification mode is stable, switch sw4 remains closed, and the PGA amplification voltage V sig The output is sampled by the SS-ADC. The reset mode outputs a reset voltage Vres, and the amplification mode outputs an amplified voltage Vsig; according to the charge conservation principle of the switched-capacitor circuit, the transfer function between the PGA output voltage and the input logarithmic voltage can be represented as:

[0047]

[0048] In the transfer function, V sig represents the output voltage in the PGA amplification mode, V log represents the input logarithmic voltage, C s / C h represents the adjustable gain, which is realized in the circuit by changing the size of the sampling capacitor array through the voltage comparator output; V in_cm represents the adjustable input reference voltage, and the circuit provides a dual-reference voltage source V in_cm1 and V in_cm2 correspond to the first gain and the second gain, respectively; when the PGA selects the first gain, V in_cm1 is connected to the circuit through sw2, and vice versa V in_cm2 is connected to the circuit.

[0049] The gain dynamic adjustment method of the embodiment of the application, in cooperation with the extension of the voltage comparator flag, the N-bit quantization result of the ADC, and the output flag of the voltage comparator, generates an equivalent digital code value of N+1 bits, expands the dynamic range of the ADC, breaks through the limitation of the physical number of bits, saves the complexity of the circuit, effectively solves the problem that resolution and range cannot be compatible in the quantization of the wide dynamic range logarithmic pixel signal, and eliminates the defects of non-linear distortion of the traditional ADC quantization of the logarithmic voltage and limited dynamic range.

[0050] The logarithmic pixel signal quantization method based on dynamic gain adjustment provided by the embodiment of the application meets the technical requirements of wide dynamic range imaging, dynamically amplifies the logarithmic voltage by using a programmable gain amplifier, and combines a comparator flag extension technology.

[0051] Compared with a traditional logarithmic pixel signal quantization scheme, the embodiment of the application prevents ADC quantization saturation in a weak light scene and improves the resolution of ADC quantization in a strong light scene through dynamic gain adjustment, thereby realizing fine quantization in a wide dynamic range. Meanwhile, the effective resolution of an N-bit ADC is extended to an equivalent N+1 bit through a flag bit output by a voltage-type comparator, thereby significantly improving the dynamic range of the system without increasing hardware cost.

[0052] In addition, the embodiment of the application adjusts the corresponding input reference voltage in cooperation with different gain intervals, thereby ensuring that the PGA output always adapts to the quantization range of the ADC, effectively solving the problem that the resolution and the range cannot be compatible in logarithmic voltage quantization in a wide dynamic range, and eliminating the defects of nonlinear distortion of traditional ADC quantization of logarithmic voltage and limited dynamic range.

[0053] The embodiment of the application further provides a logarithmic pixel signal quantization module based on gain dynamic adjustment, as shown in Figure 1 , which comprises:

[0054] a logarithmic response unit, configured to logarithmically amplify a photoelectric current I ph to convert the photoelectric current I log into a logarithmic voltage V log ;

[0055] a voltage-type comparator, configured to compare the logarithmic voltage V log with a preset threshold voltage V th , and output a gain control signal for gain configuration and input reference voltage switching of a programmable gain amplifier according to a comparison result, so that the programmable gain amplifier works in different gain modes and inputs a flag bit to an N-bit analog-to-digital converter;

[0056] the programmable gain amplifier, configured to amplify and shift the logarithmic voltage V log to an output within a quantization range of the N-bit analog-to-digital converter based on a current gain mode;

[0057] the N-bit analog-to-digital converter, configured to sample an output voltage signal of the programmable gain amplifier in different gain modes and combine the flag bit to output an N+1-bit equivalent digital code value signal.

[0058] In the embodiment of the application, after the logarithmic response unit logarithmically amplifies a photoelectric current I ph to convert the photoelectric current I log into a logarithmic voltage V th , an interval discrimination stage is entered, a voltage-type comparator is used to compare the logarithmic voltage with a preset threshold voltage V log , and the input logarithmic voltage is discriminated to determine whether it is in a first interval or a second interval. After the interval discrimination stage is completed, a gain adjustment stage is entered.The programmable gain amplifier is set as a fixed multiple gain amplifier according to the output regulation of the voltage comparator, the logarithmic voltage is amplified and translated into the quantization range of the SS-ADC, and finally enters the analog-digital conversion stage, the ADC samples the voltage output by the PGA, and the output of the voltage comparator is combined with the output of the N-bit ADC as a flag bit, and an N+1-bit digital code value is output.

[0059] For example, if the logarithmic voltage V log <Threshold voltage V th , the PGA adopts the first gain, if V log >V th , the PGA adopts the second gain, and the input reference voltage V in_cm of the PGA also changes accordingly, so as to scale V log in different input ranges to the same output range for AD quantization.

[0060] Figure 2 is a specific implementation schematic diagram of the voltage comparator preprocessing of the embodiment of the application. In the interval discrimination stage, the voltage comparator adjusts the PGA circuit structure through the switch controlled by a pair of complementary signals amp_low and amp_high. The voltage comparator has two inputs, namely the logarithmic input voltage V log and the set threshold voltage V th ; the two are compared, when V log <V th , the voltage comparator outputs 0, so that the PGA works in the first gain mode, adopts low gain and the first input reference voltage V in_cm1 , and avoids ADC saturation caused by high slope of the logarithmic curve in the low light intensity interval; when V log >V th , the voltage comparator outputs 1, switches to the second gain mode, adopts high gain and the second input reference voltage V in_cm2 , and solves the problem of insufficient resolution caused by low slope of the logarithmic curve in the high light intensity interval. The dynamic gain-common mode collaborative adjustment mechanism ensures that the signals in each interval can be accurately matched with the ADC range after amplification. The design that the first gain is significantly lower than the second gain not only retains the inherent sensitivity in the low light intensity interval, but also improves the quantization accuracy in the high light intensity interval.

[0061] Figure 3 The circuit diagram of the programmable gain amplifier of the embodiment of the application is shown, to further illustrate how the voltage comparator adjusts the gain through the switch controlled by the complementary signals amp_low and amp_high. Figure 3 In the formula, V log represents the logarithmic voltage, V res represents the reset voltage, and Vin_cm1 represents the first input reference voltage, V in_cm2 represents the second input reference voltage. The gain is determined by the ratio of the sampling capacitance C s to the holding capacitance C h (G = C s / C h ), where the holding capacitance C h is fixed as the minimum unit C0, and the sampling capacitance C s is designed as a configurable array. The complementary switching signals amp_low and amp_high of the voltage comparator output synchronously control the gain configuration and input reference voltage switching of the PGA: when the comparator output is 0 (low light intensity interval), the first switch controlled by the signal amp_high is open, so that C s is partially connected to form a low gain G1 = C s1 / C h , and the first input reference voltage V in_cm1 is selected when the third switch controlled by the signal amp_low is closed; when the comparator output is 1 (high light intensity interval), the first switch and the second switch controlled by the signal amp_high are closed, so that C s is fully connected to achieve a high gain G2 = C s2 / C h , and the second input reference voltage V in_cm2 is switched to.

[0062] In the analog-to-digital conversion stage, the output of the voltage comparator is used as a flag bit to indicate whether the current logarithmic voltage V log is in the first interval or the second interval. Although the code value range of the ADC output of each interval is the same, in combination with the flag bit of the voltage comparator output and the N-bit ADC output N+1-bit digital code value, the equivalent quantization code value range is doubled.

[0063] Figure 4 The working timing diagram of the PGA of the embodiment of the application is shown. The voltage comparator works first to compare the input logarithmic voltage V log and the threshold voltage V th , and then transmits the result to the PGA to dynamically adjust the gain and the input reference voltage V in_cm of the PGA through the switches controlled by the complementary signals amp_low and amp_high. The PGA alternately works between the reset mode and the amplification mode.

[0064] In the reset mode, the switches sw1 and sw2 are closed, and sw3 is open. The switches controlled by the complementary signals amp_low and amp_high controlled by the voltage comparator output are stable early during this period, that is, the gain and the input reference voltage V in_cmDetermination. Switch sw1 is closed, the reset switch across the op-amp is turned on, and the capacitor C h Charge empty, PGA output voltage is equal to the reset voltage Vres; sw2 is closed, V in_cm1 or V in_cm2 Access circuit, input reference voltage is connected to the left plate of the sampling capacitor. After the output of the reset mode is stable, sw4 is closed, and the PGA reset voltage Vres is output and sampled by the SS-ADC.

[0065] In the amplification mode, switch sw3 is closed, sw1 and sw2 are disconnected, and the switches controlled by the complementary signals amp_low and amp_high remain unchanged. Since sw3 is closed and sw2 is disconnected, the logarithmic voltage is connected to the left plate of the sampling capacitor; sw1 is disconnected, and the voltage across the holding capacitor dynamically changes with the input signal. After the output of the amplification mode is stable, switch sw4 remains closed, and the PGA amplification voltage Vsig is output and sampled by the SS-ADC. The reset mode outputs the reset voltage Vres, and the amplification mode outputs the amplification voltage Vsig; according to the charge conservation principle of the switched-capacitor circuit, the transfer function between the output voltage of the PGA and the input logarithmic voltage can be represented as:

[0066]

[0067] In the transfer function, V sig represents the output voltage in the PGA amplification mode, V log represents the input logarithmic voltage, C s / C h represents the adjustable gain, which is realized in the circuit by changing the size of the sampling capacitor array through the output of the voltage comparator; V in_cm represents the adjustable input reference voltage, and the circuit provides a dual reference voltage source V in_cm1 and V in_cm2 correspond to the first gain and the second gain, respectively, and when the PGA selects the first gain, V in_cm1 is connected to the circuit through sw2, and vice versa V in_cm2 is connected to the circuit.

[0068] The gain dynamic adjustment method of the embodiment of the application cooperates with the extension of the voltage comparator flag, combines the N-bit quantization result of the ADC with the output flag of the voltage comparator, and generates an equivalent digital code value of N+1 bits, thereby extending the dynamic range of the ADC, breaking through the limitation of the physical number of bits, saving the complexity of the circuit, effectively solving the problem that resolution and range cannot be compatible in the quantization of the wide dynamic range logarithmic pixel signal, and eliminating the defects of non-linear distortion of the traditional ADC quantization of the logarithmic voltage and limited dynamic range.

[0069] The logarithmic pixel signal quantization method based on dynamic gain adjustment provided by the embodiments of the present application adopts a programmable gain amplifier to dynamically amplify the logarithmic voltage and combines the voltage type comparator flag bit extension technology. Compared with the traditional logarithmic pixel signal quantization scheme, the embodiments of the present application prevent ADC quantization saturation in a weak light scene through dynamic gain adjustment, improve the resolution of ADC quantization in a strong light scene, and realize fine quantization of a wide dynamic range. Meanwhile, the effective resolution of an N-bit ADC is extended to an equivalent N+1 bit through the flag bit output by the voltage type comparator, which significantly improves the dynamic range of the system without increasing the hardware cost.

[0070] In addition, the different gain intervals are matched with the corresponding input reference voltage adjustment to ensure that the PGA output always adapts to the quantization range of the ADC, effectively solving the problem that the resolution and the range cannot be compatible in the wide dynamic range logarithmic voltage quantization, and eliminating the defects of nonlinear distortion and limited dynamic range of the traditional ADC quantization logarithmic voltage.

[0071] In summary, the embodiments of the present application divide the logarithmic voltage into intervals through the voltage type comparator, dynamically adjust the gain, and adopt a programmable gain amplifier PGA to dynamically amplify the logarithmic voltage, which can realize logarithmic pixel signal quantization processing based on dynamic gain adjustment. Through the adaptive switching mechanism of the gain, high-sensitivity quantization of low light intensity signals and high-precision conversion of high light intensity signals are realized at the same time, effectively expanding the dynamic range of the imaging system.

[0072] The embodiments of the present application further provide an image sensor comprising the logarithmic pixel signal quantization module based on gain dynamic adjustment. The image sensor divides the logarithmic voltage into intervals through the voltage type comparator, dynamically adjusts the gain, and adopts a programmable gain amplifier PGA to dynamically amplify the logarithmic voltage, which can realize logarithmic pixel signal quantization processing based on dynamic gain adjustment. Through the adaptive switching mechanism of the gain, high-sensitivity quantization of low light intensity signals and high-precision conversion of high light intensity signals are realized at the same time, effectively expanding the dynamic range of the imaging system.

[0073] The basic principles and main features of the present application and the advantages of the present application are shown and described above, and it is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be realized in other specific forms without departing from the spirit or essential characteristics of the present application; therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application.

[0074] Furthermore, it should be understood that although the specification is described in terms of embodiments, not every embodiment includes every feature described. The specification can include implicit combinations of explicitly mentioned features and / or explicit combinations of implicitely mentioned features. Each embodiment depends on the explicit combinations of features and / or the implicit combinations of features made specifically within that embodiment, and each such embodiment can be combined with every other such embodiment to create further embodiments.

Claims

1. A method of quantizing a log pixel signal based on gain dynamic adjustment, characterized by, The method comprises the following steps: The photo current I is converted into a logarithmic voltage V by a logarithmic response unit ph The logarithmic amplification is converted into a logarithmic voltage V log A post input voltage comparator and programmable gain amplifier The voltage type comparator compares the logarithmic voltage V log with a preset threshold voltage V th , and outputs a gain control signal for gain configuration and input reference voltage switching of the programmable gain amplifier according to a comparison result, so that the programmable gain amplifier works in different gain modes and inputs a flag bit to an N-bit analog-to-digital converter; the programmable gain amplifier amplifies and translates the logarithmic voltage V log to an output within an SS-ADC quantization range based on a current gain mode. The N-bit analog-to-digital converter samples the output voltage signal of the programmable gain amplifier, and combines the flag bit to output an N+1-bit equivalent digital code value signal.

2. The method of claim 1, wherein the gain is adjusted based on a difference between a maximum value of the log pixel signal and a minimum value of the log pixel signal. If the logarithmic voltage V log < threshold voltage V th , the programmable gain amplifier operates in a first gain mode; if the logarithmic voltage V log > threshold voltage V th , the programmable gain amplifier operates in a second gain mode.

3. The method of claim 2, wherein the gain is adjusted based on a difference between the quantized log pixel signal and the log pixel signal. The first gain mode is a low gain mode, and the second gain mode is a high gain mode.

4. The method of claim 3, wherein the gain is adjusted based on a difference between the first and second pixel signal values. In the first gain mode, the programmable gain amplifier inputs a first input reference voltage. In the second gain mode, the programmable gain amplifier inputs a second input reference voltage.

5. The method of claim 1, wherein the gain is adjusted based on a difference between a maximum value of the log pixel signal and a minimum value of the log pixel signal. The voltage comparator is connected to the programmable gain amplifier through complementary switches controlled by complementary signals amp_low and amp_high, and inputs a gain control signal to the programmable gain amplifier.

6. The method of claim 5, wherein the gain is adjusted based on a difference between the first and second pixel signal values. The programmable gain amplifier comprises a sampling capacitor C formed in a configurable array of n minimum unit capacitors C0 s , a holding capacitor C formed by one minimum unit capacitor C0 h ; one end of one minimum unit capacitor C0 in the array of sampling capacitors C s is connected to the source of the first switch, the drain of switch SW2, and the drain of switch SW3, and the other end is connected to one end of n-1 minimum unit capacitors C0 in parallel, one end of holding capacitor C h , the source of switch SW1, and the negative phase input of OPA, the other end of the n-1 minimum unit capacitors C0 in parallel is connected to the drain of the first switch; the other end of holding capacitor C h is connected to the drain of switch SW1, the output of OPA, and the source of switch SW4, the drain of switch SW4 is connected to ground through a capacitor, and the positive phase input of OPA is connected to a reset voltage V res ; the source of switch SW3 is connected to a logarithmic voltage V log , the source of switch SW2 is connected to the drain of a third switch and a second switch, and the sources of the third switch and the second switch are respectively connected to a first input reference voltage V in_cm1 , a second input reference voltage V in_cm2 ; the signal amp_low of the complementary switch signal output by the voltage comparator is connected to the gate of the third switch, and the signal amp_high is connected to the gates of the first switch and the second switch.

7. The method of claim 6, wherein the gain is adjusted based on a difference between the quantized log pixel signal and the log pixel signal. The gain of the programmable gain amplifier is determined by the sampling capacitor C. s With holding capacitor C h The ratio determines G=C s / C h When the voltage comparator outputs 0, the first switch is turned off, causing the sampling capacitor C to... s Part of the capacitor is connected to form a low-gain G1=C s1 / C h At the same time, the third switch closes to select the first input reference voltage V. in_cm1 When the voltage comparator outputs 1, the first and second switches close, causing the sampling capacitor C to... s High gain G2 = C is achieved by connecting all capacitors in the middle. s2 / C h And switch to the second input reference voltage V in_cm2 . ​ 8. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 7, characterized in that, The programmable gain amplifier alternately works between a reset mode and an amplification mode. In the reset mode, the switches sw1, sw2 are closed, sw3 is open, the gain of the programmable gain amplifier and the input reference voltage are determined; the switch sw1 is closed, the reset switch across the OPA is turned on, and the capacitor C is kept h empty, the output voltage of the programmable gain amplifier is equal to the reset voltage Vres; the switch sw2 is closed, the first input reference voltage V in_cm1 / the second input reference voltage V in_cm2 is accessed to the circuit; when the output in the reset mode is stable, the switch sw4 is closed, the reset voltage Vres of the programmable gain amplifier is output, and is sampled by the N-bit analog-to-digital converter; In the amplification mode, switch sw3 is closed, sw1, sw2 are opened, the state of the switches controlled by complementary signals amp_low, amp_high remains unchanged; the logarithmic voltage is connected to the left plate of the sampling capacitor, the voltage across the capacitor dynamically changes with the input signal, and when the output of the amplification mode is stable, switch sw4 remains closed, and the PGA amplification voltage V sig The output is sampled by the SS-ADC; the reset mode outputs a reset voltage Vres, and the amplification mode outputs an amplified voltage Vsig; the output voltage of the programmable gain amplifier in the amplification mode is calculated according to the following formula:

9. A log pixel signal quantization module based on dynamic adjustment of gain, characterized in that, The method comprises the following steps: a logarithmic response unit for converting the photocurrent I ph into a logarithmic voltage V log ; A voltage comparator is used to compare the logarithmic voltage V log with a preset threshold voltage V th According to the comparison result, a gain control signal for gain configuration and input reference voltage switching of a programmable gain amplifier is outputted, so that the programmable gain amplifier works in different gain modes, and a mark bit is inputted to an N-bit analog-to-digital converter. The programmable gain amplifier is configured to amplify and shift the logarithmic voltage V log to an output within a SS-ADC quantization range. The N-bit analog-to-digital converter samples the output voltage signal of the programmable gain amplifier in different gain modes, and combines the flag bit to output an N+1-bit equivalent digital code value signal.

10. An image sensor, characterized by, The logarithmic pixel signal quantization module based on gain dynamic adjustment comprises the gain dynamic adjustment module.

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