High voltage semiconductor device and method of manufacturing the same

Abstract

The application provides a high-voltage semiconductor device and a manufacturing method thereof. A field plate slot is etched in a drift region in a traditional active region etching step, and doped polysilicon is filled in the slot in a subsequent process to form an embedded field plate structure. Compared with the prior art, the process reliability problem caused by a large-size contact hole is completely solved, and the device performance is improved while the manufacturing cost is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a high-voltage semiconductor device and its manufacturing method. Background Technology

[0002] High-voltage lateral double-diffused metal-oxide-semiconductor (HV LDMOS) devices are widely used in power integrated circuits. To withstand high drain voltages, traditional LDMOS devices require a long drift region and a field plate structure above it to alleviate electric field concentration.

[0003] In existing technologies, such as Figure 1 As shown, field plates often adopt a contact via field plate (CFP) structure 100, which achieves electrical connection through tungsten-filled contact holes. However, as the device size increases, the contact hole size also increases, resulting in incomplete tungsten filling and voids, which in turn cause metal peeling and device failure.

[0004] To address this issue, existing technologies attempt to increase the thickness of tungsten deposition, but this leads to problems such as silicon wafer warping, stress changes, and increased target material costs, and remains ineffective, especially in the case of large-size contact holes (e.g., >1μm). Summary of the Invention

[0005] The purpose of this invention is to provide a high-voltage semiconductor device and its manufacturing method to solve one or more problems existing in the formation of existing field plate structures.

[0006] To address the above problems, the present invention provides a method for manufacturing a high-voltage semiconductor device, comprising:

[0007] A substrate is provided, and the substrate is etched with an active region to simultaneously form STI trenches and field plate grooves in the substrate, the field plate grooves being formed within the drift region of the active region;

[0008] Deposit an STI oxide layer to fill the STI trenches and the field plate strip grooves;

[0009] The STI oxide layer in the field plate groove is etched to retain an STI oxide layer of predetermined thickness in the field plate groove as a field plate dielectric layer;

[0010] A doped polysilicon layer is formed on the substrate, and the doped polysilicon layer and the gate oxide layer are etched to form a field plate structure, the field plate structure filling the area of ​​the field plate groove that is not filled by the field plate dielectric layer;

[0011] A metal silicide process is performed to form a metal silicide layer, the metal silicide layer being formed at least on the surface of the field plate structure;

[0012] An interlayer dielectric layer is deposited, the interlayer dielectric layer covering the field plate structure and the substrate surface; and...

[0013] The interlayer dielectric layer is etched to form contact holes, the positions of which correspond to the formation positions of the metal silicide layer.

[0014] Optionally, in the manufacturing method of the high-voltage semiconductor device, the critical dimension of the contact hole is less than 0.6 μm.

[0015] Optionally, in the manufacturing method of the high-voltage semiconductor device, the predetermined thickness is taken as 1000 Å to 1500 Å.

[0016] Optionally, in the manufacturing method of the high-voltage semiconductor device, after etching the STI oxide layer in the field plate groove and before forming a doped polysilicon layer on the substrate, the manufacturing method further includes: performing trap ion implantation in the active region to form a drift region, a body region and a source region.

[0017] Optionally, in the method for manufacturing the high-voltage semiconductor device, before forming a doped polysilicon layer on the substrate, the method further includes: growing a gate oxide layer on the substrate;

[0018] The doped polysilicon layer covers the gate oxide layer, and the gate structure and the field plate structure are formed simultaneously by etching the doped polysilicon layer and the gate oxide layer simultaneously; the metal silicide layer also covers the surface of the gate structure.

[0019] Optionally, in the manufacturing method of the high-voltage semiconductor device, the thickness of the doped polycrystalline silicon layer is 2000Å~3000Å, and the sheet resistance is 2000Ω~3000Ω.

[0020] Optionally, in the manufacturing method of the high-voltage semiconductor device, the metal silicide includes cobalt silicide.

[0021] Optionally, in the manufacturing method of the high-voltage semiconductor device, when depositing the STI oxide layer, the STI oxide layer fills the STI trench and the field plate strip groove while also covering the surface of the substrate;

[0022] Before etching the STI oxide layer and before performing trap ion implantation, the manufacturing method further includes performing a chemical mechanical polishing process on the remaining STI oxide layer until the surface of the substrate is exposed.

[0023] Optionally, in the method for manufacturing the high-voltage semiconductor device, before depositing the STI oxide layer, the method further includes: forming a protective layer on the surface of the substrate, the protective layer serving as a barrier layer for the chemical mechanical polishing process.

[0024] Optionally, in the manufacturing method of the high-voltage semiconductor device, the material of the protective layer includes silicon nitride.

[0025] The present invention also provides a high-voltage semiconductor device, the high-voltage semiconductor device comprising:

[0026] A substrate having STI trenches formed therein for isolating an active region, and a field plate strip groove formed therein;

[0027] The STI oxide layer fills the STI trench and covers the sidewalls and bottom wall of the field plate groove. The STI oxide layer located in the field plate groove constitutes the field plate dielectric layer.

[0028] A field plate structure, wherein the field plate structure fills the area of ​​the field plate groove that is not filled by the field plate medium layer;

[0029] A metal silicide layer, the surface of the field plate structure being covered by the metal silicide layer; and,

[0030] An interlayer dielectric layer covers the substrate and the metal silicide layer, and contact holes are formed in the interlayer dielectric layer, the positions of which correspond to the formation positions of the metal silicide layer.

[0031] In summary, the high-voltage semiconductor device and its manufacturing method provided by this invention simultaneously etch field plate grooves within the drift region during the conventional active region etching step, and then fill the grooves with doped polysilicon in subsequent processes to form an embedded field plate structure. Compared with the prior art, it has the following advantages:

[0032] (1) Completely solves the process reliability problem caused by large-size contact holes: In the prior art, metal field plates need to be connected through contact holes with a size greater than 1μm, which easily leads to incomplete tungsten filling and voids, which in turn causes defects such as metal layer peeling, seriously damaging the yield; The present invention uses an embedded polycrystalline silicon field plate, whose surface is treated with metal silicide, and low resistance connection can be achieved by using small-size contact holes that are mature in standard logic processes, completely eliminating various process defects caused by the difficulty of filling large-size contact holes, and significantly improving the manufacturing yield;

[0033] (2) While improving device performance, manufacturing costs are significantly reduced: This invention integrates the formation of the field plate structure into the front-end process, and uses the active region etching step to form the field plate pattern simultaneously without adding any additional photomask. This not only avoids the huge cost of adding a photomask, but also the embedded polysilicon field plate structure can more effectively modulate the electric field of the drift region, further optimizing the performance balance of breakdown voltage (BV) and on-resistance (Rdson). Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a high-voltage semiconductor device in the prior art;

[0035] Figure 2 A flowchart illustrating a method for manufacturing a high-voltage semiconductor device according to an embodiment of the present invention;

[0036] Figures 3-10 for Figure 2 Schematic diagrams of the device structures corresponding to each step in the process;

[0037] In the attached image:

[0038] 100-CFP structure;

[0039] 11-Substrate; 12-Protective layer; 13-STI oxide layer; 131-Field plate dielectric layer; 141-Drift region; 142-Bulk region; 143-Source region; 144-Drain region; 151-Gate oxide layer; 152-Doped polysilicon layer; 15-Gate structure; 16-Field plate structure; 17-Metal silicide layer;

[0040] 101-STI groove; 102-Field plate strip groove; 103-Contact hole. Detailed Implementation

[0041] The high-voltage semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may have different emphases and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element would now be below that element.

[0042] like Figure 2As shown, this embodiment of the invention provides a method for manufacturing a high-voltage semiconductor device, comprising the following steps:

[0043] S1, providing a substrate and etching the active region of the substrate to simultaneously form STI trenches and field plate grooves in the substrate, the field plate grooves being formed within the drift region of the active region;

[0044] S2, deposit an STI oxide layer to fill the STI trenches and the field plate strip grooves;

[0045] S3, etch the STI oxide layer in the field plate groove to retain an STI oxide layer of predetermined thickness in the field plate groove as the field plate dielectric layer;

[0046] S4, a doped polysilicon layer is formed on the substrate, and the doped polysilicon layer is etched to form a field plate structure, the field plate structure filling the area of ​​the field plate groove that is not filled by the field plate dielectric layer;

[0047] S5, Perform a metal silicide process to form a metal silicide layer, the metal silicide layer being formed at least on the surface of the field plate structure;

[0048] S6, depositing an interlayer dielectric layer, the interlayer dielectric layer covering the field plate structure and the substrate surface; and...

[0049] S7, the interlayer dielectric layer is etched to form contact holes, the positions of which correspond to the formation positions of the metal silicide layer.

[0050] The manufacturing method provided in this invention uses an embedded polysilicon field plate. After the surface of the field plate is treated with metal silicide, low-resistance connections can be achieved using small-sized contact holes, which are mature in standard logic processes. This completely eliminates various process defects caused by the difficulty of filling large-sized contact holes, and significantly improves the manufacturing yield. In addition, the formation of the field plate structure is integrated into the front-end process. The field plate pattern is formed simultaneously using the active region etching step, without the need to add any additional photomask. This not only avoids the huge cost of adding a photomask, but also allows the embedded polysilicon field plate structure to more effectively modulate the electric field in the drift region, further optimizing the performance balance between breakdown voltage (BV) and on-resistance (Rdson).

[0051] The following combination Figures 3-8 The manufacturing method provided in the embodiments of the present invention will be further described.

[0052] First, such as Figure 3As shown, step S1 is performed by providing a substrate 11 and etching the active region of the substrate 11 to simultaneously form an STI (shallow trench isolation) trench 101 and a field plate groove 102 in the substrate 11. The STI trench 101 defines the isolation region between adjacent active regions, and the field plate groove 102 is formed within the drift region of the active region. Therefore, it can be understood that the field plate groove 102 is formed between two adjacent STI trenches 101.

[0053] The width of the field plate groove 102 determines the width of the subsequently formed field plate structure. Using the manufacturing method provided in this embodiment, the width of the field plate structure can be increased as the pressure resistance requirement increases. By simply designing the width of the field plate groove 102 according to the target width of the field plate structure, the final width of the field plate structure can meet the target requirement.

[0054] Secondly, such as Figure 4 As shown, step S2 is performed to deposit an STI oxide layer 13 to fill the STI trench 101 and the field plate strip groove 102.

[0055] Preferably, the oxide layer used to fill the STI trench 101 and the field plate strip groove 102 is formed by HDP-CVD (high-density plasma chemical vapor deposition) process, which can achieve void-free filling through the mechanism of simultaneous deposition and sputtering.

[0056] To achieve planarization, when depositing the STI oxide layer 13, the STI oxide layer 13 fills the STI trench 101 and the field plate strip groove 102, and also covers the surface of the substrate 11. Then, the excess STI oxide layer 13 on the surface is removed by a chemical mechanical polishing process.

[0057] Please combine Figure 3 Preferably, after providing the substrate 11, a protective layer 12 is formed on the surface of the substrate 11, the protective layer 12 serving as a barrier layer for subsequent chemical mechanical polishing processes. The STI trench 101 and the field plate stripe 102 are formed by sequentially etching the protective layer 12 and the substrate 11.

[0058] Next, as Figure 5 As shown, step S3 is performed to etch the STI oxide layer 13 within the field plate groove 102 to thin the STI oxide layer 13 within the field plate groove 102, retaining a predetermined thickness of STI oxide layer 13 as the field plate dielectric layer 131. The retained field plate dielectric layer 131 covers the sidewalls and bottom wall of the field plate groove 102, and the unfilled area within the field plate groove 102 serves as a window for subsequent formation of the field plate structure.

[0059] The dielectric layer 131 of the field plate serves as an isolation layer between the field plate structure and the substrate 11 (drift region), and its thickness directly determines the effect of the field plate in modulating the surface electric field. The filling and then etch-back process ensures the consistency and accuracy of the dielectric layer thickness. Preferably, the predetermined thickness is between 1000 Å and 1500 Å. Within this range, the field plate maintains a sufficiently close fixed distance from the silicon surface of the drift region, thereby most effectively flattening the surface electric field distribution and improving the device's breakdown voltage.

[0060] Since the STI oxide layer 13 fills the STI trench 101 and the field plate groove 102 while also covering the surface of the substrate 11, after etching the STI oxide layer 13 within the field plate groove 102 is completed, as... Figure 6 As shown, the STI oxide layer 13 on the surface is removed by chemical mechanical polishing.

[0061] After performing step S3 and before performing step S4, such as Figure 7 As shown, the manufacturing method provided in this embodiment may further include: performing trap ion implantation in the active region to form a drift region 141, a body region 142, a source region 143, and a drain region 144.

[0062] Understandably, taking a P-type substrate 11 as an example, for high-voltage semiconductor devices, well region ion implantation in the active region generally includes:

[0063] (1) Drift region 141 implantation: Using a drift region photomask, a window is opened above the long strip-shaped active region that is planned to be the drift region 141. A lightly doped N-type region is formed by implanting N-type impurity ions such as phosphorus (P) or arsenic (As) with medium dose and medium-high energy to deplete and withstand high voltage.

[0064] (2) Body region 142 implantation: After the drift region 141 is implanted, a P-type body mask is used to open a window in the area where the source is to be fabricated. This window will cover part of the drift region 141. Then, a P-type region is formed by boron ion implantation with a medium dose and energy to construct an NMOS channel and prevent the source region from penetrating with the drift region 141.

[0065] (3) Source region 143 and drain region 144 are implanted by high dose low energy arsenic ion implantation to form source region 143 and drain region 144, wherein source region 143 ions are implanted into P body region 142 and drain region 144 ions are implanted into the end of drift region 141.

[0066] Then, as Figure 8 and Figure 9As shown, step S4 is performed to form a doped polysilicon layer 152 on the substrate 11 and to etch the doped polysilicon layer 152 to form a field plate structure 16, the field plate structure 16 at least filling the area of ​​the field plate groove 102 that is not filled by the field plate dielectric layer 131; and step S5 is performed to perform a metal silicide process to form a metal silicide layer 17 on the surface of the field plate structure 16.

[0067] In the manufacture of high-voltage semiconductor devices, after ion implantation in the trap region, a step of forming a gate structure is generally included. In this embodiment, preferably, as follows: Figure 9 As shown, the field plate structure 16 and the gate structure 15 are formed simultaneously. This is achieved by growing a gate oxide layer 151 and forming a doped polysilicon layer 152 on the substrate 11, and then etching the doped polysilicon layer 152 and the gate oxide layer 151. Furthermore, during the metal silicide process in step S5, a metal silicide layer 17 is also simultaneously formed on the surface of the gate structure 15. Since the surfaces of the source region 143 and the drain region 144 are also exposed during the metal silicide process, the metal silicide layer 17 is also simultaneously formed on the surfaces of the source region 143 and the drain region 144.

[0068] Specifically, step S4 may include:

[0069] S41, a gate oxide layer 151 is formed on the entire wafer surface through a high-temperature thermal oxidation process;

[0070] S42, selectively etch the gate oxide layer 151 to at least expose the field plate groove 102;

[0071] S43 uses LPCVD (low-pressure chemical vapor deposition) to deposit an undoped polycrystalline silicon (α-Si) layer;

[0072] S44, the polysilicon layer and gate oxide layer 151 are etched to form the gate structure 15. After etching, the source region 143 and the drain region 144 are also exposed.

[0073] The gate structure 15 and the field plate structure 16 are formed in the same photolithography process. This reduces the number of photolithography steps, thereby reducing manufacturing costs and improving production efficiency. It also enables self-alignment between the gate structure 15 and the field plate structure 16, eliminating alignment errors.

[0074] Since the doped polysilicon layer 152 forming the gate structure 15 has a certain thickness, and the field plate structure 16 is formed simultaneously with the gate structure 15, a portion of the final field plate structure 16 will protrude from the surface of the substrate 11. Furthermore, since the doped polysilicon layer 152 will have a partial depression above the field plate groove 102 after deposition, the surface of the final field plate structure 16 will also have a partial depression. This depression can increase the area of ​​the metal silicide subsequently formed on the surface of the field plate structure 16, thereby further reducing the contact resistance.

[0075] Preferably, the thickness of the doped polysilicon layer 152 is 2000 Å to 3000 Å, and the sheet resistance is 2000 Ω to 3000 Ω. Choosing a thickness of 2000 Å to 3000 Å for the doped polysilicon layer 152 ensures reliable filling and compatibility with existing processes, while selecting a sheet resistance of 2000 Ω to 3000 Ω enables optimal electric field modulation, improving breakdown voltage while ensuring device stability and reliability.

[0076] Optionally, the material of the metal silicide layer 17 may be cobalt silicide (CoSi2). In other embodiments, the metal silicide layer 17 may also be made of materials that can reduce contact resistance, such as nickel silicide (NiSi) or titanium silicide (TiSi2).

[0077] In this embodiment, the width of the field plate structure 16 is controlled by the size of the polycrystalline silicon material (doped polycrystalline silicon material itself has a certain conductivity) in the field plate groove 102. Based on this, after metallization treatment of the field plate surface, low-resistance contact can be achieved synchronously with the source, drain and gate, so that the field plate contact hole size can be reduced to the standard logic process level. This completely avoids the process defects such as tungsten filling voids and metal layer peeling caused by large contact holes in traditional metal field plates, greatly improving yield and reducing manufacturing costs.

[0078] from Figure 9 As can be seen, the field plate structure 16 formed by the manufacturing method provided in this embodiment is an embedded field plate structure 16, which not only has a simple process (the field plate pattern can be formed simultaneously by the etching step of the active region 143), but also has the following advantages compared with the field plate formed on the surface of the substrate 11:

[0079] (1) The effectiveness of the field plate modulating the electric field depends on its distance from the drift region 141. By slotting and subsequently filling with polysilicon, the lower surface of the field plate is "embedded" in the silicon substrate 11. This makes the distance between the field plate and the critical point of the silicon surface of the drift region 141 closer, which can more effectively flatten the electric field distribution on the surface, thereby improving the breakdown voltage more efficiently.

[0080] (2) The field plate is formed on the surface of the substrate 11 and is easily affected by unstable interface charge. The embedded field plate is isolated from the substrate 11 by a thermal oxide layer, which has better interface quality, is less affected by surface charge, and has more stable performance.

[0081] Finally, as Figure 10 As shown, step S6 is performed to deposit an interlayer dielectric layer 18, and step S7 is performed to etch the interlayer dielectric layer 18 to form a contact hole 103. The position of the contact hole 103 corresponds to the formation position of the metal silicide layer 17. The contact hole 103 is used to achieve electrical connection between the source region 143, the drain region 144, the gate structure 15, the field plate structure 16 and the metal layer subsequently formed on the interlayer dielectric layer 18 by filling with a metal conductive material (generally tungsten).

[0082] Since the width of the field plate structure 16 is controlled by the size of the polysilicon material filling the field plate groove 102 in this embodiment, the critical size of the contact hole used to achieve electrical connection can be less than 0.6 μm, and no voids will be generated when the deposition thickness of the contact hole metal material is 3000 Å ~ 5000 Å.

[0083] In addition, embodiments of the present invention also provide a high-voltage semiconductor device, please refer to [link to relevant documentation]. Figure 10 and combined Figure 1 The high-voltage semiconductor device includes:

[0084] Substrate 11, wherein an STI trench 101 for isolating the active region is formed therein, and a field plate strip groove 102 is formed therein in the active region;

[0085] STI oxide layer 13, the STI oxide layer 13 fills the STI trench 101 and covers the sidewalls and bottom wall of the field plate strip groove 102, the STI oxide layer 13 located in the field plate strip groove 102 constitutes the field plate dielectric layer 131;

[0086] Field plate structure 16, which fills the area of ​​the field plate groove 102 that is not filled by the field plate medium layer 131;

[0087] A metal silicide layer 17, the surface of the field plate structure 16 is covered by the metal silicide layer 17; and,

[0088] An interlayer dielectric layer 18 covers the substrate and the metal silicide layer 17. A contact hole 103 is formed in the interlayer dielectric layer 18, and the position of the contact hole 103 corresponds to the position of the metal silicide layer 17.

[0089] The high-voltage semiconductor device provided in this embodiment of the invention can be manufactured using the manufacturing method described in this embodiment. Corresponding to the manufacturing method described above, the active region of the substrate of the high-voltage semiconductor device has a drift region 141, a body region 142, a source region 143, and a drain region 144 formed by ion implantation. A gate structure 15 is also formed on the surface of the substrate 11. A metal silicide layer 17 is formed on the surface of the field plate structure 16, and also on the surfaces of the gate structure 15, the source region 143, and the drain region 144. Contact holes 103 are formed above the metal silicide layers 17 at different locations. After filling each contact hole 103 with conductive material, electrical connections are respectively established between the source region 143, the drain region 144, the gate structure 15, the field plate structure 16, and the metal layers subsequently formed on the interlayer dielectric layer 18.

[0090] In summary, the high-voltage semiconductor device and its manufacturing method provided by this invention simultaneously etch field plate grooves within the drift region during the conventional active region etching step, and then fill the grooves with doped polysilicon in subsequent processes to form an embedded field plate structure. Compared with the prior art, it has the following advantages:

[0091] (1) Completely solves the process reliability problem caused by large-size contact holes: In the prior art, metal field plates need to be connected through contact holes with a size greater than 1μm, which easily leads to incomplete tungsten filling and voids, which in turn causes defects such as metal layer peeling, seriously damaging the yield; The present invention uses a polysilicon field plate that is integrated synchronously with the gate. After its surface is treated with metal silicide, it can use the mature small-size contact holes in the standard logic process to achieve low resistance connection, completely eliminating various process defects caused by the difficulty of filling large-size contact holes, and significantly improving the manufacturing yield;

[0092] (2) While improving device performance, manufacturing costs are significantly reduced: This invention integrates the formation of the field plate structure into the front-end process, and uses the active region etching step to form the field plate pattern simultaneously without adding any additional photomask. This not only avoids the huge cost of adding a photomask, but also the embedded polysilicon field plate structure can more effectively modulate the electric field of the drift region, further optimizing the performance balance of breakdown voltage (BV) and on-resistance (Rdson).

[0093] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method of manufacturing a high voltage semiconductor device, characterized by, The method comprises the following steps: providing a substrate and etching an active region on the substrate to form an STI trench and a field plate strip groove in the substrate simultaneously, the field plate strip groove being formed in a drift region of the active region; depositing an STI oxide layer to fill the STI trench and the field plate strip groove; etching the STI oxide layer in the field plate strip groove to keep a predetermined thickness of the STI oxide layer as a field plate dielectric layer in the field plate strip groove; forming a doped polysilicon layer on the substrate and etching the doped polysilicon layer to form a field plate structure, the field plate structure filling at least a region of the field plate strip groove which is not filled by the field plate dielectric layer; performing a metal silicide process to form a metal silicide layer, the metal silicide layer being formed at least on a surface of the field plate structure; depositing an interlayer dielectric layer, the interlayer dielectric layer covering the field plate structure and a surface of the substrate; and etching the interlayer dielectric layer to form a contact hole, the contact hole being located at a position corresponding to a position where the metal silicide layer is formed. A critical dimension of the contact hole is less than 0.6 μm.

2. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein The predetermined thickness is 1000 Å to 1500 Å.

3. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein After etching the STI oxide layer in the field plate strip groove and before forming the doped polysilicon layer on the substrate, the method further comprises performing ion implantation in a well region in the active region to form a drift region, a body region, a source region and a drain region.

4. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein Before forming the doped polysilicon layer on the substrate, the method further comprises growing a gate oxide layer on the substrate.

5. The method of manufacturing a high voltage semiconductor device according to claim 1, wherein The doped polysilicon layer covers the gate oxide layer, and a gate structure and the field plate structure are formed simultaneously by etching the doped polysilicon layer and the gate oxide layer simultaneously. The doped polysilicon layer has a thickness of 2000 Å to 3000 Å and a sheet resistance of 2000 Ω to 3000 Ω.

6. The method of manufacturing a high voltage semiconductor device according to claim 5, wherein The metal silicide comprises cobalt silicide.

7. The method of manufacturing a high voltage semiconductor device according to Claim 1, wherein When depositing the STI oxide layer, the STI oxide layer fills the STI trench and the field plate strip groove and covers a surface of the substrate at the same time.

8. The method of manufacturing a high voltage semiconductor device according to Claim 1, wherein Before etching the STI oxide layer and before performing ion implantation in the well region, the method further comprises: performing a chemical mechanical polishing process on the remaining STI oxide layer until a surface of the substrate is exposed. Before depositing the STI oxide layer, the method further comprises forming a protective layer on the surface of the substrate, the protective layer serving as a barrier layer for the chemical mechanical polishing process.

9. The method of manufacturing a high voltage semiconductor device according to claim 8, wherein The protective layer comprises silicon nitride. The high-voltage semiconductor device comprises:

10. A high voltage semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 9, characterized by a substrate, the substrate having an STI trench formed therein for isolating an active region, and the active region having a field plate strip groove formed therein; an STI oxide layer, the STI oxide layer filling the STI trench and covering a sidewall and a bottom wall of the field plate strip groove, the STI oxide layer in the field plate strip groove constituting a field plate dielectric layer; a field plate structure, the field plate structure filling a region of the field plate strip groove which is not filled by the field plate dielectric layer. ​ a metal silicide layer, a surface of the field plate structure being covered by the metal silicide layer; and an interlayer dielectric layer covering the substrate and the metal silicide layer, a contact hole being formed in the interlayer dielectric layer, a position of the contact hole corresponding to a position where the metal silicide layer is formed.

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