Super-junction MOSFET device and preparation method thereof

Abstract

The invention relates to a super-junction MOSFET device, and the device comprises a first column structure and a second column structure which are located at the same side of a substrate and are sequentially arranged in the same direction parallel to the surface of the substrate; the opposite surfaces of the first column structure and the second column structure are in contact, and the doping types of the first column structure and the second column structure are different; the island structures and the first column structures are located on the same side of the substrate, and the island structures are located on the sides, away from the second column structures, of the first column structures; the island structures are sequentially arranged in the direction perpendicular to the surface of the substrate, the opposite surfaces of every two adjacent island structures make contact with each other, and the doping types of every two adjacent island structures are different; wherein the island structure is in contact with opposite surfaces of the first pillar structure; a well structure; a gate polysilicon layer; due to two times of recovery of the hole, the current decay time is prolonged, soft recovery is realized, and EMI oscillation is inhibited.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of MOSFET, in particular to a super junction MOSFET device and a preparation method thereof. BACKGROUND

[0002] The super junction (SJ) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device occupies a core position in the high-efficiency power conversion field due to its low on-resistance and high-frequency switching capability, and is widely used in high-power scenarios such as electric vehicle driving systems, photovoltaic inverters, and server power supplies.

[0003] However, the parasitic inductance and parasitic capacitance coupling caused by the high-speed switching characteristic will cause RLC oscillation, resulting in drain voltage spikes and EMI (Electromagnetic Interference), which may cause device failure. "Soft recovery" delays the decay time of the reverse recovery current of the SJ MOSFET device body diode, reduces the voltage spikes and LC oscillation energy caused by parasitic inductance coupling, and thus suppresses EMI.

[0004] In related technologies, most cases are to introduce more minority carriers to prolong the reverse recovery time, thereby alleviating "hard recovery". Although this can alleviate the risk of oscillation, it will also cause Qrr (Reverse Recovery Charge) to increase, which in turn leads to increased power consumption and reduced switching speed. SUMMARY

[0005] Therefore, it is necessary to provide a new super junction MOSFET device capable of realizing soft recovery and a preparation method thereof, so as to suppress the EMI oscillation caused by the super junction MOSFET device in the high-speed switching application scenario and provide device reliability.

[0006] In a first aspect, the present application provides a super junction MOSFET device, comprising:

[0007] a substrate;

[0008] a first pillar structure and a second pillar structure located on the same side of the substrate and arranged in the same direction parallel to the surface of the substrate; the opposite surfaces of the first pillar structure and the second pillar structure are in contact, and the doping types of the first pillar structure and the second pillar structure are different;

[0009] a plurality of island structures, each of which is located on the same side of the substrate as the first pillar structure and on the side of the first pillar structure away from the second pillar structure, and in a direction perpendicular to the surface of the substrate, the plurality of island structures are arranged in sequence, and the opposite surfaces of two adjacent island structures are in contact, and the doping types of the two adjacent island structures are different; wherein the opposite surfaces of the island structure and the first pillar structure are in contact;

[0010] a well structure, at least partially located on the side of the second pillar structure away from the substrate; and an N+ region and a P+ region are formed on the side of the well structure away from the substrate;

[0011] a gate polysilicon layer, at least partially located on the side of the island structure farthest from the substrate away from the substrate.

[0012] For example, the doping types of the two adjacent island structures are N-type doping and P-type doping, respectively, so that when the device is reverse recovered, the holes in the first pillar structure first return to the second pillar structure, completing the first reverse recovery of the holes, and then as the device source voltage decreases, the holes in the P-type doped island structure return to the second pillar structure, completing the second reverse recovery of the holes. The reverse recovery of the holes before and after makes all the holes that go out of the second pillar structure return to the second pillar structure during reverse current conduction, and because of the two-time recovery of the holes, the current decay time is prolonged, the reverse recovery time is effectively delayed, and the Irr is reduced, achieving "soft recovery", alleviating "hard recovery", thereby suppressing EMI oscillation and not increasing Qrr, so the suppression effect is significantly improved.

[0013] In one embodiment, the doping concentration of the island structure is 1x10 17 cm -3 to 1x10 20 cm -3 .

[0014] In one embodiment, the doping concentration of the island structure is 1x10 19 cm -3 .

[0015] In one embodiment, in a direction perpendicular to the surface of the substrate, the depth of the island structure is 4um to 12um.

[0016] In one embodiment, in a direction perpendicular to the surface of the substrate, the depth of the island structure is 10um.

[0017] In one embodiment, in a direction parallel to the surface of the substrate, the width of the island structure is 0.1um to 0.5um.

[0018] In one embodiment, the width of the island structure is 0.2 μm in a direction parallel to the surface of the substrate.

[0019] In one embodiment, the first pillar structure is N-type doped;

[0020] The second pillar structure and the island structure closest to the substrate are both P-type doped.

[0021] In one embodiment, the gate polysilicon layer has a planar structure;

[0022] The orthogonal projection of the well structure onto the substrate covers the orthogonal projection of the second pillar structure onto the substrate;

[0023] The orthogonal projection of the gate polysilicon layer on the substrate covers the orthogonal projections of the island structure, the first pillar structure, and part of the well structure on the substrate.

[0024] In one embodiment, the structure of the gate polysilicon layer includes a polysilicon trench;

[0025] The orthographic projection of the well structure onto the substrate covers the orthographic projections of the second pillar structure and part of the first pillar structure onto the substrate;

[0026] The orthographic projection of the gate polysilicon layer on the substrate covers the orthographic projection of the island structure and part of the first pillar structure on the substrate.

[0027] In one embodiment, the substrate is a silicon substrate;

[0028] Alternatively, the substrate is a silicon carbide substrate, and the superjunction MOSFET device further includes a buffer layer disposed on the surface of the substrate, wherein the first pillar structure, the second pillar structure, and the island structure are all disposed on the surface of the buffer layer.

[0029] In one embodiment, a source metal layer and a drain metal layer are also included;

[0030] The source metal layer is located on the side of the gate polysilicon layer away from the substrate;

[0031] The drain metal layer is located on the side of the substrate away from the first pillar structure.

[0032] Secondly, based on the same inventive concept, embodiments of this application provide a method for fabricating a superjunction MOSFET device. This method can be used to fabricate the superjunction MOSFET device as described in the first aspect above. The method includes:

[0033] Provide substrate;

[0034] The substrate is subjected to multiple epitaxial growths of multiple epitaxial layers and multiple ion implantations to complete the preparation of the first pillar structure, the second pillar structure and the multiple island structures; wherein after each epitaxial growth of an epitaxial layer, an ion implantation is performed to complete the preparation of an island structure, part of the first pillar structure and part of the second pillar structure; and each ion implantation before the last ion implantation is not subjected to a thermal annealing treatment, and the last ion implantation is subjected to a thermal annealing treatment.

[0035] The well structure is formed.

[0036] The gate polysilicon layer is formed.

[0037] The super-junction MOSFET device and the preparation method thereof, wherein the super-junction MOSFET device comprises a substrate, a first pillar structure, a second pillar structure, multiple island structures, a well structure and a gate polysilicon layer, wherein the doping types of two adjacent island structures are different, for example, the doping types of the two adjacent island structures are N-type doping and P-type doping respectively, so that by introducing the floating island structure, when the device is reversed, the holes in the first pillar structure first return to the second pillar structure to complete the first reverse recovery of the holes, and then as the voltage of the source of the device decreases, the holes in the P-type doped island structure return to the second pillar structure to complete the second reverse recovery of the holes, the reverse recovery of the holes in the two times makes all the holes going out of the second pillar structure return to the second pillar structure, and due to the two-time recovery of the holes, the current decay time is prolonged, the reverse recovery time is effectively delayed, the reverse recovery current peak Irm is reduced, the "soft recovery" is realized, the "hard recovery" is alleviated, the EMI oscillation is inhibited, and the Qrr is not increased, so the inhibition effect is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 It is a cross-sectional schematic diagram of a super-junction MOSFET device of an embodiment;

[0040] Figure 2A It is a cross-sectional schematic diagram of a super-junction MOSFET device of an embodiment; Figure 1 It is a hole distribution diagram simulated for the super-junction MOSFET device shown in the figure;

[0041] Figure 2B It is a gray scale diagram of the figure; Figure 2A It is a gray scale diagram of the figure;

[0042] Figure 3 Cross-sectional schematic view of a super junction MOSFET device of an embodiment, part 2;

[0043] Figure 4 Cross-sectional schematic view of a super junction MOSFET device of an embodiment, part 3;

[0044] Figure 5 Cross-sectional schematic view of a super junction MOSFET device of an embodiment, part 4;

[0045] Figure 6 Flow chart of a method of fabricating a super junction MOSFET device of an embodiment;

[0046] Figure 7 Schematic view of a structure involved in a method of fabricating a super junction MOSFET device of an embodiment, part 1;

[0047] Figure 8 Schematic view of a structure involved in a method of fabricating a super junction MOSFET device of an embodiment, part 2;

[0048] Figure 9 Schematic view of a structure involved in a method of fabricating a super junction MOSFET device of an embodiment, part 3;

[0049] Figure 10 Schematic view of a structure involved in a method of fabricating a super junction MOSFET device of an embodiment, part 4;

[0050] Figure 11 Schematic view of a structure involved in a method of fabricating a super junction MOSFET device of an embodiment, part 5.

[0051] BRIEF DESCRIPTION OF DRAWINGS 10 - substrate, 20 - first pillar structure, 30 - second pillar structure, 40 - island structure, 41 - N island, 42 - P island, 50 - well structure, 60 - gate polysilicon layer, 70 - barrier layer, 80 - source metal layer, 90 - drain metal layer, 100 - buffer layer. DETAILED DESCRIPTION

[0052] In order to facilitate the understanding of the present application, a more complete description of the application will be provided below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0054] It is to be understood that the terms "first", "second", and the like, used herein do not connote any hierarchy or order, but are used to distinguish one element from another. For example, a first element can be termed a second element, and, similarly, a second element can be termed a first element, without departing from the scope of the present application.

[0055] It is to be understood that, in the following embodiments, "connected" or "coupled" or "linked" or the like means that the circuit, module, unit, or the like, connected or coupled or linked with each other can transmit or exchange electrical signal or data.

[0056] It is to be understood that "at least one" means one or more, and "multiple" means two or more. "At least part of an element" means part or all of the element.

[0057] As used herein, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is to be understood that the terms "comprise / comprising", "have / having" or "include / including" or the like, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0058] In one exemplary embodiment, referring to Figure 1 , there is provided a super-junction MOSFET device, which includes a substrate 10, a first pillar structure 20, a second pillar structure 30, a plurality of island structures 40, a well structure 50pwell, and a gate polysilicon layer 60.

[0059] The substrate 10 can be an N-type substrate 10 or a P-type substrate 10; the substrate 10 can be a silicon (Si) substrate 10 or a silicon carbide (SiC) substrate 10. In an exemplary embodiment, the substrate 10 is an N-type Si substrate 10. Figure 1 The case where the substrate 10 is an N-type Si substrate 10 is schematically shown in FIG. 1.

[0060] The first pillar structure 20 and the second pillar structure 30 are located on the same side of the substrate 10 and are arranged in sequence in the same direction parallel to the surface of the substrate 10. The opposite surfaces of the first pillar structure 20 and the second pillar structure 30 are in contact, and the doping types of the first pillar structure 20 and the second pillar structure 30 are different. For example, the doping type of the first pillar structure 20 is N-type doping, and the doping type of the second pillar structure 30 is P-type doping, that is, the first pillar structure 20 is a longitudinal N-pillar, and the second pillar structure 30 is a longitudinal P-pillar. The N-pillar and the P-pillar are located on the same side of the substrate 10 and can be arranged in sequence in the same direction. The N-pillar is an N-type semiconductor pillar (doped with a donor impurity such as phosphorus), and the P-pillar is a P-type semiconductor pillar (doped with an acceptor impurity such as boron). The volumes of the N-pillar and the P-pillar can be the same or different. The heights of the N-pillar and the P-pillar can be the same or different. The shapes of the N-pillar and the P-pillar can be the same or different. For example, Figure 1 In the middle, the first pillar structure 20 is an N-pillar, and the second pillar structure 30 is a P-pillar. The structure shape of the first pillar structure 20 and the structure of the second pillar structure 30 are exactly the same, both are cuboid.

[0061] The plurality of island structures 40 are all located on the same side of the substrate 10 as the first pillar structure 20 and are all located on the side of the first pillar structure 20 away from the second pillar structure 30. In the direction perpendicular to the surface of the substrate 10, the plurality of island structures 40 are arranged in sequence, and the opposite surfaces of two adjacent island structures 40 are in contact, and the doping types of the two adjacent island structures 40 are different. The island structure 40 is in contact with the opposite surface of the first pillar structure 20. The doping type of the island structure 40 can be N-type doping or P-type doping. The island structure 40 with N-type doping is referred to as an N-island 41, and the island structure 40 with P-type doping is referred to as a P-island 42. The shape of the island structure 40 is, for example, a cuboid. For example, Figure 1 In the middle, four island structures 40 are arranged. In the direction away from the substrate 10, the four island structures 40 are in sequence: a P-island 42, an N-island 41, a P-island 42, and an N-island 41.

[0062] At least part of the well structure 50pwell is located on the side of the second pillar structure 30 away from the substrate 10. The side of the well structure 50pwell away from the substrate 10 is formed with an N+ region and a P+ region.

[0063] At least part of the gate polysilicon layer 60 is located on the side of the island structure 40 farthest from the substrate 10 away from the substrate 10.

[0064] Generally, trr (reverse recovery time) = ta (storage time) + tb (fall time).

[0065] ta (storage time) refers to the time required from the initial application of reverse voltage until the reverse current reaches its peak value (Irm). During this stage, the minority carriers stored inside the device (such as holes and electrons in a diode) begin to be extracted, but are not yet completely cleared, and the reverse current increases to its peak value as the carriers move.

[0066] tb (fall time) refers to the time required from the time the reverse current reaches its peak value (Irm) until it decreases to a specified stable value (typically 25% of the peak value, i.e., 25% of Irm). During this phase, the remaining minority carriers are rapidly eliminated, and the reverse current decreases rapidly until it approaches a stable reverse leakage current.

[0067] In this embodiment, the introduction of P-island 42 and N-island 41 mitigates the "hard recovery" of reverse recovery, avoids oscillation risk, and does not increase Qrr. When the device is reverse-following current, holes from the P-pillar are injected into the N-pillar, and some holes drift into P-island 42 and are "stored" there. During reverse recovery, electrons in the P-pillar complete the reverse recovery via substrate 10 - drift region - N-island 41. N-island 41 extends the electron conduction path. Although holes are the main factor affecting the reverse recovery time, extending the electron conduction path can also have a beneficial effect on "soft recovery." However, the main function of N-island 41 is to maintain the charge balance between N-island 41 and P-island 42. At the same time, holes in the N-pillar also return to the P-pillar, but the holes "stored" by P-island 42 cannot cross the PN junction barrier (at this time, the voltage difference between the drain and source of the device is less than the PN junction barrier) to return to the P-pillar. The first reverse recovery occurs, followed by the tb stage. During this stage, the ability of P-island 42 to confine the stored holes decreases (the voltage difference between the drain and source is greater than the PN junction barrier, and the source voltage is much smaller than the drain voltage). The holes stored in P-island 42 are forcibly swept back into the P-pillar by the high voltage of the drain, and the holes complete the second reverse recovery. This "secondary recovery" effectively delays the reverse recovery time (the second reverse recovery occurs within the tb stage, so it mainly prolongs tb) and reduces Irm (referring to the reduction in the absolute value of the peak reverse recovery current), thus alleviating the "hard recovery" and avoiding EMI oscillation.

[0068] refer to Figure 2AThis diagram illustrates the "secondary recovery" process in the simulation, which can also be understood as the distribution of holes in the tb stage. Holes flow from P-island 42 to P-pillar. Arrow A indicates the drift direction of the holes; arrow B indicates the location of the PN junction; and arrow C indicates the location of the depletion line. The current rise time in the ta stage is relatively slow, and Irm is smaller (meaning the absolute value of the reverse recovery current peak is smaller). Observing the electron current during the tb current decline stage, electrons recover from the P-pillar through the substrate 10, the bottom N-island 41 (the N-island 41 relatively close to the substrate 10), and the top N-island 41 (the N-island 41 relatively far from the substrate 10). The current density is the highest in the top N-island 41, indicating that during reverse freewheeling of the PN junction, most of the injected electrons are provided by the top N-island 41, followed by the bottom N-island 41 and the drift region. Observing the hole current during the tb stage, holes in the top P-island 42 (the P-island 42 relatively far from the substrate 10) and the bottom P-island 42 (the P-island 42 relatively close to the substrate 10) flow over the PN junction (P-island 42 and N-pillar) barrier into the P-pillar (i.e., the second reverse recovery of holes), while the holes in the N-pillar have already completed their reverse recovery (i.e., the first reverse recovery of holes) during the ta stage. This exhibits the phenomenon of "secondary recovery". The effect of the above-mentioned "secondary recovery" prolongs the time of the tb stage and achieves "soft recovery".

[0069] Furthermore, this application embodiment does not limit the number of P islands 42 and N islands 41. The time of the reverse recovery Irm and tb stages can be controlled by adjusting the number of N islands 41 and P islands 42, as well as adjusting the depth and width of each island structure 40.

[0070] In one exemplary embodiment, the doping concentration of the island structure 40 is 1 × 10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 This allows for a longer tb stage, achieving "soft recovery." In one exemplary embodiment, the doping concentration of the island structure 40 is 1×10⁻⁶. 19 cm -3 This allows for a longer tb phase, enabling a "soft recovery".

[0071] In one exemplary embodiment, the island structure 40 has a depth of 4µm to 12µm in the direction perpendicular to the surface of the substrate 10 to better extend the time of the tb stage and achieve "soft recovery". In another exemplary embodiment, the island structure 40 has a depth of 10µm in the direction perpendicular to the surface of the substrate 10 to better extend the time of the tb stage and achieve "soft recovery".

[0072] In one exemplary embodiment, the island structure 40 has a width of 0.1µm to 0.5µm in the direction parallel to the surface of the substrate 10 to better extend the time of the current drop phase (tb) and achieve "soft recovery". In another exemplary embodiment, the island structure 40 has a width of 0.2µm in the direction parallel to the surface of the substrate 10 to better extend the time of the current drop phase (tb) and achieve "soft recovery"; wherein, the length direction of the island structure 40 may be along a direction perpendicular to the plane of the paper.

[0073] In one exemplary embodiment, reference is made to Figure 1 The first pillar structure 20 is doped with N-type; the second pillar structure 30 and the island structure 40 closest to the substrate 10 are both doped with P-type.

[0074] In one exemplary embodiment, reference is made to Figure 1 and Figure 3 It is a planar SJ MOSFET device, wherein: the gate polysilicon layer 60 has a flat structure; the orthogonal projection of the well structure 50pwell on the substrate 10 covers the orthogonal projection of the second pillar structure 30 on the substrate 10; the orthogonal projection of the gate polysilicon layer 60 on the substrate 10 covers the orthogonal projections of the island structure 40, the first pillar structure 20 and part of the well structure 50pwell on the substrate 10.

[0075] In one exemplary embodiment, reference is made to Figure 4 and Figure 5 This is a trench-type SiC SJ MOSFET device, wherein: the structure of the gate polysilicon layer 60 includes a polysilicon trench; the orthogonal projection of the well structure 50pwell on the substrate 10 covers the orthogonal projection of the second pillar structure 30 and part of the first pillar structure 20 on the substrate 10; the orthogonal projection of the gate polysilicon layer 60 on the substrate 10 covers the orthogonal projection of the island structure 40 and part of the first pillar structure 20 on the substrate 10.

[0076] In one exemplary embodiment, reference is made to Figure 1 and Figure 4 Substrate 10 is a silicon substrate 10; or, refer to Figure 3 and Figure 5 The substrate 10 is a silicon carbide substrate 10. The superjunction MOSFET device also includes a buffer layer 100 disposed on the surface of the substrate 10. The first pillar structure 20, the second pillar structure 30 and the island structure 40 are all disposed on the surface of the buffer layer 100.

[0077] In one exemplary embodiment, reference is made to Figure 1 , Figure 3 , Figure 4 and Figure 5The superjunction MOSFET device further includes a barrier layer 70 (silicon dioxide layer), a source metal layer 80, and a drain metal layer 90. The source metal layer 80 is located on the side of the gate polysilicon layer 60 away from the substrate 10, and the drain metal layer 90 is located on the side of the substrate 10 away from the first pillar structure 20. Additionally, the superjunction MOSFET device may also include a gate metal layer.

[0078] Based on the same inventive concept, this application also provides a method for fabricating a superjunction MOSFET device. This method can be used to fabricate the superjunction MOSFET device in any of the above embodiments. The method may include the following steps S602 to S608.

[0079] S602 provides a substrate.

[0080] S604 involves multiple epitaxial growths on a substrate followed by multiple ion implantations to fabricate a first pillar structure, a second pillar structure, and multiple island structures. Each time an epitaxial layer is grown, an ion implantation is performed to fabricate an island structure, part of the first pillar structure, and part of the second pillar structure. Each ion implantation prior to the final ion implantation is performed without thermal annealing, while the final ion implantation is thermally annealed.

[0081] S606 forms a trap structure.

[0082] S608 forms the gate polysilicon layer.

[0083] In one embodiment, step S604 may include the following steps:

[0084] refer to Figure 7 The silicon N-type drift region is epitaxially grown on an N-type Si substrate for the first time. After epitaxy, an ion implantation is performed to complete the implantation of P islands, N pillars and P pillars. No annealing treatment is performed.

[0085] refer to Figure 8 Then, a second epitaxy is performed, followed by ion implantation to complete the implantation of N islands, N pillars, and P pillars, without annealing.

[0086] refer to Figure 9 Then, a third epitaxial growth process was performed, followed by ion implantation to complete the implantation of P islands, N pillars, and P pillars, without annealing.

[0087] refer to Figure 10 Continue with the fourth epitaxy and ion implantation to complete the implantation of N islands, N pillars and P pillars, and then anneal uniformly to finally form N islands, P islands, N pillars and P pillars.

[0088] refer to Figure 11 Oxidation forms a silicon dioxide barrier layer. Then refer to... Figure 1Ion implantation and annealing form a pwell structure, and finally ion implantation and rapid thermal annealing form N+ and P+ regions.

[0089] The superjunction MOSFET device and its fabrication method provided in this application belong to the same inventive concept, solve the same technical problem, and achieve the same technical effect. Specifically, during reverse recovery, the holes in the first pillar structure return to the second pillar structure, completing the first reverse recovery. Then, as the source voltage decreases, the holes in the P-type doped island structure return to the second pillar structure, completing the second reverse recovery. These two reverse recoveries ensure that all holes exiting from the second pillar structure during reverse freewheeling return to the second pillar structure. Due to these two recovery processes, the current decay time is extended, effectively delaying the reverse recovery time and reducing Irm, achieving "soft recovery" and alleviating "hard recovery," thereby suppressing EMI oscillations without increasing Qrr. Therefore, the suppression effect is significantly improved.

[0090] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A superjunction MOSFET device, characterized in that, include: Substrate; The first pillar structure and the second pillar structure are located on the same side of the substrate and are arranged sequentially in the same direction parallel to the surface of the substrate; the opposing surfaces of the first pillar structure and the second pillar structure are in contact, and the first pillar structure and the second pillar structure have different doping types; Multiple island structures are located on the same side of the substrate as the first pillar structure, and are all located on the side of the first pillar structure away from the second pillar structure; the multiple island structures are arranged sequentially in a direction perpendicular to the surface of the substrate, and the opposing surfaces of two adjacent island structures are in contact with each other, and the doping types of two adjacent island structures are different; wherein, the island structures are in contact with the opposing surfaces of the first pillar structure; A well structure, at least partially located on the side of the second pillar structure away from the substrate; an N+ region and a P+ region are formed on the side of the well structure away from the substrate; A gate polysilicon layer, at least partially located on the side of the island structure furthest from the substrate.

2. The superjunction MOSFET device according to claim 1, characterized in that, The island structure has a doping concentration of 1×10⁻⁶. 17 cm -3 Up to 1×10 20 cm -3 .

3. The superjunction MOSFET device according to claim 1, characterized in that, The depth of the island structure is 4 μm to 12 μm in a direction perpendicular to the surface of the substrate.

4. The superjunction MOSFET device according to claim 1, characterized in that, The width of the island structure is 0.1 μm to 0.5 μm in a direction parallel to the surface of the substrate.

5. The superjunction MOSFET device according to claim 1, characterized in that, The first pillar structure is N-type doped; The second pillar structure and the island structure closest to the substrate are both P-type doped.

6. The superjunction MOSFET device according to claim 1, characterized in that, The structure of the gate polysilicon layer is a flat structure; The orthographic projection of the well structure onto the substrate covers the orthographic projection of the second pillar structure onto the substrate; The orthogonal projection of the gate polysilicon layer on the substrate covers the orthogonal projections of the island structure, the first pillar structure, and part of the well structure on the substrate.

7. The superjunction MOSFET device according to claim 1, characterized in that, The structure of the gate polysilicon layer includes polysilicon trenches; The orthographic projection of the well structure onto the substrate covers the orthographic projections of the second pillar structure and part of the first pillar structure onto the substrate; The orthographic projection of the gate polysilicon layer on the substrate covers the orthographic projection of the island structure and part of the first pillar structure on the substrate.

8. The superjunction MOSFET device according to any one of claims 1-7, characterized in that, The substrate is a silicon substrate; Alternatively, the substrate is a silicon carbide substrate, and the superjunction MOSFET device further includes a buffer layer disposed on the surface of the substrate, wherein the first pillar structure, the second pillar structure, and the island structure are all disposed on the surface of the buffer layer.

9. The superjunction MOSFET device according to any one of claims 1-7, characterized in that, Also includes: The source metal layer is located on the side of the gate polysilicon layer away from the substrate; A drain metal layer is located on the side of the substrate away from the first pillar structure.

10. A method for fabricating a superjunction MOSFET device, characterized in that, The method is used to fabricate a superjunction MOSFET device as described in any one of claims 1-9, the method comprising: Provide substrate; Multiple epitaxial layers are grown on the substrate and ion implanted multiple times to complete the fabrication of a first pillar structure, a second pillar structure, and multiple island structures. Each time an epitaxial layer is grown, an ion implantation is performed to complete the fabrication of an island structure, part of the first pillar structure, and part of the second pillar structure. Each ion implantation before the last ion implantation is not thermally annealed, while the last ion implantation is thermally annealed. Forming a trap structure; A gate polysilicon layer is formed.

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