Interface device and automatic testing device

Abstract

The invention provides an interface device capable of improving the contact position precision of a socket board and an automatic test device. An interface device (200C) is provided between the test head and the device under test (DUT). The front-end module (300C) comprises a pin electronic circuit and a connection surface (302) with electrical contacts, and the front-end module (300C) is provided with a plurality of positioning pins (502) perpendicular to the connection surface (302). The interposer (218) has a plurality of positioning holes (504) into which the plurality of positioning pins (502) are fitted, and the socket board (210C) has a plurality of positioning holes (506) into which the plurality of positioning pins (502) are fitted. The interposer (218) and the receptacle plate (210C) are positioned in the in-plane direction by fitting the plurality of positioning pins (502) with the plurality of positioning holes (504, 506).

Description

TECHNICAL FIELD

[0001] The present application relates to an interface device. BACKGROUND

[0002] An automatic test equipment (ATE) is used in the inspection of various semiconductor devices such as memories and CPUs (Central Processing Unit). The ATE supplies a test signal to a semiconductor device (hereinafter, referred to as a device under test (DUT)) as a test target, measures a response of the DUT to the test signal, determines whether the DUT is qualified or not, or determines a non-qualified site.

[0003] In recent years, the high speed of DRAM (Dynamic Random Access Memory) is progressing. In a GDDR (Graphics Double Data Rate) memory mounted on a drawing tablet, under the GDDR6X standard, a transfer speed of 21 Gbps is realized by an NRZ (Non Return to Zero) method.

[0004] In the next generation GDDR7, PAM4 (Pulse Amplitude Modulation 4) is adopted, and the transfer speed is increased to 40 Gbps. The NRZ method is also progressing in high speed year by year, and in the next generation, the high speed is increased to about 28 Gbps.

[0005] Patent Literature 1 discloses an interface device capable of testing a high-speed device with high precision, and an automatic test equipment. In the interface device, a socket board and a pin electronic circuit are connected via an interposer and a wiring.

[0006] PRIOR ART DOCUMENTS

[0007] PATENT LITERATURE

[0008] Patent Literature 1 Japanese Patent Application Publication No. 2024-014522 SUMMARY

[0009] SUMMARY

[0010] PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] As a structure for making the contact pins contact the substrate surface to be in conduction, there is a structure for connecting to the substrate using a pogo pin plate, a pogo pin block. In the case of using a pogo pin plate, it is necessary to use a tool for adjusting the position of the pogo pin plate to perform assembly. In the case of using a pogo pin block, it becomes a structure in which the position accuracy with the contacted substrate is ensured by making the pogo pin block with one structure. In general, a guide pin is provided to create contact position accuracy in order to position the contact pins and the substrate.

[0012] In the case of using a pogo pin plate, replacement of only one contact pin cannot be performed, so that position adjustment based on a tool is required each time, and thus the replacement workability is poor. Also, even in the case of a pogo pin block, the pogo pin block is one structure, so that it needs to be completely removed, and the replacement workability is poor.

[0013] In the case where a guide pin is provided outside the contact portion, the cumulative tolerance to the guide pin increases, so that it is necessary to increase the pad diameter of the substrate. When the pad diameter increases, the number of pads that can be arranged decreases, so that the number of pins that can be corresponded to decreases.

[0014] The present application is made in view of such a situation, and one of the exemplary objects of one aspect of the present application is to provide an interface device in which the contact position accuracy is improved.

[0015] Solutions for solving the problems

[0016] One aspect of the present application relates to an interface device provided between a test head and a device under test (DUT). The interface device includes a front end module including a pin electronic circuit and a connection surface having an electrical contact point, a plurality of positioning pins provided perpendicular to the connection surface, an interposer having a plurality of positioning holes into which the plurality of positioning pins are fitted, and a socket plate having a plurality of positioning holes into which the plurality of positioning pins are fitted, wherein the interposer and the socket plate are positioned in the in-plane direction by fitting of the plurality of positioning pins and the plurality of positioning holes.

[0017] Note that a manner of arbitrarily combining the above-described constituent elements, a manner of mutually replacing the constituent elements, the expressions between the method, the device, the system, and the like are also effective as the aspects of the present application or the present disclosure. Furthermore, the description of this column (solutions for solving the problems) is not indispensable to all the features of the present application, and thus a sub-combination of the described features can also be the present application. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a diagram of an ATE that represents an embodiment.

[0019] Figure 2 is a cross-sectional view of an interface device of an embodiment.

[0020] Figure 3is a diagram showing a front end module of an embodiment.

[0021] Figure 4 is a diagram showing a front end module of an embodiment. Figure 3 is a perspective view showing a configuration example of the FEU of

[0022] Figure 5 is a cross-sectional view showing a configuration example of the FEU of Figure 3

[0023] Figure 6

[0024] Figure 7 is a cross-sectional view of a socket board of an embodiment.

[0025] Figure 8 is a diagram showing a layout of a plurality of second pads of a second face of a socket PCB.

[0026] Figure 9 is a diagram showing a layout of a plurality of second pads of a second face of a socket PCB of a modification example.

[0027] Figure 10 is a perspective view showing a layout of a socket board of an embodiment.

[0028] Figure 11 is a plan view showing a layout of a socket board of an embodiment.

[0029] Figure 12 is a plan view showing a layout of a socket board of a comparative technique.

[0030] Figure 13 is a plan view showing a layout of a socket board of a modification example.

[0031] Figure 14 is a diagram showing a socket board of an embodiment.

[0032] Figure 15 is an exploded perspective view of an interface device of an embodiment.

[0033] Figure 16 is an exploded perspective view of an interface device.

[0034] Figure 17 is a cross-sectional view of an interface device in an assembled state.

[0035] Symbol explanation

[0036] ​​1 DUT, 100 ATE, 120 tester, 130 test head, 200 interface device, 210 socket board, 212 socket, 214 socket PCB, P1 first pad, P2 second pad, SIG signal pin, GND ground pin, 216 socket board side connector, 218 interposer, 219 cable clip, 220 wiring, 222 FPC cable, 230 motherboard, 240 nonvolatile memory, 300 front end module, 400 pin electronics IC, 500 FPC frame, 210C DSA, 502 positioning pin, 504 positioning hole, 506 positioning hole. DETAILED DESCRIPTION

[0037] (SUMMARY)

[0038] A summary of several illustrative embodiments of the present application is described. The summary is provided as a prelude to the detailed description that follows and is intended to provide a basic understanding of one or more embodiments of the application, not an inclusive or exhaustive summary of the application or the scope of the embodiments. The summary is not an inclusive or exhaustive summary of all embodiments of the application and determinations of important elements of all embodiments are not intended to delineate the scope of a portion or all aspects. For the sake of brevity, "an embodiment" is sometimes used as a shorthand for one embodiment (example, modification) or more embodiments (examples, modifications) disclosed in the specification.

[0039] An interface device of an embodiment is provided between a test head and a device under test (DUT). The interface device has: a front end module including a pin electronics circuit, a connection surface having an electrical contact, the front end module being provided with a plurality of positioning pins perpendicular to the connection surface; an interposer having a plurality of positioning holes into which the plurality of positioning pins are fitted; and a socket board having a plurality of positioning holes into which the plurality of positioning pins are fitted, the interposer and the socket board being positioned in a planar direction by fitting of the plurality of positioning pins and the plurality of positioning holes.

[0040] According to this structure, an error factor of accumulated tolerances can be minimized, and a tool for position adjustment is not required. Furthermore, the interposer (contactor) is divided for each mounting module, so even if damage to the pins exists, replacement can be easily performed by replacing the mounting module. Furthermore, the error factor of accumulated tolerances is minimized, so the diameter of the metal pad can be reduced.

[0041] In an embodiment, the front end module can have: a rigid body provided with the plurality of positioning pins; a substrate for mounting the pin electronics circuit; and a flexible substrate wiring for the plurality of positioning pins to pass through, and having the electrical contact in a portion corresponding to the connection surface.

[0042] An automatic test device of an embodiment can have any one of the above-described interface devices.

[0043] (Embodiment)

[0044] Hereinafter, a preferred embodiment will be described with reference to the accompanying drawings. Like or equivalent components shown in the drawings are designated by like reference numerals, and repetitive explanation will be appropriately omitted. Moreover, the embodiment is not limited to disclose and invent, but is exemplified, and all the features and combinations thereof described in the embodiment are not necessarily essential features and combinations thereof of the disclosure and the invention.

[0045] In addition, the size (thickness, length, width, etc.) of each component described in the drawings is sometimes appropriately enlarged or reduced for the sake of convenience in understanding. Furthermore, the size of a plurality of components is not necessarily indicative of the size relationship thereof, and even if a certain component A is depicted thicker than another component B on the drawing, the component A can be thinner than the component B.

[0046] In the present specification, the "state where component A is connected to component B" includes, in addition to the case where component A and component B are directly connected physically, the case where component A and component B are indirectly connected via another component which does not substantially affect the electrically connected state thereof or does not impair the function or effect exerted by the combination thereof.

[0047] Likewise, the "state where component C is connected to (provided between) component A and component B" includes, in addition to the case where component A and component C, or component B and component C are directly connected, the case where they are indirectly connected via another component which does not substantially affect the electrically connected state thereof or does not impair the function or effect exerted by the combination thereof.

[0048] Figure 1 is a diagram showing the ATE 100 of the embodiment. The ATE 100 is provided with a tester 120, a test head 130, a processor 150, and an interface device 200.

[0049] The tester 120 centrally controls the ATE 100. Specifically, the tester 120 executes a test program, controls the test head 130 and the processor 150, and collects measurement results.

[0050] The processor 150 supplies (loads) the DUT 1 to the interface device 200, and unloads the DUT 1 tested from the interface device 200. Moreover, the processor 150 classifies the DUT 1 into a good product and a defective product.

[0051] The test head 130 is provided with hardware which generates a test signal to be supplied to the DUT 1, and detects a signal (referred to as a device signal) from the DUT 1. Moreover, a power supply circuit or the like which generates a power supply voltage to be supplied to the DUT 1 and the interface device 200 can be included.

[0052] The interface device 200 includes a socket board 210, wiring 220, and a front-end module 300.

[0053] In this embodiment, multiple pin-based electronic ICs (PE-ICs) 400 are disposed in the interface device 200 rather than within the test head 130. The pin-based electronic ICs 400 are application-specific integrated circuits (ASICs) that integrate a driver for generating test signals and a comparator for receiving device signals. The test signals and device signals are NRZ signals or PAM4 signals.

[0054] More specifically, the multi-pin electronic IC 400 is modularized. This module is referred to as the front-end module 300.

[0055] The socket board 210 has multiple sockets 212. The DUT1 is mounted on the socket 212. The front-end module 300 is connected to the socket 212 via wiring 220.

[0056] The above is the structure of ATE100.

[0057] According to the ATE100, a front-end module 300, which is modularly composed of multiple pin-based electronic ICs 400, is built into the interface device 200, thereby allowing the pin-based electronic ICs 400 to be positioned near the DUT1. As a result, the transmission distance of test signals and device signals can be significantly shortened compared to the past.

[0058] For example, in conventional ATEs, the pin-controlled electronic IC and the socket board are connected by a coaxial cable with a length of approximately 500mm to 600mm. However, in this embodiment, the length of the wiring 220 can be shortened to approximately 100mm to 150mm. This significantly reduces the loss of high-frequency components and enables the transmission of high-speed test signals and device signals. The ATE100 equipped with this interface device 200 can perform high-speed memory testing exceeding 20Gbps.

[0059] Figure 2 This is a cross-sectional view of an interface device 200A according to an embodiment. Figure 2 Only the structure associated with one DUT is shown. In this embodiment, the interface device 200A includes a motherboard 230 and a socket board 210 that is detachable from the motherboard 230. The socket board 210 includes a socket (also called a socket guide) 212 as a mechanical component, a socket printed circuit board (socket PCB) 214, and a socket board side connector 216. It should be noted that the socket PCB itself is sometimes referred to as a socket board, and the socket PCB with the socket guide mounted is referred to as a DSA (Device Specific Adapter) or device board.

[0060] The front-end module 300A includes multiple printed circuit boards (PCBs) 310 for mounting multiple pin electronic ICs 400. The multiple pin electronic PCBs 310 are arranged in a direction perpendicular to the surfaces (surface and back) of the DUT, in other words, perpendicular to the surface S1 of the socket board 210. In this embodiment, the socket board 210 is parallel to the ground, therefore the multiple pin electronic PCBs 310 are arranged parallel to the direction of gravity.

[0061] The front-end module 300A also features a plate-shaped cooling device (hereinafter referred to as a cold plate) 320. The cold plate 320 has a flow path for refrigerant circulation.

[0062] Multiple pin electronic PCBs 310a and 310b and a cold plate 320 are stacked in a manner where the pin electronic IC 400 and the cold plate 320 are thermally coupled.

[0063] The motherboard 230 includes a socket board-side connector 232, a spacer frame 234, and a relay connector 236. The front-end module 300A is fixed to the spacer frame 234. The relay connector 236 is electrically and mechanically coupled to the test head-side connector 132.

[0064] As detailed below, wiring 220 can replace conventional coaxial cables with cables made of flexible printed circuits (FPCs) (also known as FPC cables).

[0065] On the other hand, the wiring 224 between the pin electronics PCB 310 and the relay connector 236 only transmits control signals for the pin electronics IC 400, and does not transmit test signals or device signals. Therefore, wiring 224 can utilize a coaxial cable.

[0066] Figure 3 This is a diagram illustrating a front-end module 300B according to one embodiment.

[0067] One DUT1 is assigned 2 × M (M≥1) pin electronic ICs 400. Multiple DUTs and pin electronic ICs 400 are labeled with A to D to distinguish them as needed. In this example, with DUT1 having 192 I / Os and pin electronic ICs 400 having 24 I / Os, each DUT is assigned 192 / 24 = 8 (i.e., M = 4) pin electronic ICs 400.

[0068] The front-end module 300B is configured such that each N (N≥2) DUT1 is divided into multiple units, and this division unit is called a front-end unit (FEU). In this example, the block corresponding to 4 DUTs constitutes 1 FEU, and 1 FEU has 2×M×N = 2×4×4 = 32 pins of electronic IC 400.

[0069] Figure 3 The diagram shows two FEUs, but in reality, the front-end module 300B can have more than two FEUs. For example, in an ATE capable of simultaneously measuring 64, setting 64 / 4 = 16 FEUs, as a whole, the front-end module 300B has 64 × 192 I / O = 12288 I / Os.

[0070] Figure 4 It means Figure 3 A perspective view of the configuration example of the FEU. The sockets 212A to 212D corresponding to the four DUTs are arranged in a matrix of two rows and two columns. Considering one DUT 1A, the eight-pin electronic IC 400A assigned to it is mounted in pairs on four pin electronic PCBs 310a to 310d arranged along the X direction. The socket PCB 214 for mounting the sockets 212 can be divided according to each DUT, or the socket PCBs 214 corresponding to the four DUTs can be integrally constructed as a single substrate.

[0071] Two pin-mounted electronic ICs 400A are arranged along the Y direction and mounted on a single-pin electronic PCB 310. The two pin-mounted electronic ICs 400A are positioned at equal distances from the DUT1A.

[0072] Figure 5 It means Figure 3 A cross-sectional view of an example of the components of a FEU. For example... Figure 5 As shown, a cold plate 320 is placed between two pin electronics PCBs 310a and 310b. Similarly, a cold plate 320 is also placed between two pin electronics PCBs 310c and 310d. As described above, the pin electronics IC 400 is mounted on the pin electronics PCB 310 at a location close to the socket board 210. To improve cooling efficiency, the pin electronics IC 400 can be a bare chip, and the pin electronics IC 400 and the cold plate 320 are thermally coupled via a thermal interface material (TIM) 322.

[0073] In addition, when viewing the FEU from above along the Y-axis, the center of the DUT, namely the socket 212A, is located at the center of the four (M) pin electronic PCBs 310a to 310d stacked along the X-direction.

[0074] The above is the structure of FEU.

[0075] The advantages of this FEU are explained. Focusing on DUT1A marked with annotation A, multiple (eight in this example) pin-type electronic ICs 400A corresponding to one DUT1A are mounted in pairs on four pin-type electronic PCBs 310a-310d. This allows the distance from each of the eight pin-type electronic ICs 400A to the socket 212A to be uniform. Consequently, the transmission line loss from each pin-type electronic IC 400A to the socket 212A (DUT1A) is uniformized, enabling accurate testing.

[0076] Next, the electrical connection between the pin electronics IC400 and the socket 212 will be explained.

[0077] Figure 6 This is a cross-sectional view showing an example of the connection between the pin electronics IC and the socket (DUT1). The transmission path for test signals and device signals, i.e., the wiring 220 between the pin electronics PCB310 and the socket board 210, uses FPC cable 222.

[0078] If a coaxial cable is used as the wiring 220 between the pin electronics PCB 310 and the socket board 210, the minimum distance between them is limited due to the rigidity of the coaxial cable. In contrast, by using an FPC cable 222, the distance h between the pin electronics PCB 310 and the socket board 210 can be shortened compared to using a coaxial cable due to its flexibility, thus reducing the transmission distance of test signals and device signals.

[0079] In conventional testing setups, LIF (Low Insulation Force) connectors were typically used when it was desired to make the socket board 210 removable. These LIF connectors exhibit a non-negligible loss of approximately -3dB in frequency bands higher than 14GHz, which can cause waveform distortion at high-speed transmissions of 28Gbps or 40Gbps. By using FPC cable 222 via wiring 220 without requiring LIF connectors, waveform distortion caused by losses (attenuation in high-frequency bands) can be suppressed, enabling accurate testing.

[0080] More specifically, the socket board 210 includes a socket 212 and a socket PCB 214. The socket PCB 214 is a multilayer substrate including a wiring layer and an insulating layer. Wiring is formed in the wiring layer to allow signal paths to move horizontally, and vias VH are formed in the insulating layer to allow signal paths to move vertically. Test signals and device signals are preferably led out to the back of the socket board 210 as horizontally as possible (X and Y directions) without shifting. Conversely, power signals and low-frequency control signals can move horizontally throughout the interior of the socket PCB 214.

[0081] FPC cable 222 is connected to socket board 210 by socket board side connector 216. Socket board side connector 216 includes interposer 218 and cable clip 219.

[0082] Intermediate layer 218 and socket PCB 214 are detachable. The electrodes exposed on the surface of intermediate layer 218 are electrically connected to the electrodes exposed on the back of socket PCB 214. FPC cable 222 is clamped in by cable clip 219 in contact with the back electrode of intermediate layer 218.

[0083] Figure 7 This is a cross-sectional view of the socket board 210 according to the embodiment. A socket 212 is provided on the first side of the socket PCB 214 of the socket board 210, which is connected to the DUT. The second side of the socket board 210 is connected to the interposer layer 218 so that it can be detached.

[0084] Additionally, a surface mount device (SMD) 213 is mounted on the second side of the socket board 210. Examples of SMD 213 include chip capacitors, chip resistors, and chip inductors. Multiple first pads P1 for mounting the SMD 213 are formed on the second side of the socket PCB 214.

[0085] Additionally, a plurality of second pads P2 are formed on the second side of the socket PCB214 to serve as electrical contacts with the interposer layer 218. The second pads P2 are electrically connected to the corresponding contacts (pins) P3 of the interposer layer 218.

[0086] The first pad P1 has a thickness t1, and the second pad P2 has a thickness t2. The thicknesses t1 and t2 of the two pads P1 and P2 are different (t1 ≠ t2). Specifically, the relationship t2 > t1 holds true.

[0087] Preferably, the thickness t2 of the second pad P2 is more than twice the thickness t1 of the first pad P1. More preferably, the thickness t2 of the second pad P2 is more than five times the thickness t1 of the first pad P1. Even more preferably, the thickness t2 of the second pad P2 is more than eight times the thickness t1 of the first pad P1.

[0088] For example, the thickness t1 of the first pad P1 is 0.03 micrometers with a dimensional tolerance of ±30%. In contrast, the thickness t2 of the second pad P2 is 0.5 micrometers with a dimensional tolerance of ±30%. In this case, the thickness t2 of the second pad P2 is 16 times the thickness t1 of the first pad P1.

[0089] According to the socket board 210, the first pad P1 for component mounting and the second pad P2, which becomes the electrical contact with the interposer layer 218, have different thicknesses. As a result, the peel strength of the SMD 213 can be improved, the wear resistance of the electrical contact with the interposer layer 218 can be improved, and the long-term reliability can be improved.

[0090] Figure 8 This diagram shows the layout of multiple second pads P2 on the second side of the socket PCB 214. Multiple positioning pins configured in a matrix are provided on the surface of the interposer layer 218. Figure 7 P3), and corresponding to multiple positioning pins P3, multiple second pads P2 are arranged in a matrix on the second side of the socket PCB214.

[0091] Multiple second pads P2 are alternately assigned signal pins SIG and ground pins GND in the row direction (top and bottom) and column direction (left and right). In other words, each signal pin SIG is assigned such that it is adjacent to the ground pin GND along both the row and column directions, and adjacent to each other along the diagonal direction. Furthermore, this can be understood as a structure where the two rows and two columns of second pins SIG are considered the smallest unit PU, and this smallest unit PU is arranged along the row and column directions. The smallest unit PU contains two diagonally arranged signal pins SIG and two diagonally arranged ground pins GND.

[0092] The above is the layout of the second pad P2 in the socket PCB214. Compared with the layout where the signal pins are completely surrounded by the ground pins in the row, column, and diagonal directions, this layout can increase the density of signal pins and reduce the area of ​​the socket printed circuit board.

[0093] Figure 9 This is a modified example of the layout of multiple second pads P2 on the second side of the socket PCB214. In this modified example, the ground pins GND in the multiple second pads P2 are formed continuously to each other.

[0094] According to this variation, the impedance of the ground pin GND can be reduced.

[0095] Next, the layout of the DUT and signals in the socket board will be explained.

[0096] Figure 10 This is a perspective view showing the layout of the socket board 210 according to the embodiment. Figure 11 This is a top view showing the layout of the socket panel 210 according to the embodiment.

[0097] The socket board 210 includes a socket PCB 214 and N socket guides (referred to as sockets) 212_1 to 212_N. In this example, N = 2.

[0098] N sockets 212_1 to 212_N are arranged on the first side (top surface in the figure) of socket PCB214.

[0099] On the second side (lower surface in the figure) of the socket PCB214, multiple pads P2 are formed, divided into a first region RGN1 and a second region RGN2. The multiple pads P2 become electrical contacts with the interposer layer 218.

[0100] The first region RNG1 and the second region RGN2 are rectangles with the same shape and size, with the first direction (y) as the longer side, and are separated from each other along the second direction (x).

[0101] N sockets 212_1 to 212_N are respectively located in the third region RNG3, which is sandwiched between the first region RGN1 and the second region RNG2 in the x direction, and are arranged adjacently in the y direction.

[0102] Each socket 212_1 to 212_N is electrically connected to a portion of the plurality of pads P2 contained in the first region RGN1 and a portion of the plurality of pads P2 contained in the second region RNG2. Each pin of socket 212 and its corresponding pad P2 are connected to wiring provided on socket PCB 214 via through-holes.

[0103] One socket 212_1 is positioned between y0 and y1 in the y direction, and the other socket 212_2 is positioned between y1 and y2 in the y direction. y0 is the coordinate of one end of the rectangular regions RGN1 and RGN2, y2 is the coordinate of the other end of the regions RGN1 and RGN2, and y1 is the coordinate of the center.

[0104] exist Figure 11 In the layout, Pa represents the farthest pad among the pads connected to socket 212_1, and Pb represents the nearest pad among the pads connected to socket 212_1.

[0105] The above describes the layout of the socket panel 210. The advantages of this socket panel 210 become clear through comparison with comparative technologies.

[0106] Figure 12 This is a top view showing the layout of the socket panel 210R of the comparative technology.

[0107] In this comparative technique, one socket 212_1 is connected to the pad P2 contained in the first region RNG1, and the other socket 212_2 is connected to the pad P2 contained in the second region RNG2.

[0108] exist Figure 12 In the layout, Pc represents the farthest pad among the pads connected to socket 212_1, and Pd represents the nearest pad among the pads connected to socket 212_1.

[0109] Will Figure 11 (Implementation Method) and Figure 12 (Comparative techniques) show that, Figure 11 (Implementation Method) The length of the wiring connecting the socket to the farthest pad can be shortened. As a result, parasitic impedance is reduced, thus widening the bandwidth and enabling the testing of higher speed signals.

[0110] Will Figure 11 (Implementation Method) and Figure 12 When making comparisons using (comparative techniques) Figure 11 In the (implementation method), the difference between the distance Pa to the farthest pad and the distance Pb to the nearest pad is less than [the required value]. Figure 12 The difference between the distance Pc to the farthest pad and the distance Pd to the nearest pad in the (comparative technique). That is, according to the implementation, the wiring length of the multiple positioning pins P2 can be made more uniform compared to the comparative technique.

[0111] Figure 13 This is a top view showing the layout of a modified socket panel 210. In this modified example, the number N of sockets 212 is 4. In this layout, regarding the two central sockets 212_2 and 212_3, in the y-direction, the range y0 to y2 of the rectangular regions RGN1 and RGN2 converge. Therefore, it is possible to enjoy the same... Figure 10 The layout has the same advantages.

[0112] Next, we will explain the management of the socket board.

[0113] Figure 14 This diagram illustrates a socket board 210A according to one embodiment. In addition to the socket PCB 214 and socket 212, the socket board 210A also includes a non-volatile memory 240. The non-volatile memory 240 can be read from the tester body. The non-volatile memory 240 is either an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash memory.

[0114] The non-volatile memory 240 can be configured at a location along the outer periphery of the socket PCB 214, such as any of the four corners. A ground pattern 242 is formed along the outer periphery of the socket PCB 214, and the non-volatile memory 240 can be configured adjacent to the ground pattern 242.

[0115] Typically, multiple (e.g., 16) socket boards are connected by a mechanical component called a socket frame, forming a unit. This unit is sometimes referred to as a DSA or device board. Traditionally, each DSA was equipped with non-volatile memory, storing its inherent information.

[0116] The inventors, through research on previous DSA (Digital Subtraction Angiography) methods, independently recognized the following issues. In conventional ATE (Automatic Equipment) systems that process relatively low-speed signals, individual variations in the socket board were negligible or did not pose a significant problem. However, in tests of high-speed memory exceeding 20Gbps, individual variations in the socket board became unavoidable.

[0117] Therefore, in this embodiment, a non-volatile memory 240 is provided for each socket board 210A, and inherent information for each socket board 210 can be stored in the non-volatile memory 240. For example, the following information can be pre-stored in the non-volatile memory 240.

[0118] (i) Information related to socket 212 set on socket board 210A. Specifically, this may include the location of the socket board, pin configuration, etc. The tester body reads this information from socket board 210A and transmits it to the processor. As a result, the processor can place the DUT in the correct position on socket board 210A.

[0119] Furthermore, the precision of mechanical components changes due to temperature variations and the effects of time. By comparing the actual location of the processor placed in the DUT, i.e., the actual location of the socket, with the location information of the socket 212 stored in the non-volatile memory 240, the user of ATE100 can observe how the actual location of the socket 212 has shifted due to time-related or temperature changes.

[0120] (ii) Manufacturing serial number and management serial number of socket board 210A

[0121] (iii) It can manage information about the processor's contact with the socket board on a per-socket basis, such as the number of contacts and the depth of contact.

[0122] The above describes the structure of the socket board 210A. Based on this socket board 210A, various types of information can be managed at the socket board level, rather than at the DSA level. Therefore, testing applications that take into account the individual differences of the socket board can be performed, enabling accurate testing of high-speed memory devices exceeding 20Gbps.

[0123] Next, we will explain the structure related to the connection between the socket board (DSA) and the front-end module.

[0124] Figure 15 This is an exploded perspective view of an interface device 200C according to one embodiment. The interface device 200C includes a front-end module 300C, a DSA 210C, and an FPC frame 500.

[0125] The front-end module 300 is mounted, supported, and fixed to the FPC frame 500 from the bottom. In this example, two front-end modules 300 are mounted on one FPC frame 500.

[0126] The DSA210C has a socket PCB214 and a frame 215 as a mechanical component. The DSA210C also has a socket (not shown). The frame 215 is mounted from the top of the FPC frame 500.

[0127] The front-end module 300 has an FPC cable 222. The FPC cable 222 is electrically connected to the pads on the back of the DSA210C socket PCB214 via an interposer layer 218.

[0128] Figure 16 This is an exploded perspective view of the interface device 200C. The front-end module 300C has a connection surface 302. In this example, the connection surface 302 is formed by an FPC cable 222. The front-end module 300 has a plurality of positioning pins 502 perpendicular to the connection surface 302.

[0129] Specifically, positioning pin 502 is pressed into cable clip 219, which is a rigid body. Positioning pin 502 passes through FPC cable 222.

[0130] Intermediate layer 218 has positioning holes 504 that engage with positioning pins 502. Receptacle PCB 214 has positioning holes 506 that engage with positioning pins 502.

[0131] Intermediate layer 218 and DSA210C are positioned in the in-plane direction by the interlocking of multiple positioning pins 502 and multiple positioning holes 504, 506.

[0132] Figure 17 This is a cross-sectional view of the interface device 200C after assembly.

[0133] The above describes the structure of the interface device 200C. In this interface device 200, positioning pins 502 are provided on the connection surface 302 of the front-end module 300C, and corresponding positioning holes 504 and 506 are provided on the interposer layer 218 and the socket PCB 214. This minimizes the cumulative tolerance of the pads of the FPC cable 222, the interposer layer 218, and the pads on the back of the DSA 210C, thereby improving the contact position accuracy.

[0134] No positioning tools are required during assembly. Furthermore, by separating the interposer layer 218 (contact) for each front-end module 300, even if pin damage occurs, replacement of the front-end module 300 is possible. Moreover, by minimizing accumulated tolerance error, the diameter of the metal pads can be reduced.

[0135] The interface device 200 exists in various forms, but this disclosure is applicable to any form.

[0136] • SBC (Socket Board Change) type

[0137] The SBC type is an interface device that replaces the socket board 210 type according to the type of DUT.

[0138] • CLS (Cable Less) type

[0139] The CLS type is an interface device 200 that can be separated into an upper DSA (Device Specific Adapter) and a lower motherboard, and the type of DSA can be replaced according to the type of DUT. When applying the interface device 200 of this embodiment to the CLS type, two methods can be considered.

[0140] One approach is to configure the front-end module 300 on the motherboard side. In this case, the front-end module 300 can be shared in the testing of different DUTs, which is advantageous from a cost perspective.

[0141] Another approach is to configure the front-end module 300 on the DSA side. In this case, the front-end module 300 is configured according to each DSA, thus increasing the cost of the device. On the other hand, since the front-end module 300 can be placed close to the DUT, it is advantageous from the viewpoint of high-speed testing.

[0142] • CCN (Cable Connection) type

[0143] The CCN type is an interface device in which the entire interface device 200 is replaced according to the type of DUT. If the interface device 200 of this embodiment is applied to the CCN type, the front-end module 300 can be brought closer to the limit of the DUT, which is advantageous from the point of view of high-speed testing.

[0144] • Wafer motherboard

[0145] The interface device 200 can be a wafer motherboard used in wafer-level testing. In this case, the interface device 200 can have a probe card instead of a socket board.

[0146] The above-described embodiments are illustrative, and it will be self-evident to those skilled in the art that the combination of the above-described components and processing techniques may include various modifications. Such modifications will be described below.

[0147] (Variation Example 1)

[0148] In one embodiment, the pin electronics IC 400 electrically connects the FPC to the printed circuit board using an interposer, but this disclosure is not limited to this. Wiring 220 may be a printed circuit board or other wiring other than the FPC cable 222.

[0149] (Variation Example 2)

[0150] In this embodiment, an interface device 200 with the socket plate 210 parallel to the ground is described, but this disclosure is not limited thereto. For example, the socket plate 210 may be perpendicular to the ground. In this case, Figure 4 , Figure 5 In equations, the Y-direction becomes the direction of gravity.

[0151] While specific terminology has been used to describe embodiments of this disclosure, such description is merely illustrative and does not limit the scope of this disclosure or the claims. The scope of this invention is defined by the claims; therefore, embodiments, examples, and modifications not described herein are also included within the scope of this invention.

Claims

1. An interface device disposed between a test head and a device under test, characterized in that, The interface device includes: A front-end module includes pin electronics and a connection surface with electrical contacts, wherein the front-end module is provided with a plurality of positioning pins perpendicular to the connection surface; An intermediate layer having a plurality of positioning holes that engage with the plurality of positioning pins; and The socket board has multiple positioning holes that engage with the plurality of positioning pins. The intermediate layer and the socket plate are positioned in the in-plane direction by the engagement of the plurality of positioning pins and the plurality of positioning holes.

2. The interface device according to claim 1, characterized in that, The front-end module has the following features: A rigid body having the aforementioned plurality of positioning pins; A substrate for mounting the pin electronics; and The flexible substrate wiring allows the plurality of positioning pins to pass through, and has the electrical contacts in the portion corresponding to the connecting surface.

3. An automatic testing device, characterized in that, It has the interface device as described in claim 1 or 2.

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