Current detection circuit and electronic chip thereof

Abstract

The invention provides a current detection circuit and an electronic chip thereof, and the current detection circuit comprises a first power tube, a second power tube, a first resistor, a sensing control module and a first copying module. Grid electrodes of the first power tube and the second power tube receive driving signals, drain electrodes of the first power tube and the second power tube are connected with power voltage, and a source electrode of the first power tube is connected with reference ground through a first resistor. The sensing control module is connected with the source electrode of the first power tube and the source electrode of the second power tube, and the source electrode potential of the second power tube is equal to the source electrode potential of the first power tube, so that second current corresponding to the first current of the first power tube is sensed at the second power tube; the first copying module is connected with the output end of the sensing control module, and copies the second current to generate a third current. According to the invention, the problems of low current detection precision and fixed proportion in the prior art are solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a current detection circuit and its electronic chip. Background Technology

[0002] In chips for motor drivers, LED drivers, and power management, current sensing is crucial. The current sensing function serves two main purposes:

[0003] One is to perform accurate load current estimation. For example, in LED driver chips, constant current output is maintained by monitoring the load current in real time.

[0004] Secondly, it implements overcurrent protection. Driver chips often operate under harsh conditions and have large load currents. The detected current is sent to a fast comparator. Once the detected current exceeds the set threshold, the gate drive of the power transistor is immediately pulled down to prevent the power transistor from being thermally broken down.

[0005] Therefore, how to achieve wide detection range and high precision current detection has become one of the technical problems that those skilled in the art urgently want to solve. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a current detection circuit and its electronic chip to solve the problems of low current detection accuracy and fixed ratio in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a current detection circuit, comprising a first power transistor, a second power transistor, a first resistor, a sensing control module, and a first replication module, wherein:

[0008] The gates of the first power transistor and the second power transistor receive drive signals, the drains of the first power transistor and the second power transistor are connected to the power supply voltage, and the source of the first power transistor is connected to the reference ground via the first resistor.

[0009] The sensing control module connects the source terminals of the first power transistor and the second power transistor. By making the source potential of the second power transistor equal to the source potential of the first power transistor, a second current corresponding to the first current of the first power transistor is induced at the second power transistor.

[0010] The first copying module is connected to the output terminal of the sensing control module, and generates a third current by copying the second current.

[0011] Optionally, the sensing control module includes an operational amplifier and a first PMOS transistor, wherein:

[0012] The first input terminal of the operational amplifier is connected to the source of the first power transistor, the second input terminal of the operational amplifier is connected to the source of the second power transistor, the output terminal of the operational amplifier is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor serves as the output terminal of the sensing control module, and the source of the first PMOS transistor is connected to the source of the second power transistor.

[0013] Optionally, the third current is used as the detection current; the first replication module has an adjustable first replication ratio, and the detection current is proportionally adjusted by adjusting the first replication ratio.

[0014] Optionally, the first replication module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, M fourth NMOS transistors, and M-1 first switches, where M is a natural number greater than 1.

[0015] The gate of the first NMOS transistor is connected to its drain, and the drain of the first NMOS transistor is connected to the output terminal of the sensing control module. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to its drain, and the source of the second NMOS transistor is connected to reference ground. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor serves as the output terminal of the first replication module. The source of the third NMOS transistor is connected to the drain of the first fourth NMOS transistor. The gates of M fourth NMOS transistors are connected to each other and to the gates of the second NMOS transistors. The drains of the M fourth NMOS transistors are connected to each other through M-1 first switches, and the sources of the M fourth NMOS transistors are connected to reference ground. The first replication ratio is adjusted by controlling the opening and closing of the M-1 first switches.

[0016] Optionally, the current detection circuit further includes a second replication module connected to the output terminal of the first replication module, which generates a fourth current by replicating the third current; wherein the fourth current serves as the detection current, and the second replication module has an adjustable second replication ratio, which is used to proportionally adjust the detection current.

[0017] Optionally, the first replication module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein:

[0018] The gate of the first NMOS transistor is connected to its drain, and the drain of the first NMOS transistor is connected to the output terminal of the sensing control module. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to its drain, and the source of the second NMOS transistor is connected to reference ground. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor serves as the output terminal of the first replication module. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor, and the source of the fourth NMOS transistor is connected to reference ground.

[0019] Optionally, the second replication module includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, N fifth PMOS transistors, and N-1 second switches, where N is a natural number greater than 1.

[0020] The gate of the second PMOS transistor is connected to its drain, and the drain of the second PMOS transistor is connected to the output terminal of the first replication module. The source of the second PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third PMOS transistor is connected to its drain. The source of the third PMOS transistor is connected to the power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the fourth PMOS transistor serves as the output terminal of the second replication module. The source of the fourth PMOS transistor is connected to the drain of the first fifth PMOS transistor. The gates of N fifth PMOS transistors are connected to each other and to the gate of the third PMOS transistor. The drains of N fifth PMOS transistors are connected to each other through N-1 second switches, and the sources of N fifth PMOS transistors are connected to the power supply voltage. The second replication ratio is adjusted by controlling the opening and closing of the N-1 second switches.

[0021] Optionally, the current detection circuit further includes a second resistor connected between the output terminal of the first replication module and the power supply voltage, or connected between the output terminal of the second replication module and the reference ground, for converting the detected current into a detected voltage and outputting it.

[0022] The present invention also provides an electronic chip, including the current detection circuit described in any one of the above claims.

[0023] Optionally, the electronic chip includes a first chip and a second chip, wherein the first power transistor and the second power transistor are integrated in the first chip, and the rest except for the first resistor are integrated in the second chip, and the first resistor serves as an external load of the chip.

[0024] As described above, the current detection circuit and its electronic chip of the present invention can not only achieve high-precision current detection, but also achieve flexible adjustment of the current detection ratio with a wide range and high precision by adjusting the first replication ratio or the second replication ratio without changing the physical size of the power transistor, so that the same chip can be used for different application scenarios. Attached Figure Description

[0025] Figure 1 The diagram shown is a schematic diagram of the current detection circuit in Embodiment 1 of the present invention.

[0026] Figure 2 The diagram shown is a schematic diagram of the current detection circuit in Embodiment 2 of the present invention.

[0027] Figure 3 Displayed as a pair Figure 2 The diagram shows the relevant signal waveforms during the first simulation of the circuit shown.

[0028] Figure 4 Displayed as a pair Figure 2 The diagram shows the relevant signal waveforms during the second simulation of the circuit shown.

[0029] Component labeling: 100 Current detection circuit, 101 Sensing control module, 102 First replication module, 103 Voltage readout module, 104 Gate drive module, 105 Second replication module. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] Example 1

[0033] like Figure 1 As shown, this embodiment provides a current detection circuit 100, including a first power transistor Q1, a second power transistor Q2, a first resistor R1, a sensing control module 101 and a first replication module 102, and further includes a second resistor R2.

[0034] The gate of the first power transistor Q1 receives the drive signal DRV, the drain of the first power transistor Q1 is connected to the power supply voltage VDD, and the source of the first power transistor Q1 is connected to the reference ground GND via the first resistor R1. The source of the first power transistor Q1 is also connected to the sensing control module 101. In this embodiment, the first power transistor Q1 serves as the main power transistor, and the first resistor R1 serves as the load resistor. The first power transistor Q1 is controlled by the drive signal DRV to perform on / off control and generate a first current I1.

[0035] The gate of the second power transistor Q2 receives the drive signal DRV, the drain of the second power transistor Q2 is connected to the power supply voltage VDD, and the source of the second power transistor Q2 is connected to the sensing control module 101. In this embodiment, the second power transistor Q2 serves as a sensing power transistor, used to sense the current flowing through the main power transistor under the action of the sensing control module 101.

[0036] The sensing control module 101 is connected to the source of the first power transistor Q1 and the source of the second power transistor Q2. By making the source potential of the second power transistor Q2 equal to the source potential of the first power transistor Q1, a second current I2 corresponding to the first current I1 of the first power transistor Q1 is induced at the second power transistor Q2, wherein the second current I2 is proportional to the first current I1.

[0037] In one embodiment, the sensing control module 101 includes an operational amplifier OTA and a first PMOS transistor MP1. Specifically: the first input terminal (e.g., non-inverting input terminal) of the operational amplifier OTA is connected to the source of the first power transistor Q1; the second input terminal (e.g., inverting input terminal) of the operational amplifier OTA is connected to the source of the second power transistor Q2; the output terminal of the operational amplifier OTA is connected to the gate of the first PMOS transistor MP1; the drain of the first PMOS transistor MP1 serves as the output terminal of the sensing control module 101; and the source of the first PMOS transistor MP1 is connected to the source of the second power transistor Q2.

[0038] In this embodiment, the first PMOS transistor MP1 acts as an adjustment transistor and, together with the operational amplifier OTA, forms a negative feedback structure with the first power transistor Q1 and the second power transistor Q2, making the source potential of the second power transistor Q2 equal to the source potential of the first power transistor Q1, thereby reducing the difference in the on-state voltage drop of the two power transistors and achieving accurate current sensing.

[0039] The specific analysis is as follows: When the first power transistor Q1 and the second power transistor Q2 are controlled by the drive signal DRV and operate in the deep linear region, assuming that the on-resistance of the first power transistor Q1 is RQ1 and the on-resistance of the second power transistor Q2 is RQ2, then: the first current I1 satisfies the formula I1=(VDD-OTA+) / RQ1, and the second current I2 satisfies the formula I2=(VDD-OTA-) / RQ2, where OTA+ is the source potential of the first power transistor Q1 and OTA- is the source potential of the second power transistor Q2.

[0040] Due to the negative feedback effect, OTA+ and OTA- can be approximated as equal, so we have the formula I1 / I2=RQ2 / RQ1. It can be seen that the first current I1 and the second current I2 are only related to the ratio of the on-resistance of the two power transistors. Therefore, accurate current sensing can be achieved, thereby realizing high-precision current detection. In addition, the negative feedback structure can also effectively suppress the effects of process deviations and temperature drift, thereby ensuring consistency and stability over a wide operating range.

[0041] The first copying module 102 is connected to the output terminal of the sensing control module 101, and generates a third current I3 by copying the second current I2. In this embodiment, the third current I3 is used as the detection current; wherein, the first copying module 102 has an adjustable first copying ratio, and by adjusting the first copying ratio, the detection current can be proportionally adjusted, that is, the ratio between the detection current and the first current I1 can be adjusted.

[0042] In one embodiment, the first replication module 102 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, M fourth NMOS transistors MN41~MN4m, and M-1 first switches K11~K1m-1, where M is a natural number greater than 1. Wherein: the gate of the first NMOS transistor MN1 is connected to its drain, the drain of the first NMOS transistor MN1 is connected to the output terminal of the sensing control module 101, the source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 is connected to its drain, the source of the second NMOS transistor MN2 is connected to the reference ground GND, the gate of the third NMOS transistor MN3 is connected to the gate of the first NMOS transistor MN1, the drain of the third NMOS transistor MN3 serves as the output terminal of the first replication module 102, the source of the third NMOS transistor MN3 is connected to the drain of the first fourth NMOS transistor MN41, the gates of M fourth NMOS transistors MN41~MN4m are connected to each other and connected to the gate of the second NMOS transistor MN2, the drains of M fourth NMOS transistors MN41~MN4m are connected to each other through M-1 first switches K11~K1m-1, and the sources of M fourth NMOS transistors MN41~MN4m are connected to the reference ground GND.

[0043] In this embodiment, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the first fourth NMOS transistor MN41 constitute a Cascode current mirror structure to facilitate high-precision current replication. Furthermore, by controlling the opening and closing of M-1 first switches K11~K1m-1, the physical size of the fourth NMOS transistor in the current mirror structure can be adjusted, i.e., the ratio of the physical size of the fourth NMOS transistor to that of the second NMOS transistor can be adjusted, thereby adjusting the first replication ratio. For example, when all M-1 first switches K11~K1m-1 are closed, the physical size of the fourth NMOS transistor in the current mirror structure is maximized, and the corresponding first replication ratio is maximized; when all M-1 first switches K11~K1m-1 are open, the physical size of the fourth NMOS transistor in the current mirror structure is minimized, and the corresponding first replication ratio is minimized. In practical applications, the adjustment of the first replication ratio can be achieved by controlling the number of opening and closing first switches according to specific requirements, thereby realizing high-precision adjustment of the current detection ratio. This embodiment adjusts the current detection ratio by adjusting the first replication ratio, without changing the physical dimensions or even the packaging of the first power transistor Q1 and the second power transistor Q2, which greatly improves flexibility and applicability.

[0044] The second resistor R2 is connected between the output terminal of the first replication module 102 and the power supply voltage VDD. The second resistor R2 serves as a detection resistor, used to convert the detection current into a detection voltage and output it.

[0045] To accurately determine the status of the first current I1, it is usually necessary to read the detection voltage. In this case, the current detection circuit 100 of this embodiment also includes a voltage reading module 103, which is connected to the end of the second resistor R2 away from the power supply voltage VDD, and is used to read the detection voltage for subsequent processing. The voltage reading module 103 can be implemented in different ways according to different application requirements. For example, for overcurrent protection requirements, the voltage reading module 103 is implemented using a comparator, and for constant current drive requirements, the voltage reading module 103 is implemented using an analog-to-digital converter. Of course, it is not limited to these.

[0046] In practical applications, the current detection circuit 100 of this embodiment also includes a gate drive module 104, which provides a drive signal DRV to the first power transistor Q1 and the second power transistor Q2 to control the on / off state of the first power transistor Q1 and the second power transistor Q2. It should be noted that the so-called on / off control includes not only controlling the power transistor to turn on or off, but also controlling the degree of conduction of the power transistor.

[0047] Example 2

[0048] like Figure 2As shown, this embodiment provides a current detection circuit 100, including a first power transistor Q1, a second power transistor Q2, a first resistor R1, a sensing control module 101, a first replication module 102 and a second replication module 105, and further includes a second resistor R2.

[0049] The gate of the first power transistor Q1 receives the drive signal DRV, the drain of the first power transistor Q1 is connected to the power supply voltage VDD, and the source of the first power transistor Q1 is connected to the reference ground GND via the first resistor R1. The source of the first power transistor Q1 is also connected to the sensing control module 101. In this embodiment, the first power transistor Q1 serves as the main power transistor, and the first resistor R1 serves as the load resistor. The first power transistor Q1 is controlled by the drive signal DRV to perform on / off control and generate a first current I1.

[0050] The gate of the second power transistor Q2 receives the drive signal DRV, the drain of the second power transistor Q2 is connected to the power supply voltage VDD, and the source of the second power transistor Q2 is connected to the sensing control module 101. In this embodiment, the second power transistor Q2 serves as a sensing power transistor, used to sense the current flowing through the main power transistor under the action of the sensing control module 101.

[0051] The sensing control module 101 is connected to the source of the first power transistor Q1 and the source of the second power transistor Q2. By making the source potential of the second power transistor Q2 equal to the source potential of the first power transistor Q1, a second current I2 corresponding to the first current I1 of the first power transistor Q1 is induced at the second power transistor Q2, wherein the second current I2 is proportional to the first current I1.

[0052] In one embodiment, the sensing control module 101 includes an operational amplifier OTA and a first PMOS transistor MP1. Specifically: the first input terminal (e.g., non-inverting input terminal) of the operational amplifier OTA is connected to the source of the first power transistor Q1; the second input terminal (e.g., inverting input terminal) of the operational amplifier OTA is connected to the source of the second power transistor Q2; the output terminal of the operational amplifier OTA is connected to the gate of the first PMOS transistor MP1; the drain of the first PMOS transistor MP1 serves as the output terminal of the sensing control module 101; and the source of the first PMOS transistor MP1 is connected to the source of the second power transistor Q2.

[0053] In this embodiment, the first PMOS transistor MP1 acts as an adjustment transistor and, together with the operational amplifier OTA, forms a negative feedback structure with the first power transistor Q1 and the second power transistor Q2, making the source potential of the second power transistor Q2 equal to the source potential of the first power transistor Q1, thereby reducing the difference in the on-state voltage drop of the two power transistors and achieving accurate current sensing.

[0054] The specific analysis is as follows: When the first power transistor Q1 and the second power transistor Q2 are controlled by the drive signal DRV and operate in the deep linear region, assuming that the on-resistance of the first power transistor Q1 is RQ1 and the on-resistance of the second power transistor Q2 is RQ2, then: the first current I1 satisfies the formula I1=(VDD-OTA+) / RQ1, and the second current I2 satisfies the formula I2=(VDD-OTA-) / RQ2, where OTA+ is the source potential of the first power transistor Q1 and OTA- is the source potential of the second power transistor Q2.

[0055] Due to the negative feedback effect, OTA+ and OTA- can be approximated as equal, so we have the formula I1 / I2=RQ2 / RQ1. It can be seen that the first current I1 and the second current I2 are only related to the ratio of the on-resistance of the two power transistors. Therefore, accurate current sensing can be achieved, thereby realizing high-precision current detection. In addition, the negative feedback structure can also effectively suppress the effects of process deviations and temperature drift, thereby ensuring consistency and stability over a wide operating range.

[0056] The first copy module 102 is connected to the output terminal of the sensing control module 101, and generates a third current I3 by copying the second current I2; wherein, the first copy module 102 has a fixed first copy ratio.

[0057] In one embodiment, the first replication module 102 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. Specifically: the gate of the first NMOS transistor MN1 is connected to its drain, the drain of the first NMOS transistor MN1 is connected to the output terminal of the sensing control module 101, the source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 is connected to its drain, the source of the second NMOS transistor MN2 is connected to reference ground (GND), the gate of the third NMOS transistor MN3 is connected to the gate of the first NMOS transistor MN1, the drain of the third NMOS transistor MN3 serves as the output terminal of the first replication module 102, the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is connected to the gate of the second NMOS transistor MN2, and the source of the fourth NMOS transistor MN4 is connected to reference ground.

[0058] In this embodiment, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 constitute a Cascode current mirror structure to facilitate high-precision current replication. The ratio of the physical dimensions of the fourth NMOS transistor MN4 to the second NMOS transistor MN2 is fixed, thus the current mirror structure has a fixed first replication ratio. In practical applications, the first replication ratio can be set to 1:1, but other ratios are also feasible.

[0059] The second copy module 105 is connected to the output terminal of the first copy module 102, and generates a fourth current I4 by copying the third current I3. In this embodiment, the fourth current I4 serves as the detection current. The second copy module 105 has an adjustable second copy ratio. By adjusting the second copy ratio, the detection current can be proportionally adjusted, that is, the ratio between the detection current and the first current I1 can be adjusted. By adding the second copy module 105, the detection voltage can be converted to a voltage relative to ground, and a smaller detection voltage is beneficial for subsequent circuit design and processing.

[0060] In one embodiment, the second replication module 105 includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, N fifth PMOS transistors MP51~MP5n, and N-1 second switches K21~K2n-1, where N is a natural number greater than 1. Wherein: the gate of the second PMOS transistor MP2 is connected to its drain, the drain of the second PMOS transistor MP2 is connected to the output terminal of the first replication module 102, the source of the second PMOS transistor MP2 is connected to the drain of the third PMOS transistor MP3, the gate of the third PMOS transistor MP3 is connected to its drain, the source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, the gate of the fourth PMOS transistor MP4 is connected to the gate of the second PMOS transistor MP2, the drain of the fourth PMOS transistor MP4 serves as the output terminal of the second replication module 105, the source of the fourth PMOS transistor MP4 is connected to the drain of the first fifth PMOS transistor MP51, the gates of N fifth PMOS transistors MP51~MP5n are connected to each other and connected to the gate of the third PMOS transistor MP3, the drains of N fifth PMOS transistors MP51~MP5n are connected to each other through N-1 second switches K21~K2n-1, and the sources of N fifth PMOS transistors MP51~MP5n are connected to the power supply voltage VDD.

[0061] In this embodiment, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the first fifth PMOS transistor MP51 constitute a Cascode current mirror structure to facilitate high-precision current replication. Furthermore, by controlling the opening and closing of N-1 second switches K21~K2n-1, the physical size of the fifth PMOS transistor in the current mirror structure can be adjusted, i.e., the ratio of the physical size of the fifth PMOS transistor to that of the third PMOS transistor can be adjusted, thereby adjusting the second replication ratio. For example, when all N-1 second switches K21~K2n-1 are closed, the physical size of the fifth PMOS transistor in the current mirror structure is the largest, and the corresponding second replication ratio is the largest; when all N-1 second switches K21~K2n-1 are open, the physical size of the fifth PMOS transistor in the current mirror structure is the smallest, and the corresponding second replication ratio is the smallest. In practical applications, the adjustment of the second replication ratio can be achieved by controlling the number of opening and closing second switches according to specific requirements, thereby realizing high-precision adjustment of the current detection ratio. This embodiment adjusts the current detection ratio by adjusting the second replication ratio, without changing the physical dimensions or even the packaging of the first power transistor Q1 and the second power transistor Q2, which greatly improves flexibility and applicability.

[0062] The second resistor R2 is connected between the output terminal of the second replication module 105 and the reference ground GND. The second resistor R2 serves as a detection resistor, used to convert the detection current into a detection voltage and output it.

[0063] To accurately determine the status of the first current I1, it is usually necessary to read the detected voltage. In this case, the current detection circuit 100 of this embodiment also includes a voltage reading module 103, which is connected to the end of the second resistor R2 away from the reference ground GND, and is used to read the detected voltage for subsequent processing. The voltage reading module 103 can be implemented in different ways according to different application requirements. For example, for overcurrent protection requirements, the voltage reading module 103 is implemented using a comparator, and for constant current drive requirements, the voltage reading module 103 is implemented using an analog-to-digital converter. Of course, it is not limited to these.

[0064] In practical applications, the current detection circuit 100 of this embodiment also includes a gate drive module 104, which provides a drive signal DRV to the first power transistor Q1 and the second power transistor Q2 to control the on / off state of the first power transistor Q1 and the second power transistor Q2. It should be noted that the so-called on / off control includes not only controlling the power transistor to turn on or off, but also controlling the degree of conduction of the power transistor.

[0065] Below, on Figure 2 The circuit structure shown was simulated twice, and the feasibility and advantages of the current detection circuit 100 shown in this invention were demonstrated by simulation comparison.

[0066] The same parts in the two simulation designs:

[0067] Power supply voltage VDD=12V, reference ground GND=0V; first resistor R1=10Ω, second resistor R2=1000Ω;

[0068] The first power transistor Q1 is composed of 1000 NMOS transistors with a width-to-length ratio of 100μm / 1.7μm, the second power transistor Q2 is composed of 1 NMOS transistor with a width-to-length ratio of 100μm / 1.7μm, and the first PMOS transistor MP1 is composed of 16 PMOS transistors with a width-to-length ratio of 80μm / 2μm.

[0069] The first NMOS transistor MN1 consists of four NMOS transistors with a width-to-length ratio of 6μm / 2μm; the second NMOS transistor MN2 consists of eight NMOS transistors with a width-to-length ratio of 6μm / 2μm; the third NMOS transistor MN3 consists of four NMOS transistors with a width-to-length ratio of 6μm / 2μm; and the fourth NMOS transistor MN4 consists of eight NMOS transistors with a width-to-length ratio of 6μm / 2μm.

[0070] The second PMOS transistor MP2 consists of 6 PMOS transistors with a width-to-length ratio of 6μm / 4μm, the third PMOS transistor MP3 consists of 12 PMOS transistors with a width-to-length ratio of 6μm / 4μm, and the fourth PMOS transistor MP4 consists of 6 PMOS transistors with a width-to-length ratio of 6μm / 4μm.

[0071] Differences between the two simulation designs:

[0072] In the first simulation design, the fifth PMOS transistor consists of 12 PMOS transistors with a width-to-length ratio of 6μm / 4μm, which can be regarded as connecting a fifth PMOS transistor.

[0073] In the second simulation design, the fifth PMOS transistor consists of 24 PMOS transistors with a width-to-length ratio of 6μm / 4μm, which can be regarded as two fifth PMOS transistors connected together.

[0074] The results of the first simulation are as follows Figure 3As shown, after the power supply voltage VDD stabilizes, at 250μs, the first current I1 = 1.188A, OTA+≈OTA- = 11.88V, which is consistent with the clamping effect of the operational amplifier OTA. The second current I2 = 1.188mA, which is consistent with the size ratio of the first power transistor Q1 to the second power transistor Q2 being 1000:1. The third current I3 = 1.18mA, which is consistent with the size ratio of the fourth NMOS transistor MN4 to the second NMOS transistor MN2 being 1:1. The fourth current I4 = 1.168mA. Ignoring simulation errors, this is consistent with the size ratio of the fifth PMOS transistor to the third PMOS transistor MP3 being 1:1. Thus, the positive terminal voltage VR2 of the second resistor R2 is obtained as 1.168V.

[0075] The results of the second simulation are as follows Figure 4 As shown, after the power supply voltage VDD stabilizes, at 250μs, the first current I1 = 1.188A, OTA+≈OTA- = 11.88V, which is consistent with the clamping effect of the operational amplifier OTA. The second current I2 = 1.188mA, which is consistent with the size ratio of the first power transistor Q1 to the second power transistor Q2 being 1000:1. The third current I3 = 1.18mA, which is consistent with the size ratio of the fourth NMOS transistor MN4 to the second NMOS transistor MN2 being 1:1. The fourth current I4 = 2.358mA. Ignoring simulation errors, this is consistent with the size ratio of the fifth PMOS transistor to the third PMOS transistor MP3 being 2:1. Thus, the positive terminal voltage VR2 of the second resistor R2 is obtained as 2.358V.

[0076] Therefore, the current detection circuit 100 of the present invention can achieve current detection with high accuracy, and can change the current detection ratio originally determined by the power transistor by adjusting the second replication ratio without changing the power transistor specifications (e.g., physical size and package), thus realizing flexible adjustment of the current detection ratio without depending on the power transistor.

[0077] Example 3

[0078] This embodiment provides an electronic chip, including a current detection circuit 100; wherein the current detection circuit 100 is implemented using the circuit structure described in Embodiment 1 or Embodiment 2. In practical applications, the electronic chip in this embodiment can be a motor driver chip, an LED driver chip, a power management chip, etc., and there is no limitation thereto.

[0079] In this embodiment, the electronic chip is a packaged chip, including a first chip and a second chip; wherein, the first power transistor Q1 and the second power transistor Q2 are integrated in the first chip, and the rest except the first resistor R1 are integrated in the second chip, such as the second resistor R2, the sensing control module 101, the first replication module 102, the voltage readout module 103, the gate drive module 104, the second replication module 105, etc. The first resistor R1 serves as an external load of the chip and is located outside the first chip and the second chip.

[0080] In summary, the current detection circuit and its electronic chip of the present invention not only achieve high-precision current detection, but also enable flexible adjustment of the current detection ratio over a wide range and with high precision by adjusting the first or second replication ratio without changing the physical dimensions of the power transistor. This allows the same chip to be applied to different application scenarios. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0081] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A current detection circuit, characterized in that, It includes a first power transistor, a second power transistor, a first resistor, a sensing and control module, and a first replication module, wherein: The gates of the first power transistor and the second power transistor receive drive signals, the drains of the first power transistor and the second power transistor are connected to the power supply voltage, and the source of the first power transistor is connected to the reference ground via the first resistor. The sensing control module connects the source terminals of the first power transistor and the second power transistor. By making the source potential of the second power transistor equal to the source potential of the first power transistor, a second current corresponding to the first current of the first power transistor is induced at the second power transistor. The first copying module is connected to the output terminal of the sensing control module, and generates a third current by copying the second current.

2. The current detection circuit according to claim 1, characterized in that, The sensing control module includes an operational amplifier and a first PMOS transistor, wherein: The first input terminal of the operational amplifier is connected to the source of the first power transistor, the second input terminal of the operational amplifier is connected to the source of the second power transistor, the output terminal of the operational amplifier is connected to the gate of the first PMOS transistor, the drain of the first PMOS transistor serves as the output terminal of the sensing control module, and the source of the first PMOS transistor is connected to the source of the second power transistor.

3. The current detection circuit according to claim 1, characterized in that, The third current serves as the detection current; the first replication module has an adjustable first replication ratio, and the detection current is proportionally adjusted by adjusting the first replication ratio.

4. The current detection circuit according to claim 3, characterized in that, The first replication module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, M fourth NMOS transistors, and M-1 first switches, where M is a natural number greater than 1. The gate of the first NMOS transistor is connected to its drain, and the drain of the first NMOS transistor is connected to the output terminal of the sensing control module. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to its drain, and the source of the second NMOS transistor is connected to reference ground. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor serves as the output terminal of the first replication module. The source of the third NMOS transistor is connected to the drain of the first fourth NMOS transistor. The gates of M fourth NMOS transistors are connected to each other and to the gates of the second NMOS transistors. The drains of the M fourth NMOS transistors are connected to each other through M-1 first switches, and the sources of the M fourth NMOS transistors are connected to reference ground. The first replication ratio is adjusted by controlling the opening and closing of the M-1 first switches.

5. The current detection circuit according to claim 1, characterized in that, The current detection circuit further includes a second replication module connected to the output terminal of the first replication module, which generates a fourth current by replicating the third current; wherein the fourth current serves as the detection current, and the second replication module has an adjustable second replication ratio, which is used to proportionally adjust the detection current.

6. The current detection circuit according to claim 5, characterized in that, The first replication module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein: The gate of the first NMOS transistor is connected to its drain, and the drain of the first NMOS transistor is connected to the output terminal of the sensing control module. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to its drain, and the source of the second NMOS transistor is connected to reference ground. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, and the drain of the third NMOS transistor serves as the output terminal of the first replication module. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor, and the source of the fourth NMOS transistor is connected to reference ground.

7. The current detection circuit according to claim 5, characterized in that, The second replication module includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, N fifth PMOS transistors, and N-1 second switches, where N is a natural number greater than 1. The gate of the second PMOS transistor is connected to its drain, and the drain of the second PMOS transistor is connected to the output terminal of the first replication module. The source of the second PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third PMOS transistor is connected to its drain. The source of the third PMOS transistor is connected to the power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the fourth PMOS transistor serves as the output terminal of the second replication module. The source of the fourth PMOS transistor is connected to the drain of the first fifth PMOS transistor. The gates of N fifth PMOS transistors are connected to each other and to the gate of the third PMOS transistor. The drains of N fifth PMOS transistors are connected to each other through N-1 second switches, and the sources of N fifth PMOS transistors are connected to the power supply voltage. The second replication ratio is adjusted by controlling the opening and closing of the N-1 second switches.

8. The current detection circuit according to claim 3 or 5, characterized in that, The current detection circuit further includes a second resistor, connected between the output terminal of the first replication module and the power supply voltage, or connected between the output terminal of the second replication module and the reference ground, for converting the detected current into a detected voltage and outputting it.

9. An electronic chip, characterized in that, Includes the current detection circuit as described in any one of claims 1 to 8.

10. The electronic chip according to claim 9, characterized in that, The electronic chip includes a first chip and a second chip, wherein the first power transistor and the second power transistor are integrated in the first chip, and the rest except the first resistor are integrated in the second chip, and the first resistor serves as an external load of the chip.

Images