Limited semiconductor device for real-time power-up performance test and preparation method thereof

Abstract

The invention relates to a limited semiconductor device for real-time power-up performance test and a preparation method thereof, the limited semiconductor device comprises a support base, a bottom electrode, a semiconductor material layer, a top electrode and a dielectric layer, the bottom electrode is located above the support base; the semiconductor material layer is located above the bottom electrode; the top electrode is located above the semiconductor material layer; through mutually independent nanometer columnar structures are arranged among the bottom electrode, the semiconductor material layer and the top electrode, and a dielectric material is filled to form a dielectric layer. According to the invention, the microstructure change of the semiconductor material in the in-situ power-up experiment process can be better observed, meanwhile, the damage probability of the sample is reduced, the success rate of the in-situ power-up experiment is improved, and the pollution of melting and sublimation of the sample in the power-up process to an experiment instrument cavity and the environment is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a restricted semiconductor device for real-time power-on performance test and a preparation method thereof. BACKGROUND

[0002] The vigorous development of information technology related industries puts forward higher requirements for semiconductor materials. Semiconductor materials, relying on their dynamic regulation ability between conductors and insulators under external conditions such as electric field, thermal field, and light, become the cornerstone of the semiconductor industry. Therefore, for the integrated circuit industry, observing the structural transformation process of semiconductor materials under the action of electric field is very crucial for optimizing the performance of semiconductor materials and devices and the electrical driving conditions of semiconductor devices. At present, a large number of studies have used experimental instruments such as scanning electron microscope (SEM) and transmission electron microscope (TEM) to characterize the microstructure of semiconductor devices before and after electrical operation, but there is still a lack of real-time observation of semiconductor materials under the action of electric field.

[0003] Since most semiconductor device units are packaged inside the chip, direct use of focused ion beam (FIB) processing can easily cause serious sample damage, which is not conducive to real-time observation under in-situ electric field. Especially when the size of the semiconductor device unit is small, this adverse effect will be very significant, interfering with normal characterization experiments. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a restricted semiconductor device for real-time power-on performance test and a preparation method thereof, which can better observe the microstructure changes of semiconductor materials during in-situ power-on experiments, while reducing the probability of sample damage, improving the success rate of in-situ power-on experiments and reducing the pollution of experimental instrument cavities and environment caused by sample melting and sublimation during the power-on process.

[0005] The present application provides a restricted semiconductor device for real-time power-on performance test, comprising a support base, a bottom electrode, a semiconductor material layer, a top electrode and a dielectric layer, the bottom electrode is located above the support base; the semiconductor material layer is located above the bottom electrode; the top electrode is located above the semiconductor material layer; a through and mutually independent nano-pillar structure is provided between the bottom electrode, semiconductor material layer and top electrode, and is filled with a dielectric material to form a dielectric layer.

[0006] Preferably, the material of the support base is selected from one or more of Cu, Al, Ag, and Au; the support base should be subjected to surface oxide removal and thinning treatment.

[0007] Preferably, the material of the bottom electrode is selected from one or more of Ti, W, Ta, Cu, WCN, WN, TiN, and TaN.

[0008] Preferably, the material of the semiconductor material layer is selected from one or more of the materials used for integrated circuits and logic devices, materials used for radio frequency devices, materials used for power electronics devices, materials used for sensors and detectors, materials used for memory devices.

[0009] Preferably, the material of the top electrode is one or more of Ti, W, Ta, Cu, WN, TiN, TaN.

[0010] Preferably, the dielectric material is one or more of SiN x , SiO2, HfO2, Al2O3.

[0011] Preferably, the thickness of the dielectric layer is less than 15 nm, and does not affect the microstructure analysis during in-situ power-on testing.

[0012] The present application also provides a preparation method of a confined semiconductor device for real-time power-on performance testing, comprising the following steps:

[0013] S1, providing a support base;

[0014] S2, forming a bottom electrode on the support base;

[0015] S3, forming a semiconductor material layer on the surface of the bottom electrode;

[0016] S4, forming a top electrode on the surface of the semiconductor material layer;

[0017] S5, forming a trench through the bottom electrode, the semiconductor material layer and the top electrode to obtain a nano-pillar structure independent of each other;

[0018] S6, filling a dielectric material around the nano-pillar structure to form a dielectric layer;

[0019] S7, removing the dielectric material on the surface of the top electrode to expose the top of the top electrode, to obtain the confined semiconductor device.

[0020] Advantages

[0021] (1) The present application avoids the physical and chemical damage caused by using FIB to directly cut the chip, reduces the probability of experimental failure caused by sample problems during power-on experiment, and facilitates microscopic observation during power-on experiment.

[0022] (2) The present application adopts a dielectric layer to wrap the independent nano-pillar structure, so that the heat generated by the electric pulse is concentrated in the nano-pillar structure, effectively improving the thermal efficiency; at the same time, the melting or volatilization of the semiconductor material due to overheating is limited, effectively improving the success rate of the power-on experiment, and reducing the pollution to the vacuum cavity of the experimental instruments such as SEM and TEM.

[0023] (3) The preparation process of the present application is simple, the production cost is low, and it is suitable for industrialized production. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a structure schematic diagram of the semiconductor device of the present application.

[0025] Figure 2 It is a TEM image of the semiconductor device (a) of the present application and the device (b) after in-situ power-on experiment.

[0026] Figure 3 It is a preparation process schematic diagram of the semiconductor device of the present application.

[0027] Figures 4 to 9 It is a structure schematic diagram of each process of the preparation process of the semiconductor device of the present application.

[0028] Element number explanation

[0029] 01 Support base;

[0030] 02 Bottom electrode;

[0031] 03 Semiconductor material layer;

[0032] 04 Top electrode;

[0033] 05 Dielectric layer. DETAILED DESCRIPTION

[0034] The present application will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present application and not to limit the scope of the present application. In addition, it should be understood that after reading the content taught by the present application, those skilled in the art can make various modifications or modifications to the present application, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0035] Example 1

[0036] As shown in the present embodiment, a limiting type semiconductor device for real-time power-on performance test is provided, and the structure of the limiting type semiconductor device for real-time power-on performance test comprises: Figure 1

[0037] Support base 01;

[0038] ​Bottom electrode 02 is located on the support base and is connected to the support base;

[0039] Semiconductor material layer 03 is located on the bottom electrode and is connected to the bottom electrode;

[0040] Top electrode 04 is located on the semiconductor material layer and is connected to the semiconductor material layer;

[0041] Dielectric layer 05 has a through-type independent nanopillar structure between the bottom electrode, the semiconductor material layer and the top electrode, and is filled with dielectric material to form a dielectric layer.

[0042] This confined semiconductor device for real-time power-on performance testing is simple to fabricate, effectively reduces sample damage during FIB (Fixed In-Situ Power-On) testing, and enables in-situ observation of the microstructure of semiconductor materials under power. Furthermore, because the independent nanopillar structures are encapsulated by a dielectric layer, melting and sublimation due to overheating during power-on are reduced, improving the success rate of in-situ power-on experiments and minimizing contamination of the experimental apparatus.

[0043] like Figure 2 As shown, Figure 2 a is a TEM image of an unrestricted device used for in-situ electrical experiments on semiconductor materials after being powered on. Figure 2 b is a TEM image of the restricted semiconductor device after power-on for real-time power-on performance testing. In non-restricted devices, the semiconductor material melts after in-situ power-on experiments, causing the semiconductor material to detach from the top electrode and resulting in damage to the nanopillar structure, making it impossible to simulate the actual situation of the semiconductor material in the chip during power-on. However, in the restricted semiconductor device of this invention for real-time power-on performance testing, because the dielectric layer surrounds the nanopillar structure, the integrity of the nanopillar structure can be maintained even if the semiconductor material melts, which is beneficial for the smooth conduct of in-situ power-on experiments.

[0044] like Figure 3 As shown, this embodiment also provides a method for fabricating a restricted semiconductor device for real-time power-on performance testing, comprising the following steps:

[0045] S1. Provides a support base;

[0046] S2. A bottom electrode is formed on the support base;

[0047] S3. A semiconductor material layer is formed on the surface of the bottom electrode;

[0048] S4. A top electrode is formed on the surface of the semiconductor material layer;

[0049] S5, forming a trench through the bottom electrode, the semiconductor material layer and the top electrode to obtain a nano-pillar structure;

[0050] S6, filling a dielectric material around the nano-pillar structure to form a dielectric layer;

[0051] S7, removing the dielectric layer material on the surface of the top electrode to expose the top of the top electrode.

[0052] In step S1, refer to the S1 step in Figure 3 and Figure 4 , a support base 01 is provided.

[0053] As an example, the support base 01 should be composed of a material with good electrical conductivity, such as Cu, Al, Ag, Au, etc. In this embodiment, etching and other processes can be used to remove oxides on the surface of the support base 01, and FIB can be used to thin the support base 01.

[0054] In step S2, refer to the S2 step in Figure 3 and Figure 5 , a bottom electrode 02 is formed on the support base 01.

[0055] As an example, physical vapor deposition (PVD), atomic layer deposition (ALD), etc. can be used to deposit the bottom electrode 02 on the support base, and the material of the bottom electrode 02 can be any one of Ti, W, Ta, Cu, WCN, WN, TiN and TaN, etc.

[0056] In step S3, refer to the S3 step in Figure 3 and Figure 6 , a semiconductor material layer 03 is formed on the bottom electrode 02.

[0057] As an example, PVD can be used to deposit the semiconductor material layer 03 on the bottom electrode 02, and the material of the semiconductor material layer 03 can be: Si, Ge, Si-Ge, etc. material system for integrated circuits and logic devices, Ga-As, In-P, Ga-N, etc. material system for radio frequency devices, Si-C, Ga-O, etc. material system for power electronic devices, Cd-Se, Pb-S, etc. material system for sensors and detectors, Ge-Sb-Te, Sb-Te, Ge-Te, As-Se, Ge-As-Se, Hf-O, Ti-O, Mo-S, B-N, Co-Fe-B, Co-Mn-Si, etc. material system for memory devices.

[0058] In step S4, refer to the S4 step in Figure 2 andFigure 7 A top electrode 04 is formed on the semiconductor material layer 03.

[0059] As an example, the top electrode 04 can be deposited on the semiconductor material layer 03 by using, but not limited to, PVD, ALD, etc. The material of the top electrode 04 can be any one of Ti, W, Ta, Cu, WN, TiN, TaN, etc.

[0060] In step S5, please refer to the S5 step in Figure 3 and Figure 8 , a trench is formed through the bottom electrode 02, the semiconductor material layer 03 and the top electrode 04, so as to form independent nano-pillar structures.

[0061] As an example, the designed structure can be etched by using, but not limited to, FIB controlled ion beam deflection.

[0062] In step S6, please refer to the S6 step in Figure 3 and Figure 9 , a dielectric layer 05 is formed by filling a dielectric material around the nano-pillar structures.

[0063] As an example, the dielectric layer can be deposited around the nano-pillar structures by using, but not limited to, PVD, chemical vapor deposition (CVD), etc. In the FIB system, gas assisted ion beam deposition, etc. can also be used. The material of the dielectric layer 05 can be any one of SiN x , SiO2, HfO2, Al2O3, etc.

[0064] In step S7, please refer to the S7 step in Figure 3 and Figure 1 , the dielectric layer 05 material on the surface of the top electrode 04 is removed, and the top of the top electrode 04 is exposed.

[0065] As an example, the designed structure can be etched by using, but not limited to, a plasma etching machine or FIB controlled ion beam deflection.

[0066] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A restricted semiconductor device for real-time power-on performance testing, comprising a support base, a bottom electrode, a semiconductor material layer, a top electrode, and a dielectric layer, characterized in that: The bottom electrode is located above the support base; The semiconductor material layer is located above the bottom electrode; the top electrode is located above the semiconductor material layer; a through-type independent nanopillar structure is provided between the bottom electrode, the semiconductor material layer and the top electrode, and a dielectric material is filled to form a dielectric layer.

2. The confinement semiconductor device according to claim 1, characterized in that: The material of the support base is selected from one or more of Cu, Al, Ag, and Au; the support base shall undergo surface oxide removal and thinning treatment.

3. The confinement semiconductor device according to claim 1, characterized in that: The material of the bottom electrode is selected from one or more of Ti, W, Ta, Cu, WCN, WN, TiN, and TaN.

4. The confinement semiconductor device according to claim 1, characterized in that: The material of the semiconductor material layer is selected from one or more of the following: materials used in integrated circuits and logic devices, materials used in radio frequency devices, materials used in power electronic devices, materials used in sensors and detectors, and materials used in storage devices.

5. The confinement semiconductor device according to claim 1, characterized in that: The material of the top electrode is one or more of Ti, W, Ta, Cu, WN, TiN, and TaN.

6. The confinement semiconductor device according to claim 1, characterized in that: The dielectric material is SiN. x One or more of SiO2, HfO2, and Al2O3.

7. The confinement semiconductor device according to claim 1, characterized in that: The thickness of the dielectric layer is less than 15 nm.

8. A method for fabricating a restricted semiconductor device for real-time power-on performance testing as described in claim 1, comprising the following steps: S1. Provides a support base; S2. A bottom electrode is formed on the support base; S3. A semiconductor material layer is formed on the surface of the bottom electrode; S4. A top electrode is formed on the surface of the semiconductor material layer; S5. Form a trench that connects the bottom electrode, the semiconductor material layer and the top electrode to obtain an independent nanopillar structure; S6. A dielectric layer is formed by filling the periphery of the nano-column structure with a dielectric material. S7. Remove the dielectric material from the surface of the top electrode to expose the top of the top electrode, thereby obtaining the confined semiconductor device.

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