Method and system for measuring transmission delay of input / output unit

Abstract

The invention relates to the technical field of transmission time delay measurement, in particular to an input and output unit transmission time delay measurement method and system.The method comprises the steps that a ring oscillator is obtained, the ring oscillator comprises an input and output unit, a monitoring mode control circuit and an oscillation control circuit, the input and output unit comprises a plurality of cascaded test units, and the monitoring mode control circuit is connected with the oscillation control circuit; the method comprises the following steps: determining a monitoring mode by using a monitoring mode control circuit, acquiring a fixed level signal based on the monitoring mode, extracting an internal intermediate signal from a ring oscillator, driving the ring oscillator to start oscillation based on the fixed level signal and an oscillation control circuit to obtain a ringout signal, and performing combinational logic processing on the internal intermediate signal to obtain a reset signal. And measuring the pulse width of the ringout signal according to the reset signal, determining the transmission time delay based on the pulse width, and completing the measurement of the transmission time delay of the input / output unit. According to the invention, the real-time performance, the measurement precision and the measurement efficiency of the measurement of the transmission time delay of the chip input / output unit can be improved.

Description

Technical Field

[0001] This invention relates to the field of transmission delay measurement technology, and in particular to a method and system for measuring the transmission delay of an input / output unit. Background Technology

[0002] With the continuous development of semiconductor technology, the design scale of chips is constantly expanding. The transmission delay of important chip units is a key parameter that determines the chip's highest operating frequency. Its accurate measurement is of great significance for ensuring chip performance, power consumption and reliability.

[0003] Traditional methods for measuring the propagation delay of critical chip units typically employ delay measurement methods based on external test equipment and measurement using on-chip ring oscillator monitoring circuits. While these methods can measure propagation delay, they cannot provide real-time feedback. Furthermore, due to the complexity and diversity of chip designs, they also suffer from limitations in measurement accuracy and efficiency. Therefore, current methods for measuring the propagation delay of critical chip units suffer from insufficient real-time performance, low measurement accuracy, and low measurement efficiency. Summary of the Invention

[0004] This invention provides a method and system for measuring the transmission delay of input / output units, the main purpose of which is to improve the real-time performance, accuracy and efficiency of measuring the transmission delay of chip input / output units.

[0005] To achieve the above objectives, the present invention provides a method for measuring the transmission delay of an input / output unit, comprising:

[0006] Obtain a ring oscillator, wherein the ring oscillator includes: an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, and the input / output unit contains multiple cascaded test units;

[0007] The monitoring mode is determined by the monitoring mode control circuit.

[0008] Based on monitoring mode, acquire fixed-level signals;

[0009] Extract the internal intermediate signal from the ring oscillator;

[0010] Based on a fixed-level signal and an oscillation control circuit, a ring oscillator is driven to start oscillating, and the ring_out signal is obtained.

[0011] The internal intermediate signals are processed by combinational logic to obtain set / reset signals;

[0012] Measure the pulse width of the ring_out signal based on the reset signal;

[0013] Based on the pulse width, the transmission delay is determined, and the transmission delay of the input and output units is measured.

[0014] Optionally, the test unit includes: an input port A and an output port Z, wherein the input port A is a 1-bit input port and the output port Z is a 1-bit output port. The input port A and the output port Z form an internal timing path, which is used to measure the transmission delay of the ring_out signal in the input-output unit.

[0015] Optionally, the internal timing path includes: a custom logic circuit, a first level conversion unit, a second level conversion unit, and an output buffer unit, wherein the ring_out signal is input from input port A, passes through the custom logic circuit, the first level conversion unit, the second level conversion unit, and the output buffer unit in sequence, and is finally output from output port Z.

[0016] Optionally, determining the monitoring mode using the monitoring mode control circuit includes:

[0017] The 3-to-8 decoder was identified from the monitoring mode control circuit;

[0018] The monitoring mode is determined by receiving a preset external enable signal and a preset mode selection signal using a 3-8 decoder. The monitoring mode includes monitoring input / output unit data transmission "1" and monitoring input / output unit data transmission "0".

[0019] Optionally, the step of using a 3-8 decoder to receive a preset external enable signal and a preset mode selection signal to determine the monitoring mode includes:

[0020] Confirm the level state of the external enable signal and the 3-bit code of the mode selection signal, wherein the level state of the enable signal includes "0" and "1", and the 3-bit code of the mode selection signal includes "000", "001", "010", "011", "100", "101", "110" and "111".

[0021] The monitoring mode is determined based on the level state and the 3-bit code. When the level state is "0" and the 3-bit code is "100", the monitoring mode is to monitor the transmission of "1" by the input / output unit. When the level state is "0" and the 3-bit code is "001", the monitoring mode is to monitor the transmission of "0" by the input / output unit.

[0022] Optionally, acquiring a fixed-level signal based on the monitoring mode includes:

[0023] Based on the monitoring mode, a 3-to-8 decoder is used for decoding to obtain the output of the 3-to-8 decoder.

[0024] Obtain a D flip-flop, wherein the D flip-flop includes: a D terminal, a Q terminal, a CLK terminal, a SET terminal, and a RESET terminal;

[0025] The output of the 3-8 decoder is combined with a preset first combinational logic circuit to obtain a fixed-level signal. The fixed-level signal is used as input to the D terminal of the D flip-flop. The fixed-level signal includes a high-level fixed signal and a low-level fixed signal. The high-level fixed signal corresponds to the monitoring mode of data transmission "1" in the monitoring input / output unit, and the low-level fixed signal corresponds to the monitoring mode of data transmission "0" in the monitoring input / output unit.

[0026] Optionally, the step of driving the ring oscillator to oscillate based on a fixed-level signal and an oscillation control circuit to obtain the ring_out signal includes:

[0027] The initial state of the internal intermediate signal is determined, wherein the initial state of the internal intermediate signal is "0" or "1", the initial state "0" corresponds to a high-level fixed signal, and the initial state "1" corresponds to a low-level fixed signal.

[0028] The enable signal is obtained based on the internal intermediate signal and the fixed level signal;

[0029] The delay unit is identified from the oscillation control circuit, and the enable signal is input to the delay unit to obtain the delay signal;

[0030] The enable signal and the delay signal are XORed to obtain the XOR output signal.

[0031] The XOR output signal is input to the CLK terminal of the D flip-flop, and after being output from the Q terminal of the D flip-flop, it is combined and output through a preset third combinational logic circuit to obtain the ring_out signal.

[0032] Optionally, obtaining the enable signal based on the internal intermediate signal and the fixed-level signal includes:

[0033] The internal intermediate signal is XORed with a fixed-level signal to obtain an enable signal. When the monitoring mode is monitoring the data transmission of the input / output unit "1", the initial state of the internal intermediate signal is "0" and when the monitoring mode is monitoring the data transmission of the input / output unit "0", the initial state of the internal intermediate signal is "1".

[0034] Optionally, the step of performing combinational logic processing on the internal intermediate signals to obtain the set / reset signal includes:

[0035] The internal intermediate signal is input to a preset second combinational logic circuit for combination and output to obtain a set / reset signal. The set / reset signal includes a set signal and a reset signal. When the monitoring mode is monitoring the data transmission of the input / output unit "1", the reset signal is input to the RESET terminal of the D flip-flop. When the monitoring mode is monitoring the data transmission of the input / output unit "0", the set signal is input to the SET terminal of the D flip-flop.

[0036] To achieve the above objectives, the present invention also provides a measurement system for the transmission delay of an input / output unit, comprising:

[0037] An oscillator configuration module is used to acquire a ring oscillator, wherein the ring oscillator includes: an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, and the input / output unit contains multiple cascaded test units;

[0038] The monitoring mode control module is used to determine the monitoring mode using the monitoring mode control circuit and to acquire a fixed level signal based on the monitoring mode.

[0039] The signal generation module is used to extract the internal intermediate signal from the ring oscillator, drive the ring oscillator to start oscillating based on the fixed level signal and the oscillation control circuit, obtain the ring_out signal, and perform combinational logic processing on the internal intermediate signal to obtain the set / reset signal.

[0040] The transmission delay calculation module is used to measure the pulse width of the ring_out signal based on the reset signal, determine the transmission delay based on the pulse width, and complete the measurement of the transmission delay of the input and output units.

[0041] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0042] A memory that stores at least one instruction; and a processor that executes the instructions stored in the memory to implement the above-described method for measuring the transmission delay of the input / output unit.

[0043] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the above-described method for measuring the transmission delay of an input / output unit.

[0044] To address the problems described in the background section, this invention provides a ring oscillator comprising an input / output unit, a monitoring mode control circuit, and an oscillation control circuit. The input / output unit includes multiple cascaded test units. By incorporating the transmission delay of the input / output unit into the ring oscillator for measurement and evaluation, this invention ensures that the oscillation frequency of the ring oscillator accurately reflects the transmission delay characteristics of the input / output unit, thereby improving the real-time performance, accuracy, and efficiency of the measurement. The monitoring mode control circuit determines the monitoring mode, and based on this mode, a fixed-level signal is acquired. An internal intermediate signal is extracted from the ring oscillator, and the measurement is then performed based on the fixed-level signal and the oscillation control circuit. The circuit drives a ring oscillator to oscillate, generating a ring_out signal. Combinatorial logic processing is performed on the internal intermediate signal to obtain a reset signal. Based on the reset signal, the pulse width of the ring_out signal is measured. This invention generates the reset signal by inputting the internal intermediate signal into a second combinational logic circuit, and then inputs the reset signal into a D flip-flop to trigger the level state of the ring_out signal to flip, thereby determining the pulse width of the ring_out signal. This invention determines the transmission delay by measuring the pulse width, resulting in a more accurate transmission delay. Based on the pulse width, the transmission delay is determined, completing the measurement of the transmission delay of the input / output unit. Therefore, this invention can improve the real-time performance, measurement accuracy, and measurement efficiency of the transmission delay measurement of the chip's input / output unit. Attached Figure Description

[0045] Figure 1 A flowchart illustrating a method for measuring the transmission delay of an input / output unit according to an embodiment of the present invention;

[0046] Figure 2 This is an overall block diagram of a ring oscillator for an input / output unit provided in an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of the key timing path of an input / output unit provided in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the key timing path of a test unit provided in an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the circuit structure of the monitoring data transmission "1" mode of the input / output unit provided in an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram of the circuit structure of the input / output unit in monitoring data transmission mode "0" according to an embodiment of the present invention;

[0051] Figure 7This is a schematic diagram of the circuit timing relationship of the monitoring data transmission "1" mode of the input / output unit provided in an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of the circuit timing relationship of the monitoring data transmission of the input / output unit in the "0" mode according to an embodiment of the present invention;

[0053] Figure 9 This is a schematic diagram showing the change in circuit timing relationship of the monitoring data transmission "1" mode of the input / output unit according to an embodiment of the present invention;

[0054] Figure 10 This is a schematic diagram illustrating the changes in circuit timing relationships during the monitoring data transmission "0" mode of an input / output unit according to an embodiment of the present invention.

[0055] Figure 11 This is a functional block diagram of an input / output unit transmission delay measurement system provided in an embodiment of the present invention.

[0056] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0057] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0058] This application provides a method for measuring the transmission delay of an input / output unit. The execution subject of this method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the method for measuring the transmission delay of an input / output unit can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0059] Reference Figure 1 The diagram shown is a flowchart illustrating a method for measuring the transmission delay of an input / output unit according to an embodiment of the present invention. In this embodiment, the method for measuring the transmission delay of the input / output unit includes:

[0060] S1. Obtain a ring oscillator, wherein the ring oscillator includes: an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, and the input / output unit contains multiple cascaded test units.

[0061] Understandably, see Figure 2As shown, the ring oscillator refers to an oscillator composed of an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, used to measure the transmission delay of the input / output unit. The input / output unit refers to the functional unit inside the chip responsible for communication between the chip's internal logic and external pins, typically composed of input registers, output registers, and driver circuits. The timing performance of the input / output unit directly determines the interface speed between the chip and external devices (such as DDR, ADC / DAC, and processors). The monitoring mode control circuit refers to the circuit module used to select and switch the ring oscillator's operating mode, allowing selection of two monitoring modes: monitoring input / output unit data transmission "1" and monitoring input / output unit data transmission "0". The oscillation control circuit refers to the circuit module used to generate and control the ring oscillation. It generates an enable signal by performing an XOR operation between an internal intermediate signal and a fixed-level signal. After inputting this signal to a delay unit, a delay signal is generated. An XOR operation is then performed between the enable signal and the delay signal to generate a clock pulse input to the CLK terminal of the D flip-flop, causing the ring oscillator to start oscillating.

[0062] In detail, the test unit includes: input port A and output port Z, wherein input port A is a 1-bit input port and output port Z is a 1-bit output port. Input port A and output port Z form an internal timing path, which is used to measure the transmission delay of the ring_out signal in the input and output unit.

[0063] It should be noted that, for reference Figure 3 As shown, the test unit refers to the basic structure of the timing critical path constituting the input / output unit, and each test unit contains one internal timing path. In this method, multiple test units are connected in a cascaded manner to form a complete signal transmission channel. The output port A of the previous stage test unit is connected to the input port Z of the next stage test unit, so that the signal is transmitted sequentially in the cascaded structure. The delay generated by all test units in the cascaded structure is accumulated to form the total transmission delay.

[0064] Specifically, the internal timing path includes: a custom logic circuit, a first level conversion unit, a second level conversion unit, and an output buffer unit. The ring_out signal is input from input port A, passes through the custom logic circuit, the first level conversion unit, the second level conversion unit, and the output buffer unit in sequence, and is finally output from output port Z.

[0065] It needs to be explained that, see reference Figure 4As shown, the internal timing path refers to the critical timing path of the test unit, and the custom logic circuit refers to the logic circuit connected to A in the internal timing path. The first level conversion unit refers to the level conversion circuit connected to the custom logic circuit. The second level conversion unit refers to the level conversion circuit connected to the output buffer. The output buffer unit refers to the output buffer connected to Z.

[0066] S2. Use the monitoring mode control circuit to determine the monitoring mode.

[0067] Furthermore, the method of determining the monitoring mode using the monitoring mode control circuit includes:

[0068] The 3-to-8 decoder was identified from the monitoring mode control circuit;

[0069] The monitoring mode is determined by receiving a preset external enable signal and a preset mode selection signal using a 3-8 decoder. The monitoring mode includes monitoring input / output unit data transmission "1" and monitoring input / output unit data transmission "0".

[0070] It should be understood that the external enable signal refers to the signal used to control the operating state of the 3-to-8 decoder, which can control the 3-to-8 decoder to turn on and off according to its own level state. The mode selection signal refers to the 3-bit binary encoded signal used to determine the monitoring mode executed by the monitoring mode control circuit, which can select the corresponding monitoring mode according to the specific value of its 3-bit encoding. The level state of the mode selection signal and the specific value of the 3-bit encoding of the external enable signal are both set based on actual measurement requirements.

[0071] In detail, the method of using a 3-8 decoder to receive a preset external enable signal and a preset mode selection signal to determine the monitoring mode includes:

[0072] Confirm the level state of the external enable signal and the 3-bit code of the mode selection signal, wherein the level state of the enable signal includes "0" and "1", and the 3-bit code of the mode selection signal includes "000", "001", "010", "011", "100", "101", "110" and "111".

[0073] The monitoring mode is determined based on the level state and the 3-bit code. When the level state is "0" and the 3-bit code is "100", the monitoring mode is to monitor the transmission of "1" by the input / output unit. When the level state is "0" and the 3-bit code is "001", the monitoring mode is to monitor the transmission of "0" by the input / output unit.

[0074] It is understood that the external enable signal level includes "0" and "1". When the external enable signal level is "0", the 3-to-8 decoder is in operation; when the external enable signal level is "1", the 3-to-8 decoder is in disabled state, does not decode the mode selection signal, and disables the monitoring mode. Each bit in the 3-bit code of the mode selection signal has a value of either "0" or "1". When the value of the 3-bit code of the mode selection signal changes, the monitoring mode will also change accordingly. The monitoring input / output unit data transmission "1" refers to the monitoring mode of the transmission delay of the measurement data "1" (i.e., high-level signal) in the timing critical path of the input / output unit. The monitoring input / output unit data transmission "0" refers to the monitoring mode of the transmission delay of the measurement data "0" (i.e., low-level signal) in the timing critical path of the input / output unit.

[0075] S3. Based on monitoring mode, acquire fixed level signals.

[0076] Specifically, acquiring a fixed-level signal based on the monitoring mode includes:

[0077] Based on the monitoring mode, a 3-to-8 decoder is used for decoding to obtain the output of the 3-to-8 decoder.

[0078] Obtain a D flip-flop, wherein the D flip-flop includes: a D terminal, a Q terminal, a CLK terminal, a SET terminal, and a RESET terminal;

[0079] The output of the 3-8 decoder is combined with a preset first combinational logic circuit to obtain a fixed-level signal. The fixed-level signal is used as input to the D terminal of the D flip-flop. The fixed-level signal includes a high-level fixed signal and a low-level fixed signal. The high-level fixed signal corresponds to the monitoring mode of data transmission "1" in the monitoring input / output unit, and the low-level fixed signal corresponds to the monitoring mode of data transmission "0" in the monitoring input / output unit.

[0080] It should be explained that the decoding process refers to the process by which the 3-to-8 decoder decodes the mode selection signal. The 3-to-8 decoder output refers to the 8-bit signal obtained after the 3-to-8 decoder decodes the mode selection signal, for example, when the level state... "0", mode selection signal When 3'b000, the output Y of the 3-to-8 decoder is <7:0>. 8'b0000_0001; When the level state "0", mode_sel<2:0> At 3'b001, the output Y of the 3-to-8 decoder is <7:0>. 8'b0000_0010; When the level state "0", mode_sel<2:0> When 3'b010, the output Y of the 3-to-8 decoder is <7:0>. 8'b0000_0100.

[0081] It should be noted that the phrase "combining the output of the 3-to-8 decoder with a preset first combinational logic circuit to obtain a fixed-level signal" means that after the output of the 3-to-8 decoder is input into the first combinational logic circuit, the first combinational logic circuit outputs a stable level signal to the D terminal of the D flip-flop. This stable level signal is the fixed-level signal. (See also...) Figure 5 , Figure 6 As shown, the first combinational logic circuit refers to the combinational logic circuit located between the 3-8 decoder and the D terminal of the D flip-flop. The high-level fixed signal refers to the logic high-level signal output by the first combinational logic circuit when the monitoring mode is monitoring the data transmission of input / output unit "1". This signal is input to the D terminal of the D flip-flop to ensure that the D flip-flop outputs a high level when the ring oscillator starts oscillating, thereby measuring the transmission delay of data "1" in the timing critical path. The low-level fixed signal refers to the logic low-level signal output by the first combinational logic circuit when the monitoring mode is monitoring the data transmission of input / output unit "0". This signal is input to the D terminal of the D flip-flop to ensure that the D flip-flop outputs a low level when the ring oscillator starts oscillating, thereby measuring the transmission delay of data "0" in the timing critical path.

[0082] It is understandable that measuring the data "1" represents measuring the propagation delay of the signal's rising edge in the input / output unit, while measuring the data "0" represents measuring the propagation delay of the signal's falling edge in the input / output unit.

[0083] S4. Extract the internal intermediate signal from the ring oscillator, and drive the ring oscillator to start oscillating based on the fixed level signal and the oscillation control circuit to obtain the ring_out signal.

[0084] Furthermore, the step of driving the ring oscillator to oscillate based on a fixed-level signal and an oscillation control circuit to obtain the ring_out signal includes:

[0085] The initial state of the internal intermediate signal is determined, wherein the initial state of the internal intermediate signal is "0" or "1", the initial state "0" corresponds to a high-level fixed signal, and the initial state "1" corresponds to a low-level fixed signal.

[0086] The enable signal is obtained based on the internal intermediate signal and the fixed level signal;

[0087] The delay unit is identified from the oscillation control circuit, and the enable signal is input to the delay unit to obtain the delay signal;

[0088] The enable signal and the delay signal are XORed to obtain the XOR output signal.

[0089] The XOR output signal is input to the CLK terminal of the D flip-flop, and after being output from the Q terminal of the D flip-flop, it is combined and output through a preset third combinational logic circuit to obtain the ring_out signal.

[0090] It should be understood that the internal intermediate signals refer to the node signals extracted from the timing critical path of the input / output unit. See also... Figure 5 , Figure 6 As shown, optionally, in this method, the internal intermediate signal is ring_in<2:0>. The enable signal will be explained in subsequent steps; optionally, in this method, the enable signal is en_osc. The delay unit refers to the timing delay circuit (i.e., DLY_BUF in the figure), whose function is to generate an output signal that is the same as the input signal but delayed by a fixed time after the input signal (i.e., en_osc) is input to the delay unit. The delay signal refers to the output signal generated by the delay unit that is the same as the input signal but delayed by a fixed time. Optionally, in this method, the delay signal is the en_osc_delay signal. The XOR output signal refers to the signal obtained by performing an XOR logic operation between the enable signal and the delay signal, and this signal is input to the CLK terminal of the D flip-flop. The third combinational logic circuit refers to the combinational logic circuit connected to the Q terminal of the D flip-flop.

[0091] It needs to be explained that, see reference Figure 5 , Figure 6 , Figure 7 , Figure 8 As shown, the ring_out signal refers to the final output signal of the oscillation control circuit. For example, in the monitoring mode for monitoring the data transmission of "1" in the input / output unit, after the enable signal and the delay signal undergo an XOR operation, a pulse (i.e., the XOR output signal) is input to the CLK register. The ring oscillator then starts oscillating, and the ring_out signal is pulled high until the first pulse input to the RESET terminal of the D flip-flop arrives, pulling it low. During this period, the data "1" is transmitted in the timing critical path of the input / output unit. In the monitoring mode for monitoring the data transmission of "0" in the input / output unit, after the enable signal and the delay signal undergo an XOR operation, a pulse (i.e., the XOR output signal) is input to the CLK register. The ring oscillator then starts oscillating, and the ring_out signal is pulled low until the first pulse input to the SET terminal of the D flip-flop arrives, pulling it high. During this period, the data "0" is transmitted in the timing critical path of the input / output unit.

[0092] Specifically, obtaining the enable signal based on the internal intermediate signal and the fixed-level signal includes:

[0093] The internal intermediate signal is XORed with a fixed-level signal to obtain an enable signal. When the monitoring mode is monitoring the data transmission of the input / output unit "1", the initial state of the internal intermediate signal is "0" and when the monitoring mode is monitoring the data transmission of the input / output unit "0", the initial state of the internal intermediate signal is "1".

[0094] It should be noted that the enable signal refers to the control signal obtained by performing an XOR logic operation between the fixed level signal and the internal intermediate signal. For example, when the monitoring mode is monitoring the data transmission of the input / output unit "1", the fixed level signal is 0 (i.e., a low-level fixed signal), the initial state of the internal intermediate signal is "1", and the enable signal obtained by performing an XOR logic operation between the fixed level signal and the internal intermediate signal is 0.

[0095] S5. Perform combinational logic processing on the internal intermediate signals to obtain the reset signal.

[0096] Specifically, the step of performing combinational logic processing on the internal intermediate signals to obtain the set / reset signal includes:

[0097] The internal intermediate signal is input to a preset second combinational logic circuit for combination and output to obtain a set / reset signal. The set / reset signal includes a set signal and a reset signal. When the monitoring mode is monitoring the data transmission of the input / output unit "1", the reset signal is input to the RESET terminal of the D flip-flop. When the monitoring mode is monitoring the data transmission of the input / output unit "0", the set signal is input to the SET terminal of the D flip-flop.

[0098] Understandably, see Figure 5 , Figure 6 As shown, the second combinational logic circuit refers to the combinational logic circuit responsible for receiving ring_in<2:0> and transmitting it to the SET or RESET terminal of the D flip-flop.

[0099] S6. Measure the pulse width of the ring_out signal based on the reset signal.

[0100] It needs to be explained that, see reference Figure 5 , Figure 7 As shown, when the RESET terminal of the D flip-flop receives a reset signal, the Q output of the D flip-flop will be reset to a low level, thereby causing the ring_out signal to jump from a high level to a low level. At this time, the pulse width of the ring_out signal is measured, which is the duration of the ring_out signal from the rising edge to the falling edge within one CLK cycle.

[0101] Understandably, see Figure 6 , Figure 8 As shown, when the SET terminal of the D flip-flop receives a set signal, the Q output of the D flip-flop will be set to a high level, which will cause the ring_out signal to jump from a low level to a high level. At this time, the pulse width of the ring_out signal is measured, which is the duration of the ring_out signal from the falling edge to the rising edge within one CLK cycle.

[0102] S7. Based on the pulse width, determine the transmission delay and complete the measurement of the transmission delay of the input / output unit.

[0103] It should be understood that, see Figure 9 , Figure 10 As shown, the ring_in in ring_in<2:0> <0> The ring_out signal is a direct interface signal in the timing critical path of the input / output unit that does not pass through any logic or oscillation control circuit. Therefore, the ring_out signal in one CLK cycle reflects the delay of data "0" or data "1" in the timing critical path of the input / output unit. Thus, the transmission delay of the input / output unit can be determined based on the pulse width of the ring_out signal.

[0104] To address the problems described in the background section, this invention provides a ring oscillator comprising an input / output unit, a monitoring mode control circuit, and an oscillation control circuit. The input / output unit includes multiple cascaded test units. By incorporating the transmission delay of the input / output unit into the ring oscillator for measurement and evaluation, this invention ensures that the oscillation frequency of the ring oscillator accurately reflects the transmission delay characteristics of the input / output unit, thereby improving the real-time performance, accuracy, and efficiency of the measurement. The monitoring mode control circuit determines the monitoring mode, and based on this mode, a fixed-level signal is acquired. An internal intermediate signal is extracted from the ring oscillator, and the measurement is then performed based on the fixed-level signal and the oscillation control circuit. The circuit drives a ring oscillator to oscillate, generating a ring_out signal. Combinatorial logic processing is performed on the internal intermediate signal to obtain a reset signal. Based on the reset signal, the pulse width of the ring_out signal is measured. This invention generates the reset signal by inputting the internal intermediate signal into a second combinational logic circuit, and then inputs the reset signal into a D flip-flop to trigger the level state of the ring_out signal to flip, thereby determining the pulse width of the ring_out signal. This invention determines the transmission delay by measuring the pulse width, resulting in a more accurate transmission delay. Based on the pulse width, the transmission delay is determined, completing the measurement of the transmission delay of the input / output unit. Therefore, this invention can improve the real-time performance, measurement accuracy, and measurement efficiency of the transmission delay measurement of the chip's input / output unit.

[0105] likeFigure 11 The diagram shown is a functional block diagram of an input / output unit transmission delay measurement system provided in an embodiment of the present invention.

[0106] The input / output unit transmission delay measurement system 100 of the present invention can be installed in an electronic device. Depending on the functions implemented, the input / output unit transmission delay measurement system 100 may include an oscillator configuration module 101, a monitoring mode control module 102, a signal generation module 103, and a transmission delay calculation module 104. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0107] The oscillator configuration module 101 is used to acquire a ring oscillator, wherein the ring oscillator includes: an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, and the input / output unit includes multiple cascaded test units.

[0108] The monitoring mode control module 102 is used to determine the monitoring mode using the monitoring mode control circuit and to obtain a fixed level signal based on the monitoring mode.

[0109] The signal generation module 103 is used to extract the internal intermediate signal from the ring oscillator, drive the ring oscillator to start oscillating based on the fixed level signal and the oscillation control circuit, obtain the ring_out signal, and perform combinational logic processing on the internal intermediate signal to obtain the reset signal.

[0110] The transmission delay calculation module 104 is used to measure the pulse width of the ring_out signal according to the reset signal, determine the transmission delay based on the pulse width, and complete the measurement of the transmission delay of the input / output unit.

[0111] In detail, the modules in the input / output unit transmission delay measurement system 100 described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The method used is the same as the measurement method for the transmission delay of the input / output unit described above, and it can produce the same technical effect, so it will not be repeated here.

[0112] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0113] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0115] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for measuring the transmission delay of an input / output unit, characterized in that, The method includes: Obtain a ring oscillator, wherein the ring oscillator includes: an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, and the input / output unit contains multiple cascaded test units; The monitoring mode is determined by the monitoring mode control circuit. Based on monitoring mode, acquire fixed-level signals; Extract the internal intermediate signal from the ring oscillator; Based on a fixed-level signal and an oscillation control circuit, a ring oscillator is driven to start oscillating, and the ring_out signal is obtained. The internal intermediate signals are processed by combinational logic to obtain set / reset signals; Measure the pulse width of the ring_out signal based on the reset signal; Based on the pulse width, the transmission delay is determined, and the transmission delay of the input and output units is measured.

2. The method for measuring the transmission delay of an input / output unit as described in claim 1, characterized in that, The test unit includes an input port A and an output port Z, wherein the input port A is a 1-bit input port and the output port Z is a 1-bit output port. The input port A and the output port Z form an internal timing path, which is used to measure the transmission delay of the ring_out signal in the input and output unit.

3. The method for measuring the transmission delay of an input / output unit as described in claim 2, characterized in that, The internal timing path includes: a custom logic circuit, a first level conversion unit, a second level conversion unit, and an output buffer unit. The ring_out signal is input from input port A, passes through the custom logic circuit, the first level conversion unit, the second level conversion unit, and the output buffer unit in sequence, and is finally output from output port Z.

4. The method for measuring the transmission delay of an input / output unit as described in claim 1, characterized in that, The method of determining the monitoring mode using the monitoring mode control circuit includes: The 3-to-8 decoder was identified from the monitoring mode control circuit; The monitoring mode is determined by receiving a preset external enable signal and a preset mode selection signal using a 3-8 decoder. The monitoring mode includes monitoring input / output unit data transmission "1" and monitoring input / output unit data transmission "0".

5. The method for measuring the transmission delay of an input / output unit as described in claim 4, characterized in that, The step of using a 3-8 decoder to receive a preset external enable signal and a preset mode selection signal to determine the monitoring mode includes: Confirm the level state of the external enable signal and the 3-bit code of the mode selection signal, wherein the level state of the enable signal includes "0" and "1", and the 3-bit code of the mode selection signal includes "000", "001", "010", "011", "100", "101", "110" and "111"; The monitoring mode is determined based on the level state and the 3-bit code. When the level state is "0" and the 3-bit code is "100", the monitoring mode is to monitor the input / output unit to transmit "1". When the level state is "0" and the 3-bit code is "001", the monitoring mode is to monitor the input / output unit to transmit "0".

6. The method for measuring the transmission delay of an input / output unit as described in claim 4, characterized in that, The acquisition of fixed-level signals based on monitoring mode includes: Based on the monitoring mode, a 3-to-8 decoder is used for decoding to obtain the output of the 3-to-8 decoder. Obtain a D flip-flop, wherein the D flip-flop includes: a D terminal, a Q terminal, a CLK terminal, a SET terminal, and a RESET terminal; The output of the 3-8 decoder is combined with a preset first combinational logic circuit to obtain a fixed-level signal. The fixed-level signal is used as input to the D terminal of the D flip-flop. The fixed-level signal includes a high-level fixed signal and a low-level fixed signal. The high-level fixed signal corresponds to the monitoring mode of data transmission "1" in the monitoring input / output unit, and the low-level fixed signal corresponds to the monitoring mode of data transmission "0" in the monitoring input / output unit.

7. The method for measuring the transmission delay of an input / output unit as described in claim 6, characterized in that, The method based on a fixed-level signal and an oscillation control circuit drives a ring oscillator to oscillate, obtaining the ring_out signal, including: The initial state of the internal intermediate signal is determined, wherein the initial state of the internal intermediate signal is "0" or "1", the initial state "0" corresponds to a high-level fixed signal, and the initial state "1" corresponds to a low-level fixed signal. The enable signal is obtained based on the internal intermediate signal and the fixed level signal; The delay unit is identified from the oscillation control circuit, and the enable signal is input to the delay unit to obtain the delay signal; The enable signal and the delay signal are XORed to obtain the XOR output signal. The XOR output signal is input to the CLK terminal of the D flip-flop, and after being output from the Q terminal of the D flip-flop, it is combined and output through a preset third combinational logic circuit to obtain the ring_out signal.

8. The method for measuring the transmission delay of an input / output unit as described in claim 7, characterized in that, The step of obtaining the enable signal based on the internal intermediate signal and the fixed level signal includes: The internal intermediate signal is XORed with a fixed-level signal to obtain an enable signal. When the monitoring mode is monitoring the data transmission of the input / output unit "1", the initial state of the internal intermediate signal is "0" and when the monitoring mode is monitoring the data transmission of the input / output unit "0", the initial state of the internal intermediate signal is "1".

9. The method for measuring the transmission delay of an input / output unit as described in claim 8, characterized in that, The step of performing combinational logic processing on the internal intermediate signals to obtain the set / reset signals includes: The internal intermediate signal is input to a preset second combinational logic circuit for combination and output to obtain a set / reset signal. The set / reset signal includes a set signal and a reset signal. When the monitoring mode is monitoring the data transmission of the input / output unit "1", the reset signal is input to the RESET terminal of the D flip-flop. When the monitoring mode is monitoring the data transmission of the input / output unit "0", the set signal is input to the SET terminal of the D flip-flop.

10. A measurement system for the transmission delay of an input / output unit, characterized in that, The system includes: An oscillator configuration module is used to acquire a ring oscillator, wherein the ring oscillator includes: an input / output unit, a monitoring mode control circuit, and an oscillation control circuit, and the input / output unit contains multiple cascaded test units; The monitoring mode control module is used to determine the monitoring mode using the monitoring mode control circuit and to acquire a fixed level signal based on the monitoring mode. The signal generation module is used to extract the internal intermediate signal from the ring oscillator, drive the ring oscillator to start oscillating based on the fixed level signal and the oscillation control circuit, obtain the ring_out signal, and perform combinational logic processing on the internal intermediate signal to obtain the set / reset signal. The transmission delay calculation module is used to measure the pulse width of the ring_out signal based on the reset signal, determine the transmission delay based on the pulse width, and complete the measurement of the transmission delay of the input and output units.

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