Data transmission method and device, computer equipment, storage medium and product

Abstract

The invention relates to the technical field of data transmission, and particularly discloses a data transmission method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps that under the condition that a controller executes a main task, if a data transmission task between the controller and a peripheral memory is obtained, a target subtask is obtained from the data transmission task, and the data transmission task comprises a plurality of subtasks; when the target sub-task is a first type of sub-task, pausing execution of the main task and executing the first type of sub-task at the same time, and continuing to execute the main task after executing the first type of sub-task; when the target sub-task is the second type of sub-task, executing the main task and the second type of sub-task at the same time; wherein the execution duration of the second type of subtasks is longer than that of the first type of subtasks. By adopting the method, the influence of the data transmission task on the execution of the main task can be reduced.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to a data transmission method, apparatus, computer equipment, storage medium, and product. Background Technology

[0002] In various application scenarios of the controller, the controller needs to communicate with its peripheral memory to transmit data. When the controller is executing its main task (business), if it needs to transmit data with the peripheral memory, it needs to wait for a long time for the data transmission task to be executed. Only after the data transmission task is completed can the main task continue to be executed. Therefore, the entire transmission process will block the execution of the controller's main task, causing the controller to wait for a long time, which seriously affects the execution of the controller's main task. Summary of the Invention

[0003] Therefore, it is necessary to provide a data transmission method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can reduce the impact of data transmission tasks on the execution of the main task, in order to address the above-mentioned technical problems.

[0004] In a first aspect, this application provides a data transmission method applied between a controller and a peripheral memory, the method comprising:

[0005] When the controller is executing the main task, if a data transfer task between the controller and the peripheral memory is obtained, a target subtask is obtained from the data transfer task, which includes multiple subtasks.

[0006] When the target subtask is a first type of subtask, the execution of the main task is paused while the first type of subtask is executed, and the execution of the main task continues after the first type of subtask is executed.

[0007] When the target subtask is a second type of subtask, the main task and the second type of subtask are executed simultaneously.

[0008] The execution time of the second type of subtask is longer than that of the first type of subtask.

[0009] In one embodiment, after obtaining the data transfer task between the controller and the peripheral memory, the method further includes:

[0010] The data transmission task is divided into multiple sub-tasks;

[0011] Determine the execution duration of the subtask;

[0012] Determine the task scheduling cycle of the controller;

[0013] Each subtask is determined to be either a first-type subtask or a second-type subtask based on the task scheduling cycle and the execution duration.

[0014] In one embodiment, splitting the data transmission task into multiple subtasks includes: splitting the data transmission task into multiple subtasks according to the internal execution order of the data transmission task.

[0015] In one embodiment, obtaining the target subtask from the data transmission task includes: obtaining the target subtask one by one from the data transmission task according to the internal execution order of the data transmission task.

[0016] In one embodiment, determining whether each subtask is a first type of subtask or a second type of subtask based on the task scheduling period and the execution duration includes:

[0017] If the execution time of a subtask is less than one-third of the task scheduling cycle, then the subtask is determined to be a first-class subtask.

[0018] If the execution time of a subtask is greater than or equal to one-third of the task scheduling cycle, then the subtask is determined to be a second type of subtask.

[0019] In one embodiment, determining whether each subtask is a first type of subtask or a second type of subtask based on the task scheduling period and the execution duration includes:

[0020] If the execution time of a subtask is less than the task scheduling period, and the time difference between the scheduling period and the execution time of the subtask is less than or equal to a preset difference, then the subtask is determined to be a second type of subtask.

[0021] If the execution time of a subtask is less than the task scheduling period, and the time difference between the scheduling period and the execution time of the subtask is greater than a preset difference, then the subtask is determined to be a first type of subtask.

[0022] If the execution duration of a subtask is greater than or equal to the task scheduling period, then the subtask is determined to be a second type of subtask.

[0023] In one embodiment, the simultaneous execution of the main task and the second type of sub-task includes:

[0024] While executing the main task, direct memory access is controlled to transfer the data corresponding to the second type of subtask to the peripheral memory.

[0025] After the transmission is complete, the direct memory access control sends an interrupt request signal to the controller via an interrupt service routine.

[0026] Upon receiving the interruption request signal, the execution results of the second type of subtask are queried in a polling manner according to the task scheduling cycle.

[0027] In one embodiment, the method further includes:

[0028] The peripheral memory is divided into two partitions. One partition is used as a temporary storage area for the upgrade package, and the other partition is used as a backup area. The program in the backup area is the same as the program in the application partition before the controller is upgraded. The upgrade package is used to upgrade the controller.

[0029] In one embodiment, the method further includes: when the data transmission task is used for controller upgrade, determining the number of upgrades corresponding to the target upgrade package; when the number of upgrades reaches a preset number, resetting the number of upgrades to zero, deleting the program in the application partition of the controller, and transferring the program before the upgrade from the backup area of ​​the peripheral memory to the application partition of the controller.

[0030] Secondly, this application also provides a data transmission apparatus, comprising:

[0031] The acquisition module is used to acquire a target subtask from the data transmission task if a data transmission task between the controller and the peripheral memory is acquired when the controller is executing the main task. The data transmission task includes multiple subtasks.

[0032] The first execution module is configured to pause the execution of the main task and execute the first type of subtask simultaneously when the target subtask is a first type of subtask, and to continue the execution of the main task after the first type of subtask is executed;

[0033] The second execution module is used to execute the main task and the second type of subtask simultaneously when the target subtask is a second type of subtask;

[0034] The execution time of the second type of subtask is longer than that of the first type of subtask.

[0035] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in the first aspect above.

[0036] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0037] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.

[0038] The aforementioned data transmission method, apparatus, computer equipment, computer-readable storage medium, and computer program product, when the controller is executing the main task, if a data transmission task between the controller and peripheral memory is obtained, then a target subtask is obtained from the data transmission task. The data transmission task includes multiple subtasks. When the target subtask is a first type of subtask, the main task is paused while the first type of subtask is executed, and the main task continues to execute after the first type of subtask is executed. When the target subtask is a second type of subtask, the main task and the second type of subtask are executed simultaneously, with the execution time of the second type of subtask being longer than that of the first type of subtask. Therefore, for subtasks with shorter execution times, the main task is paused to wait for the subtask's execution, while the target subtask with a longer execution time is executed simultaneously with the main task, eliminating the need to wait or reducing the waiting time for that subtask, thus reducing the controller's waiting time for the data transmission task. Furthermore, without the embedded operating system intervening in the waiting process, both blocking-driven and non-blocking-driven execution of the data transmission task between the controller and peripheral memory can be achieved. Therefore, while ensuring that the controller's interrupts are not controlled by the embedded operating system, the impact of the data transmission task on the main task's execution is reduced. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is an application environment diagram of a data transmission method in one embodiment;

[0041] Figure 2 This is a flowchart illustrating a data transmission method in one embodiment;

[0042] Figure 3 This is a flowchart illustrating the process of determining whether a subtask is a first-type subtask or a second-type subtask in one embodiment.

[0043] Figure 4 This is a waveform diagram illustrating task scheduling in a single-task system according to one embodiment;

[0044] Figure 5 This is a flowchart illustrating the process of executing the main task and the second type of subtask simultaneously in an example.

[0045] Figure 6 This is a flowchart illustrating the SPI write operation of an MCU to a peripheral FLASH in a specific example.

[0046] Figure 7 This is a schematic diagram of the waveforms of the main task being executed periodically and the CLK signal of the SPI bus during SPI erase, read, and write operations in an example.

[0047] Figure 8 This is a block diagram illustrating how the peripheral FLASH is divided into two partitions, A and B, in one embodiment.

[0048] Figure 9 This is a schematic diagram of the version rollback process in one embodiment;

[0049] Figure 10 This is a flowchart illustrating the process of version rollback for an MCU in a specific example.

[0050] Figure 11 This is a structural block diagram of a data transmission device in one embodiment;

[0051] Figure 12 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0054] A controller is a device or apparatus in an automated control system that automatically monitors, adjusts, and controls the operating state of the system. The main task of a controller is to calculate and process the input signals of the controlled object and a predetermined control law to generate corresponding output signals to the controlled object, thereby achieving control over the controlled object.

[0055] The primary task of the controller can be determined by the application scenario. For example, when the controller is used in a new energy power generation system (such as photovoltaic, wind power, and energy storage systems), it controls the operation of the power converters (such as inverters, energy storage converters, PCS, etc.) in the system. In this case, the primary task can be to generate and output drive signals (PWM waves) to the power converter in real time to control the on and off of the power switching transistors in the power converter, enabling the corresponding power converter to perform rectification, inversion, and other functions. For instance, when the controller is used to control the converter of a photovoltaic power generation system, its primary task can be to detect the electrical parameters of the photovoltaic array in real time and perform maximum power point tracking control based on the electrical parameters to ensure that the output power of the photovoltaic array is at its maximum value.

[0056] When executing its main task, the controller may need to manage communication between its CPU (Central Processing Unit) and at least one peripheral device to achieve corresponding control. Data transfer between the controller and peripheral memory exists in various application scenarios. Taking the controller upgrade task as an example, data transfer between the controller and its peripheral memory is required in the scenario of upgrading the controller's business code (firmware). The conventional practice for upgrading the controller's business code is to partition the program area, where the bootloader partition is specifically responsible for the upgrade function, and the app partition is specifically responsible for the execution function of the business (main task). To ensure that the upgrade does not interrupt the business, such as... Figure 1 As shown, data transmission requires the cooperation of at least the following devices: host computer 101, file transfer channel 102, controller 103, and peripheral memory 104. Host computer 101 transmits the upgrade package to controller 103, such as MCU (Microcontroller Unit), via file transfer channel 102, such as a UART (Universal Asynchronous Receiver / Transmitter) or SPI (Serial Peripheral Interface). Controller 103 is responsible for storing the file in internal or peripheral memory 104 (such as FLASH).

[0057] To ensure uninterrupted service during transmission, the upgrade package can be downloaded to the external memory 104 first, and then the program can be moved from the external memory 104 to the internal memory during the actual upgrade. Since data transmission is time-consuming, while moving the program from the external memory 104 to the internal memory is quick, separating data transmission and program upgrade into two steps minimizes the impact of the upgrade on services. However, during the upgrade process, the real-time performance of the controller 103's main task must be strictly guaranteed (it cannot block the main task execution for extended periods), otherwise unpredictable problems may occur. The read / write speed of the external memory 104 is much slower than the execution speed of the controller 103; therefore, read / write operations on the external memory 104 will block the execution of the main task for a long time, causing the controller 104 to wait for the execution result from the external memory 104. Therefore, data transmission between the controller and the external memory during the upgrade process will block the execution of the controller's main task.

[0058] In related technologies, to prevent data transfer between the controller and its peripheral memory (such as data transfer in upgrade scenarios) from blocking the main task execution for extended periods, an embedded operating system is typically used to handle the waiting process. However, while handling the waiting process, the embedded operating system also needs to manage the on / off switching of the controller's interrupts; for example, enabling or disabling controller interrupts, which affects the execution of the main task. Therefore, the embedded operating system's control over controller interrupts can still impact the execution of the controller's main task.

[0059] Therefore, this application proposes a data transmission method for use between a controller and a peripheral memory, which can reduce the controller's waiting time and reduce the impact on the execution of the controller's main tasks without the need for an embedded operating system.

[0060] The data transmission method provided in this application embodiment can be applied to, for example... Figure 1 The application environment shown is illustrated. In this environment, the host computer 101 communicates with the controller 103 via a network. The host computer 101 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and drones. The controller 103 can include PLC controllers, MCUs, etc.

[0061] In the embodiments of this application, such as Figure 2 As shown, a data transfer method for use between a controller and a peripheral memory is provided, which is applied to... Figure 1 The following steps are used as an example to illustrate the process, taking controller 103 as an example: Steps 201 to 203. Wherein:

[0062] Step 201: When the controller is executing the main task, if a data transfer task between the controller and the peripheral memory is obtained, the target subtask is obtained from the data transfer task. The data transfer task includes multiple subtasks.

[0063] For example, when the controller is performing a main task, such as controlling the power generation of a photovoltaic array in a new energy power generation system, if it obtains a data transmission task between itself and its peripheral memory, it can first divide the data transmission task into multiple sub-tasks according to a preset splitting rule, and then obtain the target sub-task from each sub-task according to the internal execution order of the data transmission task. The target sub-task can be understood as a sub-task that needs to be executed at the moment.

[0064] Step 202: When the target subtask is a first-type subtask, pause the execution of the main task and execute the first-type subtask simultaneously, and continue the execution of the main task after executing the first-type subtask.

[0065] Step 203: When the target subtask is a second type of subtask, execute the main task and the second type of subtask simultaneously.

[0066] The execution time of the second type of subtask is longer than that of the first type of subtask. It should be noted that during data transmission, the peripheral memory needs to perform certain operations after receiving each instruction from the controller, and this operation also takes time. The execution time refers to the time required for the peripheral memory to perform the corresponding operation, which can be obtained through querying.

[0067] The criteria for determining the first and second types of subtasks can be pre-written into the controller. These criteria can characterize the degree of blocking on the controller's main task. For example, the criteria can be that target subtasks with variable execution time or those that reach a preset time are classified as second-type subtasks, while target subtasks with fixed execution time or those that do not reach a preset time are classified as first-type subtasks. The preset time can be determined based on the acceptable waiting time when the controller executes the main task. Therefore, the controller can combine the criteria and the execution time of each subtask to determine whether it is a first-type or second-type subtask.

[0068] For example, when the controller is executing the main task, for each target subtask it acquires, it can determine the required execution time of the target subtask based on the measured values ​​and the parameters given in the chip manual of the peripheral memory. Based on the required execution time of the target subtask, it judges the degree of blocking on the main task. If the execution time of the target subtask reaches the preset time, it indicates that the degree of blocking on the main task is large. That is, if the controller pauses the execution of the main task and starts executing the target subtask, the controller needs to wait for a long time. Therefore, the target subtask is judged to be a second type of subtask. If the execution time of the target subtask does not reach the preset time, it indicates that the degree of blocking on the main task is small or negligible. That is, if the controller pauses the execution of the main task and starts executing the target subtask, the controller only needs to wait for a short time. Therefore, the target subtask is judged to be a first type of subtask.

[0069] If the currently acquired target subtask is a first-type subtask, the controller pauses the execution of the main task and simultaneously executes the first-type subtask. Specifically, it sends the corresponding instruction to the first-type subtask to enable the peripheral memory to execute it. After sending the instruction, it queries the execution result using a blocking polling method. Once the first-type subtask is completed, the main task resumes execution, thus achieving blocking-driven execution of target subtasks belonging to the first-type subtask category. Because the execution time of the first-type subtask is short, the controller interrupts the execution of the main task to send the corresponding instruction and wait for the peripheral memory to execute the first-type subtask. After the first-type subtask is completed, the execution of the main task resumes. The interruption time of the controller's main task is short or negligible, and its impact on the main task's execution is small or negligible.

[0070] If the currently acquired target subtask is a second-type subtask, the controller executes both the main task and the second-type subtask simultaneously. That is, while executing the main task, the controller sends the corresponding instructions for the second-type subtask to the peripheral memory. The controller does not need to intervene in the entire sending process of the target subtask, and after sending, it does not need to wait but triggers an interrupt or directly accesses memory to begin executing the second-type subtask. The execution result from the peripheral memory is queried every preset interval, achieving non-blocking drive for the execution of target subtasks belonging to the second-type subtask category. Because the execution time of the second-type subtask is relatively long, the controller's simultaneous execution of the main task and the drive of the second-type subtask greatly reduces the phenomenon of long pauses in the main task caused by waiting for the second-type subtask to execute.

[0071] In this embodiment, when the controller is executing the main task, if a data transfer task between the controller and the peripheral memory is obtained, a target subtask is obtained from the data transfer task. The data transfer task includes multiple subtasks. When the target subtask is a first type of subtask, the main task is paused while the first type of subtask is executed, and the main task continues after the first type of subtask is executed. When the target subtask is a second type of subtask, the main task and the second type of subtask are executed simultaneously, and the execution time of the second type of subtask is longer than that of the first type of subtask. Thus, for subtasks with shorter execution times, the main task is paused to wait for the subtask to execute, while the target subtask with longer execution times is executed simultaneously with the main task, eliminating the need to wait or reducing the waiting time for the subtask, thereby reducing the controller's waiting time for the data transfer task. Moreover, the controller can achieve both blocking-driven and non-blocking-driven execution of the data transfer task between the controller and the peripheral memory without the need for the embedded operating system to take over the waiting process. Therefore, the use of an embedded operating system is unnecessary, avoiding the situation where the embedded operating system takes over the controller's interrupts, causing the controller's interrupts to become uncontrollable. At the same time, by executing the main task and some subtasks simultaneously, the impact of the data transfer task on the main task execution is reduced.

[0072] In one exemplary embodiment, such as Figure 3 As shown, after obtaining the data transfer task between the controller and the peripheral memory in step 201, steps 301 to 304 are also included. Wherein:

[0073] Step 301: Divide the data transmission task into multiple subtasks.

[0074] Further, step 301 includes: splitting the data transmission task into multiple subtasks according to the internal execution order of the data transmission task.

[0075] For example, the data transmission task can be broken down into multiple steps based on its specific internal execution flow, and these multiple steps are multiple sub-tasks.

[0076] Step 302: Determine the execution duration of the subtask.

[0077] The execution time of a subtask refers to the time required for the peripheral memory to perform the corresponding operation for that subtask.

[0078] For example, the execution time of each subtask can be queried by querying the command, or the execution time of each subtask can be determined by actual measurement and parameters given in the chip manual.

[0079] Step 303: Determine the task scheduling cycle of the controller.

[0080] The task scheduling cycle refers to the scheduling cycle of the controller tasks. The controller can be a single-task system or a multi-task system. For a single-task system, the task scheduling cycle can be obtained through hardware measurement or software timing. For a multi-task system, the task scheduling cycle of each task system can be obtained through hardware measurement or software timing, and the final task scheduling cycle can be determined based on the scheduling cycles of each task. Alternatively, the target task system for scheduling data transmission tasks can be identified, and the scheduling cycle of that target task system can be determined to obtain the task scheduling cycle.

[0081] Taking a single-task system as an example, all tasks in the system are driven by a single task, whose execution cycle is T0. System tasks are periodically scheduled and executed at time intervals of T0. That is, the task scheduling cycle of a single-task system refers to the time it takes for the entire main loop to execute once, which can be a few microseconds, tens of microseconds, or even a few seconds. Assuming the system task's status flag is 1 when executing and 0 when idle, the waveform of the status flag would be as follows. Figure 4 As shown, Figure 4 In this context, T0 represents the task scheduling cycle under a task scheduling of the controller, Ton represents the execution duration of the task, and Toff represents the idle time.

[0082] Step 304: Determine whether each subtask is a first-class subtask or a second-class subtask based on the task scheduling cycle and execution duration.

[0083] It should be noted that the actual execution time (Ton) of the subtask in the peripheral memory can vary dynamically, but it cannot exceed T0; otherwise, it will cause task pushback in the next cycle. Especially for power software, the execution cycle T0 of this task must be strictly guaranteed. Therefore, to avoid task pushback and to ensure the effectiveness of task scheduling and execution at intervals of T0, the execution time of each subtask in data transmission must be within or much less than T0 in order to enable blocking drive execution. If the subtask execution time reaches or is close to T0, blocking drive execution is not possible, and non-blocking drive execution is adopted instead.

[0084] For example, when the controller is executing the main task, if it obtains a data transfer task between itself and the peripheral memory, it divides the task into multiple subtasks according to the internal execution flow, determines the execution duration of each subtask, and determines the controller's task scheduling cycle. If the execution duration of a subtask is less than or much less than the task scheduling cycle, the subtask is identified as a first-type subtask and is driven in a blocking manner. That is, after sending the corresponding instruction, the execution result of the peripheral memory is obtained through blocking query, and the main task continues to be executed after the execution is completed. If the execution duration of a subtask reaches or is close to the task scheduling cycle, the subtask is identified as a second-type subtask and is driven in a non-blocking manner. That is, after sending the corresponding instruction, the main task continues to be executed, while actively querying the execution result of the peripheral memory.

[0085] For example, assuming the controller is an MCU and its peripheral memory is peripheral FLASH, when the MCU is executing its main task, if it receives an upgrade command from the host computer, the MCU will break down the data transfer task between itself and the peripheral FLASH during the upgrade process into multiple sub-tasks. Then, it will acquire each sub-task one by one according to the execution time. For each target sub-task acquired, it will determine the task type and execute it. Taking the acquisition of a target sub-task as an example of performing a write operation on the peripheral FLASH: the SPI write operation task of the peripheral FLASH is broken down into three sub-tasks according to the execution order:

[0086] Subtask 1: Send a write enable signal to the peripheral FLASH (transmit a 1-byte command word via the SPI bus);

[0087] Subtask 2: Send a write address signal to the peripheral FLASH (transmit a 4-byte command word via the SPI bus);

[0088] Subtask 3: Send data of a certain length (N bytes) (transmit N bytes of data via the SPI bus).

[0089] Then, the controller first obtains the write enable subtask according to the execution order. Based on actual measurements and parameters provided by the chip, it is determined that the execution time of the write enable subtask is less than the preset time. Therefore, it can be identified as a first-type subtask and executed using a blocking operation. That is, the execution of the main task is paused while the write enable task for the peripheral FLASH is executed, and a waiting period is implemented. After the peripheral FLASH write enable subtask is found to be completed, the main task continues execution. Next, the controller obtains the write address subtask. Based on actual measurements and parameters provided by the chip, it is determined that the execution time of the write address subtask is less than the preset time. Therefore, it can be identified as a first-type subtask and executed using a blocking operation. That is, the execution of the main task is paused while the write enable task for the peripheral FLASH is executed. The controller performs a write address task for the peripheral FLASH and waits for the write address subtask to complete. After confirming that the peripheral FLASH has completed the write address subtask, it continues to execute the main task. Finally, the controller obtains the write data subtask. Since the length of the data to be sent is variable, the execution time of the write data subtask may reach or may reach the preset time. Therefore, it can be identified as a second type of subtask and uses non-blocking transmission. That is, the main task is executed simultaneously, and the interrupt is triggered or memory is directly accessed to start working. The data corresponding to the write data subtask is sent to the peripheral FLASH through the interrupt or direct memory access. This process does not require MCU intervention in the entire data transmission process. The MCU can check the execution result of the peripheral FLASH every preset time interval.

[0090] The reason why the three subtasks of the SPI write operation in the above example are identified as subtasks of type 1, type 2, and type 3, respectively:

[0091] The time consumption of SPI underlying serial data transmission includes the following: Data transmission in the three subtasks mentioned above is bit-by-bit, and transmitting a certain number of bytes takes time; the larger the data volume, the longer the time consumption. The peripheral FLASH needs to perform certain operations after receiving each instruction, and waiting for these operations to complete also takes time. This time is mainly determined by the chip's own performance. The MCU can confirm whether the write operation is complete by sending a query message. Because the number of bytes transmitted in subtasks 1 and 2 is fixed, the serial data transmission time is fixed. The variable is the time for executing write enable and write address, which needs to be queried using a query command. Based on actual measurements and the parameters given in the chip manual, the execution time of subtasks 1 and 2 is much shorter than the preset time. Therefore, these two steps are identified as the first type of subtask, which can use blocking operation, i.e., obtaining the execution result of the external FLASH through blocking query after sending the instruction. However, for subtask 3, because the length of the data to be sent is variable, the execution time of writing data may exceed the preset time. Therefore, subtask 3 is identified as the second type of subtask, which uses blocking transmission.

[0092] In summary, the above data transmission method takes into account the execution time of each subtask of the data transmission task. For subtasks with shorter execution times, a blocking-driven approach is adopted, that is, after sending the corresponding instruction, the execution result of the peripheral memory is obtained through blocking query, and the main task continues to be executed after the execution is completed. For subtasks with longer execution times, a non-blocking-driven approach is adopted, that is, after sending the corresponding instruction, the main task continues to be executed, while actively querying the execution result of the peripheral memory.

[0093] Therefore, after splitting into multiple subtasks, the controller determines whether each subtask is a first-class subtask or a second-class subtask based on its task scheduling cycle and execution duration, ensuring the accuracy of task division. It also collects blocking drivers and non-blocking drivers respectively to implement the execution of each subtask, avoiding the execution of second-class subtasks from exceeding the task scheduling cycle. This not only ensures that tasks are not pushed back, but also reduces the time the controller waits for subtasks to execute, thus reducing the impact on the execution of the controller's main task.

[0094] After breaking down the data transmission task and classifying each subtask into a first-class or second-class subtask through steps 301 to 304, the target subtask is obtained from the data transmission task. Specifically, the subtasks can be obtained one by one according to the internal execution order.

[0095] In one exemplary embodiment, obtaining the target subtask from the data transmission task in step 201 may include: obtaining the target subtask one by one from the data transmission task according to the internal execution order of the data transmission task.

[0096] For example, when the controller is performing a main task, such as controlling the switching of the power converter in a new energy power generation system, it receives a data transfer task A between peripheral memory. This data transfer task is then divided into subtasks a1 and a2 according to the internal execution order. First, a1 is obtained. Based on measured parameters and the chip datasheet, the execution duration of a1 is determined to be t1. Since t1 is much less than or less than the controller's task scheduling period T0, a1 is determined to be a first-type subtask and is executed in a blocking manner. Next, a2 is obtained. Based on measured parameters and the chip datasheet, the execution duration of a2 is determined to be t2. Since t2 is equal to or greater than the controller's task scheduling period T0, a2 is determined to be a second-type subtask and is executed in a non-blocking manner.

[0097] For example, after the SPI write operation task of the peripheral FLASH is split into three subtasks according to the execution order: write enable subtask, write address subtask and write data subtask, the write enable subtask, write address subtask and write data subtask are obtained and executed in sequence according to the execution order.

[0098] Therefore, by obtaining each subtask according to the internal execution order and executing them accordingly, the accuracy of obtaining and executing the subtasks that need to be executed is guaranteed, which further ensures the accuracy of the data transmission task execution.

[0099] In an exemplary embodiment, step 304 includes: if the execution time of a subtask is less than one-third of the task scheduling cycle, then the subtask is determined to be a first type of subtask; if the execution time of a subtask is greater than or equal to one-third of the task scheduling cycle, then the subtask is determined to be a second type of subtask.

[0100] For example, suppose the controller is a single-task system with a task scheduling cycle of 9 microseconds. For a data transmission task, subtasks b1 and b2, b1 has an execution time of 2 microseconds, so it is determined to be a first-type subtask and the controller performs a blocking operation on it; b2 has an execution time of 4 microseconds, so it is determined to be a second-type subtask and the controller performs a non-blocking operation on it.

[0101] Therefore, based on the relationship between the execution duration of the subtask and the task scheduling cycle of the controller, the subtasks are divided into the first and second categories. This ensures that subtasks whose execution duration has not reached the scheduling cycle are driven in a blocking manner, while subtasks whose execution duration has reached the scheduling cycle are driven in a non-blocking manner, thereby reducing the impact on the main task.

[0102] In another exemplary embodiment, step 304 includes: if the execution duration of the subtask is less than the task scheduling period, and the time difference between the scheduling period and the execution duration of the subtask is less than or equal to a preset difference, then the subtask is determined to be a second type of subtask; if the execution duration of the subtask is less than the task scheduling period, and the time difference between the scheduling period and the execution duration of the subtask is greater than the preset difference, then the subtask is determined to be a first type of subtask; if the execution duration of the subtask is greater than or equal to the task scheduling period, then the subtask is determined to be a second type of subtask.

[0103] The preset difference can be determined based on the acceptable non-blocking time of the controller's main task and the task scheduling time. It can be equal to or less than the difference between the task scheduling period and the acceptable non-blocking time, so as to avoid the controller's main task being blocked for too long due to the controller waiting.

[0104] For example, assuming the controller is a single-task system with a task scheduling cycle of 10 microseconds and a preset difference of 7 microseconds, for subtasks c1, c2, and c3 of a data transmission task, c1 has an execution time of 8 microseconds. The difference of 2 microseconds between the task scheduling cycle of 10 microseconds and 8 microseconds is less than the preset difference of 7 microseconds, so it is determined to be a second-type subtask, and the controller performs a non-blocking operation on it; c2 has an execution time of 5 microseconds, and the time difference of 5 microseconds is less than the preset difference, so it is determined to be a second-type subtask, and the controller performs a non-blocking operation on it; c3 has an execution time of 2 microseconds, and the time difference of 8 microseconds is greater than the preset difference, so it is determined to be a first-type subtask, and the controller performs a blocking operation on it.

[0105] Therefore, based on the difference between the controller's task scheduling cycle and the execution time of the subtask, the subtasks are divided into first and second categories. This ensures that subtasks with execution times much shorter than the task scheduling cycle are blocked, subtasks with execution times not much shorter than the task scheduling cycle (i.e., those that have not yet reached but are about to reach the scheduling cycle) are not blocked, and subtasks that have reached the task scheduling cycle are not blocked, thus further reducing the impact on the main task.

[0106] In one exemplary implementation, such as Figure 5 As shown, step 203, when the target subtask is a second type of subtask, executes both the main task and the second type of subtask simultaneously, including steps 501 to 503. Wherein:

[0107] Step 501: While executing the main task, control direct access to memory to transfer the data corresponding to the second type of subtask to the peripheral memory.

[0108] Step 502: After the transfer is completed, the control direct access memory sends an interrupt request signal to the controller through the interrupt service routine.

[0109] Step 503: After receiving the interrupt request signal, poll the execution results of the second type of subtask according to the task scheduling cycle.

[0110] For example, assuming the controller is an MCU and the peripheral memory is peripheral FLASH, the write data subtask of the SPI write operation is used as an example to illustrate how to simultaneously execute the main task and the second type of subtask:

[0111] Non-blocking transmission is employed, meaning the MCU triggers an interrupt task or DMA (Direct Memory Access) to begin operation. The data to be written is automatically transferred to the external FLASH memory via interrupt or DMA. The MCU does not need to intervene in the entire transmission process while simultaneously executing its main task. After the transmission is complete, an interrupt request signal is sent to the MCU via an interrupt service routine. Upon receiving the interrupt request signal, the MCU checks the execution result of the external FLASH memory every task scheduling cycle T0 in its system task. This achieves non-blocking driving of the SPI write operation's write data subtask, preventing the write data subtask from blocking the main task's execution for extended periods.

[0112] In a specific example, taking the data transmission task between the MCU and the peripheral FLASH as an example of writing to the peripheral memory via SPI, the data transmission method of this application embodiment is illustrated as follows:

[0113] like Figure 6 As shown, the SPI write operation of the MCU to the peripheral FLASH (specifically controlled by the CPU in the MCU) includes the following steps:

[0114] Step 601: Execute the main task.

[0115] For example, the MCU controls the power converter of the new energy power generation system.

[0116] Step 602: Determine whether an SPI write operation instruction has been received (from the host computer). If not, continue execution; if yes, proceed to the next step.

[0117] Step 603: The SPI write operation is divided into three subtasks according to the internal execution order: write enable subtask, write address subtask, and write data subtask.

[0118] Write enable subtask: Send a write enable command, which is to transmit a 1-byte command word via the SPI bus.

[0119] Write address subtask: Send the write start address, which means transmitting 4 bytes of data via the SPI bus.

[0120] Write data subtask: Send data of a certain length (N bytes), that is, transmit N bytes of data through the SPI bus.

[0121] Step 604: Determine the execution duration of each of the three subtasks.

[0122] The time consumed by SPI write operations mainly comes from:

[0123] First, the time consumed by the underlying serial data transmission of SPI. For example, in the three subtasks mentioned above, data transmission is performed bit by bit. It takes time to transmit a certain number of bytes of data. The larger the amount of data to be transmitted, the longer it takes.

[0124] Secondly, the peripheral FLASH needs to perform certain operations after receiving each instruction, and it also takes time to wait for the operation to complete. This time is mainly determined by the chip's own performance. The MCU can confirm whether the write operation has been completed by sending a query message.

[0125] Because the number of bytes transferred in the write enable and write address subtasks is fixed, the serial data transmission time is also fixed. The variable time is the execution time of the write enable and write address subtasks, which needs to be queried using a query command. Based on actual measurements and the parameters given in the chip datasheet, the execution time of the write enable and write address subtasks is much shorter than the MCU's task scheduling cycle T0. However, for the write data subtask, because the length of the data to be sent is variable, the execution time of writing data may exceed the task scheduling cycle T0.

[0126] Step 605: Determine the task scheduling cycle of the MCU.

[0127] The MCU is a single-task system, and its task scheduling cycle is T0.

[0128] Step 606: Determine the enable subtask and write address subtask as the first type of subtask, and determine the write data subtask as the second type of subtask.

[0129] For the write enable subtask and write address subtask, since their execution time is less than the MCU's task scheduling period T0, they are classified as first-class subtasks. For the write data subtask, since its execution time may reach or exceed the task scheduling period T0, it is classified as a second-class subtask.

[0130] Step 607: The MCU pauses the execution of the main task and executes the first type of subtask simultaneously, and resumes the execution of the main task after the subtask is completed.

[0131] The write enable subtask and write address subtask are processed sequentially using blocking operations. That is, after sending the corresponding instructions, the execution result of the peripheral FLASH is obtained by blocking query.

[0132] Step 608 triggers the write data subtask.

[0133] An interrupt or DMA (Direct Memory Access) is triggered to begin operation.

[0134] Step 609: The interrupt or DMA automatically transfers the data to be written to the peripheral FLASH.

[0135] For the data writing subtask, a non-blocking operation is used. During this process, the MCU does not need to intervene in the entire sending process, but instead operates simultaneously with the main task.

[0136] Step 610: Determine if the transmission is complete. If yes, notify the MCU via an interrupt service routine and execute step 612; otherwise, continue the transmission.

[0137] Step 611: During interrupt or DMA execution, the MCU executes the main task.

[0138] Step 612: The MCU determines whether the transmission is complete. If not, it continues to execute the main task; if so, it executes the next step.

[0139] Step 613: While executing the main task, query the execution result of the peripheral FLASH every T0 time interval.

[0140] Step 614: Determine whether the write operation has been completed. If yes, return to step 601; otherwise, return to step 613.

[0141] In this way, the entire SPI write operation of the peripheral FLASH is implemented as a non-blocking drive.

[0142] In addition to write operations, SPI operations on peripheral FLASH also include read and erase operations. The implementation idea is similar to the write operation above, that is, first divide the task into subtasks. Deterministic subtasks with a time interval of less than T0 can be performed in a blocking manner, while indeterminate subtasks with a total time interval of more than T0 can be performed in a non-blocking manner. The specific process is executed by interrupt or DMA. The MCU queries the peripheral FLASH execution result every T0 time interval until the operation is completed.

[0143] The aforementioned non-blocking drive approach can be applied not only to SPI (Serial Peripheral Interface) bus FLASH, but also to I2C (Inter-Integrated Circuit) bus EEPROM or UART (Universal Asynchronous Receiver / Transmitter) bus communication links. By breaking down time-consuming tasks and leveraging the MCU's interrupt or DMA mechanisms, non-blocking drive can be implemented.

[0144] The SPI erase, read, and write operations were verified using embodiments of this application, and their waveforms were obtained. Figure 7These are waveform diagrams illustrating the periodic execution of the MCU main task and the CLK (clock) signal of the SPI bus during SPI erase, read, and write operations. In the main task waveform 701, a low level represents the execution time Ton of the main task, and a high level represents the idle time Toff. In the CLK signal waveform 702, a high level indicates that a message is being transmitted. From these two waveforms, it can be seen that the write operation initially blocks the main task briefly, then automatically transmits data, and after several T0 cycles, checks the result of the write operation. Compared to read and write operations, the erase operation is the most time-consuming. The erase operation waveform shows that an erase command is sent initially, and then a check is performed every T0 cycle until the erase operation is successful. This is the idea behind the non-blocking drive for the erase operation.

[0145] The above describes a data transfer method between the controller and its peripheral memory. The data transfer task is divided into immediate tasks and long-running (time-consuming) tasks. Immediate tasks are driven by blocking mechanisms, while long-running tasks are driven non-blockingly through interrupts or DMA mechanisms. This significantly reduces the blocking time of the data transfer task on the main task and solves the problem of peripheral memory blocking the controller's main task execution for extended periods during file transfers. The following describes a specific implementation method for using the data transfer task for controller firmware upgrades.

[0146] In related technologies, during firmware upgrades for controllers, there is a risk of accidental upgrades that can cause the controller to malfunction. In systems without a backup of the original firmware, the upgrade process erases the original firmware and replaces it with new firmware. If this new firmware is faulty and cannot execute business programs correctly, it will cause the controller to malfunction, or even become bricked (completely paralyzed and unusable).

[0147] Therefore, the data transmission method in this application implements backup of the original firmware through a partition refresh and backup strategy.

[0148] In one embodiment of this application, the method further includes: dividing the storage area of ​​the peripheral memory into two partitions, using one partition as a temporary storage area for the upgrade package and the other partition as a backup area, wherein the program in the backup area is the same as the program in the application partition before the controller upgrade, and the upgrade package is used to upgrade the controller.

[0149] For example, such as Figure 8 As shown, the peripheral FLASH is divided into two partitions, A and B. One partition serves as a temporary storage area for the upgrade package of the MCU application partition, and the other partition serves as a backup area for the application partition before the upgrade. The two partitions are the same size.

[0150] The two partitions of the peripheral FLASH memory serve as backups for each other. That is, when A is the temporary storage area for the upgrade package, B is the backup area, and vice versa. The program in the application partition before the MCU upgrade is always consistent with the program in the backup area, which is necessary to enable version rollback.

[0151] It should be noted that when the internal FLASH of the MCU is large enough, a different FLASH partitioning scheme than the above can also be used. For example, the internal FLASH of the MCU can be divided into three partitions: one boot partition and two app partitions that serve as backups for each other. The app partition can both transfer files and perform file transfers, while the boot partition only performs jump logic judgments.

[0152] Furthermore, the data transmission method also includes implementing version rollback through the following steps.

[0153] Step 901: When the data transmission task is used for controller upgrade, determine the number of upgrades corresponding to the target upgrade package.

[0154] Step 902: When the number of upgrades reaches the preset number, the number of upgrades is reset to zero, the program in the application partition of the controller is deleted, and the program before the upgrade in the backup area of ​​the peripheral storage is transferred to the application partition of the controller.

[0155] The preset number of times is the maximum number of times that can be upgraded for the same target upgrade package, such as 3 times.

[0156] For example, the peripheral FLASH stores two flags: First, an upgrade flag, indicating whether the MCU firmware needs an upgrade. If so, subsequent update actions are executed; otherwise, the process jumps directly to the corresponding app partition to execute the service. Firmware that passes the self-test and can run the service will automatically clear the upgrade flag. Conversely, abnormal firmware will not clear the upgrade flag and will time out and restart. After restarting and entering the boot partition, since the upgrade flag is still there, the firmware update will continue. Second, an upgrade count variable is incremented by 1 and stored in the peripheral FLASH each time the app partition is updated. If the target upgrade package's upgrade count is greater than the preset count of 3, it means that the program has failed to run properly after 3 attempts. In this case, the boot partition will execute a version rollback mechanism, which resets the upgrade count to zero, deletes the program in the MCU's app partition, and then loads the program from the backup area into the MCU's app partition. This is the idea behind implementing version rollback.

[0157] The following example illustrates the version rollback mechanism during MCU upgrades.

[0158] like Figure 10 As shown, the MCU version rollback mechanism is implemented through the following steps:

[0159] Step 1001: Power on;

[0160] Step 1002, enter the boot partition;

[0161] Step 1003: Determine if there is a program upgrade flag. If yes, proceed to step 1004; otherwise, proceed to step 1005.

[0162] Step 1004: Determine if the number of upgrades is less than 3. If yes, proceed to step 1010; otherwise, proceed to step 1012.

[0163] Step 1005, enter the app partition;

[0164] Step 1006: Determine if the program is running normally. If yes, proceed to step 1007; otherwise, proceed to step 1008.

[0165] Step 1007: Erase the upgrade flag and proceed to step 1009;

[0166] Step 1008: Timeout, reset and restart, then return to step 1002;

[0167] Step 1009, normal operation;

[0168] Step 1010: Increment the upgrade count by 1, write the data to the peripheral FLASH, and then execute step 1011;

[0169] Step 1011: Erase the MCU's app partition, perform a program update, and transfer the latest program from the peripheral FLASH to the MCU's app partition;

[0170] Step 1012: Reset the upgrade count to zero and write it to the peripheral FLASH, then execute step 1013;

[0171] Step 1013: Erase the MCU's app partition, perform version rollback, and transfer the old program from the peripheral FLASH to the MCU's app partition.

[0172] Thus, by using partitions for backup and file transfer, the backup area is protected, thereby enabling version rollback.

[0173] In summary, the embodiments of this application can not only realize non-blocking driving of some subtasks in the data transmission task, thereby reducing the waiting time of the controller, but also realize version rollback during the upgrade process, solving the problem of not being able to rollback when the program is abnormal.

[0174] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0175] Based on the same inventive concept, this application also provides a data transmission apparatus for implementing the data transmission method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, specific limitations in one or more data transmission apparatus embodiments provided below can be found in the limitations of the data transmission method described above, and will not be repeated here.

[0176] In one exemplary embodiment, such as Figure 11 As shown, a data transmission device is provided for use between a controller and a peripheral memory. The controller may include the data transmission device.

[0177] The data transmission device includes: an acquisition module 1101, a first execution module 1102, and a second execution module 1103, wherein:

[0178] The acquisition module 1101 is used to acquire a target subtask from the data transmission task if a data transmission task between the controller and the peripheral memory is acquired when the controller is executing the main task. The data transmission task includes multiple subtasks.

[0179] The first execution module 1102 is used to pause the execution of the main task and execute the first type of subtask when the target subtask is a first type of subtask, and to continue the execution of the main task after the first type of subtask is executed;

[0180] The second execution module 11103 is used to execute the main task and the second type of subtask simultaneously when the target subtask is a second type of subtask; wherein the execution time of the second type of subtask is longer than the execution time of the first type of subtask.

[0181] In one embodiment, the data transmission device further includes: a splitting module, a first determining module, a second determining module, and a third determining module. Wherein:

[0182] The splitting module is used to split the data transmission task into multiple sub-tasks;

[0183] The first determining module is used to determine the execution duration of the sub-task;

[0184] The second determining module is used to determine the task scheduling cycle of the controller;

[0185] The third determining module is used to determine whether each subtask is a first type of subtask or a second type of subtask based on the task scheduling cycle and the execution duration.

[0186] In one embodiment, the splitting module is specifically used to: split the data transmission task into multiple subtasks according to the internal execution order of the data transmission task.

[0187] In one embodiment, when the acquisition module 1101 acquires the target subtask from the data transmission task, it is specifically used to: acquire the target subtask one by one from the data transmission task according to the internal execution order of the data transmission task.

[0188] In one embodiment, the second determining module includes a first determining unit and a second determining unit. Wherein:

[0189] The first determining unit is used to determine that if the execution time of a subtask is less than one-third of the task scheduling cycle, then the subtask is a first type of subtask.

[0190] The second determining unit is used to determine that if the execution time of a subtask is greater than or equal to one-third of the task scheduling cycle, the subtask is a second type of subtask.

[0191] In another embodiment, the second determining module includes a third determining unit, a fourth determining unit, and a fifth determining unit. Wherein:

[0192] The third determining unit is used to determine the subtask as a second type of subtask if the execution time of the subtask is less than the task scheduling period and the time difference between the scheduling period and the execution time of the subtask is less than or equal to a preset difference.

[0193] The fourth determining unit is used to determine the subtask as a first type of subtask if the execution time of the subtask is less than the task scheduling period and the time difference between the scheduling period and the execution time of the subtask is greater than a preset difference.

[0194] The fifth determining unit is used to determine that if the execution duration of a subtask is greater than or equal to the task scheduling cycle, the subtask is a second type of subtask.

[0195] In one embodiment, the second execution module includes: a control unit, a sending unit, and a querying unit. Wherein:

[0196] The control unit is used to control the direct access memory to transfer the data corresponding to the second type of subtask to the peripheral memory while executing the main task;

[0197] The sending unit is used to control the direct access memory to send an interrupt request signal to the controller through an interrupt service routine after the transmission is completed;

[0198] The query unit is used to, upon receiving the interrupt request signal, poll the execution results of the second type of sub-task according to the task scheduling cycle.

[0199] In one embodiment, the device further includes a partitioning module, which is used to divide the storage area of ​​the peripheral memory into two partitions, and use one partition as a temporary storage area for the upgrade package and the other partition as a backup area, wherein the program in the backup area is the same as the program in the application partition before the controller is upgraded, and the upgrade package is used to upgrade the controller.

[0200] In one embodiment, the apparatus further includes a fourth determining module and a rollback module. Wherein:

[0201] The fourth determining module is used to determine the number of upgrades corresponding to the target upgrade package when the data transmission task is used for controller upgrade;

[0202] The rollback module is used to reset the upgrade count to zero when the upgrade count reaches a preset number, delete the program in the application partition of the controller, and transfer the program before the upgrade in the backup area of ​​the peripheral memory to the application partition of the controller.

[0203] Each module in the aforementioned data transmission device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0204] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 12As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data related to data transmission. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a data transmission method.

[0205] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0206] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in any of the above method embodiments.

[0207] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in any of the above method embodiments.

[0208] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the above method embodiments.

[0209] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0210] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0211] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data transmission method applied between a controller and a peripheral memory, characterized in that, The method includes: When the controller is executing the main task, if a data transfer task between the controller and the peripheral memory is obtained, a target subtask is obtained from the data transfer task, which includes multiple subtasks. When the target subtask is a first type of subtask, the execution of the main task is paused while the first type of subtask is executed, and the execution of the main task continues after the first type of subtask is executed. When the target subtask is a second type of subtask, the main task and the second type of subtask are executed simultaneously. The execution time of the second type of subtask is longer than that of the first type of subtask.

2. The method according to claim 1, characterized in that, After obtaining the data transfer task between the controller and the peripheral memory, the following is also included: The data transmission task is divided into multiple sub-tasks; Determine the execution duration of the subtask; Determine the task scheduling cycle of the controller; Each subtask is determined to be either a first-type subtask or a second-type subtask based on the task scheduling cycle and the execution duration.

3. The method according to claim 2, characterized in that, The step of dividing the data transmission task into multiple sub-tasks includes: The data transmission task is divided into multiple subtasks according to its internal execution order.

4. The method according to claim 1, characterized in that, The step of obtaining the target subtask from the data transmission task includes: The target subtasks are obtained one by one from the data transmission task according to the internal execution order of the data transmission task.

5. The method according to claim 2, characterized in that, The step of determining whether each subtask is a first-type subtask or a second-type subtask based on the task scheduling cycle and the execution duration includes: If the execution time of a subtask is less than one-third of the task scheduling cycle, then the subtask is determined to be a first-class subtask. If the execution time of a subtask is greater than or equal to one-third of the task scheduling cycle, then the subtask is determined to be a second type of subtask.

6. The method according to claim 2, characterized in that, The step of determining whether each subtask is a first-type subtask or a second-type subtask based on the task scheduling cycle and the execution duration includes: If the execution time of a subtask is less than the task scheduling period, and the time difference between the scheduling period and the execution time of the subtask is less than or equal to a preset difference, then the subtask is determined to be a second type of subtask. If the execution time of a subtask is less than the task scheduling period, and the time difference between the scheduling period and the execution time of the subtask is greater than a preset difference, then the subtask is determined to be a first type of subtask. If the execution duration of a subtask is greater than or equal to the task scheduling period, then the subtask is determined to be a second type of subtask.

7. The method according to claim 1, characterized in that, The simultaneous execution of the main task and the second type of sub-task includes: While executing the main task, direct memory access is controlled to transfer the data corresponding to the second type of subtask to the peripheral memory. After the transmission is complete, the direct memory access control sends an interrupt request signal to the controller via an interrupt service routine. Upon receiving the interruption request signal, the execution results of the second type of subtask are queried in a polling manner according to the task scheduling cycle.

8. The method according to any one of claims 1-7, characterized in that, Also includes: The peripheral memory is divided into two partitions. One partition is used as a temporary storage area for the upgrade package, and the other partition is used as a backup area. The program in the backup area is the same as the program in the application partition before the controller is upgraded. The upgrade package is used to upgrade the controller.

9. The method according to claim 8, characterized in that, Also includes: When the data transmission task is used for controller upgrade, the number of upgrades corresponding to the target upgrade package is determined; When the number of upgrades reaches a preset number, the number of upgrades is reset to zero, the program in the application partition of the controller is deleted, and the program before the upgrade in the backup area of ​​the peripheral memory is transferred to the application partition of the controller.

10. A data transmission device, used between a controller and a peripheral memory, characterized in that, The device includes: The acquisition module is used to acquire a target subtask from the data transmission task if a data transmission task between the controller and the peripheral memory is acquired when the controller is executing the main task. The data transmission task includes multiple subtasks. The first execution module is configured to pause the execution of the main task and execute the first type of subtask simultaneously when the target subtask is a first type of subtask, and to continue the execution of the main task after the first type of subtask is executed; The second execution module is used to execute the main task and the second type of subtask simultaneously when the target subtask is a second type of subtask; The execution time of the second type of subtask is longer than that of the first type of subtask.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1-9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-9.

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