Method and system for monitoring IIC bus to obtain data

Abstract

The embodiment of the invention discloses a method and system for monitoring an IIC bus to obtain data, and the method comprises the steps: monitoring an IIC bus clock signal, triggering interruption at each rising edge of the IIC bus to read the level of a data line, storing an obtained bit sequence into a buffer area, taking the data in the buffer area as a continuous bit stream in a non-interruption stage, and storing the continuous bit stream in the buffer area; according to the method, byte feature matching is performed through left shift operation according to a foreseen slave address, a register address and a communication time sequence, so that effective data are directly extracted, the specific positions of starting, stopping and answering signals in communication do not need to be identified in the process, bus conflicts caused by using a hardware IIC slave mode are effectively avoided, and the communication efficiency is improved. And meanwhile, the dependence of a software interruption scheme on the CPU performance and the interruption response speed is greatly reduced, so that stable monitoring of a higher-frequency IIC bus on lower-cost hardware becomes possible, and good protocol format adaptability is achieved.

Description

Technical Field

[0001] This invention relates to the field of serial communication technology, specifically to a method and system for monitoring the IIC bus to acquire data. Background Technology

[0002] In the fields of reverse engineering and serial communication, especially for data monitoring of synchronous communication such as the IIC bus, existing technologies mainly rely on two common methods:

[0003] One approach is to configure the microcontroller's hardware IIC peripheral as a slave device, allowing it to directly receive data from the host.

[0004] Another method is to use the microcontroller's software I / O interrupts to reverse-engineer the IIC communication data by processing the level changes on the bus in real time, which is the so-called bitbang method.

[0005] However, these existing solutions have obvious drawbacks:

[0006] When using a hardware IIC peripheral as a slave device, communication conflicts can easily occur with the actual slave device being monitored. For example, sending an ACK response signal may cause bus interference, or even multiple ACKs may cause communication chaos, ultimately leading to monitoring failure.

[0007] While software I / O interrupt schemes offer greater flexibility, they require high-performance CPU support. They must simultaneously handle rising and falling edge interrupts of SDA to identify start and stop signals, as well as rising edge interrupts of SCL to acquire data and ACK signals.

[0008] This multi-interrupt handling method causes the CPU to frequently push and pop data onto and off the stack, resulting in huge overhead and extremely high requirements for response speed. If not handled carefully, it can lead to incomplete or incorrect data listening.

[0009] In addition, due to the real-time nature of interrupt handling, the frequency of the monitored IIC bus is usually limited to a low level, with 100kHz being close to the limit, making it difficult to adapt to higher frequency application scenarios. Summary of the Invention

[0010] Therefore, embodiments of the present invention provide a method and system for monitoring the IIC bus to acquire data, in order to solve the technical problems of existing technologies that are prone to bus interference and have high requirements for response speed, making them difficult to adapt to application scenarios with higher frequencies.

[0011] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0012] According to a first aspect of the present invention, a method for monitoring an IIC bus to acquire data is provided, the method comprising:

[0013] Listen to the SCL signal on the IIC bus and trigger an interrupt on each rising edge of the SCL signal;

[0014] In the interrupt service routine, the SDA signal level of the IIC bus is read and the level value is stored sequentially as a single bit in a data buffer to form a continuous raw level sequence;

[0015] During the non-interrupt processing phase, the original level sequence in the data buffer is parsed. This parsing process includes:

[0016] The original level sequence is treated as a whole bit stream, and the bit stream is traversed by a left shift operation to match the known communication timing characteristics;

[0017] Based on the known slave device address, a first-level feature matching is performed in the bit stream;

[0018] After matching the slave device address, a second-level feature matching is performed in the left-shifted bitstream based on the known register address;

[0019] After continuously matching the slave device address and register address, the data byte at the specified position is extracted from the subsequent bit stream according to the known communication data format;

[0020] The parsing process does not depend on the specific location of the start signal, stop signal, or acknowledge signal in the bit stream.

[0021] Furthermore, byte feature matching based on known communication timing specifically includes:

[0022] The entire bit stream in the data buffer is shifted left until the first byte matches the known slave device address.

[0023] Furthermore, after matching the slave device address, the entire bit stream is shifted left by at least one bit to skip adjacent response signal bits;

[0024] Determine whether the next byte in the left-shifted bitstream is one of the known register addresses.

[0025] Furthermore, once a register address is matched, the entire bit stream is shifted left by at least two bits to skip an adjacent acknowledge signal bit and a start signal sequence;

[0026] Determine whether the next byte in the left-shifted bitstream is the known slave address.

[0027] Furthermore, once a slave address is matched, the entire bit stream is shifted left by at least one bit to skip adjacent response signal bits;

[0028] Extract the next byte as the lower 8 bits of the valid data;

[0029] The bit stream is then shifted left by at least one bit to skip an adjacent response bit.

[0030] Extract the next byte as the high 8 bits of the valid data.

[0031] Furthermore, the data buffer adopts a circular buffer structure. When the buffer is full and the current parsing is completed, the old data is cleared or overwritten to continue receiving new level sequences.

[0032] According to a second aspect of the present invention, a system for monitoring the IIC bus to acquire data is provided, the system comprising:

[0033] The interrupt control module is configured to listen for the SCL signal of the IIC bus and generate an interrupt when a rising edge of SCL is detected.

[0034] The data sampling and storage module, which is connected to the interrupt control module, is used to read the level of the SDA signal when an interrupt is triggered, and store the level value into a data buffer in sequence;

[0035] A data parsing module, which is connected to the data sampling and storage module, is used to process the bit stream in the data buffer in a non-interrupted state;

[0036] The data parsing module further includes:

[0037] A sequence matching unit, configured to match a known slave device address and register address in a bitstream via a left shift operation;

[0038] The data extraction unit is configured to extract valid data bytes from a predetermined position in the bit stream according to a predefined communication data format after a successful address match.

[0039] Furthermore, the interrupt control module and the data sampling and storage module are integrated into a microcontroller, which uses only the rising edge of SCL as an interrupt source to listen to the IIC bus.

[0040] Furthermore, the logic of the sequence matching unit and the data extraction unit in the data parsing module can be modified through software configuration to adapt to different slave device addresses, register addresses, and communication timings.

[0041] Furthermore, the data extraction unit continuously extracts multiple bytes from the bit stream and combines them into complete data according to the known communication data format.

[0042] The embodiments of the present invention have the following advantages:

[0043] This invention reads the data line level by listening to the IIC bus clock signal and triggering an interrupt on each rising edge. The acquired bit sequence is stored in a buffer. Then, in the non-interrupt phase, the buffer data is treated as a continuous bit stream. By left-shifting and matching byte features based on the known slave address, register address, and communication timing, valid data is directly extracted. This process does not require identifying the specific locations of start, stop, and acknowledge signals in the communication. This invention effectively avoids bus conflicts caused by using hardware IIC slave mode, and significantly reduces the dependence of software interrupt schemes on CPU performance and interrupt response speed. This makes it possible to stably listen to higher frequency IIC buses on lower-cost hardware, and has good protocol format adaptability. Attached Figure Description

[0044] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0045] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0046] Figure 1 A schematic diagram of the logical structure of a system for monitoring the IIC bus and acquiring data is provided in an embodiment of the present invention;

[0047] Figure 2 This is a second flowchart illustrating a method for acquiring data by monitoring the IIC bus according to an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the bus level data obtained in a method for monitoring the IIC bus to acquire data according to an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram illustrating the method of finding the first byte of the IIC slave address by left shifting in a method for monitoring the IIC bus and acquiring data according to an embodiment of the present invention.

[0050] Figure 5This invention provides a method for monitoring the IIC bus to acquire data, which involves shifting the second byte left by one bit (ACK signal) to determine if the second byte is one of 08, 09, 0A, or 0D. A schematic diagram showing a 09 match is provided.

[0051] Figure 6 This is a schematic diagram illustrating the left shift by two bits (start and ACK signals) to search for the third byte 17 (0x16 + read command) in a method for monitoring the IIC bus and acquiring data according to an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram illustrating the process of left-shifting by one bit (ACK signal) to obtain the fourth byte as the lower 8 bits of data (0x4E) in a method for monitoring the IIC bus and acquiring data according to an embodiment of the present invention.

[0053] Figure 8 This is a schematic diagram illustrating the process of left-shifting by one bit (ACK signal) to obtain the fifth byte as the high 8 bits of data = 0x3A in a method for monitoring the IIC bus and acquiring data according to an embodiment of the present invention. Detailed Implementation

[0054] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] In the fields of reverse engineering and serial communication, especially for data monitoring of synchronous communication such as the IIC bus, existing technologies mainly rely on two common methods:

[0056] One approach is to configure the microcontroller's hardware IIC peripheral as a slave device, allowing it to directly receive data from the host.

[0057] Another method is to use the microcontroller's software I / O interrupts to reverse-engineer the IIC communication data by processing the level changes on the bus in real time, which is the so-called bitbang method.

[0058] However, these existing solutions have obvious drawbacks:

[0059] Configuring a slave device with a hardware IIC peripheral can cause communication conflicts with the slave device being monitored. Sending ACK commands simultaneously or twice can interfere with the monitoring bus. Two ACK commands on the bus can cause communication chaos and lead to monitoring failure.

[0060] The software I / O interrupt reception scheme requires a high-performance CPU. During reception, SDA rising and falling edge interrupts need to be enabled to determine start and stop signals, and SCL rising edge interrupts need to be enabled to receive data and ACK acknowledge signals. Subsequently, the received data can be deduced by reverse engineering based on the IIC bus timing. Due to the large number of interrupts, the CPU stack push and pop overhead is very large and the response speed needs to be extremely fast, otherwise it may cause incomplete data listening, data errors, etc. At the same time, the frequency of the IIC bus being monitored should not be too high. Since three interrupts need to be processed simultaneously with very small intervals, a bus frequency of 100KHz is already the limit.

[0061] In order to solve the above-mentioned technical problems that are prone to bus interference, have high requirements for response speed, and are difficult to adapt to higher frequency application scenarios.

[0062] refer to Figure 1 This invention discloses a system for monitoring the IIC bus to acquire data. The system includes: an interrupt control module 1; a data sampling and storage module 2; and a data parsing module 3, wherein the data parsing module 3 includes a sequence matching unit 31 and a data extraction unit 32.

[0063] Corresponding to the system for monitoring the IIC bus and acquiring data disclosed above, this invention also discloses a method for monitoring the IIC bus and acquiring data. The following describes in detail, with reference to the system for monitoring the IIC bus and acquiring data described above, a method for monitoring the IIC bus and acquiring data disclosed in this invention.

[0064] This invention discloses a method for monitoring the IIC bus to acquire data. The method involves monitoring the SCL signal of the IIC bus and triggering an interrupt on each rising edge of the SCL signal. In the interrupt service routine, the SDA signal level of the IIC bus is read and the level value is stored sequentially as a single bit in a data buffer to form a continuous original level sequence.

[0065] During the non-interrupt processing phase, the original level sequence in the data buffer is parsed. This parsing process includes: treating the original level sequence as a whole bit stream, traversing the bit stream by left shifting to match known communication timing features; performing a first-level feature matching in the bit stream based on the known slave device address; after matching the slave device address, performing a second-level feature matching in the left-shifted bit stream based on the known register address; and after consecutively matching the slave device address and register address, extracting the data byte at the specified position from the subsequent bit stream according to the known communication data format.

[0066] The parsing process does not depend on the specific location of the start signal, stop signal, or acknowledge signal in the bit stream.

[0067] refer to Figure 2 The algorithm logic of this embodiment of the invention is as follows:

[0068] 1. Wait for the SDA level data buffer to be full;

[0069] 2. Confirm that there are at least 6 bytes left to move; otherwise, exit.

[0070] 3. Shift the entire data left until the first byte equals 0x16;

[0071] 4. Shift the entire data left by 1 bit again;

[0072] 5. Determine if the second byte is equal to one of 08, 09, 0A, or 0D. If not, proceed to step 2.

[0073] 6. Shift the entire data left by 2 bits again;

[0074] 7. Check if the third byte is equal to 0x17. If not, go to step 2.

[0075] 8. Shift the entire data left by 1 bit again;

[0076] 9. Obtain the fourth byte as the lower 8 bits of the data;

[0077] 10. Shift the entire data left by 1 bit again;

[0078] 11. Obtain the fifth byte as the high 8 bits of the data;

[0079] 12. Merge the high and low bytes and save them to the corresponding address variables;

[0080] 13. Skip to step 2.

[0081] In specific applications of the embodiments of the present invention, modifications and adaptations should be made according to the slave address, register address, communication timing, etc. of the monitored bus.

[0082] The IIC bus uses a rising edge interrupt to receive data from the data bus. Start, stop, data, and acknowledge signals are all saved locally as serial bits. Data at the corresponding location is retrieved based on the known IIC address and register address. The analysis algorithm matches the IIC bus timing. It doesn't care when the start or stop occurs or the location of the acknowledge signal; it only receives the data bus level via a rising edge interrupt and saves it to the local buffer.

[0083] The left-shift method ignores start, stop, and acknowledge signals and performs byte feature matching and capture based on known communication timing.

[0084] Before use, you need to know the slave IIC address, data register address and communication timing of the bus being monitored. The following example uses a certain type of BMS to communicate with the host.

[0085] A certain model of BMS communicates with the host to obtain data such as battery voltage, current, temperature and charge. It is known that the slave IIC address is 0x16, the temperature register address is 0x08, the voltage register is 0x09, the current register is 0x0A, and the charge register is 0x0D.

[0086] The communication timing is as follows: H is the host control bus, and S is the slave control bus.

[0087] (XXX is unrelated to XXX)

[0088] H: (Start signal)

[0089] H: (Slave address 0x16)

[0090] S: (1-bit ACK acknowledge signal)

[0091] H: (One of register addresses 08, 09, 0A, or 0D)

[0092] S: (1-bit ACK acknowledge signal)

[0093] H: (Start signal)

[0094] H: (Slave address | Read command 0x17)

[0095] S: (1-bit ACK acknowledge signal)

[0096] S: (lower 8 bits of data)

[0097] H: (1-bit ACK signal)

[0098] S: (High 8 bits of data)

[0099] (XXX is unrelated to XXX)

[0100] refer to Figure 3 After obtaining the bus level data, we can deduce the data in the registers by working backwards. The following is an example of the original data.

[0101] Figure 4 To find the first byte of the IIC slave address by left shifting, Figure 5 To left-shift by one bit (ACK signal), check if the second byte is one of 08, 09, 0A, or 0D. 09 is a match. Figure 6 To find the third byte as 17 by shifting left by two bits (start and ACK signals), a 17-byte match was found. Figure 7To obtain the fourth byte as the lower 8 bits of data by left shifting by one bit (ACK signal) = 0x4E, Figure 8 The fifth byte is obtained by left-shifting by one bit (ACK signal) as the high 8 bits, which is 0x3A. Combining the two 8-bit data gives 0x3A4E. Since the data register address is 09, this data is voltage data; 0x3A4E = 14926, meaning the battery voltage is 14.926V. Other register data such as 08, 0A, and 0D can be obtained using the same method.

[0102] The embodiments of the present invention have the following advantages:

[0103] This invention uses known communication timing and slave register address information to reverse-engineer captured data without needing to determine the start, stop and acknowledge signal positions, thus reducing the CPU's interrupt handling burden. It uses a left-shift method to ignore start, stop and acknowledge signals and performs byte feature matching based on known communication timing, slave address and register address.

[0104] Compared to the hardware IIC peripheral method, this solution does not require the use of hardware IIC peripherals and will not interfere with the bus level being monitored, allowing the two parties to communicate normally.

[0105] Compared to the software bitbang reverse method, this solution only requires one interrupt source. The captured IIC bus clock frequency can easily reach 100KHz, and if a high-performance microcontroller is used, it can even reach 400KHz or even 1MHz. Moreover, the interrupt logic is simple, reducing the CPU interrupt frequency and greatly increasing the response speed. Lower-speed and lower-cost microcontroller hardware solutions can be used, thereby reducing hardware costs. After saving the SDA pin level using the interrupt, the parsing stage can begin. At this time, there is no need to pay attention to the interrupt. After the saved level data is parsed, the SDA level can continue to be captured. After enough samples are collected for parsing, the next parsing and data update can be performed.

[0106] The monitoring program algorithm can be easily and flexibly adjusted according to the communication frame format of both parties being monitored to adapt to the frame format of both parties, including single-byte and multi-byte frames.

[0107] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A method for monitoring the IIC bus to acquire data, characterized in that, The method includes: Listen to the SCL signal on the IIC bus and trigger an interrupt on each rising edge of the SCL signal; In the interrupt service routine, the SDA signal level of the IIC bus is read and the level value is stored sequentially as a single bit in a data buffer to form a continuous raw level sequence; During the non-interrupt processing phase, the original level sequence in the data buffer is parsed. This parsing process includes: The original level sequence is treated as a whole bit stream, and the bit stream is traversed by a left shift operation to match the known communication timing characteristics; Based on the known slave device address, a first-level feature matching is performed in the bit stream; After matching the slave device address, a second-level feature matching is performed in the left-shifted bitstream based on the known register address; After continuously matching the slave device address and register address, the data byte at the specified position is extracted from the subsequent bit stream according to the known communication data format; The parsing process does not depend on the specific location of the start signal, stop signal, or acknowledge signal in the bit stream.

2. The method for acquiring data by monitoring the IIC bus as described in claim 1, characterized in that, Byte feature matching based on known communication timing specifically includes: The entire bit stream in the data buffer is shifted left until the first byte matches the known slave device address.

3. The method for acquiring data by monitoring the IIC bus as described in claim 2, characterized in that, After matching the slave device address, the entire bit stream is shifted left by at least one bit to skip adjacent response signal bits; Determine whether the next byte in the left-shifted bitstream is one of the known register addresses.

4. The method for acquiring data by monitoring the IIC bus as described in claim 3, characterized in that, Once a register address is matched, the entire bit stream is shifted left by at least two bits to skip an adjacent acknowledge bit and a start signal sequence. Determine whether the next byte in the left-shifted bitstream is the known slave address.

5. The method for acquiring data by monitoring the IIC bus as described in claim 4, characterized in that, Once a slave address is matched, the entire bit stream is shifted left by at least one bit to skip adjacent response signal bits; Extract the next byte as the lower 8 bits of the valid data; The bit stream is then shifted left by at least one bit to skip an adjacent response bit. Extract the next byte as the high 8 bits of the valid data.

6. The method for acquiring data by monitoring the IIC bus as described in claim 1, characterized in that, The data buffer adopts a circular buffer structure. When the buffer is full and the current parsing is completed, the old data is cleared or overwritten to continue receiving new level sequences.

7. A system for monitoring the IIC bus to acquire data, characterized in that, The system includes: The interrupt control module is configured to listen for the SCL signal of the IIC bus and generate an interrupt when a rising edge of SCL is detected. The data sampling and storage module, which is connected to the interrupt control module, is used to read the level of the SDA signal when an interrupt is triggered, and store the level value into a data buffer in sequence; A data parsing module, which is connected to the data sampling and storage module, is used to process the bit stream in the data buffer in a non-interrupted state; The data parsing module further includes: A sequence matching unit, configured to match a known slave device address and register address in a bitstream via a left shift operation; The data extraction unit is configured to extract valid data bytes from a predetermined position in the bit stream according to a predefined communication data format after a successful address match.

8. The system for monitoring the IIC bus and acquiring data as described in claim 7, characterized in that, The interrupt control module and the data sampling and storage module are integrated into a microcontroller, which uses only the rising edge of SCL as an interrupt source to listen to the IIC bus.

9. The system for monitoring the IIC bus and acquiring data as described in claim 8, characterized in that, The logic of the sequence matching unit and data extraction unit in the data parsing module can be modified through software configuration to adapt to different slave device addresses, register addresses and communication timings.

10. A system for monitoring the IIC bus and acquiring data as described in claim 8, characterized in that, The data extraction unit extracts multiple bytes continuously from the bit stream and combines them into complete data according to the known communication data format.

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