A method and device for predicting interconnection delay in a chip design, and an electronic device

Abstract

This application relates to a method, apparatus, and electronic device for predicting interconnect delay in chip design. The method includes: receiving first routing layout information of a target routing layer of a chip under test; and predicting the interconnect delay information of the chip under test using a trained prediction model based on at least two types of first routing layout characteristics in the first routing layout information, for analysis of the rationality of the chip under test design. The interconnect delay information includes predicted interconnect delay values ​​corresponding to different combinations of signal conditions. The technical solution of this application, by using at least two types of first routing layout characteristics as input to the prediction model, can quickly predict the interconnect delay information of the chip under test, simplifying the interconnect delay estimation process in the prior art chip field and improving the efficiency of chip design.

Description

Technical Field

[0001] This application relates to the field of chip design technology, specifically to a method, apparatus, electronic device, and storage medium for predicting interconnect delay in chip design. Background Technology

[0002] In the design of very large-scale integrated circuits (VLSI), interconnect delay is one of the key factors affecting chip performance and timing convergence. With the continuous advancement of process nodes, the proportion of interconnect delay has exceeded that of gate delay, becoming the dominant factor determining circuit performance. Therefore, it is crucial to quickly and accurately predict interconnect delay in the early stages of design for optimizing placement and routing and accelerating timing convergence.

[0003] The current industry standard chip design flow typically involves precise resistor and capacitor parameter extraction only after placement and routing are completed, followed by static timing analysis. If the timing analysis results do not meet the requirements, design engineers need to manually adjust the placement and routing strategy, and then repeat RC extraction and timing analysis, iterating in this cycle until timing convergence. This process heavily relies on the manual intervention of experienced engineers and involves frequent data exchange and iteration between various Electronic Device Automation (EDA) tools, resulting in a lengthy and inefficient design cycle.

[0004] Therefore, improving the efficiency of predicting interconnection delays in the chip design stage, increasing chip design efficiency, and simplifying the chip design process have become urgent technical problems to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a method, apparatus, electronic device, and storage medium for predicting interconnect delay in chip design. Based on at least two types of first-class routing layout characteristics of the target routing layer in the chip under test, the interconnect delay information of the chip under test can be predicted using a prediction model, thereby improving the prediction efficiency of interconnect delay in chip design and thus improving the efficiency of chip design.

[0006] To address the aforementioned technical problems, this application provides a method for predicting interconnect delay in chip design, the method comprising the following steps:

[0007] Receive the first routing layout information of the target routing layer of the chip under test;

[0008] Based on at least two types of first trace layout characteristics in the first trace layout information, the interconnect delay information of the chip under test is predicted by a trained prediction model, so as to analyze whether the design of the chip under test is reasonable. The interconnect delay information includes the predicted interconnect delay values ​​corresponding to different signal condition combinations.

[0009] In some embodiments, the method further includes:

[0010] Obtain a training dataset, which includes multiple training samples. The training samples include at least two types of sample routing layout characteristics of a specific routing layer in the sample chip, and the interconnect delay truth information corresponding to the sample chip. The interconnect delay truth information includes the interconnect delay truth values ​​corresponding to different signal condition combinations. The at least two types of sample routing layout characteristics correspond to at least two types of the first routing layout characteristics.

[0011] Using the routing layout characteristics of at least two samples as input features and the ground truth information of interconnect delay as training labels, an initial model is trained to obtain a trained prediction model. The sample chip and the chip under test are of the same chip type, and the level of the specific routing layer in the sample chip is the same as the level of the target routing layer in the chip under test.

[0012] In some embodiments, obtaining a training dataset includes: obtaining sample design layout information of a sample chip, determining that the sample information includes multiple routing layers; and determining, based on the sample design layout information, interconnect extension truth information corresponding to at least two types of sample routing layout characteristics of a specific routing layer in the multiple routing layers.

[0013] In some embodiments, determining the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of a specific routing layer in a multi-layer routing layer based on the sample design layout information includes: determining the first sample routing layout information of the specific routing layer and the second sample routing layout information of the adjacent routing layer adjacent to the specific routing layer based on the sample design layout information, wherein the second sample routing layout information of the adjacent routing layer does not change with design changes; and determining the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of the specific routing layer based on the first sample routing layout information and the second sample routing layout information.

[0014] In some embodiments, the at least two types of sample trace layout characteristics include sample trace length and sample track density, wherein the sample trace length and sample track density are respectively the trace length and trace track density of a specific trace layer;

[0015] The step of determining the interconnect delay truth information corresponding to at least two types of sample trace layout characteristics of the specific trace layer based on the first sample trace layout information and the second sample trace layout information includes:

[0016] Based on the first sample routing layout information and the second sample routing layout information, resistance-capacitance extraction is performed on the specific routing layer and the adjacent routing layer to generate a simulated parasitic parameter file;

[0017] Dynamic timing simulation is performed on the simulated parasitic parameter file to obtain the true value of interconnect delay under different signal condition combinations.

[0018] In some embodiments, the step of using the routing layout characteristics of the at least two first samples as input features and the ground truth interconnect delay as training labels to train an initial model to obtain a trained prediction model includes:

[0019] By using the sample trace length and the interconnect delay truth value under different signal condition combinations in the interconnect delay truth value information, the scaling factor corresponding to different signal condition combinations is determined.

[0020] Using the sample orbit density and interconnection delay ground truth information, an initial model is trained so that the initial model learns multiple sets of functional relationships from the sample orbit density to the interconnection delay ground truth under different combinations of signal conditions;

[0021] The prediction model is constructed based on the proportionality coefficient and the functional relationship.

[0022] In some embodiments, the at least two types of first routing layout characteristics include the wire mesh length and wire mesh track density of the target routing layer, wherein the wire mesh length and wire mesh track density are respectively the routing length and routing track density of the target routing layer;

[0023] The step of predicting the interconnect delay information of the chip under test using a trained prediction model based on at least two first routing layout characteristics in the first routing layout information includes:

[0024] Based on the wire mesh length and the wire mesh density, the interconnect delay prediction value corresponding to different signal condition combinations of the chip under test is predicted by the trained prediction model.

[0025] This application also provides a device for predicting interconnect delay in chip design, comprising:

[0026] The receiving module is used to receive the first routing layout information of the target routing layer of the chip under test;

[0027] The prediction module is used to predict the interconnect delay information of the chip under test based on at least two types of first trace layout characteristics in the first trace layout information, using a trained prediction model, so as to analyze whether the design of the chip under test is reasonable. The interconnect delay information includes the predicted interconnect delay values ​​corresponding to different combinations of signal conditions.

[0028] This application also provides an electronic device, including a storage medium and a controller, wherein a computer program is stored on the storage medium, and when the computer program is executed by the controller, it implements the steps of the interconnect delay prediction method in chip design as described above.

[0029] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the interconnect delay prediction method in chip design as described above.

[0030] This application discloses a method, apparatus, electronic device, and storage medium for predicting interconnect delay in chip design. The method includes: receiving first routing layout information of a target routing layer of a chip under test; predicting interconnect delay information of the chip under test using a trained prediction model based on at least two types of first routing layout characteristics in the first routing layout information, for analysis of whether the design of the chip under test is reasonable, wherein the interconnect delay information includes predicted interconnect delay values ​​corresponding to different combinations of signal conditions. The technical solution of this application receives the first routing layout information of the target routing layer of the chip under test, and directly outputs the predicted value of interconnect delay under multiple signal condition combinations using a trained prediction model based on at least two types of routing layout characteristics of the first routing layout information. This bypasses the computationally intensive and process-replicating RC parameter extraction and dynamic timing simulation steps required in the prior art, and realizes rapid prediction of interconnect delay in the chip design process. At the same time, designers can quickly judge the rationality of the current design based on the interconnect delay prediction results covering different signal conditions output by the prediction model, thereby reducing the waiting and calculation time caused by modifying a routing. Furthermore, designers do not need to learn various simulation software, which lowers the threshold and manpower cost of interconnect delay prediction and improves the efficiency of chip design. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating a method for predicting interconnect delay in chip design according to one embodiment.

[0032] Figure 2 This is a schematic diagram of the structure of the chip under test according to one embodiment.

[0033] Figure 3 This is a flowchart illustrating a method for constructing a predictive model in chip design, according to one embodiment.

[0034] Figure 4 This is a schematic diagram illustrating a scenario where a scaling factor is determined using the sample trace length and the true value of the interconnect delay, according to one embodiment.

[0035] Figure 5 This is a schematic diagram illustrating a scenario where a functional relationship is determined using sample orbital density and interconnection delay truth value, according to one embodiment.

[0036] Figure 6 This is a schematic diagram of the structure of an interconnect delay prediction device in a chip design, according to one embodiment. Detailed Implementation

[0037] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. In this invention, "each" includes one or more items.

[0039] Figure 1 This is a flowchart illustrating a method for predicting interconnect delay in chip design according to one embodiment. Figure 1 As shown, a method for predicting interconnect delay in chip design according to this application includes the following steps:

[0040] S1, Receive the first routing layout information of the target routing layer of the chip under test;

[0041] S3. Based on at least two types of first trace layout characteristics in the first trace layout information, predict the interconnect delay information of the chip under test through a trained prediction model, so as to analyze whether the design of the chip under test is reasonable. The interconnect delay information includes the predicted interconnect delay values ​​corresponding to different signal condition combinations.

[0042] In this context, "chip under test" (DUT) refers to an integrated circuit chip whose physical layout is still in the design or verification stage. Specifically, DUT also refers to integrated circuit chips containing multi-layered interconnect structures, which utilize metal traces at different levels to achieve complex three-dimensional connections between transistors. For example, DUT encompasses various types of chips. If categorized by function and degree of customization, DUT can be at least one of a system-on-a-chip (SoC), a central processing unit (CPU) and a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a memory chip, or an analog / mixed-signal chip. If categorized by integration and packaging technology, DUT can be a 3D integrated circuit (3D-IC) or an advanced packaged chip. In practice, DUT can be a product of the corresponding type of chip in the design or verification stage.

[0043] The first routing layout information is a combination of physical geometric data describing the routing status of the target routing layer that needs to be studied and designed. It can be understood that the first routing layout information is a dataset containing various quantifiable parameters. For example, the specific electronic components designed on the target routing layer, the arrangement order of these components, and their electrical connections.

[0044] It should be noted that the target routing layer is the routing layer determined based on design analysis requirements. For example, the target routing layer can be determined based on at least one of the following methods:

[0045] The target routing layer can be determined based on the layout characteristics of its adjacent routing layers;

[0046] The target routing layer can be determined based on the timing criticality of the signals it carries;

[0047] The target routing layer can be determined based on its own routing congestion level;

[0048] The target routing layer can also be determined based on manual specification by the user;

[0049] The target routing layer can also be determined based on the process conditions of each routing layer. For example, routing layers that use a specific new process or have special electrical characteristics can be determined as target routing layers.

[0050] For example, the target routing layer is manually specified by the user, meaning the system determines it through the routing layer identifier specified by the user. For example, receiving the first routing layout information of the target routing layer of the chip under test may include: receiving the first routing layout information of the target routing layer of the chip under test based on the user's input operation regarding the first routing layout information of the target routing layer.

[0051] For example, receiving the first routing layout information of the target routing layer of the chip under test may further include: receiving the design layout information of the chip under test, and extracting the first routing layout information of the target routing layer from the multi-layer routing layers based on the design layout information.

[0052] For example, extracting the first routing layout information of the target routing layer from the multi-layer routing layers according to the design layout information includes: determining the second routing layout information of each routing layer according to the design layout information; determining the target routing layer from the multi-layer routing layers according to the second routing layout information, and determining the first routing layout information corresponding to the target routing layer.

[0053] For example, determining the target routing layer from multiple routing layers based on the fourth routing layout information further includes: determining two mutually spaced routing layers from multiple routing layers whose second routing layout characteristics satisfy preset conditions based on at least two types of second routing layout characteristics in the fourth routing layout information, and determining the routing layer between the two mutually spaced routing layers as the target routing layer. The preset conditions include that at least two types of second routing layout characteristics of the two mutually spaced routing layers do not change with design changes, wherein at least two types of second routing layout characteristics correspond to at least two types of first routing layout characteristics.

[0054] Design layout information, which is a database describing the physical implementation of a chip, is typically generated by place-and-route tools. This information can include physical layout data, logic netlists, and technical documents. Physical layout data, for example, can be files in GDSII or OASIS format, precisely defining the shape, location, and size of transistors, contacts, and interconnects on each layer (e.g., metal layers M1, M2, ...). Logic netlists can describe the logical connections between components in a circuit. Technical documents define process rules, such as the thickness, width, and spacing of each metal layer, as well as the electrical properties of interlayer dielectrics.

[0055] In some embodiments, based on design layout information, determining two mutually spaced routing layers that meet preset conditions from a multi-layer routing layer, and defining the routing layer between the two mutually spaced routing layers as the target routing layer, includes:

[0056] Based on the design layout information, determine the second wiring layout information for each wiring layer;

[0057] Based on the second routing layout information, the target routing layer is determined from the multi-layer routing layers, and the first routing layout information corresponding to the target routing layer is determined.

[0058] It should be noted that the second wiring layout information is a macro-statistic used for inter-layer comparison and screening.

[0059] For example, determining the second routing layout information for each routing layer based on the design layout information may include: first reading and parsing the design layout information of the entire chip under test using an embedded or external EDA tool script, then traversing each routing layer of the chip under test, and calculating a series of quantifiable second routing layout information for each routing layer.

[0060] Taking the determination of a target routing layer based on the layout characteristics of its adjacent routing layers as an example. In some embodiments, determining the target routing layer from multiple routing layers based on second routing layout information includes:

[0061] Based on at least two types of second routing layout characteristics in the second routing layout information, two spaced routing layers whose second routing layout characteristics satisfy preset conditions are determined from the multi-layer routing layers, and the routing layer between the two spaced routing layers is defined as the target routing layer. The preset conditions include that the second routing layout characteristics of the two spaced routing layers do not change with design changes, and at least two types of second routing layout characteristics correspond to at least two types of first routing layout characteristics.

[0062] It should be noted that at least two types of second routing layout characteristics correspond to at least two types of first routing layout characteristics. This can be understood as the number and types of first routing layout characteristics selected for the target routing layer being the same as the number and types of second routing layout characteristics selected for the routing layer. For example, both are judged by the routing length and routing track density of the routing layer.

[0063] It should be noted that this embodiment aims to automatically determine the routing layers that require key interconnect delay prediction analysis, i.e., the target routing layers. In other words, by identifying reference layers with stable and invariant characteristics in the information under test, the target routing layers located between them, whose routing characteristics change with the design, and which need to be evaluated, are located.

[0064] Specifically, the computer system first parses the design layout information of the entire chip under test using EDA tools, and calculates the second routing layout information for each routing layer. For example, at least two types of second routing layout characteristics in the second routing layout information can be the routing length and track density of the routing layer. After traversing all routing layers, the computer system searches for two or more routing layers that meet the following preset conditions. In some embodiments, the preset conditions can be that the routing layer length is fixed and the track density is explicitly fixed to a constant value, such as 1, by design rules or the design engineer. For example, please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of the structure of the chip under test according to one embodiment, such as... Figure 2 As shown, if the trace lengths of layers M+1 and M-1 are fixed and the track density is equal to 1, then layer M between them is considered the target trace layer. In other embodiments, the preset condition may also be that the layer is a dedicated power or ground layer, which is typically filled with a large area of ​​metal and has fixed wiring characteristics. In other embodiments, the preset condition may also be that the trace layer is disabled or not used in the current design, and its layout characteristics remain unchanged.

[0065] Taking at least two types of second routing layout characteristics, namely routing length and track density, as an example, in this embodiment, by utilizing the invariance of routing length and track density of adjacent routing layers, a controlled environment is created, and then the change in interconnect delay caused by the change of the target layer located between them in these two types of the same layout characteristics is studied. Thus, the prediction of the external interconnect delay of the entire chip under test is simplified and can be predicted only by the two types of first routing layout characteristics of the target routing layer, thereby reducing the learning threshold of chip design.

[0066] The above embodiments determine the target routing layer based on preset conditions, transforming the designer's intent, such as the designer's desire to study a certain layer in a fixed environment, into precise logic that can be executed by a computer. This not only reduces the subjectivity and tediousness of manual selection, but more importantly, it provides a foundation for generating highly intelligent standardized training data for training prediction models, thereby ensuring the consistency and accuracy of the prediction models.

[0067] Taking the determination of the target routing layer based on the timing criticality of the signals it carries as an example, the target routing layer is determined from multiple routing layers based on the second routing layout information. This includes: obtaining the physical distribution information of the critical path by interacting with a static timing analysis tool, and statistically analyzing the critical path data carried by each layer, thereby optimizing the analysis of the layer with the greatest impact on timing. The static timing analysis tool here can also be a pre-defined timing analysis model, i.e., a model that can directly obtain the physical distribution information of the critical path based on the input of the second routing layout information.

[0068] Taking the determination of the target cabling layer based on its own cabling congestion level as an example, for instance, the target cabling layer is determined from multiple cabling layers according to the second cabling layout information, including: based on the second cabling layout information, by comparing the preset congestion threshold with the calculated track density statistics, etc., the cabling layer that meets the congestion conditions is automatically identified as the target cabling layer.

[0069] Taking the target routing layer as an example, which can also be determined based on the user's manual specification, for instance, determining the target routing layer from multiple routing layers according to the second routing layout information includes: determining the routing layer with the manually specified first label as the target routing layer according to the second routing layer layout information.

[0070] Taking the determination of the target routing layer based on the process conditions of each routing layer as an example, for instance, the target routing layer is determined from multiple routing layers according to the second routing layout information, including: determining the routing layer with a second label having a new process and / or a special structure as the target routing layer according to the second routing layout information.

[0071] The above method automates and automates the target routing layer selection process, enabling the subsequent six-step process of predicting the interconnect delay information of the chip under test based on at least two types of first routing layout characteristics in the first routing layout information of the target routing layer to be integrated into the chip design automation process. This allows for the automatic identification of the routing layer that needs attention, i.e. the target routing layer, without manual intervention, and the initiation of interconnect delay prediction, thereby improving the efficiency and automation level of the entire design process.

[0072] It should be noted that using a routing layer located between two or more specific adjacent routing layers as the target routing layer can be used to evaluate the impact of routing changes on interconnect delay under specific, controllable interference environments. Target routing layers determined in this way are ideal for model training and controllable analysis. Using a routing layer carrying timing-critical signals as the target routing layer prioritizes ensuring the accuracy of the paths with the highest performance requirements and the greatest likelihood of timing violations—the most critical parts of the product design. Examples include routing layers containing high-frequency global clock lines, data buses, and critical control signals. Using a routing layer with the highest routing congestion or the most anticipated crosstalk as the target routing layer proactively identifies and resolves potential performance bottlenecks caused by physical design issues. Examples include routing layers with frequent signal switching activity below specific functional modules of the chip, such as CPU cores and high-speed interfaces. If a routing layer is manually specified by the chip design engineer based on their experience and design intent, it provides designers with greater flexibility and allows for targeted analysis of any layer of interest. For example, a designer might suspect a timing issue in the routing layer of a newly adopted semi-custom module and directly designate that layer as the target routing layer. Designating a routing layer with specific processes or unique electrical characteristics as the target routing layer can verify the accuracy of the performance model for the new process or special structure. For instance, the first use of an ultra-low resistance metal layer in a chip, or a layer employing low-k dielectrics such as air gaps, results in coupling capacitance characteristics different from conventional layers.

[0073] Among them, trace layout characteristics refer to key geometric parameters selected from trace layout information that have been proven to be strongly correlated with interconnect delay. Analyzing at least two types of trace layout characteristics allows for a more comprehensive characterization of the physical nature of interconnect delay, resulting in more accurate predictions. For example, trace layout characteristics include, but are not limited to, at least one of the following: characteristics related to the geometry of the trace layer's conductor network itself; characteristics related to the coupling effect between conductors in the trace layer's conductor network; characteristics related to the trace layer's process; and characteristics related to the trace layer's drive and load. For example, characteristics related to the geometry of the trace layer's conductor network itself may include, but are not limited to, at least one of the following: trace length, trace width, trace thickness, number of bends, and number of vias. Characteristics related to the coupling effect between conductors in the trace layer's conductor network may include, but are not limited to, at least one of the following: trace track density, adjacent trace spacing, parallel length, and interlayer overlap area. It should be noted that a track refers to a parallel traversable path arranged at a certain interval, and trace track density refers to the ratio of the actual number of trace tracks in the target trace layer to the total number of tracks. Characteristics related to the process of the trace layer may include, but are not limited to, at least one of the following: the identification of the metal layer in which it is located, and the type of the metal layer; characteristics related to the drive and load of the trace layer may include, but are not limited to, at least one of the following: the drive strength of the drive unit, and the number of fan-outs.

[0074] The prediction model can be any machine learning model or mathematical model that learns from input features and maps them to output values. In this embodiment, the core of the prediction model is to learn the complex, non-linear mapping relationship between routing layout characteristics and interconnect latency.

[0075] The signal conditions include at least one of the following: the input signal direction of the chip under test is rising or falling; whether the coupling capacitance between the target trace layer and the adjacent trace layer is converted to ground capacitance in the chip under test; and whether the input signal direction of the adjacent trace layer in the chip under test is the same as or opposite to the input signal direction of the target trace layer.

[0076] Specifically, the interconnection delay types corresponding to different combinations of signal conditions can be seen in Table 1:

[0077]

[0078] Rise means to rise, and Fall means to fall.

[0079] Based on this, the interconnect delay information can characterize the predicted interconnect delay value of the chip under test under various signal condition combinations. For example, it can predict the intrinsic delay value of the chip under test under signal condition combination 1, the maximum delay under signal condition combination 2, the maximum delay under signal condition combination 3, the minimum delay under signal condition combination 4, and the minimum delay under signal condition combination 5.

[0080] By using the above method, the routing layout characteristics of the target routing layer in the chip are directly mapped to interconnect delay, thereby improving the efficiency of interconnect delay prediction in chip design and simplifying the complex process that requires multiple tools and iterations in traditional technology, thus improving the efficiency and agility of chip design.

[0081] In some embodiments, at least two types of first routing layout characteristics include the wire net length and wire net track density of the target routing layer, wherein the wire net length and wire net track density are the routing length and routing track density of the target routing layer, respectively; Step S3, based on at least two types of first routing layout characteristics in the first routing layout information, predicting the interconnect delay prediction value corresponding to different signal condition combinations of the chip under test using a trained prediction model, including:

[0082] Based on the wire mesh length and wire mesh track density, the interconnect delay prediction value corresponding to different signal condition combinations of the chip under test is predicted by the trained prediction model.

[0083] The length of the conductor network directly determines its parasitic resistance and capacitance to ground. According to Kirchhoff's laws and the RC delay model, the signal transmission delay on the conductor is proportional to the RC product, and both resistance R and capacitance C are positively correlated with the conductor length. Therefore, the conductor network length is the most fundamental physical quantity determining the interconnection delay. In this embodiment, using the conductor network length as an input feature ensures a more accurate predicted interconnection delay value.

[0084] Among these factors, the track density of the cabling network is a key factor in quantifying the impact of crosstalk. At advanced process nodes, the coupling capacitance between conductors has a far greater impact on delay than the conductor's own capacitance to ground. Track density accurately quantifies the congestion level of the cabling area; high track density means smaller conductor spacing and larger coupling capacitance, thus altering signal transmission characteristics. When adjacent network signals transition in opposite phase, the coupling capacitance becomes equivalent to a larger load capacitance, leading to an increase in maximum delay and threatening settling time. When adjacent network signals transition in phase, the coupling capacitance produces an acceleration effect, resulting in a decrease in minimum delay and threatening hold time. Therefore, track density is an efficient and quantifiable key indicator for capturing this complex nonlinear effect.

[0085] It should be noted that although the delay is also affected by multiple factors such as conductor width, thickness, and dielectric material, under a fixed process, these parameters are usually constant or strongly correlated with length / density. However, introducing too many features will increase the complexity of the prediction, for example, by increasing the complexity of the prediction model and the risk of overfitting.

[0086] In the above method, by selecting two relatively independent and information-complete routing layout characteristics, namely the wire mesh length and the wire mesh track density, it is sufficient to predict the interconnection delay information under a fixed process. This simplifies the multi-feature extraction of the routing layout characteristics of the target layer, thereby simplifying the entire prediction process, improving prediction efficiency, and reducing prediction costs.

[0087] In some embodiments, please refer to Figure 3 , Figure 3 This is a flowchart illustrating a method for constructing a predictive model in chip design, based on an embodiment. Figure 3 As shown, the method includes:

[0088] Step S31: Obtain the training dataset. The training dataset includes multiple training samples. The training samples include at least two types of sample routing layout characteristics of a specific routing layer in the sample chip, and the interconnect delay truth information corresponding to the sample chip. The interconnect delay truth information includes the interconnect delay truth value corresponding to different signal condition combinations. The at least two types of sample routing layout characteristics correspond to at least two types of first routing layout characteristics.

[0089] Step S32: Using at least two types of sample trace layout characteristics as input features and interconnect delay ground truth as training labels, train an initial model to obtain a trained prediction model. The sample chip and the chip under test have the same chip type, and the level of a specific trace layer in the sample chip is the same as the level of the target trace layer in the chip under test.

[0090] The initial model here can be, but is not limited to, one of the following types: gradient boosting decision tree model, feedforward neural network / neural network model, support vector regression model, and fusion model. Gradient boosting decision tree models can be, for example, XGBoost or LightGBM. These models are powerful in handling mixed-type features and capturing complex nonlinear interactions, and have high training efficiency. Feedforward neural network / neural network models can be, for example, composed of multiple fully connected layers, capable of approximating any complex functional relationship through multi-layer nonlinear transformations, making them very suitable for high-precision latency prediction. Support vector regression models can be, for example, models that aim to find a hyperplane in the feature space that minimizes the deviation of all data points, and perform well on small to medium-sized datasets. Fusion models can be, for example, models composed of multiple basic models stacked or weighted averaged to integrate the advantages of each model, further improving prediction accuracy and robustness.

[0091] It should be noted that the sample chip is of the same type as the chip under test. Specifically, for example, they both use the same semiconductor manufacturing process node, such as chips manufactured using the 7nm process; or they are chips with similar circuit architecture and design rules, such as chips belonging to the same product family or application area.

[0092] It should be noted that the layer position of a specific routing layer in the sample chip is the same as the layer position of the target routing layer in the chip under test. Specifically, for example, if the target layer of the chip under test is the 6th metal layer M6, then the specific routing layer in the sample chip is also M6, to ensure that the model learns the delay pattern of a specific layer.

[0093] Among them, the true information of interconnect delay refers to the actual delay measurement value under different combinations of signal conditions that are close to the physical reality, obtained through a precise electronic design automation simulation process.

[0094] The above method ensures the accuracy of the prediction model's interconnect delay prediction for the current chip under test by aligning the sample chip types and specific routing layers used in the model training, as well as the characteristics of at least two types of routing layouts. This provides a reliable guarantee for using the prediction model to predict fast interconnect delays, while also ensuring the accuracy of the predicted values ​​and the reliability of the chip design.

[0095] In some embodiments, step S31, obtaining the training dataset includes: obtaining sample design layout information of the sample chip, the sample chip including multiple routing layers; and determining the interconnect delay truth information corresponding to at least two types of sample routing characteristics of a specific routing layer in the multiple routing layers based on the sample design layout information.

[0096] The sample design layout information here refers to the design layout information for the sample chip. Thus, in this embodiment, by considering multiple routing layers and determining the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of a specific routing layer within the multiple routing layers, the at least two types of sample routing layout characteristics of the specific routing layer to be trained can be determined more accurately.

[0097] In some embodiments, determining the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of a specific routing layer in a multi-layer routing layer based on sample design layout information includes: determining the first sample routing layout information of the specific routing layer and the second sample routing layout information of the adjacent routing layer adjacent to the specific routing layer based on the sample design layout information, wherein the second sample routing layout information of the adjacent routing layer does not change with design changes; and determining the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of the specific routing layer based on the first sample routing layout information and the second sample routing layout information.

[0098] Here, the first sample routing layout information refers to the routing layout information for a specific routing layer, and the second sample routing layout information refers to the second sample routing layout information for two adjacent routing layers adjacent to the specific routing layer. Please refer to [further details needed]. Figure 2 If a specific routing layer is layer M, then the adjacent routing layers are layers M-1 and M+1. Here, the second sample routing layout information of the adjacent routing layers does not change with design changes; this can be understood as at least two types of sample routing layout characteristics in the second sample routing layout information of the adjacent routing layers not changing with design changes. For example, as... Figure 2 As shown, if the trace lengths of the M+1th layer and the M-1th layer are fixed, the track density is equal to 1.

[0099] Thus, in this embodiment, by considering the second sample routing layout information of the adjacent routing layers adjacent to the specific routing layer, the interconnect delay ground truth information corresponding to at least two types of sample routing layout characteristics of the specific routing layer can be determined more accurately, thereby determining at least two types of sample routing layout characteristics of the specific routing layer to be trained.

[0100] In some embodiments, at least two types of sample trace layout characteristics include sample trace length and sample track density, wherein the sample trace length and sample track density are respectively the trace length and trace track density of a specific trace layer;

[0101] Based on the first sample routing layout information and the second sample routing layout information, determine the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics for a specific routing layer, including:

[0102] Based on the first sample routing layout information and the second sample routing layout information, the resistance-capacitance of a specific routing layer and adjacent routing layers are extracted to generate a simulated parasitic parameter file.

[0103] Dynamic timing simulations were performed on the simulated parasitic parameter file to obtain the true value of the interconnection delay under different combinations of signal conditions.

[0104] Resistor-capacitor extraction (hereinafter referred to as RC extraction) is an electronic design automation process that refers to the precise calculation of the parasitic resistance (R) and parasitic capacitance (C) of each trace from the physical layout geometry of the chip.

[0105] It is important to note that the total capacitance of a conductor located on a specific layer, such as layer M, is not solely determined by that layer, but rather by the overall electric field environment formed by the conductor and all adjacent conductors. This includes, but is not limited to, at least one of the following: interlayer capacitance, the reference plane effect of the capacitance to ground, and edge electric field coupling. Interlayer capacitance is the most direct and crucial factor. The conductor on layer M will form coupling capacitance with conductors in layers M+1 directly above and M-1 directly below. Interlayer capacitance depends on the vertical overlap area and spacing between the conductor on layer M and the conductors in adjacent layers. Without providing second-sample trace layout information for adjacent layers, this critical capacitance will be completely ignored or incorrectly estimated, negatively impacting the accuracy of delay prediction. Furthermore, the capacitance to ground of a conductor is not absolutely directed towards the silicon substrate. In practical designs, large-area power and ground networks serve as primary voltage reference platforms. These reference platforms may be located above or below layer M. RC extraction tools require information from these adjacent power / ground layers to accurately calculate the capacitance between the conductor on layer M and these stable reference planes. It should be noted that even without direct vertical overlap, the edge electric field of the M-layer conductor will extend to the adjacent trace layer and couple with the nearby conductor.

[0106] It should be noted that a complete wire network typically runs vertically between multiple metal layers through vias. The path from a signal driver to a receiver may pass through layers M-1, M, and M+1 in sequence. Therefore, to accurately calculate the resistance and current path of a wire segment on layer M, it is necessary to know which adjacent layers it is connected to, because vias themselves have resistance, and the current distribution is affected by the entire three-dimensional network topology.

[0107] It should be noted that the prediction model to be trained aims to predict delays under different combinations of signal conditions, including scenarios with crosstalk. Crosstalk is essentially energy coupling between adjacent traces through coupling capacitors. If only RC extraction is performed on the M-th layer, it is impossible to simulate the crosstalk effect caused by signal transitions on the traces of the adjacent layer on the traces of the M-th layer. In dynamic timing simulation, the input signal direction of the adjacent trace layer must be based on the actual physical existence and coupling relationship of the adjacent trace layer.

[0108] Therefore, in this embodiment, extracting the resistance and capacitance of a specific routing layer and adjacent routing layers based on the first sample routing layout information and the second sample routing layout information is a necessary prerequisite for obtaining accurate interconnect delay truth values. This ensures the accuracy and reliability of the standard answer used to train the initial model, thereby fundamentally guaranteeing the quality and reliability of the prediction model.

[0109] For example, extracting RC data to generate a simulated parasitic parameter file can be achieved by inputting the physical layout data of the sample chip and technical documents describing the process details into an EDA tool. The EDA tool then calculates the resistance and capacitance based on the physical layout and applying electromagnetic field solver principles. The capacitance includes capacitance to ground and coupling capacitance. It should be noted that capacitance to ground refers to the capacitance between the trace and the substrate, and coupling capacitance refers to the capacitance between adjacent parallel traces. The simulated parasitic parameter file is then output.

[0110] It's important to note that a simulated parasitic parameter file is a data file that describes the electrical characteristics of a chip's interconnect network. It's a netlist composed of circuit elements such as resistors and capacitors, translating the chip's physical layout into an electrical model that circuit simulation can understand. This is the foundation for accurate timing simulation. Common simulated parasitic file formats are SPEF (Standard Parasitic Exchange Format) or DSPF (Detailed Standard Parasitic Format).

[0111] Dynamic timing simulation is a method that simulates the dynamic response of a circuit and accurately measures signal transmission delay by solving the circuit's differential equations using numerical integration based on the design input signal waveform. Compared to static timing analysis, dynamic timing simulation is dynamic and waveform-driven, capable of accurately simulating nonlinear effects such as signal jumps and crosstalk, and its results are closer to the actual operating state of the chip. For example, dynamic simulation tools can be SPICE or FastSPICE-like simulators.

[0112] By employing the above methods, the authority and high fidelity of the data are ensured, enabling the subsequently trained prediction model to not only learn quickly but also achieve prediction accuracy that rivals that of precise SPICE simulation results. This provides a solid technical foundation for replacing time-consuming simulations with efficient model predictions.

[0113] In some embodiments, step S32, using at least two types of first sample routing layout characteristics as input features and interconnect delay ground truth information as training labels, trains an initial model to obtain a trained prediction model, including:

[0114] By using the sample trace length and interconnect delay truth value information under different signal condition combinations, the scaling factor corresponding to different signal condition combinations is determined.

[0115] Using sample track density and interconnection delay ground truth information, an initial model is trained so that the initial model learns multiple sets of functional relationships between sample track density and interconnection delay ground truth under different signal condition combinations;

[0116] A prediction model is constructed based on the proportionality coefficient and the functional relationship.

[0117] Based on empirical data, the square of the trace length is proportional to the true value of the interconnect delay. For example, please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram illustrating a scenario where a scaling factor is determined using sample trace length and interconnect truth value, based on an embodiment. Figure 4 As shown, the interconnect delay truth value is calculated using sample trace length and interconnect delay truth value information under different signal condition combinations. This includes: calculating the trend curve between the square of the sample trace length and the interconnect delay truth value, and then determining the scaling factor based on the trend curve. It can be understood that the scaling factor is the slope of this trend curve. It should be noted that this trend curve is plotted under the condition that the sample track density is at a specific value.

[0118] Further, please refer to Figure 5 , Figure 5 This is a schematic diagram illustrating a scenario where a functional relationship is determined using sample orbital density and interconnection delay truth values, as shown in one embodiment. Figure 5 As shown, the initial model is trained using sample track density and interconnect delay ground truth information, including: constructing a functional relationship between the sample track density and the interconnect delay ground truth information under different signal condition combinations. This functional relationship is uncertain. The initial model is then used to learn and train based on the functional relationship so that a definite interconnect delay ground truth can be output by inputting the sample track density into the functional relationship.

[0119] The above approach, by combining traditional physical models with machine learning techniques, can create more accurate, efficient, and reliable prediction models, thus laying a solid foundation for using these models to predict the interconnect latency of the chip under test and ensuring improved prediction accuracy.

[0120] For example, the prediction model is a single model that uses at least two classes of sample routing layout characteristics as input features and interconnect delay ground truth information as training labels to train an initial model to obtain a trained prediction model, including:

[0121] The sample signal condition combination and the at least two sample trace layout characteristics are used together as input features, and the interconnect delay ground truth is used as training label to train the initial model to obtain the trained prediction model. The prediction model is configured to receive the trace layout characteristics and signal condition combination and output the interconnect delay prediction value under the corresponding signal conditions.

[0122] In this way, by building a unified intelligent prediction architecture, the practicality and efficiency of the model can be improved while ensuring prediction accuracy, providing a more convenient and reliable interconnect delay analysis tool for chip design.

[0123] In other embodiments, the step of using the at least two sample routing layout characteristics as input features and the interconnect delay ground truth as training labels to train an initial model to obtain the trained prediction model includes:

[0124] The training dataset is divided into multiple sub-training sets based on the combination of sample signal conditions, and the sample signal conditions corresponding to different sub-training sets are different.

[0125] Using each of the sub-training sets, a dedicated sub-model is trained to obtain the prediction model consisting of multiple sub-models, wherein each sub-model corresponds to a specific signal condition.

[0126] Thus, this embodiment trains dedicated sub-models for different signal condition combinations. Because each sub-model focuses on learning the delay patterns under a single signal condition combination, it reduces feature interference between different scenarios. It can deeply explore the nonlinear mapping relationships under specific signal conditions, obtaining more accurate prediction results. Furthermore, when the physical characteristics of a certain signal condition combination change, only the corresponding sub-model needs to be retrained, which can reduce model maintenance costs and time. It allows for targeted optimization for specific scenarios with poor prediction results without retraining the entire model system. In addition, complex learning tasks can be decomposed into multiple relatively simple sub-tasks, reducing the training difficulty of individual models. Parallel training of each sub-model can significantly shorten training time. When computing resources are prioritized, sub-models for key signal condition combinations can be trained first. Moreover, the anomaly or failure of a single sub-model will not affect the prediction results of other signal conditions, facilitating the implementation of differentiated verification strategies and setting different quality standards for signal condition combinations of different importance. Furthermore, the deployment of each sub-model can be selected according to actual needs, providing greater flexibility. In summary, by constructing a model that embodies professional division of labor, a balance between accuracy, efficiency, and maintainability can be achieved in the complex and multi-scenario interconnect delay prediction problem, providing strong technical support for chip design with high reliability requirements.

[0127] Figure 6 This is a schematic diagram illustrating the structure of an interconnect delay prediction device in a chip design according to one embodiment. For example... Figure 6 As shown, this application also provides a device for predicting interconnect delay in chip design, comprising:

[0128] Receiver module 61 is used to receive the first routing layout information of the target routing layer of the chip under test;

[0129] The prediction module 63 is used to predict the interconnect delay information of the chip under test by using a trained prediction model based on at least two types of first trace layout characteristics in the first trace layout information, so as to analyze whether the design of the chip under test is reasonable. The interconnect delay information includes the predicted interconnect delay values ​​corresponding to different combinations of signal conditions.

[0130] In some embodiments, the interconnect delay prediction device in chip design further includes:

[0131] The acquisition module is used to acquire the training dataset, which includes multiple training samples. The training samples include at least two types of sample routing layout characteristics of a specific routing layer in the sample chip, as well as the interconnect delay truth information corresponding to the sample chip. The interconnect delay truth information includes the interconnect delay truth value corresponding to different signal condition combinations, and the at least two types of sample routing layout characteristics correspond to at least two types of first routing layout characteristics.

[0132] The training module is used to train an initial model with at least two types of sample trace layout characteristics as input features and interconnect delay ground truth information as training labels to obtain a trained prediction model. The sample chip and the chip under test are of the same chip type, and the level of a specific trace layer in the sample chip is the same as the level of the target trace layer in the chip under test.

[0133] In some embodiments, the acquisition module is further configured to acquire sample design layout information of a sample chip, the sample chip including multiple routing layers; and determine, based on the sample design layout information, interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of a specific routing layer in the multiple routing layers.

[0134] In some embodiments, the acquisition module is further configured to: determine, based on the sample design layout information, a first sample routing layout information of a specific routing layer and a second sample routing layout information of an adjacent routing layer of the specific routing layer, wherein the second sample routing layout information of the adjacent routing layer does not change with design changes; and determine, based on the first sample routing layout information and the second sample routing layout information, interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of the specific routing layer.

[0135] In some embodiments, at least two types of routing layout characteristics include sample routing length and sample track density, wherein the sample routing length and sample track density are the routing length and routing track density of a specific routing layer, respectively.

[0136] The acquisition module is used for:

[0137] Based on the routing layout information of the first sample and the routing layout information of the second sample, resistance-capacitance extraction is performed on specific routing layers and adjacent routing layers to generate simulated parasitic parameter files.

[0138] Dynamic timing simulations were performed on the simulated parasitic parameter file to obtain the true value of the interconnection delay under different combinations of signal conditions.

[0139] In some embodiments, the training module is used for:

[0140] By using the sample trace length and interconnect delay truth value information under different signal condition combinations, the scaling factor corresponding to different signal condition combinations is determined.

[0141] Using sample track density and interconnection delay ground truth information, an initial model is trained so that the initial model learns multiple sets of functional relationships from sample track density to interconnection delay ground truth under different signal condition combinations;

[0142] A prediction model is constructed based on the proportionality coefficient and the functional relationship.

[0143] In some embodiments, at least two types of first routing layout characteristics include the wire mesh length and wire mesh track density of the target routing layer, wherein the wire mesh length and wire mesh track density are respectively the routing length and routing track density of the target routing layer.

[0144] The prediction module is used for:

[0145] Based on the wire mesh length and wire mesh track density, the interconnect delay prediction value corresponding to different signal condition combinations of the chip under test is predicted by the trained prediction model.

[0146] For the specific implementation process of the steps performed by each module in the interconnect delay prediction device in chip design, please refer to the description of the method embodiment, which will not be repeated here.

[0147] This application also provides an electronic device, including a storage medium and a controller, wherein a computer program is stored on the storage medium, and when the computer program is executed by the controller, it implements the steps of the interconnect delay prediction method in chip design as described in the above embodiments.

[0148] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the interconnect delay prediction method in chip design as described in the above embodiments.

[0149] This application discloses a method, apparatus, electronic device, and storage medium for predicting interconnect delay in chip design. The method includes: receiving first routing layout information of the target routing layer of the chip under test; predicting the interconnect delay information of the chip under test using a trained prediction model based on at least two types of first routing layout characteristics in the first routing layout information, for analysis of the rationality of the chip under test design. The interconnect delay information includes predicted interconnect delay values ​​corresponding to different combinations of signal conditions. This technical solution, by receiving at least two types of routing layout characteristics of the target routing layer of the chip and then using a pre-trained prediction model to directly output predicted interconnect delay values ​​under multiple signal condition combinations, enables rapid prediction of interconnect delay during the chip design process and quick assessment of the rationality of the current design. This reduces the waiting and computation time caused by modifying a routing element, lowers the threshold and labor costs for interconnect delay prediction, and improves the efficiency of chip design.

[0150] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for predicting interconnect delay in chip design, characterized in that, The method includes the following steps: Receive the first routing layout information of the target routing layer of the chip under test; Based on at least two types of first trace layout characteristics in the first trace layout information, the interconnect delay information of the chip under test is predicted by a trained prediction model to analyze whether the design of the chip under test is reasonable. The interconnect delay information includes predicted interconnect delay values ​​corresponding to different signal condition combinations. The at least two types of first trace layout characteristics include the trace length and trace track density of the target trace layer. The signal conditions include at least one of the following: the input signal direction of the chip under test is rising or falling; whether the coupling capacitance between the target trace layer and its adjacent trace layers is converted to ground capacitance in the chip under test; and whether the input signal direction of the adjacent trace layers of the target trace layer in the chip under test is the same as or opposite to the input signal direction of the target trace layer.

2. The method according to claim 1, characterized in that, The method further includes: Obtain a training dataset, which includes multiple training samples. The training samples include at least two types of sample routing layout characteristics of a specific routing layer in the sample chip, and the interconnect delay truth information corresponding to the sample chip. The interconnect delay truth information includes interconnect delay truth values ​​corresponding to different signal condition combinations. The at least two types of sample routing layout characteristics correspond to at least two types of the first routing layout characteristics. Using the at least two types of sample trace layout characteristics as input features and the interconnect delay ground truth information as training labels, an initial model is trained to obtain the trained prediction model. The sample chip and the chip under test are of the same chip type, and the specific trace layer in the sample chip is at the same level as the target trace layer in the chip under test.

3. The method according to claim 2, characterized in that, The acquisition of the training dataset includes: Obtain the sample design layout information of the sample chip, which includes multiple wiring layers; Based on the sample design layout information, determine the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of the specific routing layer in the multi-layer routing layer.

4. The method according to claim 3, characterized in that, The step of determining the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of a specific routing layer in the multi-layer routing layers based on the sample design layout information includes: Based on the sample design layout information, the first sample routing layout information of the specific routing layer and the second sample routing layout information of the adjacent routing layer adjacent to the specific routing layer are determined, wherein the second sample routing layout information of the adjacent routing layer does not change with the design. Based on the first sample routing layout information and the second sample routing layout information, determine the interconnect delay truth information corresponding to at least two types of sample routing layout characteristics of the specific routing layer.

5. The method according to claim 4, characterized in that, The at least two types of sample trace layout characteristics include sample trace length and sample track density, wherein the sample trace length and sample track density are respectively the trace length and trace track density of a specific trace layer; The step of determining the interconnect delay truth information corresponding to at least two types of sample trace layout characteristics of the specific trace layer based on the first sample trace layout information and the second sample trace layout information includes: Based on the first sample routing layout information and the second sample routing layout information, resistance-capacitance extraction is performed on the specific routing layer and the adjacent routing layer to generate a simulated parasitic parameter file; Dynamic timing simulation is performed on the simulated parasitic parameter file to obtain the true value of interconnect delay under different signal condition combinations.

6. The method according to claim 5, characterized in that, The step of using the routing layout characteristics of at least two types of samples as input features and the ground truth information of interconnect delay as training labels to train an initial model to obtain the trained prediction model includes: By using the sample trace length and the interconnect delay truth value under different signal condition combinations in the interconnect delay truth value information, the proportional coefficient corresponding to different signal condition combinations is determined; Using the sample orbit density and interconnection delay ground truth information, the initial model is trained so that the initial model learns multiple sets of functional relationships from the sample orbit density to the interconnection delay ground truth under different signal condition combinations; The prediction model is constructed based on the proportionality coefficient and the functional relationship.

7. The method according to claim 1, characterized in that, The at least two types of first routing layout characteristics include the wire mesh length and wire mesh track density of the target routing layer, wherein the wire mesh length and wire mesh track density are respectively the routing length and routing track density of the target routing layer; The step of predicting the interconnect delay information of the chip under test using a trained prediction model based on at least two types of first trace layout characteristics in the first trace layout information includes: Based on the wire mesh length and the wire mesh track density, the interconnect delay prediction value corresponding to different signal condition combinations of the chip under test is predicted by the trained prediction model.

8. A device for predicting interconnect delay in chip design, characterized in that, include: The receiving module is used to receive the first routing layout information of the target routing layer of the chip under test; The prediction module is used to predict the interconnect delay information of the chip under test (DUT) based on at least two types of first trace layout characteristics in the first trace layout information using a trained prediction model, so as to analyze whether the design of the DUT is reasonable. The interconnect delay information includes predicted interconnect delay values ​​corresponding to different combinations of signal conditions. The at least two types of first trace layout characteristics include the trace length and trace track density of the target trace layer. The signal conditions include at least one of the following: the input signal direction of the DUT is rising or falling; whether the coupling capacitance between the target trace layer and its adjacent trace layers is converted to ground capacitance in the DUT; and whether the input signal direction of the adjacent trace layers of the target trace layer in the DUT is the same as or opposite to the input signal direction of the target trace layer.

9. An electronic device comprising a storage medium and a controller, characterized in that, The storage medium stores a computer program that, when executed by the controller, implements the steps of the method for predicting interconnect delay in chip design as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the steps of the method for predicting interconnect delay in a chip design as described in any one of claims 1 to 7.

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