Automatic design method and equipment of storage circuit and storage medium

Abstract

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design and simulation verification technology, specifically to an automated design method and device for memory circuits and a memory medium. Background Technology

[0002] Currently, in the field of integrated circuit design, including memory circuits, after a standard memory circuit is designed, it is generally manually disassembled into several circuit units. Then, suitable circuit units are selected according to user requirements, and these selected circuit units are assembled into the desired target memory circuit. This manual assembly design method is labor-intensive, and more importantly, it is prone to errors and misjudgments, thus affecting the reliability of the circuit design. Summary of the Invention

[0003] In view of this, this application provides an automated design method, device, and storage medium for storage circuits, which can improve the problems of low efficiency, high error, and poor reliability caused by manual splicing design methods.

[0004] This application provides an automated design method for memory circuits, comprising: Obtain the required parameters input by the user in the compiler; The compiler imports multiple circuit units, which are the result of disassembling a standard memory circuit; Determine the target circuit architecture based on the aforementioned requirements parameters; Based on the required parameters, the compiler calls the corresponding circuit units. Several circuit units are assembled into positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters.

[0005] Optionally, the required parameters include storage capacity setting parameters and function setting parameters.

[0006] Optionally, determining the target circuit architecture based on the requirement parameters includes: Extract the function setting parameters from the aforementioned requirement parameters; The target circuit architecture is determined based on the aforementioned functional setting parameters.

[0007] Optionally, the step of calling the corresponding circuit units from the compiler according to the requirement parameters includes: Extract storage capacity setting parameters from the aforementioned requirement parameters; The target number of circuit units required is determined based on the storage capacity setting parameters. The compiler calls the circuit units corresponding to the target circuit architecture and the target number of circuit units.

[0008] Optionally, the step of splicing the called circuit units to the positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters includes: Retrieve the netlist of the called circuit units; The netlists of the aforementioned circuit units are spliced ​​together to obtain a spliced ​​netlist; A storage circuit is generated based on the spliced ​​netlist to serve as the target storage circuit.

[0009] Optionally, the step of splicing the netlists of the plurality of circuit units to obtain a spliced ​​netlist includes: Standardize the naming conventions for the ports of the aforementioned circuit units; The names of the ports of the circuit units are modified according to the naming convention to ensure that the port names of each circuit unit are consistent and that a connection relationship is established between them.

[0010] Optionally, the step of splicing the called circuit units to the positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters includes: Obtain the layout of the several circuit units to be called; The layouts of the aforementioned circuit units are spliced ​​together to obtain a spliced ​​layout; A storage circuit is generated based on the splicing layout to serve as the target storage circuit.

[0011] Optionally, the step of splicing the layouts of the plurality of circuit units to obtain a spliced ​​layout includes: In response to the layout of the plurality of circuit units passing the design rule consistency check, the plurality of circuit units are placed at the positions corresponding to the target circuit architecture; The active layers and metal layers of adjacent circuit units are connected accordingly to obtain a spliced ​​layout.

[0012] This application provides a design device for a storage circuit, including a processor and a memory. The memory stores a design program, and when the design program is executed by the processor, it implements the steps of the automated design method for the storage circuit as described in any of the preceding claims.

[0013] This application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the automated design method for any of the above storage circuits.

[0014] As described above, the automated design method of this application includes: obtaining the requirement parameters input by the user in the compiler; importing multiple circuit units after disassembling a standard memory circuit into the compiler; determining the target circuit architecture based on the requirement parameters; calling corresponding circuit units from the compiler based on the requirement parameters; and concatenating the called circuit units to the positions corresponding to the target circuit architecture to obtain a target memory circuit that meets the requirement parameters. The user's requirement parameters and the multiple circuit units obtained from the disassembly are both input into the compiler, and the compiler determines the target circuit architecture, calls the corresponding circuit units, and executes the concatenation of the circuit units. That is, the entire design process of the target memory circuit can be automated in the compiler, reducing manual intervention, increasing overall efficiency, and eliminating the possibility of human error, thus ensuring the reliability of the entire circuit design. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating an automated design method for a storage circuit according to an embodiment of this application; Figure 2 This is a schematic diagram of splicing together a layout of circuit units according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an automated design device provided in an embodiment of this application. Detailed Implementation

[0016] To address the aforementioned problems in the prior art, this application provides an automated design method and apparatus for storage circuits, as well as a storage medium. These protection subjects are based on the same concept, and the principles for solving the problems are basically the same or similar. The implementation methods of each protection subject can be referred to mutually, and repeated details will not be elaborated.

[0017] In the solution of this application, the user's requirements and the multiple circuit units obtained by disassembly are input into the compiler. The compiler determines the target circuit architecture, calls the corresponding circuit units, and executes the splicing of the circuit units. That is, the entire design process of the target storage circuit can be completed automatically in the compiler, thereby reducing human intervention, improving overall efficiency, and eliminating the possibility of human error, thus ensuring the reliability of the entire circuit design.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0019] Figure 1 This is a flowchart illustrating an automated design method for a storage circuit provided in an embodiment of this application. The automated design method for the storage circuit can also be called a "method," "design method," or "automated design method," and is at least used for the design of storage circuits based on ROM (Read-Only Memory) compilers, i.e., at least for the automated design of ROM circuits. The execution entity for each step of this method can be a suitable storage circuit device, or a storage medium, processor, controller, etc., with storage circuit design and simulation verification functions.

[0020] See also Figure 1 As shown, the method includes at least the following steps S1 to S5: S1: Obtain the required parameters input by the user in the compiler.

[0021] In one example, the requirement parameters include storage capacity settings and function settings.

[0022] The storage capacity setting parameter is used to identify the storage capacity corresponding to the target storage circuit.

[0023] The function setting parameters can be regarded as basic configuration parameters, including but not limited to the data to be stored, the storage capacity to specify the number of address lines and data lines of the memory, the depth of the memory, the bit width of the memory, the power consumption and address-data pairs of the memory, the access parameters to specify port access and access speed, and timing parameters to ensure synchronization with the system clock. In practical scenarios, these functional setting parameters mainly fall into two categories: one is the memory capacity setting parameters, which at least include the settings for words, multiplexers (YMUX), and bits. These parameters determine the size of the memory array, the number of word lines, the number of multiplexers used (typically 4, 8, 16, or 32), and the number of bits for parallel input / output. The other category consists of parameters related to the functions included in the memory circuitry, such as whether a bit mask function is integrated, which controls whether a single bit can be written; whether a power-saving sleep mode is integrated, which allows the memory to enter a power-saving mode when it is not in a read / write state; whether an algorithm repair function is integrated, which can automatically repair the memory when data storage errors occur; and whether a write output control function is integrated, which controls whether the memory circuitry outputs synchronously during write operations.

[0024] The compiler can be a ROM compiler, a specialized compilation tool that converts source code written in high-level languages ​​or assembly languages ​​into ROM executable machine code. Its core functionality is similar to that of a general-purpose compiler but it is optimized for embedded systems; therefore, the input parameters must meet the format requirements of the ROM compiler. For example, the format of the input parameters can be .MIF or .COE. Users can manually input the input parameters by directly writing MIF or COE format files, or by batch generating data using tools such as Matlab and then exporting it as a file conforming to the format, i.e., executing the input through a preset tool generation method.

[0025] S2: Import the multiple circuit units after disassembling the standard memory circuit into the compiler.

[0026] The standard memory circuit of this application is a pre-designed, reusable memory circuit, which includes basic logic gates (such as AND gates, OR gates and NOT gates), flip-flops, registers and other circuit units. By combining these circuit units, complex memory circuits can be quickly constructed. For example, by reusing the standard memory circuit, a target memory circuit with functions such as data caching and signal synchronization can be realized.

[0027] It should be noted that the standard memory circuit of this application can be a circuit that has been simulated and verified, has been standardized and verified, has low complexity, and its type is not limited. For example, it can be a static memory cell composed of latches or flip-flops to keep the data in a constant power-on state, or a dynamic memory cell that relies on capacitor charge to store data and needs to be refreshed periodically to maintain data stability, or a register group composed of multiple flip-flops to temporarily store data or control signals.

[0028] The principle and process of disassembling the standard memory circuit mainly includes two parts: First, the memory array is decomposed, or the total memory single channel is disassembled. The total memory single channel can be disassembled into memory cell arrays (e.g., disassembled into 6T SRAM cells or 1T1C DRAM cells), word line or bit line driving circuits, row and column decoding circuits, and other sub-modules. These sub-modules are individual circuit units. Second, the disassembly is based on the separation of control logic, or the disassembly of the driving circuit. For example, independent read and write control circuits, timing generation circuits (e.g., clock trees), and state machines (Finite State Machines, FSMs) are disassembled, which also serve as individual circuit units. This disassembly can ensure that the functional boundaries of each disassembled circuit unit are clear.

[0029] Since each circuit unit is an independent sub-circuit with a corresponding function, in one example, this application can also perform simulation verification on each of the disassembled circuit units. For example, the circuit schematic of a circuit unit is first converted into a corresponding netlist, and then the layout and netlist of that circuit unit are checked for consistency. Specifically, this can include the following steps: First, a netlist is derived based on the layout, which can be called a layout netlist. For example, physical connection information is extracted from the layout using tools such as Calibre to generate a netlist containing devices, connections, and parasitic parameters, which is the layout netlist. This netlist is what is commonly referred to in the art as a logic netlist. Then, a preset algorithm is used to compare the logical equivalence of the layout netlist and the netlist. For example, signature partitioning or initial matching pair techniques are used to compare the device types, connection relationships, and attributes (e.g., resistance values, transistor sizes) of the two netlists for consistency checks, and preset tools are used to automatically mark inconsistencies, including but not limited to missing devices and misaligned connections. Optionally, a difference report is generated. If the logical equivalence is consistent, the consistency check is passed, i.e., simulation verification is passed. If the logical equivalence is inconsistent, the consistency check is failed, i.e., simulation verification is failed.

[0030] Given that the consistency check in this example essentially revolves around the LVS check, the step of comparing the logical equivalence of the layout netlist and the netlist using a preset algorithm may include at least one of the following two: 1. Using a preset algorithm to determine whether the devices corresponding to the layout netlist and the netlist match; 2. Using a preset algorithm to determine whether the node topology of the layout netlist and the netlist is consistent. Optionally, the preset algorithm is a graph isomorphism algorithm. The process and principle of the comparison based on this graph isomorphism algorithm can be found in existing technologies in this field, and will not be elaborated here.

[0031] Of course, other examples of this application can also be verified by simulation using traditional methods to analyze the individual circuit units obtained from disassembly. The process and principle can be found in the prior art.

[0032] S3: Determine the target circuit architecture based on the required parameters.

[0033] In the example where the requirement parameters include the aforementioned functional setting parameters, step S3 is implemented as follows: first, the functional setting parameters are extracted from the requirement parameters, and then the target circuit architecture is determined based on the functional setting parameters. Specifically, the functional setting parameters indicate which functions the target storage circuit to be designed needs, and the corresponding circuit units can be determined based on each function. For example, if the functional setting parameters determine that the target storage circuit, in addition to basic storage functions, also has read / write control functions and timing generation and control functions, then the determined circuit units (also called "functional circuit units") include read / write control circuits, timing generation circuits (e.g., clock trees), and state machines, and the target circuit architecture is the circuit architecture that includes these functional circuit units.

[0034] S4: Call the corresponding circuit units from the compiler according to the required parameters.

[0035] In the example where the requirement parameters include the aforementioned storage capacity setting parameters, step S4 is implemented as follows: first, the storage capacity setting parameters are extracted from the requirement parameters; then, the target number of circuit units required is determined based on the storage capacity setting parameters; and finally, the corresponding target circuit architecture and the target number of circuit units are called from the compiler. Specifically, the storage capacity setting parameters indicate how many storage units the target storage circuit to be designed includes. For example, if there are N storage units, then the target number of storage units is N. This target number can also help determine the target circuit architecture. For example, only circuit architectures that reach or exceed this target number meet the requirements. In other words, the called target circuit architecture contains at least N storage units.

[0036] S5: Connect the called circuit units to the positions corresponding to the target circuit architecture to obtain the target storage circuit that meets the required parameters.

[0037] In one example, the compiler can use netlist concatenation to concatenate the S5 steps, that is: S511. Obtain the netlist of the called circuit units; S512. The netlists of these circuit units are spliced ​​together to obtain a spliced ​​netlist; and S513. Generate a storage circuit based on the spliced ​​netlist as the target storage circuit.

[0038] In step S511, parasitic parameters are extracted based on the circuit schematics of each circuit unit, and parasitic netlists are generated based on the extracted parasitic parameters. For example, parasitic parameters such as parasitic resistance, capacitance, and coupling effects are extracted from the circuit schematics of each circuit unit based on the technology library file, generating several parasitic netlists containing parasitic effects, which can then be used as the netlists corresponding to each circuit unit. It should be understood that this application can also simulate and verify the generated parasitic netlists, for example, using parasitic netlists for timing and functional verification to check for key timing issues such as asynchronous logic and multi-clock cycle paths. Only parasitic netlists that have undergone simulation and verification can be used as the final netlists obtained.

[0039] In step S512, the compiler can first standardize the naming conventions of the ports of these circuit units, and then modify the names of the ports of these circuit units according to the naming conventions, so that the port names of each circuit unit are consistent and a connection relationship is established between them. Then, using EDA (Electronic Design Automation) tools such as Altium Designer that meet the requirements, the signal connection and hierarchical integration between each circuit unit can be automatically completed.

[0040] In step S513, register-transfer-level (RTL) code can be written first using hardware description languages ​​such as Verilog or VHDL to describe the data transfer logic between registers. Then, simulation tools (such as Modelsim or VCS) are used to verify the functional correctness of the RTL code, covering various test scenarios until high functional coverage is achieved. Next, the RTL code is converted into a gate-level netlist, and optimized using tools (such as Synopsys Design Compiler) in conjunction with technology libraries and design constraints (such as timing, area, and power consumption). Then, the dimensions, module locations, and I / O port layout are determined, providing a physical framework for routing. Components in the gate-level netlist are placed in designated areas on the silicon wafer, and metal interconnects are completed to meet signal integrity and power consumption requirements. Finally, operations such as DRC (Design Rule Check), ERC (Electrical Rule Checking), and LVS (Layout Versus Schematic) are performed. Figure 1After verification rules such as consistency checks, a design layout is generated. DRC checks parameters such as line width, spacing, and layer coverage to ensure the layout meets process rules. For example, minimum line width, minimum spacing, and interlayer distance must strictly comply with process capabilities to prevent open circuits, short circuits, and other problems. ERC checks for violations of electrical rules such as power / ground short circuits, floating nodes (floating points), open circuits, or broken circuits. For example, ERC identifies unconnected signal lines or redundant power networks to prevent functional failures after actual manufacturing. LVS checks whether circuit connections (such as nodes and device types) are consistent and verifies whether parameters such as transistor size and resistance / capacitance values ​​meet design intent. The simulated memory circuit that passes the above checks can be used as the target memory circuit.

[0041] In another example, the compiler can implement the concatenation of steps S5 through layout concatenation, namely: S521. Obtain the layout of the several circuit units to be called; S522, The layouts of the plurality of circuit units are spliced ​​together to obtain a spliced ​​layout; and S523. Generate a storage circuit based on the splicing layout to serve as the target storage circuit.

[0042] In step S522, the layout of these circuit units can first undergo a consistency check. If the consistency check passes, in response to the layout of these circuit units passing the design rule consistency check, these circuit units are placed in the positions corresponding to the target circuit architecture. Then, combined with... Figure 2 As shown, the active layers (AA layers) 11 and 12 of adjacent circuit units (i.e., circuit units 1 and 2 defined by the dashed lines in the figure) are connected accordingly, and the metal layers (21 and 22) are connected accordingly to obtain the tiled layout. In practical scenarios, active layers or metal layers located on the same layer can be directly connected, while active layers or metal layers located on different layers can be connected by drilling vias.

[0043] It should be noted that, in Figure 2 In the example, the metal layers 21 and 22 can be traces electrically connected to the corresponding Poly (polycrystalline silicon) layers 31 and 32, where black patches represent electrical connection points. The structures of circuit units 1 and 2 shown are merely illustrative and do not constitute a limitation on the scope of protection of this application.

[0044] The principle and process of generating the memory circuit based on the spliced ​​layout in step S523 can be found in existing technologies in this field for generating circuits based on the layout, and will not be described in detail here.

[0045] As described above, in the method of this application, the user's requirements and the multiple circuit units obtained by disassembly are all input into the compiler. The compiler determines the target circuit architecture, calls the corresponding circuit units, and executes the splicing of the circuit units. That is, the entire design process of the target storage circuit can be completed automatically in the compiler, reducing the degree of human intervention, improving overall efficiency, eliminating the possibility of human error, and ensuring the reliability of the entire circuit design.

[0046] This application embodiment also provides a storage medium storing an automated design program for a storage circuit, also known as an "automated design program" or "program". This program is essentially a computer program, and when executed by a processor, it implements the steps of an automated design method for a storage circuit as in any example.

[0047] The storage medium includes, but is not limited to, any one of read-only memory (ROM), random access memory (RAM), magnetic disk, and optical disk.

[0048] Since the program stored in the storage medium can execute the steps in the automated design method of the storage circuit of any embodiment provided in this application, the beneficial effects that the method of any of the foregoing embodiments can achieve can be realized, as detailed in the foregoing embodiments, which will not be repeated here.

[0049] This application also provides an automated design device (also known as an "automated design device for storage circuits") or chip, including a memory and a processor. The memory stores an automated design program. When the automated design program is executed by the processor, it can implement the corresponding steps of the automated design method for storage circuits of any of the foregoing embodiments. And / or, the automated design device or chip is provided with a storage medium as shown in the above example, and the processor loads the storage medium to execute the corresponding steps of the automated design method for storage circuits, thereby achieving the beneficial effects that the automated design method for storage circuits of the corresponding embodiments can achieve.

[0050] Figure 3 This is a schematic diagram of the structure of an automated design device provided in an embodiment of this application. For example... Figure 3 As shown, the automated design device 30 includes: The first input module 31 is used to obtain the required parameters input by the user in the compiler; The second input module 32 is used to import multiple circuit units after the standard memory circuit is disassembled into the compiler; The first processing module 331 is used to determine the target circuit architecture based on the required parameters; The second processing module 332 is used to call a number of corresponding circuit units from the compiler according to the requirement parameters; The splicing module 33 is used to splice several circuit units to the positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters.

[0051] It should be understood that the above-mentioned modules of the automated design equipment 30 can be represented as physical devices or virtual modules (i.e., logic modules) in actual scenarios. A certain module can be implemented by a single physical device or by two or more physical devices working together. Similarly, the function performed by a certain module can be implemented by a single physical device or by two or more physical devices working together.

[0052] Furthermore, the functions corresponding to each module can be implemented by the corresponding steps of the automated design method in any of the aforementioned embodiments. For example, the first processing module 331 determines the target circuit architecture by extracting functional setting parameters from the requirement parameters and determining the target circuit architecture based on the functional setting parameters. As another example, the second processing module 332 calls the corresponding circuit units by extracting storage capacity setting parameters from the requirement parameters, determining the target number of circuit units required based on the storage capacity setting parameters, and then calling the circuit units corresponding to the target circuit architecture and the target number from the compiler. Yet another example, one way the splicing module 33 obtains the target storage circuit is by first obtaining the netlists of the called circuit units, then splicing the netlists of the circuit units to obtain a spliced ​​netlist. For example, it unifies the naming conventions of the ports of the circuit units and modifies the names of the ports of the circuit units according to the naming conventions to ensure that the port names of each circuit unit are consistent and that they are connected to each other. Then, it generates a storage circuit based on the spliced ​​netlist as the target storage circuit. Another way for the splicing module 33 to splice the target storage circuit is as follows: First, obtain the layout of several circuit units to be called, and then splice the layout of the several circuit units to obtain a spliced ​​layout. For example, in response to the layout of the several circuit units passing the design rule consistency check, place the several circuit units in the position corresponding to the target circuit architecture, and connect the active layers and metal layers of adjacent circuit units accordingly to obtain the spliced ​​layout. Then, generate the storage circuit according to the spliced ​​layout to serve as the target storage circuit.

[0053] The above are only some embodiments of this application and do not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0054] The use of step designations such as S1 and S2 in this document is intended to more clearly and concisely describe the corresponding content and does not constitute a substantial restriction on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.

[0055] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. An automated design method for a storage circuit, characterized in that, The method includes: Obtain the required parameters input by the user in the compiler; The compiler imports multiple circuit units, which are the result of disassembling a standard memory circuit; Determine the target circuit architecture based on the aforementioned requirements parameters; Based on the required parameters, the compiler calls the corresponding circuit units. Several circuit units are assembled into positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters.

2. The method according to claim 1, characterized in that, The required parameters include storage capacity settings and function settings.

3. The method according to claim 2, characterized in that, Determining the target circuit architecture based on the required parameters includes: Extract the function setting parameters from the aforementioned requirement parameters; The target circuit architecture is determined based on the aforementioned functional setting parameters.

4. The method according to claim 3, characterized in that, The step of calling the corresponding circuit units from the compiler according to the requirement parameters includes: Extract storage capacity setting parameters from the aforementioned requirement parameters; The target number of circuit units required is determined based on the storage capacity setting parameters. The compiler calls the circuit units corresponding to the target circuit architecture and the target number of circuit units.

5. The method according to claim 1, characterized in that, The step of splicing the called circuit units to the positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters includes: Retrieve the netlist of the called circuit units; The netlists of the aforementioned circuit units are spliced ​​together to obtain a spliced ​​netlist; A storage circuit is generated based on the spliced ​​netlist to serve as the target storage circuit.

6. The method according to claim 5, characterized in that, The process of splicing the netlists of the plurality of circuit units to obtain a spliced ​​netlist includes: Standardize the naming conventions for the ports of the aforementioned circuit units; The names of the ports of the circuit units are modified according to the naming convention to ensure that the port names of each circuit unit are consistent and that a connection relationship is established between them.

7. The method according to claim 1, characterized in that, The step of splicing the called circuit units to the positions corresponding to the target circuit architecture to obtain a target storage circuit that meets the required parameters includes: Obtain the layout of the several circuit units to be called; The layouts of the aforementioned circuit units are spliced ​​together to obtain a spliced ​​layout; A storage circuit is generated based on the splicing layout to serve as the target storage circuit.

8. The method according to claim 7, characterized in that, The step of splicing the layouts of the plurality of circuit units to obtain a spliced ​​layout includes: In response to the layout of the plurality of circuit units passing the design rule consistency check, the plurality of circuit units are placed at the positions corresponding to the target circuit architecture; The active layers and metal layers of adjacent circuit units are connected accordingly to obtain a spliced ​​layout.

9. An automated design device for storage circuits, characterized in that, It includes a processor and a memory, the memory storing a design program, which, when executed by the processor, implements the steps of an automated design method for a storage circuit as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the automated design method for the storage circuit as described in any one of claims 1 to 8.

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