A layout optimization method and system for a semiconductor device

Abstract

The application provides a layout optimization method and system of a semiconductor device, and relates to the technical field of data processing.The method comprises the following steps: obtaining semiconductor device design data to be laid out; generating an initial layout according to the semiconductor device design data; calculating geometric environment parameters of the semiconductor device according to the initial layout; inputting the geometric environment parameters into a WPE model and an LOD model to output an electrical correction parameter set of the semiconductor device; performing performance statistical evaluation on the semiconductor device according to layout information of the initial layout to obtain a yield of the semiconductor device; constructing a semiconductor device layout optimization model according to the yield and the electrical correction parameter set; solving the semiconductor device layout optimization model to obtain an optimal layout strategy of the semiconductor device; and executing the optimal layout strategy.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method and system for optimizing the layout of semiconductor devices. Background Technology

[0002] Semiconductor device layout optimization refers to the systematic planning of the spatial position, orientation, and relative arrangement of devices during the chip layout design process, based on the electrical connection relationships, geometric characteristics, and manufacturing process requirements, in order to obtain the optimal layout that meets the functional, electrical performance, and manufacturability requirements.

[0003] As semiconductor processes continue to shrink to nanometer-level nodes, the geometric proximity effect between devices is significantly enhanced, making it difficult for experience-based layout methods to guarantee electrical consistency and manufacturing yield. At the same time, the continuous expansion of chip size and the dramatic increase in layout complexity make manual adjustments extremely inefficient and prone to uncontrollable process deviations.

[0004] However, the existing semiconductor device layout process often relies on manual experience or local heuristic adjustments, lacking accurate modeling of process proximity effects. The layout results are prone to problems such as inconsistent device electrical characteristics, uncontrollable performance deviations, and sensitivity to process fluctuations, ultimately leading to insufficient circuit reliability and difficulty in improving manufacturing yield. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a semiconductor device layout optimization method, which can solve the technical problems of the prior art where the semiconductor device layout process often relies on manual experience or local heuristic adjustment, lacks accurate modeling of process proximity effects, and the layout results are prone to problems such as inconsistent device electrical characteristics, uncontrollable performance deviation, and sensitivity to process fluctuations, ultimately leading to insufficient circuit reliability and difficulty in improving manufacturing yield.

[0006] A first aspect of this invention provides a method for optimizing the layout of a semiconductor device, comprising:

[0007] S1: Obtain the semiconductor device design data to be laid out;

[0008] S2: Generate an initial layout based on the semiconductor device design data;

[0009] S3: Calculate the geometric environment parameters of the semiconductor device based on the initial layout;

[0010] S4: Input the geometric environment parameters into the WPE model and LOD model, and output the set of electrical correction parameters for the semiconductor device;

[0011] S5: Based on the layout information of the initial layout, perform a statistical performance evaluation on the semiconductor device to obtain the yield of the semiconductor device;

[0012] S6: Construct a semiconductor device layout optimization model based on the yield and the set of electrical correction parameters;

[0013] S7: Solve the semiconductor device layout optimization model to obtain the optimal layout strategy for the semiconductor device;

[0014] S8: Execute the optimal layout strategy.

[0015] Optionally, the semiconductor device design data specifically includes: the netlist of the semiconductor circuit to be laid out, device parameters, layout constraints, and layout design rules.

[0016] Optionally, S2 specifically includes:

[0017] S201: Based on the semiconductor device design data, calculate the placement priority of the semiconductor device, and sort the semiconductor devices in descending order according to the placement priority;

[0018] S202: Based on the sorting results, the semiconductor devices are divided into clusters according to the clustering cost to generate an initial clustering structure, wherein the initial clustering structure includes multiple clusters;

[0019] S203: Determine the regional center position of each of the initial cluster structures based on the cluster area and the number of semiconductor devices within the cluster;

[0020] S204: Generate the initial coordinates of the semiconductor device based on the center position of the region and the placement priority;

[0021] S205: Based on the consistency of current direction, the initial coordinates of the semiconductor device are adjusted for orientation to obtain an initial layout that satisfies the layout design rules.

[0022] Optionally, the geometric environment parameters specifically include: well-side scattering integral, STI stress geometry, and LOD stress difference component.

[0023] Optionally, the set of electrical correction parameters specifically includes: semiconductor device threshold voltage, WPE correction body effect coefficient, WPE correction effective carrier mobility, LOD correction effective carrier mobility, LOD correction carrier saturation velocity, and LOD correction threshold voltage.

[0024] S4 specifically includes:

[0025] S401: Input the well-side scattering integral into the WPE model to obtain the threshold voltage of the semiconductor device, the corrected bulk effect coefficient, and the corrected effective carrier mobility.

[0026] S402: Input the STI stress geometry and LOD stress difference components into the LOD model to obtain the LOD-corrected effective carrier mobility, the LOD-corrected carrier saturation velocity, and the LOD-corrected threshold voltage.

[0027] Optionally, S5 specifically includes:

[0028] S501: Map the coordinates of the semiconductor devices in the initial layout to the wafer coordinate system to obtain a wafer coordinate set;

[0029] S502: Based on the wafer coordinate set, extract the width deviation value and thickness deviation value from the wafer width deviation field and the wafer thickness deviation field, respectively.

[0030] S503: The width deviation value and the thickness deviation value are weighted to obtain the equivalent geometric deviation of the semiconductor device;

[0031] S504: Based on the equivalent geometric deviation, construct a semiconductor device perturbation model, and obtain perturbation parameters based on the semiconductor device perturbation model;

[0032] S505: Construct a circuit transmission model based on the disturbance parameters;

[0033] S506: Extract the performance indicators of the semiconductor device based on the circuit transmission model;

[0034] S507: Determine the yield rate based on the performance indicators.

[0035] Optionally, S6 specifically includes:

[0036] S601: Calculate the WPE deviation index and LOD deviation index based on the electrical correction parameter set;

[0037] S602: Based on the yield, the WPE deviation index, and the LOD deviation index, construct an objective function with the goal of minimizing the semiconductor device layout cost;

[0038] S603: Set constraints;

[0039] S604: Combine the constraints and the objective function to construct the semiconductor device layout optimization model.

[0040] Optionally, S7 specifically includes:

[0041] The whale optimization algorithm is used to solve the semiconductor device layout optimization model to obtain the optimal layout strategy for the semiconductor device.

[0042] A second aspect of this invention provides a layout optimization system for a semiconductor device, comprising: a processor and a memory;

[0043] The memory stores programs or instructions that can run on the processor, which, when executed by the processor, implement the steps of the layout optimization method for the semiconductor device as described in the first aspect.

[0044] A third aspect of the present invention provides a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the semiconductor device layout optimization method as described in the first aspect.

[0045] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0046] In this embodiment of the invention, by acquiring device design data and constructing an initial layout, the layout process has an accurate structural starting point. Based on the initial layout, geometric environment parameters are extracted and input into the WPE and LOD process models to obtain electrical correction values. This quantifies the electrical differences between devices caused by process proximity effects. Combined with layout information, performance statistics and yield assessments are conducted, providing evaluation indicators that truly reflect the impact of process fluctuations for the optimization model. Finally, the layout optimization model is constructed and solved using yield and electrical correction parameters, achieving a global improvement in the layout results. This embodiment of the invention can simultaneously coordinate geometric structure, electrical performance, and process manufacturability during the layout stage, achieving a semiconductor device layout strategy with higher electrical consistency, stronger process robustness, and better yield performance. Attached Figure Description

[0047] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0048] Figure 1 This is a schematic flowchart of a semiconductor device layout optimization method provided in an embodiment of the present invention.

[0049] Figure 2 This is a schematic diagram of the structure of a semiconductor device layout optimization system provided in an embodiment of the present invention. Detailed Implementation

[0050] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0051] The layout optimization method for semiconductor devices provided by the present invention will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0052] Reference manual attached Figure 1 The diagram shows a schematic flowchart of a semiconductor device layout optimization method provided by an embodiment of the present invention.

[0053] This invention provides a method for optimizing the layout of a semiconductor device, which may include the following steps:

[0054] S1: Obtain the semiconductor device design data to be laid out.

[0055] In one possible implementation, the semiconductor device design data specifically includes: the netlist of the circuit to be laid out, device parameters, layout constraints, and layout design rules.

[0056] The layout constraints include symmetry constraints, self-symmetry constraints, current constraints, and critical matching pair constraints.

[0057] The netlist describes the electrical connections between all semiconductor devices in the circuit to be laid out. It consists of device nodes, port names, and wire connection information, defining the electrical ports (e.g., source, drain, gate) of each device, the interconnection network between devices, and the circuit topology. The netlist is the fundamental data for placement algorithms to calculate connectivity, coupling relationships, and current link structures. Device parameters describe the initial geometric and structural attributes of each semiconductor device to be laid out. These are typically provided by a process library (PDK) or design documents and include the gate length, gate width, number of fingers, finger pitch, device type, and diffusion region type and area. Placement constraints define the functional requirements and geometric rules that semiconductor devices must meet during physical placement, including symmetry constraints, self-symmetry constraints, current direction constraints, and critical matching pair constraints. Layout design rules are geometric constraints provided by the manufacturing process (Foundry PDK) to ensure that the layout is manufacturable. These rules include minimum linewidth, minimum pitch rules, manufacturing limitations for gate, polysilicon, and metal layers, boundary rules for active regions (OD) and N-well / P-well, STI (shallow trench isolation) shape requirements, diffusion region spacing, gate cap requirements, interlayer spacing, and overlap requirements.

[0058] S2: Generate the initial layout based on the semiconductor device design data.

[0059] In this embodiment of the invention, by generating an initial layout, a reasonable preset of the spatial distribution of devices can be achieved in the early stage of the layout process, so that the subsequent extraction of geometric environment parameters, electrical correction calculation and layout optimization solution have a stable starting structure, which can significantly reduce the optimization search space, reduce the number of layout iterations, and improve the overall layout generation efficiency and convergence.

[0060] In one possible implementation, S2 specifically includes:

[0061] S201: Based on semiconductor device design data, calculate the placement priority of semiconductor devices and sort them in descending order according to the placement priority.

[0062] The specific formula for calculating placement priority is as follows:

[0063]

[0064] Among them, P i This indicates the placement priority of the i-th semiconductor device. The weights representing the connectivity of semiconductor devices. This represents the connectivity of the i-th semiconductor device in the circuit netlist. This represents the i-th semiconductor device. The weights representing the geometric area of ​​a semiconductor device. This represents the geometric gate width of the i-th semiconductor device. This represents the geometric gate length of the i-th semiconductor device. The weights representing the electrical coupling strength of semiconductor devices. Let represent the set of adjacent devices that are coupled to semiconductor device i, and let e represent an exponential function. This represents the electrical coupling strength between the i-th semiconductor device and the j-th semiconductor device. This represents a scale parameter that controls the rate of decrease in coupling strength.

[0065] S202: Based on the sorting results, the semiconductor devices are divided into clusters according to the clustering cost to generate an initial cluster structure, wherein the initial cluster structure includes multiple clusters.

[0066] Specifically, starting from the beginning of the sorting results, semiconductor devices are added to clusters sequentially. When the clustering cost of a newly added semiconductor device exceeds a threshold with existing semiconductor devices in a cluster, it is assigned to that cluster; otherwise, a new cluster is created. After all semiconductor devices in the sorting results have been clustered, the area of ​​the device set within each cluster is calculated and the structure is reorganized. Finally, an initial cluster structure consisting of multiple clusters is output. Assume that the r-th cluster formed during the clustering process is... Clustering The number of existing devices is Then semiconductor devices Joining a cluster The clustering cost is specifically as follows: .

[0067] S203: Determine the regional center location of each cluster based on the cluster area and the number of semiconductor devices within each initial cluster structure.

[0068] Specifically, this invention calculates the area value and the number of devices within each cluster, calculates the layout weight of each cluster according to a preset area-quantity weighting rule, then divides the entire layout plane into several corresponding target areas according to the weight ratio, so that clusters with larger areas or more devices are allocated to a wider space, and finally calculates the regional center position of the cluster within each target area (e.g., taking the geometric center or weighted center of the area), and uses the coordinates as the spatial reference point of the cluster.

[0069] S204: Generate the initial coordinates of the semiconductor device based on the region center location and placement priority.

[0070] In this embodiment of the invention, after determining the regional center position of each cluster, the cluster regional center is used as the layout reference, and initial coordinates are assigned to the devices sequentially according to the placement priority of the semiconductor devices within the cluster. Among them, higher priority devices are arranged closer to the regional center, while lower priority devices are arranged step by step in the order from the inside to the outside or from the center to the periphery, thereby forming a compact and hierarchical initial spatial distribution of devices.

[0071] For example, suppose clustering The regional center location is The cluster contains four semiconductor devices. Its placement priority satisfies Therefore, when generating the initial coordinates, the device with the highest priority can be selected first. Place it in the location closest to the center of the area, for example, place it directly in Then, in order of priority from highest to lowest, they are: Assign adjacent grid points around the center of the region, such as placing them separately. , , Predefined grid coordinates are used to form an initial spatial distribution where "higher priority areas are closer to the center, and lower priority areas gradually expand outwards."

[0072] S205: Based on the consistency of current direction, the initial coordinates of the semiconductor device are adjusted to obtain an initial layout that meets the design rules.

[0073] The final orientation is determined as follows:

[0074]

[0075]

[0076] in, This represents the orientation cost function. and All represent weights. Represents the square of the L2 norm. This indicates that the i-th semiconductor device is in a given orientation The current direction is a unit vector. Indicates the orientation of the i-th semiconductor device. 0 indicates no flipping. 1 indicates flipping. Represents a symbolic function. This represents the unit vector indicating the direction of the target reference current within the layout area. This indicates an indicator function that takes the value 1 when the condition within the parentheses is true, and 0 otherwise. It is used to apply a penalty when the current orientation does not match the preferred orientation. This indicates the preset preferred orientation of the i-th semiconductor device. argmin represents the final orientation of semiconductor device i, and argmin represents maximization.

[0077] In this embodiment of the invention, by adjusting the orientation of the initial coordinates based on the consistency of the current direction, the actual flow direction of the current link can be unified without changing the relative position of the devices. This enables devices on the same signal path to have consistent source and drain orientations and current reference directions, thereby reducing orientation mismatch, parasitic differences and link discontinuities in the layout, improving electrical consistency between devices and meeting key design rule requirements.

[0078] Specifically, for each semiconductor device, without changing its geometric coordinates, it is assumed to be in two orientation states: "flipped" and "not flipped." The deviation cost between the current flow vector and the target current reference direction is calculated for each state, while simultaneously considering the deviation penalty relative to a preset preferred orientation. These two parts are then weighted and summed to obtain the total orientation cost for the device in a given flipped state. Subsequently, the state with the minimum orientation cost between the "flipped" and "not flipped" candidate states is selected as the final orientation of the device. While keeping the generated initial coordinates unchanged, the orientation information of each device is updated to make the current direction of devices on the same current link as consistent as possible, so as to obtain an initial layout in which the current direction consistency meets the design rules.

[0079] S3: Calculate the geometric environment parameters of the semiconductor device based on the initial layout.

[0080] In one possible implementation, the geometric environment parameters specifically include: well-side scattering integral, STI stress geometry, and LOD stress difference component.

[0081] Among them, the Scattering Contribution from Well Edge (SCA) represents the influence of the relative geometric distance between the active region (OD) and the N-well / P-well boundary on electrical characteristics such as threshold voltage and bulk effect, and is a core input quantity for WPE (Well Proximity Effect). The STI Stress Geometric Quantity is defined as a function of the geometric distance between the source and drain diffusion regions and the shallow trench isolation (STI) boundary, used to characterize the carrier mobility change and stress coupling effect caused by STI. The LOD Stress Differential Quantity (Sdiff) represents the effective geometric reciprocal difference between the source and drain in the diffusion region direction, reflecting the left-right asymmetric stress effect caused by LOD (Length of Diffusion), and is an important input parameter for correcting threshold voltage and mobility.

[0082] Specifically, based on the initial layout generated by the aforementioned steps, the initial layout is parsed through the layout database to extract the geometric positional relationship of each semiconductor device, including the device gate center coordinates, gate length and gate width, number of fingers and finger spacing, device orientation, N-well / P-well boundary position, STI (shallow trench isolation) boundary shape, and active region (OD) contour.

[0083] The specific formula for calculating the integral of trap-side scattering is as follows:

[0084]

[0085] Where SCA represents the well-side scattering integral. This represents the geometric gate width of the i-th semiconductor device. This represents the geometric gate length of the i-th semiconductor device. Indicates the process reference distance. This represents the projection length of the k-th projection segment of the well boundary along the width direction of the semiconductor device. This represents the projection width of the k-th projection segment of the well boundary along the length of the semiconductor device. denoted by , where represents the effective distance of the k-th segment between the well boundary and the semiconductor device, n represents the number of projection segments of the well boundary in the width direction of the semiconductor device, and m represents the number of projection segments of the well boundary in the length direction of the device.

[0086] Let the distance from the source / drain diffusion regions on both sides of the device to the STI boundary be... The specific STI stress geometry is as follows:

[0087]

[0088] in, This represents the percentage change in mobility of the p-th finger of a semiconductor device under the LOD (Length of Diffusion) effect. Represents the basic sensitivity coefficient of mobility. Represents the stress coupling coefficient. This indicates the distance from the p-th source-end diffusion region to the STI boundary. This represents the distance from the p-th leak end diffusion region to the STI boundary.

[0089] The LOD stress difference component is specifically:

[0090]

[0091] in, Represents the LOD stress difference component. This represents the weighted geometric term on the left side of the diffusion region at the source end of the semiconductor device. This represents the geometric reciprocal term to the right of the diffuse region at the drain end of the semiconductor device. This represents the reciprocal distance from the source-end diffusion region to the STI boundary under the reference semiconductor device distribution structure. This represents the reciprocal distance from the drain diffusion region of the reference semiconductor device distribution structure to the STI boundary.

[0092] When the semiconductor device is a single finger , When semiconductor devices are single-finger and The exponent is only 1, so SA and SB are used instead. When semiconductor devices are multi-exponential... = , The calculation formula is as follows:

[0093]

[0094] in, This refers to the average geometric reciprocal term in the source direction of a semiconductor device. An index representing semiconductors. This represents the diffusion region spacing between the p-th finger and its adjacent finger in a semiconductor device.

[0095] The average reciprocal distance on the right side of the multi-finger structure Similar to the definition of the left-hand average reciprocal distance of a multi-finger structure, only... Replace with .

[0096] S4: Input the geometric environment parameters into the WPE model and LOD model, and output the set of electrical correction parameters for the semiconductor device.

[0097] The WPE (Well Proximity Effect Model) describes the impact of variations in the distance between the device and the N-well or P-well boundary on its electrical parameters such as threshold voltage, bulk effect coefficient, and mobility. The LOD (Length of Diffusion Model) describes the impact of the difference in diffusion region length between the device's source and drain ends, as well as variations in the distance from the STI, on mobility, saturation velocity, and threshold voltage.

[0098] In this embodiment of the invention, by inputting geometric environment parameters into the WPE model and LOD model and outputting the corresponding set of electrical correction parameters, the impact of the layout geometry on key electrical performances such as device threshold voltage, mobility and saturation speed can be accurately quantified during the layout stage, thereby significantly improving the electrical accuracy of the layout strategy.

[0099] In one possible implementation, the electrical correction parameter set specifically includes: corrected semiconductor device threshold voltage, WPE corrected bulk effect coefficient, WPE corrected effective carrier mobility, LOD corrected effective carrier mobility, LOD corrected carrier saturation velocity, and LOD corrected threshold voltage.

[0100] The threshold voltage of a semiconductor device refers to the minimum gate voltage required for the formation of an inversion layer in the channel and the device to begin conduction. Factors affecting the threshold voltage include the doping concentration in the acceptor region, gate oxide thickness, gate length shortening effect, and layout geometry. The WPE (Wide-Purpose Optimization) correction coefficient describes the impact of source-to-drain voltage variations on the threshold voltage. The WPE-corrected effective carrier mobility is the effective carrier mobility obtained by correcting the original mobility based on the geometric distance between the device and the N-well / P-well boundaries under the well-side effect. The LOD (Low-Drain Optimization) correction effective carrier mobility is the corrected mobility obtained after changes in channel mobility due to the difference in source / drain diffusion region length (LOD effect) and STI (Stress-Induced Tension) stress. The LOD-corrected carrier saturation velocity is the corrected saturation velocity of carriers under a high electric field after being affected by the coupling effect of LOD (Low-Drain Optimization) and STI stress. The LOD-corrected threshold voltage is the correction value of the device threshold voltage caused by changes in the bulk electric field and mechanical stress near the channel due to diffusion region length asymmetry, STI stress differences, etc.

[0101] In one possible implementation, S4 specifically includes:

[0102] S401: Input the well-side scattering integral into the WPE model to obtain the corrected semiconductor device threshold voltage, corrected bulk effect coefficient, and corrected effective carrier mobility:

[0103]

[0104]

[0105]

[0106] in, This represents the threshold voltage of the semiconductor device after correction for the well-side nearest neighbor (WPE) effect. This represents the initial threshold voltage of a semiconductor device. This represents the sensitivity coefficient of WPE to threshold voltage offset. This represents the volume effect coefficient after WPE correction. Represents the original body effect coefficient. This represents the sensitivity coefficient of WPE to the shift in the volume effect coefficient. This represents the effective carrier mobility after WPE correction. Represents the original effective carrier mobility. This represents the sensitivity coefficient of WPE to mobility shift.

[0107] S402: Input the STI stress geometry and LOD stress difference components into the LOD model to obtain the LOD-corrected effective carrier mobility, LOD-corrected carrier saturation velocity, and LOD-corrected threshold voltage.

[0108]

[0109]

[0110]

[0111] in, This represents the effective carrier mobility after LOD correction. This represents the STI stress geometry under the actual structure of a semiconductor device. This represents the STI stress geometry under the reference structure of the semiconductor device. This represents the carrier saturation velocity after LOD correction. This represents the initial carrier saturation velocity. The sensitivity coefficient representing the effect of STI stress on saturation velocity. This represents the threshold voltage after LOD correction. This represents the threshold voltage stress sensitivity coefficient.

[0112] S5: Based on the layout information of the initial layout, perform statistical performance evaluation on the semiconductor device to obtain the yield of the semiconductor device.

[0113] Yield refers to the proportion of samples that meet all performance specifications under a given number of process samples, and is used to evaluate the manufacturability and performance consistency of devices or circuits under manufacturing deviations.

[0114] In this embodiment of the invention, by performing performance statistical evaluation based on the initial layout, wafer process deviations, geometric deviations and electrical behavior can be coupled together to quantitatively calculate the performance changes of devices under different manufacturing scenarios, and the yield is used as the evaluation index, thereby significantly improving the reliability and process robustness of the layout strategy.

[0115] In one possible implementation, S5 specifically includes:

[0116] S501: Map the coordinates of the semiconductor devices in the initial layout to the wafer coordinate system to obtain the wafer coordinate set.

[0117] The wafer coordinate system refers to an absolute two-dimensional coordinate system established with the entire wafer as a reference. It is used to describe the actual geographical location of devices on the wafer. The wafer coordinate system usually uses the wafer center as the reference point and includes global positioning information to correlate wafer process deviation fields (width deviation field, thickness deviation field, etc.). A wafer is a highly polished thin sheet of semiconductor material with a specific thickness and diameter, usually made of high-purity single-crystal silicon, and is the basic carrier for manufacturing all integrated circuit (IC) devices.

[0118] In this embodiment of the invention, by mapping the device coordinates of the initial layout to the wafer coordinate system, the positional association of the devices in the wafer physical space can be accurately established during the layout stage, so that each device can correspond to the specific deviation values ​​of the wafer width deviation field and thickness deviation field. This enables subsequent performance statistical calculations to have spatial resolution consistent with the real manufacturing environment, thereby improving the accuracy of process deviation assessment and yield prediction.

[0119] S502: Based on the wafer coordinate set, extract the width deviation value and thickness deviation value from the wafer width deviation field and the wafer thickness deviation field, respectively.

[0120] Specifically, the wafer width deviation field is a two-dimensional width deviation distribution function Δw(x,y) defined in the wafer plane coordinate domain, used to represent the deviation of the waveguide width at wafer position (x,y) from the designed width. The wafer thickness deviation field is a two-dimensional thickness deviation distribution function Δt(x,y) defined in the wafer plane coordinate domain, used to represent the deviation of the material thickness at wafer position (x,y) from the target thickness. Based on the wafer coordinate set, each wafer coordinate is used as the input to the deviation field, and the corresponding width deviation value and thickness deviation value are calculated respectively, specifically Δw. i =Δw(p k ), Δt i=Δt(p k ).

[0121] S503: Weight the width deviation value and the thickness deviation value to obtain the equivalent geometric deviation of the semiconductor device.

[0122] S504: Construct a device disturbance model based on the equivalent geometric deviation, and obtain the disturbance parameters based on the device disturbance model.

[0123] In this embodiment of the invention, the equivalent geometric deviation is substituted as an input variable into the geometric sensitivity expression of a pre-established device compact model C(w,t). The device compact model characterizes the mapping relationship between device compact parameters (e.g., effective refractive index, group refractive index, or coupling coefficient) and the nominal operating point of the waveguide width and material thickness, and includes the derivatives and second-order rates of change of the compact parameters with respect to width and thickness. By performing a second-order Taylor expansion of the compact model parameters at the nominal width and thickness, a device perturbation model with width and thickness deviations as variables can be obtained. Substituting the equivalent geometric deviation into the perturbation model, the offset of the compact model parameters under process deviations can be obtained. This offset serves as the device perturbation parameter, characterizing the actual physical properties of the device under process perturbation conditions. It can include multiple device physical parameters such as effective refractive index, group refractive index, coupling coefficient, phase shift coefficient, loss coefficient, effective length, and propagation constant, and is expressed by the local width deviation Δw(p) k ) and thickness deviation Δt(p k By substituting into the perturbation model, the perturbation amounts of each of the above compact parameters under the influence of process deviations can be obtained, thereby obtaining the equivalent physical characteristics of the device under actual manufacturing conditions.

[0124] The device disturbance model is as follows:

[0125]

[0126] in, This represents the position coordinates of the k-th discrete sampling point of the semiconductor device in the wafer coordinate system. Indicates sampling point The disturbance parameters at that location, Represents the parameters of the ideal model. Indicates sampling point Width deviation at that point Indicates sampling point The thickness deviation at that point, where C represents the compact model parameter. This represents the first-order sensitivity of the compact model parameter C to the waveguide width w. This represents the first-order sensitivity of the compact model parameter C to the waveguide thickness t. This represents the second-order rate of change of the compact model parameter C with respect to the waveguide width w. This represents the second-order rate of change of the compact model parameter C with respect to the waveguide thickness t. This represents the second-order cross sensitivity of the compact model parameter C to the waveguide width w and waveguide thickness t.

[0127] It should be noted that, suppose semiconductor device i contains N sampling points, and the local perturbation parameters at each sampling point are as follows: Then, by performing length-weighted averaging or uniform-weighted averaging on these local parameters, the equivalent compact model parameters at the device level can be obtained. This aggregation process can integrate local geometric deviations and model parameter perturbations distributed along the device into a single equivalent parameter, which can be used to characterize the overall changes of key parameters of the device, such as effective refractive index, group refractive index, or coupling coefficient, under process deviations.

[0128] S505: Construct a circuit transmission model based on the disturbance parameters:

[0129]

[0130] Where H() represents the circuit transmission model, Indicates wavelength. This represents an example of process deviation, used to characterize the combined effects of width deviation field, thickness deviation field, and random changes in circuit position on device parameters during manufacturing. F() represents the computational operator of the circuit-level frequency domain solver. In the process sample Under the given conditions, the equivalent compact model parameter vector of the i-th semiconductor device, N d This indicates the total number of semiconductor devices.

[0131] Specifically, after obtaining the perturbation parameters of each device, the perturbation parameters are input into the circuit-level frequency domain solver to construct the circuit transfer function with wavelength as the independent variable. The circuit transfer function is used to characterize the circuit in a given process sample. Under these conditions, the complex amplitude transmission characteristics from the input port to the target output port.

[0132] S506: Extract the performance indicators of semiconductor devices based on the circuit transmission model.

[0133] Through the The amplitude and phase responses are scanned and calculated to extract performance indicators for evaluating the device's operating characteristics, such as by obtaining... The peak wavelength is obtained by determining the peak position, and the insertion loss is obtained by the difference between the maximum transmission value and the reference transmission value. All of the above performance indicators are calculated based on the circuit transfer function and are used to quantitatively characterize the optical performance of the device under current process conditions.

[0134] S507: Determine the yield rate based on performance indicators.

[0135] Specifically, after obtaining the performance indicators corresponding to each semiconductor device, the performance indicators are compared with the pre-set design specifications item by item to determine whether the device under the process sample meets all performance requirements. By statistically analyzing the performance indicators of multiple semiconductor devices, the number of samples that meet the design specifications is recorded, and the proportion of this number to the total number of samples is taken as the yield of the semiconductor device.

[0136] S6: Construct a semiconductor device layout optimization model based on the yield and electrical correction parameter set.

[0137] In this embodiment of the invention, by constructing a semiconductor device layout optimization model based on yield indicators and electrical correction parameter sets, process deviations, geometric environment effects and electrical performance drift can be incorporated into the optimization objective, so that the layout decision not only meets geometric constraints, but also significantly improves the manufacturability, performance stability and overall design quality of semiconductor device layout.

[0138] In one possible implementation, S6 specifically includes:

[0139] S601: Calculate the WPE deviation index and LOD deviation index based on the electrical correction parameter set:

[0140]

[0141]

[0142] in, This indicates the WPE deviation index. This represents the LOD deviation index, where i represents the index of the semiconductor device. This represents the threshold voltage of semiconductor device i after correction for the well-side nearest neighbor (WPE) effect. This represents the volume effect coefficient of semiconductor device i after WPE correction. This represents the effective carrier mobility of semiconductor device i after LOD correction. This represents the initial carrier saturation velocity of semiconductor device i. This represents the threshold voltage of semiconductor device i after LOD correction.

[0143] S602: Based on yield, WPE deviation index and LOD deviation index, construct an objective function with the goal of minimizing semiconductor device layout cost.

[0144] It should be noted that if the yield is 1 - Yield, then the yield loss is 1 - Yield. The specific semiconductor device layout cost is the weighted sum of the yield loss, WPE deviation index, and LOD deviation index.

[0145] S603: Set constraints.

[0146] The constraints specifically include: minimum spacing constraint and yield lower limit constraint.

[0147] Minimum spacing constraints mean that the geometric distance between any two semiconductor devices must meet the minimum spacing requirements specified in the process design rules, including gate spacing, diffusion region (OD) spacing, and STI region spacing. When the device coordinates are adjusted, the distance between adjacent boundaries must not be less than the minimum allowable DRC value of the corresponding process node to avoid manufacturing short circuits or process failures.

[0148] The yield lower limit constraint requires that the device yield obtained statistically from multiple sets of process deviation samples must not be lower than the preset target yield threshold (e.g., 90%), otherwise the layout solution is considered infeasible.

[0149] S604: Combine objective functions to construct a semiconductor device layout optimization model.

[0150] S7: Solve the semiconductor device layout optimization model to obtain the optimal layout strategy for semiconductor devices.

[0151] In this embodiment of the invention, by solving the constructed semiconductor device layout optimization model, the globally optimal or near-optimal layout strategy can be automatically found among various geometric constraints, electrical deviation indicators and yield requirements. This makes the layout result no longer dependent on human experience, but based on quantifiable process-device coupling relationship for systematic optimization, thereby significantly improving the electrical consistency, process robustness and overall design performance of the layout scheme.

[0152] In one possible implementation, S7 specifically refers to:

[0153] The whale optimization algorithm is used to solve the semiconductor device layout optimization model and obtain the optimal layout strategy for semiconductor devices.

[0154] Specifically, the whale optimization algorithm is used to solve the constructed semiconductor device layout optimization model. This involves initializing a whale population composed of multiple candidate layouts, using the layout cost function (i.e., the objective function) as the fitness index, and employing three update mechanisms—surround prey, spiral update, and random search—of the whale optimization algorithm to perform an iterative global search on layout variables such as device coordinates, orientation, and cluster positions. In each iteration, the search range is dynamically adjusted based on the current optimal solution, gradually approaching the globally optimal layout. This allows the algorithm to effectively escape local optima and ultimately obtain the optimal layout strategy that satisfies electrical performance requirements, process constraints, and yield optimization goals.

[0155] S8: Execute the optimal layout strategy.

[0156] Reference manual attached Figure 2 The diagram shows a schematic of the structure of a semiconductor device layout optimization system provided in an embodiment of the present invention.

[0157] This invention provides a semiconductor device layout optimization system 20, including: a processor 201 and a memory 202;

[0158] The memory 202 stores programs or instructions that can run on the processor 201. When the program or instructions are executed by the processor 201, they implement the steps of the above-described semiconductor device layout optimization method and achieve the same technical effect. To avoid repetition, the present invention will not elaborate further.

[0159] It should be understood that the processor 201 in this embodiment of the invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0160] It should also be understood that the memory 202 in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM).

[0161] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0162] It should be understood that, in various embodiments of the present invention, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0163] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0164] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0165] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0166] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0167] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0168] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0169] This invention provides a readable storage medium comprising: storing a program or instructions on the readable storage medium, wherein when the program or instructions are executed by a processor, the program or instructions implement the steps of the above-described semiconductor device layout optimization method and achieve the same technical effect. To avoid repetition, this invention will not elaborate further.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A layout optimization method of a semiconductor device, characterized by, include: S1: Obtain the semiconductor device design data to be laid out; S2: Generate an initial layout based on the semiconductor device design data; S3: Calculate the geometric environment parameters of the semiconductor device based on the initial layout; S4: Input the geometric environment parameters into the WPE model and LOD model, and output the set of electrical correction parameters for the semiconductor device; S5: Based on the layout information of the initial layout, perform statistical performance evaluation on the semiconductor device to obtain the yield of the semiconductor device; Specifically, S5 includes: S501: Map the coordinates of the semiconductor devices in the initial layout to the wafer coordinate system to obtain a wafer coordinate set; S502: Based on the wafer coordinate set, extract the width deviation value and the thickness deviation value from the wafer width deviation field and the wafer thickness deviation field, respectively. S503: The width deviation value and the thickness deviation value are weighted to obtain the equivalent geometric deviation of the semiconductor device; S504: Based on the equivalent geometric deviation, construct a semiconductor device perturbation model, and obtain perturbation parameters based on the semiconductor device perturbation model; S505: Construct a circuit transmission model based on the disturbance parameters; S506: Extract the performance indicators of the semiconductor device based on the circuit transmission model; S507: Determine the yield rate based on the performance indicators; S6: Construct a semiconductor device layout optimization model based on the yield and the set of electrical correction parameters; S7: Solve the semiconductor device layout optimization model to obtain the optimal layout strategy for the semiconductor device; S8: Execute the optimal layout strategy.

2. The semiconductor device layout optimization method according to claim 1, characterized in that, The semiconductor device design data specifically includes: the netlist of the semiconductor circuit to be laid out, device parameters, layout constraints, and layout design rules.

3. The semiconductor device layout optimization method according to claim 1, characterized in that, S2 specifically includes: S201: Based on the semiconductor device design data, calculate the placement priority of the semiconductor device, and sort the semiconductor devices in descending order according to the placement priority; S202: Based on the sorting results, the semiconductor device is divided into clusters according to the clustering cost to generate an initial clustering structure, wherein the initial clustering structure includes multiple clusters; S203: Determine the regional center position of each of the initial cluster structures based on the cluster area and the number of semiconductor devices within the cluster; S204: Generate the initial coordinates of the semiconductor device based on the center position of the region and the placement priority; S205: Based on the consistency of current direction, the initial coordinates of the semiconductor device are adjusted for orientation to obtain an initial layout that satisfies the layout design rules.

4. The semiconductor device layout optimization method according to claim 1, characterized in that, The specific geometric environment parameters include: well-side scattering integral, STI stress geometry, and LOD stress difference component.

5. The semiconductor device layout optimization method according to claim 1, characterized in that, The electrical correction parameter set specifically includes: semiconductor device threshold voltage, WPE correction body effect coefficient, WPE correction effective carrier mobility, LOD correction effective carrier mobility, LOD correction carrier saturation velocity, and LOD correction threshold voltage. S4 specifically includes: S401: Input the well-side scattering integral into the WPE model to obtain the threshold voltage of the semiconductor device, the corrected bulk effect coefficient, and the corrected effective carrier mobility. S402: Input the STI stress geometry and LOD stress difference components into the LOD model to obtain the LOD-corrected effective carrier mobility, the LOD-corrected carrier saturation velocity, and the LOD-corrected threshold voltage.

6. The semiconductor device layout optimization method according to claim 1, characterized in that, S6 specifically includes: S601: Calculate the WPE deviation index and LOD deviation index based on the electrical correction parameter set; S602: Based on the yield, the WPE deviation index, and the LOD deviation index, construct an objective function with the goal of minimizing the semiconductor device layout cost; S603: Set constraints; S604: Combine the constraints and the objective function to construct the semiconductor device layout optimization model.

7. The semiconductor device layout optimization method according to claim 1, characterized in that, Specifically, S7 is: The whale optimization algorithm is used to solve the semiconductor device layout optimization model to obtain the optimal layout strategy for the semiconductor device.

8. A layout optimization system for semiconductor devices, characterized in that, include: Processor and memory; The memory stores a program or instructions that can run on the processor, which, when executed by the processor, implement the steps of the layout optimization method for a semiconductor device as described in any one of claims 1 to 7.

9. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the layout optimization method for a semiconductor device as described in any one of claims 1 to 7.

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