Ferroelectric memory and reading method and reading circuit thereof
By pre-charging the bit lines and sensing amplifier outputs and changing the board line voltage, the problem of bit line voltage variation affecting the read window is solved, achieving higher read accuracy and memory integration density.
Patent Information
- Application Number
- CN202511429888.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-01-13
AI Technical Summary
Changes in bit line voltage cause changes in charge on the parallel ferroelectric capacitors, reducing the 0/1 read window.
The bit line and the output of the sensing amplifier are charged to the pre-charge voltage, and the voltage of the board line connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V, causing a change in the current on the bit line, which in turn causes a change in the voltage at the output of the sensing amplifier to read the stored data of the ferroelectric capacitor; the voltage at the bit line remains constant.
The increased read window improves the integration density of the ferroelectric memory and allows for an increase in the number of parallel ferroelectric capacitors.
Smart Images
Figure CN121331184A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a ferroelectric memory and its reading method and reading circuit. Background Technology
[0002] Ferroelectric RAM (FeRAM) employs a 1TnC structure. The 1TnC structure is an architecture where one transistor (1T) shares multiple capacitors (nC). 1TnC FeRAM uses floating bit-line sensing (BL sense) to detect changes in charge during ferroelectric polarization transitions, sensing 0 and 1 through differences in bit-line voltage changes.
[0003] The drawback of this reading method is that changes in the bit line voltage will cause changes in the charge on the parallel ferroelectric capacitors. Due to the "voltage stabilization effect" of a large number of parallel ferroelectric capacitors, the changes in the bit line voltage are affected, thus reducing the 0 / 1 reading window. Summary of the Invention
[0004] The purpose of this invention is to provide a ferroelectric memory and its reading method and reading circuit to solve the problem that changes in bit line voltage can cause changes in charge on parallel ferroelectric capacitors, reducing the read window.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for reading a ferroelectric memory, comprising:
[0006] The alignment line and the output of the sense amplifier are charged to the pre-charge voltage;
[0007] The voltage on the board line connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V, the polarization of the ferroelectric capacitor to be read changes and causes a change in the current on the bit line;
[0008] The charge on the capacitor at the output of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby changing the voltage at the output of the sensing amplifier to read the stored data of the ferroelectric capacitor.
[0009] The voltage at the bit line terminal remains constant throughout.
[0010] Optionally, the voltage at the bit line terminal is always maintained at V. PRE -V THSEL , where V PRE V is the pre-charge voltage. THSEL To select the threshold voltage of the transistor.
[0011] Optionally, the ferroelectric memory uses a single transistor to share multiple ferroelectric capacitors.
[0012] Optionally, the step of pre-charging the alignment line and the output of the sensing amplifier to a preset voltage includes:
[0013] Turn on the selection transistor and charge the bit line and sense amplifier output to the pre-charge voltage by driving the transistor.
[0014] After charging, the driving transistor is turned off.
[0015] Based on the same inventive concept, the present invention also provides a ferroelectric memory, including bit lines, plate lines and ferroelectric capacitors, wherein the bit lines and the plate lines are located at both ends of the ferroelectric capacitors and are electrically connected to the ferroelectric capacitors, and the ferroelectric capacitors are arranged in a matrix.
[0016] Optionally, there are multiple ferroelectric capacitors, each of which includes an upper electrode, an insulating layer, and a lower electrode. The upper electrode is electrically connected to the bit line, and the lower electrode is electrically connected to the plate line. The bit line is perpendicular to the extension direction of the plate line. The number of bit lines is the number of columns in the matrix of the ferroelectric capacitors, and the number of plate lines is the number of rows in the matrix of the ferroelectric capacitors.
[0017] Optionally, the ferroelectric memory uses a single transistor to share multiple ferroelectric capacitors.
[0018] Based on the same inventive concept, the present invention also provides a read circuit for a ferroelectric memory, comprising:
[0019] The pre-charge circuit is used to charge the alignment line and the output of the sense amplifier to the pre-charge voltage;
[0020] The reference voltage generation circuit reduces the voltage of the plate line connected to the ferroelectric capacitor to be read from the pre-charge voltage to 0V, which changes the polarization of the ferroelectric capacitor to be read and causes a change in the current on the bit line; the charge on the output terminal of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby changing the voltage at the output terminal of the sensing amplifier, wherein the voltage at the bit line terminal remains constant.
[0021] A sensitive amplifier detects the voltage difference between the bit line and the output of the sensing amplifier to read the stored data of the ferroelectric capacitor to be read.
[0022] Optionally, it also includes a data latching and rewriting circuit. The data latched by the sensitive amplifier is rewritten into the damaged memory cell through the write drive circuit, with the cooperation of the board line and the bit line, to complete the data recovery.
[0023] Optionally, it may also include a timing control circuit, wherein the timing control circuit is a current sensing timing circuit.
[0024] In a ferroelectric memory reading method provided by this invention, the bit line and the output terminal of the sensing amplifier are charged to a pre-charge voltage; the voltage of the plate line connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V, causing a change in the polarization of the ferroelectric capacitor to be read and resulting in a change in the current on the bit line; the charge on the capacitor at the output terminal of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby causing a change in the voltage at the output terminal of the sensing amplifier to read the stored data of the ferroelectric capacitor; wherein, the voltage at the bit line terminal remains constant throughout the data reading process. Maintaining a constant voltage at the bit line terminal during reading reduces the influence of other parallel ferroelectric capacitors on the bit line voltage changes, increases the read window, and allows for an increase in the number of parallel ferroelectric capacitors, thereby improving the integration density of the ferroelectric memory. Attached Figure Description
[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0026] Figure 1 This is a flowchart of the reading method of the ferroelectric memory according to an embodiment of the present invention.
[0027] Figure 2 This is a schematic diagram of the current sensing circuit according to an embodiment of the present invention.
[0028] Figure 3 This is a schematic diagram of the ferroelectric memory structure according to an embodiment of the present invention.
[0029] Figure 4 This is a top view of the ferroelectric memory structure according to an embodiment of the present invention.
[0030] Figure 5 This is a timing diagram of current sensing according to an embodiment of the present invention.
[0031] In the picture,
[0032] 11 - Bit line; 12 - Ferroelectric capacitor; 13 - Board line; 14 - Word line. Detailed Implementation
[0033] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0034] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0035] Figure 1 This is a flowchart illustrating a method for reading a ferroelectric memory according to an embodiment of the present invention. Figure 1 As shown, the present invention provides a method for reading a ferroelectric memory, comprising:
[0036] Step S10: Charge the alignment line and the output of the sensing amplifier to the pre-charge voltage;
[0037] Step S20: The voltage of the plate line connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V, the polarization of the ferroelectric capacitor to be read changes and causes a change in the current on the bit line;
[0038] In step S30, the charge on the capacitor at the output of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby changing the voltage at the output of the sensing amplifier to read the stored data of the ferroelectric capacitor; wherein, the voltage at the bit line remains constant.
[0039] Figure 2 This is a schematic diagram of the current sensing circuit according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the ferroelectric memory structure according to an embodiment of the present invention. Figure 4 This is a top view of the ferroelectric memory structure according to an embodiment of the present invention. Figure 5 This is a current sensing timing diagram according to an embodiment of the present invention. To make the above-mentioned objects, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 5Specific embodiments of the present invention will be described in detail below.
[0040] Specifically, the steps for pre-charging the alignment line and the output of the sensing amplifier to a preset voltage include the following steps. For example... Figure 2 As shown, enable the selection transistor (M) SEL When the precharge signal (PCH) is active, the precharge transistor is turned on, and the driving transistor (M) is activated. PCH The bit line and the sense amplifier output (SO) are charged to the pre-charge voltage V. PRE Pre-charge voltage V PRE For example, VDD / 2. After charging, the driving transistor is turned off, that is, the precharge signal (PCH) is turned off, and the precharge transistor is disconnected.
[0041] like Figures 2 to 4 As shown, the ferroelectric memory in this embodiment uses a single transistor to share multiple ferroelectric capacitors. The number of ferroelectric capacitors in this embodiment is multiple, and they are distributed in a matrix. The ferroelectric capacitors are located between the bit lines and the plate lines, and are electrically connected to both the bit lines and the plate lines respectively. When reading data, the ferroelectric capacitor to be read is selected, and the voltage of the plate line PL connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V. The polarization of the ferroelectric capacitor to be read changes, causing a change in current on the bit line. The charge on the capacitor at the output of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby changing the voltage at the output of the sensing amplifier to read the stored data of the ferroelectric capacitor to be read; wherein, the voltage at the bit line remains constant at V. PRE -V THSEL , where V PRE V is the pre-charge voltage. THSEL The threshold voltage of the selected transistor is determined. In this embodiment, the ferroelectric capacitor is read by changing the voltage of the plate line PL. Multiple ferroelectric capacitors are positioned between the plate line PL and the bit line BL. Only the voltage of the plate line PL connected to the ferroelectric capacitor to be read is changed, i.e., only the potential of the ferroelectric capacitor to be read is changed. The change in the polarity of the ferroelectric capacitor is neutralized by the other capacitors, and the potential is distributed among the various capacitors, attracting charges to maintain the potential. Therefore, the voltage at the bit line BL can remain constant. Since the selected transistor SEL acts as a current source, the voltage at the bit line BL remains at V. PRE -V THSEL The capacitor Cso at the output of the sensing amplifier stores a certain amount of charge after pre-charging. The bit line BL reaches equilibrium after pre-charging. If the voltage on the plate line PL changes, it causes a reversal of the polarity of the ferroelectric capacitor. This reversal leads to a change in the current in the bit line BL, affecting the capacitance Cso at the output of the sensing amplifier. SOThe charge in the capacitor is drawn away, and the transistor SEL is selected as the current source. The current remains constant, and the bit line BL is the pinch-off voltage, so the current flows continuously. After the current in the capacitor Cso at the output of the sensing amplifier flows away, the voltage across the capacitor Cso at the output of the sensing amplifier changes. The sensitive amplifier detects the tiny voltage difference between the bit line and the capacitor Cso at the output of the sensing amplifier and quickly amplifies it to a full-amplitude logic level (0V or VDD). This amplified signal is the stored data of the ferroelectric capacitor read out. In this embodiment, the stored data of the ferroelectric capacitor is read by changing the voltage of the board line PL. The location of the changed voltage and the sensed voltage are not at the same location; that is, the location of the changed voltage and the sensed voltage are separate. The effect of separating the location of the changed voltage and the sensed voltage is that the polarity change of the ferroelectric capacitor is neutralized by other ferroelectric capacitors, the potential is distributed to each ferroelectric capacitor, attracting charge to maintain the potential, so that the voltage at the bit line remains constant. Maintaining a constant voltage at the bit line terminals during reading reduces the impact of other parallel ferroelectric capacitors on the bit line voltage changes, increases the read window, and allows for an increase in the number of parallel ferroelectric capacitors, thereby improving the integration density of the ferroelectric memory.
[0042] like Figures 3 to 4 As shown, this embodiment also provides a ferroelectric memory, including bit lines 11, plate lines 13, and ferroelectric capacitors 12. The bit lines 11 and plate lines 13 are located at both ends of the ferroelectric capacitors 12 and are electrically connected to them. The ferroelectric capacitors 12 are arranged in a matrix. There are multiple ferroelectric capacitors 12, each including an upper electrode, an insulating layer, and a lower electrode. The upper electrode is electrically connected to the bit lines 11, and the lower electrode is electrically connected to the plate lines 13. The extension directions of the bit lines 11 and plate lines 13 are perpendicular. The number of bit lines 11 is the number of columns in the ferroelectric capacitor matrix, and the number of plate lines 13 is the number of rows in the ferroelectric capacitor matrix. The ferroelectric memory also includes word lines 14, which are electrically connected to the bit lines 11, and the extension directions of the word lines 14 and bit lines 11 are perpendicular. The ferroelectric memory uses a transistor sharing multiple ferroelectric capacitors, i.e., a 1TnC structure.
[0043] like Figure 2 As shown, this embodiment also provides a read circuit for a ferroelectric memory, including:
[0044] A pre-charge circuit is used to charge the bit line and the output of the sense amplifier to the pre-charge voltage. The pre-charge circuit includes a selection transistor M. SEL and driving transistor M PCH Enable the selection transistor (M). SEL When the precharge signal (PCH) is active, the precharge transistor is turned on, and the driving transistor (M) is activated. PCHThe bit line and the sense amplifier output (SO) are charged to the pre-charge voltage V. PRE Pre-charge voltage V PRE For example, VDD / 2. After charging, the driving transistor is turned off, that is, the precharge signal (PCH) is turned off, and the precharge transistor is disconnected.
[0045] The reference voltage generation circuit reduces the voltage of the plate line connected to the ferroelectric capacitor to be read from the pre-charge voltage to 0V, causing the polarization of the ferroelectric capacitor to change and resulting in a change in current on the bit line; the charge on the output terminal of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby causing a change in the voltage at the output terminal of the sensing amplifier, wherein the voltage at the bit line terminal remains constant.
[0046] A sensitive amplifier detects the voltage difference between the bit line and the output of the sensing amplifier to read the stored data of the ferroelectric capacitor to be read.
[0047] The data latching and rewriting circuit allows the data latched by the sensitive amplifier to be rewritten into the damaged memory cell through the write drive circuit, with the cooperation of the board lines and bit lines, thus completing the data recovery.
[0048] A timing control circuit, wherein the timing control circuit is a current sensing timing circuit.
[0049] like Figure 5 As shown, the horizontal axis represents time (time, T), and the vertical axis represents voltage V. During the pre-charge phase, the driving transistor M... PCH The voltage during pre-charge is V DD +V TH The voltage of bit line BLn is pre-charged to V. PRE -V THSEL PLx board line, PL board line 1,2…n Precharge voltage to V PRE The voltage at the output SO of the sensing amplifier is pre-charged to V. DD After pre-charging, turn off the drive transistor M. PCH That is, the PCH signal is off, and the voltage driving the transistor is V. SATE When reading the stored data of a ferroelectric capacitor, the voltage of the board line PLx is changed, for example, by changing the voltage of the board line PLx connected to the ferroelectric capacitor to be read from the pre-charge voltage V. PRE Reduced to 0. The PL line on the board connected to other ferroelectric capacitors... 1,2…n The voltage at the terminals of bit line BLn remains constant at V during the read phase. PRE -V THSELSelect transistor SEL as the current source, keeping its voltage constant. Change the voltage on board line PLx, causing the polarity of the ferroelectric capacitor to reverse. This reversal causes a change in the current on bit line BLn, which in turn affects the capacitance C at the output of the sensing amplifier. SO The charge in the transistor is drawn away, selecting transistor M. SEL As a current source, the current remains constant. The bit line BLn is the pinch-off voltage, and the current flows continuously. After the current flows out of the capacitor Cso at the output of the sensing amplifier, the voltage across the capacitor Cso changes from 1 to 0. The sensitive amplifier detects the tiny voltage difference between the bit line and the capacitor Cso at the output of the sensing amplifier and quickly amplifies it to a full-amplitude logic level (0V or VDD). This amplified signal is the stored data of the ferroelectric capacitor read out.
[0050] In summary, in the ferroelectric memory reading method provided by this embodiment of the invention, the bit line and the output terminal of the sensing amplifier are charged to a pre-charge voltage; the voltage of the plate line connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V, causing a change in the polarization of the ferroelectric capacitor to be read and resulting in a change in the current on the bit line; the charge on the capacitor at the output terminal of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby causing a change in the voltage at the output terminal of the sensing amplifier to read the stored data of the ferroelectric capacitor to be read; wherein, the voltage at the bit line terminal remains constant throughout the data reading process. Maintaining a constant voltage at the bit line terminal during reading reduces the impact of other parallel ferroelectric capacitors on the bit line voltage changes, increases the reading window, and allows for an increase in the number of parallel ferroelectric capacitors, thereby improving the integration density of the ferroelectric memory.
[0051] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0052] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for reading a ferroelectric memory, characterized in that, include: The alignment line and the output of the sense amplifier are charged to the pre-charge voltage; The voltage on the board line connected to the ferroelectric capacitor to be read is reduced from the pre-charge voltage to 0V, the polarization of the ferroelectric capacitor to be read changes and causes a change in the current on the bit line; The charge on the capacitor at the output of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby changing the voltage at the output of the sensing amplifier to read the stored data of the ferroelectric capacitor. The voltage at the bit line terminal remains constant throughout.
2. The method for reading the ferroelectric memory according to claim 1, characterized in that, The voltage at the bit line terminal is always maintained at V. PRE -V THSEL , where V PRE V is the pre-charge voltage. THSEL To select the threshold voltage of the transistor.
3. The method for reading the ferroelectric memory according to claim 1, characterized in that, The ferroelectric memory uses a single transistor to share multiple ferroelectric capacitors.
4. The method for reading the ferroelectric memory according to claim 1, characterized in that, The steps for pre-charging the alignment line and the output of the sensing amplifier to a preset voltage include: Turn on the selection transistor and charge the bit line and sense amplifier output to the pre-charge voltage by driving the transistor. After charging, the driving transistor is turned off.
5. A ferroelectric memory, characterized in that, It includes bit lines, plate lines and ferroelectric capacitors, the bit lines and the plate lines are located at both ends of the ferroelectric capacitors and are electrically connected to the ferroelectric capacitors, and the ferroelectric capacitors are arranged in a matrix.
6. The ferroelectric memory according to claim 5, characterized in that, The number of ferroelectric capacitors is multiple, and each ferroelectric capacitor includes an upper electrode, an insulating layer and a lower electrode. The upper electrode is electrically connected to the bit line, and the lower electrode is electrically connected to the plate line. The bit line is perpendicular to the extension direction of the plate line. The number of bit lines is the number of columns in the matrix of the ferroelectric capacitors, and the number of plate lines is the number of rows in the matrix of the ferroelectric capacitors.
7. The ferroelectric memory according to claim 5, characterized in that, The ferroelectric memory uses a single transistor to share multiple ferroelectric capacitors.
8. A read circuit for a ferroelectric memory, characterized in that, include: The pre-charge circuit is used to charge the alignment line and the output of the sense amplifier to the pre-charge voltage; The reference voltage generation circuit reduces the voltage of the plate line connected to the ferroelectric capacitor to be read from the pre-charge voltage to 0V, which changes the polarization of the ferroelectric capacitor to be read and causes a change in the current on the bit line; the charge on the output terminal of the sensing amplifier is conducted to the ferroelectric capacitor to be read through the bit line, thereby changing the voltage at the output terminal of the sensing amplifier, wherein the voltage at the bit line terminal remains constant. A sensitive amplifier detects the voltage difference between the bit line and the output of the sensing amplifier to read the stored data of the ferroelectric capacitor to be read.
9. The reading circuit of the ferroelectric memory according to claim 8, characterized in that, It also includes a data latching and rewriting circuit. The data latched by the sensitive amplifier is rewritten into the damaged memory cell through the write drive circuit, with the cooperation of the board line and the bit line, to complete the data recovery.
10. The read circuit of the ferroelectric memory according to claim 8, characterized in that, It also includes a timing control circuit, which is a current sensing timing circuit.