A method and system for discharging a bus of a reserve integrated power system

Abstract

The application provides a kind of reserve integrated power supply system bus discharging method and system, the method comprises: detecting the input state of power supply system;When detecting that power supply system input power failure, control power supply system enters shutdown mode;Start multi-stage discharge control process, by controlling the start-stop of load powered by auxiliary power supply to adjust load power consumption, to control the discharge rate of bus capacitor in stages.The application does not need to additionally increase the special discharge circuit of bus capacitor, only uses the existing components of power supply system, by detecting the power failure state of system input and starting multi-stage discharge control process, by adjusting the power consumption of load powered by auxiliary power supply such as cooling fan to control the discharge rate of bus capacitor in stages, reduces the test cost of power supply system, and can stably meet the requirement of reducing bus voltage to below 60Vdc safe voltage within 5 minutes of whole machine power failure shutdown, while ensuring safety, the economy and working efficiency of power supply system are also considered.

Description

A method and system for bus discharge in an integrated power reserve system Technical Field

[0001] This invention relates to the field of UPS testing technology, and more specifically to a method and system for discharging the busbar of an integrated power reserve system. Background Technology

[0002] An integrated emergency power supply system is an integrated emergency power supply device that integrates energy storage units, power conversion, and control management modules. It can charge the energy storage when the mains power is normal and seamlessly switch to continuous power supply to the load when the mains power is interrupted. It is widely applicable to scenarios with high requirements for power continuity and stability, such as communication base stations, data centers, and emergency loads. A UPS (Uninterruptible Power Supply System) is its core functional unit, a device that can continuously supply power to the load when the external power supply is interrupted. It is widely used in scenarios with stringent power reliability requirements, such as data centers, medical equipment, and industrial control systems. In UPS UL certification (the UPS safety certification system used to verify the electrical and mechanical safety of products), there is a bus capacitor discharge time test, requiring the bus voltage to drop below a safe voltage of 60Vdc within 5 minutes of the UPS being powered off.

[0003] For conventional small and medium-power UPS systems, the auxiliary power supply draws power directly from the bus. After a UPS power outage, the auxiliary power supply continues to operate for a period of time, consuming energy from the bus capacitors. Once the auxiliary power supply shuts down, it continues to discharge through a resistor connected in parallel to the bus capacitors, typically meeting the requirement of keeping the bus voltage below 60Vdc for 5 minutes. However, in high-power UPS systems, due to the large number of bus capacitors and their large total stored energy, relying solely on auxiliary power supply discharge and discharge through the bus parallel resistor requires reducing the resistance value to meet the discharge time requirement. However, reducing this resistance value significantly increases power consumption during normal UPS operation, reducing the UPS's maximum efficiency.

[0004] To address this issue, existing technologies generally employ a separate bus capacitor discharge circuit, such as the discharge circuit shown in Figure 1: C1 is the positive bus capacitor, C2 is the negative bus capacitor, R2 is a smaller bus discharge resistor, R1 is the larger bus discharge first switch Q1 drive resistor, and R3, R4, and Q2 form a switching circuit controlled by the auxiliary power supply output. When the auxiliary power supply is operating normally, the VCC output voltage turns on Q2, turns off Q1, and R2 is not working. When the UPS is shut down and the auxiliary power supply is de-energized, the VCC voltage is 0, Q2 is off, and BUS+ charges the gate of Q1 through R1, turning Q1 on, and R2 begins to discharge the bus capacitor. While this solution reduces normal operating losses, it requires an additional discharge circuit, negatively impacting cost and installation space.

[0005] Therefore, there is an urgent need for a bus discharge control scheme that can meet the bus capacitor discharge time requirements without requiring additional dedicated discharge circuits and costs. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and system for discharging the bus of an integrated power supply system, so as to solve the technical problems of the additional discharge circuit and cost of the existing bus capacitor discharge scheme.

[0007] In a first aspect, embodiments of the present invention provide a bus discharge method for an integrated power supply system, applied to a power supply system including a bus capacitor, a discharge resistor connected in parallel with the bus capacitor, a control chip, an auxiliary power supply, and a cooling fan. The auxiliary power supply draws power from the bus capacitor to supply power to the cooling fan. The method includes the following steps:

[0008] Detect the input status of the power supply system;

[0009] When a power failure is detected in the power system input, the power system is controlled to enter shutdown mode;

[0010] A multi-stage discharge control process is initiated, which adjusts the load power consumption by controlling the start and stop of the load powered by the auxiliary power supply, so as to control the discharge rate of the bus capacitor in stages.

[0011] The multi-stage discharge control process, which involves controlling the start and stop of the load powered by the auxiliary power supply to adjust the load power consumption and control the discharge rate of the bus capacitor in stages, includes the following steps:

[0012] Control the cooling fan to operate in maximum power mode, so that the bus capacitor discharges to the preset first bus voltage;

[0013] When the bus voltage is detected to drop to the first bus voltage, the cooling fan is controlled to stop working and the control chip enters sleep mode, so that the bus capacitor can be discharged to the preset second bus voltage.

[0014] When the bus voltage is detected to drop to the second bus voltage, the auxiliary power supply is controlled to stop working, and the bus capacitor is discharged to the target bus voltage through the discharge resistor.

[0015] The power system also includes a display powered by an auxiliary power supply; the step of controlling the cooling fan to stop working and the control chip to enter sleep mode when the bus voltage drops to the first bus voltage, so as to discharge the bus capacitor to a preset second bus voltage, includes:

[0016] Control the cooling fan to stop working;

[0017] Turn off the monitor;

[0018] The control chip enters sleep mode;

[0019] The auxiliary power supply operates in intermittent mode, causing the bus capacitor to discharge to the preset second bus voltage.

[0020] The method of stopping the cooling fan from working includes:

[0021] By changing the level of the PWM output pin of the control chip, the switching devices in the drive circuit of the cooling fan are controlled to turn on and off, thereby cutting off the power supply to the cooling fan or reducing the voltage of the cooling fan below the supply voltage, so that the cooling fan stops working.

[0022] The step of turning off the display includes:

[0023] The control chip sends a sleep command to the display through its communication interface, causing the display to enter a low-power standby or sleep state.

[0024] Wherein, the first bus voltage is a voltage value pre-calibrated based on the bus capacitor capacity of the power system, the rated power consumption of the auxiliary power supply and / or the maximum power consumption mode of the cooling fan, and the second bus voltage is the discharge cutoff voltage of the auxiliary power supply in discontinuous mode.

[0025] The auxiliary power supply adopts a flyback topology.

[0026] Secondly, embodiments of the present invention also provide a power supply system for performing the above-described integrated power supply system bus discharge method. The power supply system includes: a bus capacitor, a discharge resistor, a control chip, an auxiliary power supply, and a cooling fan; the discharge resistor is connected in parallel to the bus capacitor, and the cooling fan is electrically connected to the auxiliary power supply; the auxiliary power supply is electrically connected to the bus capacitor and is used to draw power from the bus capacitor and supply power to the cooling fan and the control chip; the control chip is electrically connected to the bus capacitor, the auxiliary power supply, and the cooling fan, and the control chip is configured to perform the integrated power supply system bus discharge method.

[0027] The cooling fan includes a fan drive circuit, which is electrically connected to the control chip and is used to receive the output signal from the control chip to control the cooling fan to start or stop working.

[0028] The power system further includes a display powered by the auxiliary power supply; the display is electrically connected to the control chip via a serial communication interface and is controlled by the control chip.

[0029] The advantages of this invention compared to existing technologies are as follows: This invention does not require an additional dedicated discharge circuit for the bus capacitor. It utilizes existing components of the power supply system, detects the power failure state of the power supply system input, and initiates a multi-stage discharge control process. By adjusting the power consumption of auxiliary power-powered loads such as cooling fans, the discharge rate of the bus capacitor is controlled in stages, reducing the cost of power supply system testing. Furthermore, it can stably meet the requirement of reducing the bus voltage to below 60Vdc within 5 minutes of powering off the entire power supply system. While ensuring safety, it also takes into account the economy and working efficiency of the power supply system.

[0030] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, preferred embodiments are described in detail below. Attached Figure Description

[0031] Figure 1 is a schematic diagram of the circuit structure for bus discharge in an existing integrated power storage system;

[0032] Figure 2 is a block structure diagram of an integrated power storage system provided by the present invention;

[0033] Figure 3 is a timing diagram of a bus discharge method for an integrated power storage system provided by the present invention;

[0034] Figure 4 is a flowchart illustrating a bus discharge method for an integrated power storage system provided by the present invention.

[0035] Figure 5 is a flowchart illustrating a specific implementation of step S30 in Figure 4;

[0036] Figure 6 is a flowchart illustrating a specific implementation of step S32 in Figure 5;

[0037] Figure 7 is a schematic diagram of the circuit structure of the bus capacitor and discharge resistor of an integrated power storage system provided by the present invention.

[0038] Figure 8 is a schematic diagram of the circuit structure of a specific fan drive circuit of an integrated power storage system provided by the present invention.

[0039] Figure 9 is a schematic diagram of the circuit structure of another specific fan drive circuit of an integrated power storage system provided by the present invention.

[0040] Figure label:

[0041] 1. Bus capacitor; 2. Auxiliary power supply; 3. Control chip; 4. Cooling fan. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] It should be understood that, when used in this specification and the appended claims, the terms “comprising” and “including” indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0044] Example 1

[0045] Referring to Figures 2 to 6, this embodiment provides a bus discharge method for an integrated power supply system, applied to the power system shown in Figure 2. As shown in Figure 2, the power system includes a bus capacitor 1, a discharge resistor connected in parallel with the bus capacitor 1, a control chip 3, an auxiliary power supply 2, and a cooling fan 4. The auxiliary power supply 2 draws power from the bus capacitor 1 to supply power to the cooling fan 4. The core components of the power system form a basic power supply and control link. The bus capacitor 1 serves as an energy storage carrier, and the discharge resistor is connected in parallel across its two ends to achieve passive discharge. The auxiliary power supply 2 draws power directly from the two ends of the bus capacitor 1, converting the bus DC voltage into an operating voltage suitable for the cooling fan 4 and the control chip 3. The control chip 3 is connected to the bus capacitor 1, the auxiliary power supply 2, and the cooling fan 4 via pins. This component configuration fully reuses the original hardware of the power system, eliminating the need for additional dedicated discharge circuits. It provides hardware support for subsequent multi-stage discharge methods, while clearly defining the functional division of each component, ensuring smooth operation of the links for auxiliary power supply 2 supply, load power consumption adjustment, and bus voltage control during the discharge process, laying the foundation for meeting UL certification discharge requirements.

[0046] Referring to Figure 4, the bus discharge method of the integrated power reserve system in this embodiment includes the following steps S10-S30.

[0047] S10, Detect the input status of the power supply system.

[0048] In practical implementation, control chip 3 can monitor the voltage or current signal at the power system input terminal in real time through its I / O pins or dedicated input detection circuit, such as monitoring the AC voltage at the mains connection terminal. A preset normal voltage threshold range is used; if the input voltage is detected to be continuously below the lower threshold or completely absent for a duration exceeding the preset judgment time, the power system input state is determined to be abnormal. Timely and accurate capture of input power failure signals provides a trigger basis for subsequent startup of the shutdown mode and multi-stage discharge process, preventing the energy of bus capacitor 1 from being consumed by non-discharge demands due to input power failure detection delays. This ensures that the discharge process can start according to the preset time plan, guaranteeing the achievement of the goal of reducing the voltage to 60Vdc within 5 minutes.

[0049] S20. When a power failure is detected in the power system input, control the power system to enter the shutdown mode.

[0050] In practice, after determining that the input power has failed, the control chip 3 sends a shutdown command to the main circuit components of the power system, such as the main inverter and external load switch, according to a preset program. This disconnects the power supply connection between the main circuit and the external load, leaving only the discharge circuit consisting of the auxiliary power supply 2, the control chip 3, and the bus capacitor 1 powered. At the same time, it prohibits new load connection commands to avoid additional loads consuming the energy of the bus capacitor 1.

[0051] For step S20, the main load that is not related to discharge is quickly isolated to prevent the energy of bus capacitor 1 from being dispersed and consumed, to ensure that the energy is used first for the subsequent staged discharge process, to avoid insufficient discharge time due to the continuous power consumption of the main load, and to protect the main circuit components from abnormal voltage surges when there is no external power supply.

[0052] In a preferred embodiment, a load priority cut-off step can be added before entering the shutdown mode. Non-critical loads such as redundant heat dissipation modules and unnecessary communication modules are cut off first, while the power supply to critical monitoring modules such as bus voltage sampling modules is briefly retained. This further optimizes the energy distribution of bus capacitor 1 and is suitable for power systems with complex load levels.

[0053] S30. Start the multi-stage discharge control process, and adjust the load power consumption by controlling the start and stop of the load powered by the auxiliary power supply, so as to control the discharge rate of the bus capacitor in stages.

[0054] In practice, the control chip 3 initiates multi-stage control according to a preset program, using the bus voltage sampling value as the basis for stage switching. More specifically, the first stage increases the total power consumption of the auxiliary power supply 2 by starting a high-power load, accelerating the discharge of the bus capacitor 1; the second stage reduces the power consumption of the auxiliary power supply 2 by shutting down some loads, slowing down the discharge rate; the third stage uses forced power consumption to reduce the voltage to the target bus voltage of 60Vdc. The bus voltage is sampled in real time at each stage, and automatically switches to the next stage when the preset voltage threshold is reached, realizing step-by-step regulation of the discharge rate; by adjusting the load power consumption in stages, the problems of slow initial discharge leading to substandard performance or excessively fast discharge leading to energy waste caused by a single discharge rate are avoided. The discharge requirements of the bus capacitor 1 from high energy to low energy are precisely matched, ensuring a stable drop to below 60Vdc within 5 minutes, without additional hardware costs.

[0055] As can be seen from the above, the bus discharge method of the integrated power supply system in this embodiment does not require the addition of a dedicated discharge circuit for the bus capacitor 1. It only utilizes the existing components of the power supply system, detects the power failure state of the power supply system input and initiates a multi-stage discharge control process, and controls the discharge rate of the bus capacitor 1 in stages by adjusting the power consumption of the load powered by the auxiliary power supply 2, such as the cooling fan 4. This reduces the cost of power supply system testing, avoids the large space occupation caused by adding a discharge circuit, and can stably meet the requirement of reducing the bus voltage to below 60Vdc within 5 minutes of power failure of the entire power supply system. While ensuring safety, it also takes into account the economy and working efficiency of the power supply system.

[0056] In some embodiments, as shown in FIG5, a specific multi-stage discharge control scheme is provided. In step S30, that is, the multi-stage discharge control process is started, and the load power consumption is adjusted by controlling the start and stop of the load powered by the auxiliary power supply 2, so as to control the discharge rate of the bus capacitor 1 in stages. Specifically, it includes the following steps S31-S33.

[0057] S31: Control the cooling fan to operate in maximum power consumption mode, so that the bus capacitor discharges to the preset first bus voltage.

[0058] In practice, after entering the shutdown mode, the control chip 3 sends a maximum power consumption control signal to the fan drive circuit. More specifically, if the fan supports PWM speed control, the control chip 3 outputs a PWM signal with a 100% duty cycle; if the fan only supports start-stop, it outputs a full-rated drive voltage signal. At this time, the cooling fan 4 runs at its highest speed, and its power consumption reaches its rated maximum value. The auxiliary power supply 2 needs to output higher power to meet the fan's demand, thereby accelerating the rate of power extraction from the bus capacitor 1 and causing the bus voltage to drop rapidly from the initial bus voltage to the preset first bus voltage. If the power system is equipped with multiple cooling fans 4, all cooling fans 4 can be controlled to run simultaneously in maximum power consumption mode, further improving the total power consumption in the first stage. This is suitable for ultra-high power UPS with extremely large bus capacitor 1 capacity, such as 10000μF or more. If there is only a single fan, it can be paired with other high-power auxiliary loads, such as the preheating resistor for temporarily starting the backup power supply, to enhance the initial discharge effect.

[0059] Step S31 is the first stage of controlling the discharge rate of bus capacitor 1. The maximum power consumption of cooling fan 4 is used to quickly consume the large amount of energy of bus capacitor 1 in the early stage, which greatly shortens the time for the bus voltage to drop from the initial value to the first bus voltage. For example, it only takes 1 minute to drop from 500Vdc to 300Vdc, which reserves sufficient time for subsequent smooth discharge and final discharge, and avoids the total time exceeding the standard due to the lag in the initial discharge.

[0060] S32: When the bus voltage is detected to drop to the first bus voltage, the cooling fan is controlled to stop working and the control chip enters sleep mode so that the bus capacitor is discharged to the preset second bus voltage.

[0061] In practice, the control chip 3 can monitor the bus voltage in real time through the ADC sampling circuit. When the sampled value is equal to or lower than the first bus voltage threshold, it immediately sends a stop signal to the cooling fan 4 drive circuit, such as adjusting the PWM duty cycle to 0%, and shutting down other loads that consume auxiliary power supply 2. At the same time, it starts its own sleep program to shut down unnecessary functional modules such as redundant ADC channels, and only retains the voltage sampling, clock and wake-up modules to work. As the load power consumption of auxiliary power supply 2 is greatly reduced, the output power decreases accordingly, the discharge rate of bus capacitor 1 slows down, and gradually drops to the preset second bus voltage, such as 150Vdc.

[0062] Step S32 is the second stage of controlling the discharge rate of bus capacitor 1. By turning off the high-power fan and reducing the chip power consumption, the total power consumption of auxiliary power supply 2 is reduced from high load to low load, avoiding the energy of bus capacitor 1 being consumed too quickly, so that the discharge enters a smooth stage. At the same time, it creates conditions for auxiliary power supply 2 to switch to intermittent mode, ensuring that the bus voltage can be stably reduced to the second bus voltage, rather than dropping too low and causing auxiliary power supply 2 to shut down prematurely.

[0063] In a further embodiment, the power system also includes a display powered by the auxiliary power supply 2.

[0064] In practice, the monitor's power supply terminal is connected to the output terminal of auxiliary power supply 2 to obtain operating power; its control terminal is connected to the communication interface of control chip 3 to receive power consumption control commands from control chip 3; during normal operation, the monitor is in display mode, and during the discharge phase, it can switch to sleep or off state according to control commands, becoming part of the load supplied by auxiliary power supply 2. Including the monitor in the load power consumption adjustment range can further enrich the power consumption control methods during the discharge phase. More specifically, turning off the monitor in the second phase can further reduce power consumption, making it easier for auxiliary power supply 2 to enter intermittent mode, thereby reducing the bus voltage to a lower second bus voltage and reserving more sufficient discharge time for the discharge resistor.

[0065] In some embodiments, as shown in FIG6, a specific second-stage discharge scheme is provided. In step S32, when the bus voltage is detected to drop to the first bus voltage, the cooling fan is controlled to stop working and the control chip enters sleep mode so that the bus capacitor is discharged to the preset second bus voltage. Specifically, it includes the following steps S321-S324.

[0066] S321: Controls the cooling fan to stop working.

[0067] In some embodiments, controlling the cooling fan 4 to stop working includes the following steps: changing the level state of the PWM output pin of the control chip 3 to control the switching device in the drive circuit of the cooling fan 4 to cut off the power supply to the cooling fan 4 or reduce the voltage of the cooling fan 4 to below the power supply voltage, so that the cooling fan 4 stops working.

[0068] In practice, the PWM output pin of control chip 3 is directly connected to the control terminal of the switching device in the fan drive circuit. When the fan needs to be stopped, the PWM pin outputs a low level or 0% duty cycle signal, and the switching device is turned off due to the lack of a drive signal. If the switching device is connected in series in the fan power supply circuit, the power supply is directly cut off after it is turned off. If the switching device is associated with the fan voltage regulation module, the fan voltage drops below the working threshold after it is turned off, and the fan stops running due to insufficient voltage.

[0069] For step S321, the switching device is directly controlled through the PWM pin to achieve a fast response to stop the fan, avoid the delay in fan stopping caused by signal transmission delay, and ensure that the second stage of power consumption regulation starts in time. At the same time, this control method does not require additional control components, simplifying the circuit structure.

[0070] It is understood that in other embodiments, if the PWM pin fails, the spare I / O pin of the control chip 3 can be used as a redundant control terminal. The spare pin is connected to the fan drive circuit through a hardware switching circuit to ensure that the fan can still stop normally, thereby improving the system's fault tolerance and making it suitable for power supply systems with extremely high reliability requirements.

[0071] S322: Turn off the monitor.

[0072] In some embodiments, turning off the display includes the following steps: sending a sleep command to the display through the communication interface of the control chip 3 to cause the display to enter a low-power standby or sleep state.

[0073] In practice, the communication interface of the control chip 3 establishes a bidirectional connection with the communication terminal of the display. The control chip 3 encapsulates the sleep command according to the preset communication protocol and sends it to the display through differential signal or single-ended signal. After receiving the command, the display parses it, starts the internal sleep program, shuts down non-essential function modules such as backlight, touch, and display driver, and only keeps the communication module powered to receive the wake-up command.

[0074] For step S322, a soft shutdown is achieved by sending a command through the communication interface, which avoids the loss of display data caused by direct power failure. At the same time, the sleep state can be quickly woken up, which improves the lifespan of the display. In addition, the communication control method is simple to wire and reduces the complexity of hardware connection.

[0075] It is understood that in other embodiments, a sleep duration parameter can be added to the sleep command, such as setting a sleep time of 5 minutes. After the display reaches the time limit, it will automatically wake up and detect the bus voltage. If it has dropped below 60Vdc, it will maintain low power consumption. If it does not meet the standard, it will feed back a signal to the control chip 3. This is suitable for scenarios where the discharge process may be delayed.

[0076] In a preferred embodiment, the power system further includes other power-consuming circuits that can be controlled to shut down to reduce the power consumption of the auxiliary power supply 2, and the power-consuming circuits are shut down before the control chip 3 enters sleep mode.

[0077] It is understandable that other controllable power-consuming circuits are non-discharge core and non-essential auxiliary circuits in the power supply system, including but not limited to indicator light modules, redundant communication sub-modules, and non-critical sensor monitoring circuits. They are all supplied with operating voltage by auxiliary power supply 2, and their control terminals are electrically connected to the I / O pins or extended communication interfaces of control chip 3 through wires. Before executing step S323, control chip 3 outputs low-level signals or standardized shutdown commands to the control terminals of each power-consuming circuit according to a preset timing sequence, triggering the internal switching devices of the circuit to turn off, cutting off the power supply circuit or putting the circuit into a power-off state, and stopping the consumption of energy from auxiliary power supply 2.

[0078] By shutting down additional unnecessary power-consuming circuits, the total load power consumption of auxiliary power supply 2 is further reduced, which helps auxiliary power supply 2 to work more stably in discontinuous mode, allowing bus capacitor 1 to discharge to a lower second bus voltage, and significantly reducing the discharge pressure on subsequent discharge resistors.

[0079] S323: Controls the control chip to enter sleep mode.

[0080] In practice, the control chip 3 starts its internal hibernation program according to preset instructions, shuts down its non-essential functional modules, such as the LCD display driver module and redundant ADC channels, reduces the operating frequency of the core processor or enters a stop mode, and only retains the necessary bus voltage sampling module, clock module and wake-up module to work; in hibernation mode, the power supply current and power consumption of the control chip 3 are greatly reduced.

[0081] For step S323, by significantly reducing the power consumption of the control chip 3 itself, the total output demand of the auxiliary power supply 2 is further reduced, making it easier for the auxiliary power supply 2 to enter discontinuous mode (DCM mode) and to operate stably at a lower second bus voltage, thus avoiding the auxiliary power supply 2 from stopping work prematurely due to excessive power consumption of the control chip 3.

[0082] S324: The auxiliary power supply operates in discontinuous mode, causing the bus capacitor to discharge to the preset second bus voltage.

[0083] In the second stage, the auxiliary power supply 2 prefers to operate in discontinuous mode. For step S324, by utilizing the discontinuous mode characteristics of the auxiliary power supply 2, a lower discharge cutoff voltage is achieved under low power load, so that the bus capacitor 1 can release more energy during the operation of the auxiliary power supply 2, reducing the discharge pressure of the subsequent discharge resistor, and ensuring that even if the resistance value of the discharge resistor is large, the voltage can be reduced to below 60Vdc in the remaining time.

[0084] In a preferred embodiment, the auxiliary power supply 2 adopts a flyback topology.

[0085] The formula for calculating the discharge cutoff voltage in discontinuous mode of the flyback topology is as follows:

[0086] ;

[0087] Where U is the discharge cutoff voltage, Pout is the auxiliary power supply output power, L is the primary inductance of the flyback transformer, η is the auxiliary power supply efficiency, D is the maximum duty cycle of the auxiliary power supply drive, and T is the auxiliary power supply drive operating cycle.

[0088] As shown in the formula for calculating the discharge cutoff voltage in the discontinuous mode of the flyback topology, after the control chip 3 reduces the load power consumption, its output power Pout decreases significantly. The decrease in Pout reduces the discharge cutoff voltage U, and the auxiliary power supply 2 automatically switches to discontinuous mode, slowly drawing power from the bus capacitor 1 through a periodic power-on-discharge process until the bus voltage drops to the calculated second bus voltage. That is, the lower the output power, the lower the discharge cutoff voltage in discontinuous mode. When the cooling fan 4, the display, and even other loads are turned off, and the controller enters sleep mode, the power consumption of the auxiliary power supply 2 can be reduced, thereby minimizing the value of the second bus voltage.

[0089] Among them, the flyback topology is simple and low-cost, and does not require an output inductor, saving PCB space. At the same time, its discontinuous mode characteristics match the low-power discharge requirements of the second stage, ensuring that the auxiliary power supply 2 can operate stably up to the second bus voltage, avoiding excessively high discharge cutoff voltage due to topology limitations, which would affect the operation of the subsequent discharge resistor.

[0090] S33: When the bus voltage is detected to drop to the second bus voltage, the auxiliary power supply is controlled to stop working, and the bus capacitor is discharged to the target bus voltage through the discharge resistor.

[0091] In practice, the control chip 3 continuously samples the bus voltage. When it detects that the bus voltage drops to the second bus voltage, it sends a stop working command to the auxiliary power supply 2 so that the auxiliary power supply 2 stops drawing power from the bus capacitor 1. At this time, the bus capacitor 1 is passively discharged only through the parallel discharge resistor. The discharge resistor consumes the remaining energy of the capacitor by using its own impedance. According to Ohm's law, the bus voltage gradually decreases as the capacitor charge is released, and eventually drops to the target voltage below 60Vdc.

[0092] Step S33 is the third stage of controlling the discharge rate of bus capacitor 1. After the auxiliary power supply 2 stops working, the final discharge is completed by relying on the original discharge resistor. There is no need to add a special discharge resistor, which controls hardware costs and avoids the problem of increased power consumption during normal operation caused by reducing the resistance value of the discharge resistor in conventional solutions. At the same time, the preset value of the second bus voltage ensures that the discharge resistor has enough time to reduce the voltage to below 60Vdc, which meets the UL certification requirements.

[0093] In a preferred embodiment, the first bus voltage is a voltage value pre-calibrated based on the bus capacitor capacity of the power system, the rated power consumption of the auxiliary power supply, and / or the maximum power consumption mode of the cooling fan, and the second bus voltage is the discharge cutoff voltage of the auxiliary power supply in discontinuous mode.

[0094] By accurately calculating and calibrating the first bus voltage and the second bus voltage, the time and rate of each discharge stage are ensured to meet the preset plan, avoiding excessively long or short time for a certain stage due to improper voltage threshold settings, thus ensuring the achievement of the overall 5-minute discharge target.

[0095] Example 2

[0096] Referring to Figures 2 and 7 to 9, this embodiment also provides a power supply system for performing the bus discharge method of the integrated power supply system of Embodiment 1.

[0097] Referring to Figure 2, the power system of this embodiment includes: a bus capacitor 1, a discharge resistor, a control chip 3, an auxiliary power supply 2, and a cooling fan 4; the discharge resistor is connected in parallel to the bus capacitor 1, and the cooling fan 4 is electrically connected to the auxiliary power supply 2; the auxiliary power supply 2 is electrically connected to the bus capacitor 1 and is used to draw power from the bus capacitor 1 and supply power to the cooling fan 4 and the control chip 3; the control chip 3 is electrically connected to the bus capacitor 1, the auxiliary power supply 2, and the cooling fan 4, and the control chip 3 is configured to execute the bus discharge method of the integrated power supply system of Embodiment 1.

[0098] In this embodiment, the bus capacitor 1 is connected in parallel with the discharge resistor to form an energy storage-passive discharge circuit; the input terminal of the auxiliary power supply 2 is connected to both ends of the bus capacitor 1, and the output terminal is connected to the cooling fan 4 and the control chip 3 respectively, forming an energy conversion-load power supply link; the control chip 3 is connected to the bus capacitor 1 through the ADC pin and to the auxiliary power supply 2 and the cooling fan 4 through the PWM / I / O pin, forming a sampling-control closed loop to ensure that the discharge steps of Embodiment 1 can be executed. All components of this power system are conventional UPS components, eliminating the need to purchase additional dedicated devices and controlling costs.

[0099] Referring to Figure 7, which is a schematic diagram of the circuit structure of the bus capacitor and discharge resistor in this embodiment, the bus capacitor is an existing structure, a typical DC bus support capacitor bank with voltage balancing resistors. More specifically, the bus capacitor circuit consists of the positive terminal BUS+ and the negative terminal BUS- of the DC bus. Two electrolytic capacitors C1 and C2 are connected in series and then in parallel between the positive terminal BUS+ and the negative terminal BUS- of the DC bus, with their midpoint forming the bus neutral point BUSN. Two discharge resistors R1 and R2 are connected in parallel across the electrolytic capacitors C1 and C2, respectively, for static voltage equalization and passive discharge in the final stage. In this embodiment, the discharge resistors R1 and R2 can be selected with larger resistance values ​​to reduce discharge power consumption; the input terminal of the auxiliary power supply is directly connected to BUS+ and BUS- to obtain power from the bus; the control chip is connected to the bus through its analog-to-digital converter (ADC) sampling circuit to monitor the total voltage between the positive terminal BUS+ and the negative terminal BUS- of the DC bus in real time or to monitor the voltage across the electrolytic capacitors C1 and C2 respectively, thereby serving as the basis for determining the execution of the multi-stage discharge control strategy.

[0100] More specifically, the series connection of two electrolytic capacitors C1 and C2 can increase the total withstand voltage of the bus, adapting to the high bus voltage requirements of high-power UPS; the bus neutral point BUSN is used to balance the voltage of C1 and C2; the discharge resistors R1 and R2 keep the voltage across electrolytic capacitors C1 and C2 consistent through the current shunt effect, avoiding damage to individual capacitors due to overvoltage; the ADC sampling circuit of the control chip obtains the total voltage of BUS+ and BUS- through the voltage divider resistor, or directly samples the voltage between BUS+ and BUSN, or between BUSN and BUS-, to ensure accurate understanding of the overall and individual voltage status of the bus capacitors.

[0101] In a further embodiment, the cooling fan 4 is provided with a fan drive circuit, which is electrically connected to the control chip 3 and is used to receive the output signal of the control chip 3 to control the cooling fan 4 to start or stop working.

[0102] Understandably, using the original fan drive circuit of cooling fan 4 as the discharge structure simplifies the overall structure of the power supply system. Moreover, no new circuits are needed; the voltage regulation of bus capacitor 1 can be achieved simply by improving the control logic.

[0103] As shown in Figure 8, in some embodiments, a fan drive circuit for a DC cooling fan that does not support speed adjustment is provided, which includes:

[0104] The first capacitor C3 is connected between the positive output terminal VCC of the auxiliary power supply and the reference ground GND.

[0105] The first switch Q1 has its source connected to reference ground GND and its gate electrically connected to the control chip to receive PWM signals from the control chip.

[0106] The freewheeling diode D1 has its anode connected to the drain of the first switching transistor Q1.

[0107] Energy storage inductor L1, the first end of energy storage inductor L1 is connected to the cathode of freewheeling diode D1, and the second end of energy storage inductor L1 outputs the fan operating voltage.

[0108] The second capacitor C4 is connected between the second terminal of the energy storage inductor L1 and the reference ground GND.

[0109] When the control chip outputs a PWM signal with a duty cycle of 0%, the first switching transistor Q1 remains off, the operating voltage of the cooling fan drops to zero, and the cooling fan stops working.

[0110] It is understandable that the first capacitor C3 is a filter capacitor, filtering out the ripple voltage of the auxiliary power supply VCC to ensure stable input of the drive circuit; the first switch Q1 and the energy storage inductor L1 form a Buck buck structure, the PWM signal controls the turn-on / turn-off of Q1, and the energy storage inductor L1 regulates the output voltage through energy storage / release; the freewheeling diode D1 provides a freewheeling circuit for the energy storage inductor L1 when the first switch Q1 is off, avoiding voltage spikes from damaging the device; the second capacitor C4 further filters, outputting a stable fan operating voltage; when the PWM duty cycle is 0%, the first switch Q1 is always off, the energy storage inductor L1 has no energy stored, the output voltage drops to zero, and the cooling fan stops working. The Buck structure ensures stable fan operating voltage, avoiding fluctuations in the auxiliary power supply voltage that could cause unstable fan speed or abnormal power consumption, ensuring that the fan can operate stably at maximum power consumption in the first stage; at the same time, the 0% duty cycle ensures reliable fan stoppage, guaranteeing the accuracy of power consumption regulation in the second stage, making it suitable for non-speed-adjustable fans with high power supply stability requirements.

[0111] As shown in Figure 9, in some embodiments, a fan drive circuit for a speed-adjustable DC cooling fan is provided, which includes:

[0112] The current-limiting resistor R3 is connected to the I / O pin of the control chip to receive the switch control signal.

[0113] The base of the second switch Q2 is connected to the second terminal of the current limiting resistor R3, the collector of the second switch Q2 is connected to the feedback signal terminal FAN_FG of the cooling fan, and the emitter of the second switch Q2 is connected to the reference ground GND.

[0114] When the control chip outputs a shutdown signal, the second switch Q2 is turned off, thereby cutting off the circuit of the cooling fan and stopping it from working.

[0115] Understandably, the current-limiting resistor R3 limits the output current of the control chip's I / O pins, preventing excessive current from damaging the base of the second switching transistor Q2. The FAN_FG pin of the cooling fan is the speed feedback terminal, outputting a pulse signal proportional to the speed during normal operation. When the control chip outputs a high-level signal, the second switching transistor Q2 is turned on, the FAN_FG pin is grounded, and the cooling fan operates at the corresponding speed, such as the maximum speed, according to its internal logic. When the output is low-level or off, the base of the second switching transistor Q2 has no current and is turned off, the FAN_FG pin loses its grounding loop, and the internal control circuit of the cooling fan determines it as a stop command, cutting off the power supply to the motor. Utilizing the fan's own FAN_FG pin for control eliminates the need for an additional speed control pin, simplifying the drive circuit structure. The current-limiting resistor R3 protects the control chip and the switching transistor, improving circuit reliability and ensuring that the speed-adjustable fan can accurately respond to stop commands, adapting to the power consumption adjustment requirements of multi-stage discharge.

[0116] In a preferred embodiment, the power system further includes: a display (not shown) powered by an auxiliary power supply; the display is electrically connected to the control chip 3 via a serial communication interface and is controlled by the control chip 3.

[0117] Understandably, the monitor's power supply is connected to the output of auxiliary power supply 2 to obtain operating power; its communication end is connected to the communication pin of control chip 3 via a serial communication interface such as RS485, following a preset communication protocol; control chip 3 can send commands such as "sleep," "wake up," and "display parameters," and the monitor receives these commands and executes the corresponding operations. Simultaneously, the monitor can feed back its own operating status, such as current power consumption and fault codes, to control chip 3, forming a two-way interaction. Precise control of the monitor is achieved through serial communication. The second stage of shutting down the monitor further reduces the power consumption of auxiliary power supply 2. At the same time, the status information fed back by the monitor helps control chip 3 determine whether the load is responding normally, avoiding abnormal power consumption regulation caused by monitor malfunctions and improving the reliability of the discharge process.

[0118] The above examples are merely illustrative of the technical content of the present invention to facilitate easier understanding by the reader, but do not imply that the implementation of the present invention is limited to these examples. Any technical extensions or re-creations made based on the present invention are protected by the present invention. The scope of protection of the present invention is defined by the claims.

Claims

1. A bus discharge method for an integrated power supply system, applied to a power supply system, the power supply system comprising a bus capacitor, a discharge resistor connected in parallel with the bus capacitor, a control chip, an auxiliary power supply, and a cooling fan, wherein the auxiliary power supply draws power from the bus capacitor to supply power to the cooling fan, characterized in that, The method includes the following steps: detecting the input status of the power system; when a power failure is detected in the power system input, controlling the power system to enter a shutdown mode; initiating a multi-stage discharge control process, adjusting the load power consumption by controlling the start and stop of the load powered by the auxiliary power supply to control the discharge rate of the bus capacitor in stages; wherein, initiating the multi-stage discharge control process, adjusting the load power consumption by controlling the start and stop of the load powered by the auxiliary power supply to control the discharge rate of the bus capacitor in stages, includes the following steps: controlling the cooling fan to operate in maximum power consumption mode, causing the bus capacitor to discharge to a preset first bus voltage; when the bus voltage is detected to drop to the first bus voltage, controlling the cooling fan to stop working. The system includes a control chip that enters a sleep mode to discharge the bus capacitor to a preset second bus voltage. When the bus voltage drops to the second bus voltage, the auxiliary power supply is controlled to stop working, and the bus capacitor is discharged to the target bus voltage through a discharge resistor. The power system also includes a display powered by the auxiliary power supply. The step of controlling the cooling fan to stop working and the control chip to enter a sleep mode to discharge the bus capacitor to the preset second bus voltage when the bus voltage drops to the first bus voltage includes: controlling the cooling fan to stop working; turning off the display; controlling the control chip to enter a sleep mode; and the auxiliary power supply operating in an intermittent mode to discharge the bus capacitor to the preset second bus voltage.

2. The bus discharge method for an integrated power reserve system according to claim 1, characterized in that, The method of controlling the cooling fan to stop working includes: changing the level state of the PWM output pin of the control chip to control the switching device in the driving circuit of the cooling fan, thereby cutting off the power supply to the cooling fan or reducing the voltage of the cooling fan below the power supply voltage, so that the cooling fan stops working.

3. The bus discharge method for an integrated power reserve system according to claim 2, characterized in that, The process of turning off the display includes sending a sleep command to the display through the communication interface of the control chip, so that the display screen enters a low-power standby or sleep state.

4. The bus discharge method for an integrated power reserve system according to claim 1, characterized in that, The first bus voltage is a voltage value pre-calibrated based on the bus capacitor capacity of the power system, the rated power consumption of the auxiliary power supply, and / or the maximum power consumption mode of the cooling fan. The second bus voltage is the discharge cutoff voltage of the auxiliary power supply in discontinuous mode.

5. The bus discharge method for an integrated power reserve system according to claim 1, characterized in that, The auxiliary power supply adopts a flyback topology.

6. A power reserve integrated power system for performing the bus discharge method of the power reserve integrated power system as described in any one of claims 1 to 5, characterized in that, include: The system comprises a bus capacitor, a discharge resistor, a control chip, an auxiliary power supply, and a cooling fan; the discharge resistor is connected in parallel to the bus capacitor, and the cooling fan is electrically connected to the auxiliary power supply; the auxiliary power supply is electrically connected to the bus capacitor and is used to draw power from the bus capacitor and supply power to the cooling fan and the control chip; the control chip is electrically connected to the bus capacitor, the auxiliary power supply, and the cooling fan, and is configured to execute the bus discharge method of the integrated power reserve system.

7. The integrated power storage system according to claim 6, characterized in that, The cooling fan is equipped with a fan drive circuit, which is electrically connected to the control chip and is used to receive the output signal of the control chip to control the cooling fan to start or stop working.

8. The integrated power storage system according to claim 6, characterized in that, Also includes: A display powered by the auxiliary power supply; The display is electrically connected to the control chip via a serial communication interface and is controlled by the control chip.

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